[PATCH] Add RISCV_ISA_ZALRSC_ONLY to rewrite amo instructions via lr and sc

[Chao-ying Fu]

On Thu, Jan 9, 2025 at 5:12 PM Bo Gan <ganboing at gmail.com> wrote:
>
> Hi Chaoying,
>
> On 1/9/25 16:24, Chao-ying Fu wrote:
> > Some platforms implement lr and sc in hardware, and emulate amo
> > instructions via the exception handler. To get better performance,
> > we use lr and sc only, when the config is defined.
>
> This comment seems to be self-contradictory. If the core does not support
> amo, then there's no way currently in opensbi to trap/emulate it through
> exception handler. Thus, from your description, it's not only performance,
> but correctness instead. Also do you have a concrete example of such HW?
> I wonder if it's worthwhile to maintain for such special HW. I know the
> S7 hart in hifive/unmatched and starfive/jh7110 works the other way around:
> it only supports AMO, but not lr/sc.

Our core implements extra custom illegal instruction exceptions for
amo instructions and has custom exception vector address. We have
assembly source code to emulate amo via lr and sc in our platform
code. We will post our platform patch to OpenSBI later.
Note that without this patch, the original code still can run.
However, if we just replace amo with lr and sc directly in OpenSBI, we
don't need to run through our custom exception handler.
Thanks a lot!

Regards,
Chao-ying