[PATCH] atomics: fix AMO test macros

[Xiang W]

在 2025-12-25四的 13:18 +0200，Vladimir Kondratiev写道：
> The "RISC-V C API" [1] defines architecture extension test macros
> says naming rule for the test macros is __riscv_<ext_name>,
> where <ext_name> is all lower-case.
> 3 extensions dealing with atomics implementation,
> "zaamo" consists of AMO instructions, "zalrsc" - LR/SC,
> "a" extension means both "zaamo" and "zalrsc"
> Test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc.
> Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated.
> 
> Use correct test macro __riscv_zaamo for the AMO variant of atomics.
> It used to be __riscv_atomic that is both deprecated and incorrect
> because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc"
> If ISA enables only zaamo but not zalrsc, code as it was would not compile.
> 
> [1] https://github.com/riscv-non-isa/riscv-c-api-doc
> 
> Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev at mobileye.com>
> ---
>  firmware/fw_base.S            | 2 +-
>  firmware/payloads/test_head.S | 2 +-
>  lib/sbi/riscv_atomic.c        | 8 ++++----
>  lib/sbi/riscv_locks.c         | 2 +-
>  lib/sbi/sbi_illegal_atomic.c  | 6 +++---
>  5 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index 5300ecf22e0c..9fbe2b870974 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -59,7 +59,7 @@ _try_lottery:
>  	/* Jump to relocation wait loop if we don't get relocation lottery */
>  	lla	a6, _boot_lottery
>  	li	a7, BOOT_LOTTERY_ACQUIRED
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
Older toolchains may not have `__riscv_zaamo`, so it's recommended to use 
`#if defined(__riscv_atomic) || ​​defined(__riscv_zaamo)`.

Regards,
Xiang W
>  	amoswap.w a6, a7, (a6)
>  	bnez	a6, _wait_for_boot_hart
>  #elif __riscv_zalrsc
> diff --git a/firmware/payloads/test_head.S b/firmware/payloads/test_head.S
> index 070ce8aa98be..aa20a13f4b89 100644
> --- a/firmware/payloads/test_head.S
> +++ b/firmware/payloads/test_head.S
> @@ -30,7 +30,7 @@ _start:
>  	/* Pick one hart to run the main boot sequence */
>  	lla	a3, _hart_lottery
>  	li	a2, 1
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
>  	amoadd.w a3, a2, (a3)
>  #elif __riscv_zalrsc
>  _sc_fail:
> diff --git a/lib/sbi/riscv_atomic.c b/lib/sbi/riscv_atomic.c
> index df16a2eb159e..7935ca9c642c 100644
> --- a/lib/sbi/riscv_atomic.c
> +++ b/lib/sbi/riscv_atomic.c
> @@ -12,8 +12,8 @@
>  #include <sbi/riscv_atomic.h>
>  #include <sbi/riscv_barrier.h>
>  
> -#if !defined(__riscv_atomic) && !defined(__riscv_zalrsc)
> -#error "opensbi strongly relies on the A extension of RISC-V"
> +#if !defined(__riscv_zaamo) && !defined(__riscv_zalrsc)
> +#error "opensbi strongly relies on the zaamo or zalrsc extension of RISC-V"
>  #endif
>  
>  long atomic_read(atomic_t *atom)
> @@ -31,7 +31,7 @@ void atomic_write(atomic_t *atom, long value)
>  
>  long atomic_add_return(atomic_t *atom, long value)
>  {
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
>  	long ret;
>  #if __SIZEOF_LONG__ == 4
>  	__asm__ __volatile__("	amoadd.w.aqrl  %1, %2, %0"
> @@ -75,7 +75,7 @@ long atomic_sub_return(atomic_t *atom, long value)
>  	return atomic_add_return(atom, -value);
>  }
>  
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
>  #define __axchg(ptr, new, size)							\
>  	({									\
>  		__typeof__(ptr) __ptr = (ptr);					\
> diff --git a/lib/sbi/riscv_locks.c b/lib/sbi/riscv_locks.c
> index 41e8fabd08be..2e4789365962 100644
> --- a/lib/sbi/riscv_locks.c
> +++ b/lib/sbi/riscv_locks.c
> @@ -53,7 +53,7 @@ void spin_lock(spinlock_t *lock)
>  
>  	__asm__ __volatile__(
>  		/* Atomically increment the next ticket. */
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
>  		"	amoadd.w.aqrl	%0, %4, %3\n"
>  #elif __riscv_zalrsc
>  		"3:	lr.w.aqrl	%0, %3\n"
> diff --git a/lib/sbi/sbi_illegal_atomic.c b/lib/sbi/sbi_illegal_atomic.c
> index 8fd6c5575bfb..12bc438c87c0 100644
> --- a/lib/sbi/sbi_illegal_atomic.c
> +++ b/lib/sbi/sbi_illegal_atomic.c
> @@ -11,11 +11,11 @@
>  #include <sbi/sbi_illegal_atomic.h>
>  #include <sbi/sbi_illegal_insn.h>
>  
> -#if !defined(__riscv_atomic) && !defined(__riscv_zalrsc)
> -#error "opensbi strongly relies on the A extension of RISC-V"
> +#if !defined(__riscv_zaamo) && !defined(__riscv_zalrsc)
> +#error "opensbi strongly relies on the AMO or LR/SC extension of RISC-V"
>  #endif
>  
> -#ifdef __riscv_atomic
> +#ifdef __riscv_zaamo
>  
>  int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs)
>  {
> -- 
> 2.43.0
>