[PATCH] lib: sbi_trap: Add support for vectored interrupts

[Anup Patel]

On Wed, Mar 5, 2025 at 9:29 AM Samuel Holland <samuel.holland at sifive.com> wrote:
>
> When redirecting an exception to S-mode, transform the (v)stvec CSR
> value as described in the privileged spec to derive the S-mode PC.
> Since OpenSBI never redirects interrupts, only synchronous exceptions,
> the only action needed is to mask out the (v)stvec.MODE field.
>
> Reported-by: Jan Reinhard <jan.reinhard at sysgo.com>
> Closes: https://github.com/riscv-software-src/opensbi/issues/391
> Signed-off-by: Samuel Holland <samuel.holland at sifive.com>

I think it is better to have explicit clearing of the MODE
bits before setting mepc.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


> ---
> Hi Jan,
>
> Thanks for your bug report and the patch!
>
> OpenSBI requires patches to be signed off in accordance with the
> Developer Certificate of Origin (DCO)[1], and sent as complete commits
> as with git format-patch/git send-email.
>
> Since the fix is trivial now that we are aware of the bug, I took the
> liberty of sending a more complete patch, so you don't have to deal with
> a bunch of processes just to get the bug fixed. If you'd rather resend
> your own patch per the Contribution Guidelines[1], that is fine too.
>
> Regards,
> Samuel
>
> [1]: https://github.com/riscv-software-src/opensbi/blob/master/docs/contributing.md
>
>  include/sbi/riscv_encoding.h | 2 ++
>  lib/sbi/sbi_trap.c           | 4 ++--
>  2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 03c68a57..1846d750 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -85,6 +85,8 @@
>  #define HSTATUS_GVA                    _UL(0x00000040)
>  #define HSTATUS_VSBE                   _UL(0x00000020)
>
> +#define MTVEC_MODE                     _UL(0x00000003)
> +
>  #define MCAUSE_IRQ_MASK                        (_UL(1) << (__riscv_xlen - 1))
>
>  #define IRQ_S_SOFT                     1
> diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
> index e63a563b..f41db4d1 100644
> --- a/lib/sbi/sbi_trap.c
> +++ b/lib/sbi/sbi_trap.c
> @@ -169,7 +169,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>                 csr_write(CSR_VSCAUSE, trap->cause);
>
>                 /* Set MEPC to VS-mode exception vector base */
> -               regs->mepc = csr_read(CSR_VSTVEC);
> +               regs->mepc = csr_read(CSR_VSTVEC) & ~MTVEC_MODE;
>
>                 /* Set MPP to VS-mode */
>                 regs->mstatus &= ~MSTATUS_MPP;
> @@ -204,7 +204,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>                 csr_write(CSR_SCAUSE, trap->cause);
>
>                 /* Set MEPC to S-mode exception vector base */
> -               regs->mepc = csr_read(CSR_STVEC);
> +               regs->mepc = csr_read(CSR_STVEC) & ~MTVEC_MODE;
>
>                 /* Set MPP to S-mode */
>                 regs->mstatus &= ~MSTATUS_MPP;
> --
> 2.47.2
>
>
> --
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