[PATCH] lib: sbi: fix missing high 32bits when sbi_cppc_write on rv32

[Anup Patel]

On Mon, Sep 23, 2024 at 7:09 AM Xiang W <wxjstz at 126.com> wrote:
>
> sbi_cppc_write was writing to the a1 register only, which under rv32
> would cause the high 32 bits to always be 0. This patch fixes that.
>
> Resolves: https://github.com/riscv-software-src/opensbi/issues/334

Always use "Closes:" in the commit description when fixing a GitHub issue.
This allows GitHub to automatically close the issue once the patch is
merged.

>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> Reported-by: Wesley Norris <repnop at outlook.com>
> ---
>  lib/sbi/sbi_ecall_cppc.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_ecall_cppc.c b/lib/sbi/sbi_ecall_cppc.c
> index c26bb40..f3747b0 100644
> --- a/lib/sbi/sbi_ecall_cppc.c
> +++ b/lib/sbi/sbi_ecall_cppc.c
> @@ -32,7 +32,13 @@ static int sbi_ecall_cppc_handler(unsigned long extid, unsigned long funcid,
>  #endif
>                 break;
>         case SBI_EXT_CPPC_WRITE:
> -               ret = sbi_cppc_write(regs->a0, regs->a1);
> +#if __riscv_xlen == 32
> +               temp = regs->a2;
> +               temp = (temp << 32) | regs->a1;
> +else

s/else/#else/

Make sure your patches are at least compile tested before sending.

> +               temp = regs->a1;
> +#endif
> +               ret = sbi_cppc_write(regs->a0, temp);
>                 break;
>         case SBI_EXT_CPPC_PROBE:
>                 ret = sbi_cppc_probe(regs->a0);
> --
> 2.45.2
>

I have taken care of the above issues at the time of merging this patch.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup