[PATCH] lib: sbi_misaligned_ldst: Add handling of C.LHU/C.LH and C.SH

[Anup Patel]

On Mon, Feb 26, 2024 at 11:26 AM Nylon Chen <nylon.chen at sifive.com> wrote:
>
> From: "Nylon Chen" <nylon.chen at sifive.com>
>
> Added exception handling for compressed instructions C.LHU, C.LH, and
> C.SH from the zcb extension to the sbi_misaligned_ldst library.
>
> Signed-off-by: Nylon Chen <nylon.chen at sifive.com>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/riscv_encoding.h  |  7 +++++++
>  lib/sbi/sbi_misaligned_ldst.c | 10 ++++++++++
>  2 files changed, 17 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index e74cc0d..3d77e26 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -837,6 +837,13 @@
>  #define INSN_MATCH_C_FSWSP             0xe002
>  #define INSN_MASK_C_FSWSP              0xe003
>
> +#define INSN_MATCH_C_LHU               0x8400
> +#define INSN_MASK_C_LHU                0xfc43
> +#define INSN_MATCH_C_LH                0x8440
> +#define INSN_MASK_C_LH                 0xfc43
> +#define INSN_MATCH_C_SH                0x8c00
> +#define INSN_MASK_C_SH                 0xfc43
> +
>  #define INSN_MASK_WFI                  0xffffff00
>  #define INSN_MATCH_WFI                 0x10500000
>
> diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c
> index aa512de..9ca225a 100644
> --- a/lib/sbi/sbi_misaligned_ldst.c
> +++ b/lib/sbi/sbi_misaligned_ldst.c
> @@ -123,6 +123,13 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
>                 len = 4;
>  #endif
>  #endif
> +       } else if ((insn & INSN_MASK_C_LHU) == INSN_MATCH_C_LHU) {
> +               len = 2;
> +               insn = RVC_RS2S(insn) << SH_RD;
> +       } else if ((insn & INSN_MASK_C_LH) == INSN_MATCH_C_LH) {
> +               len = 2;
> +               shift = 8 * (sizeof(ulong) - len);
> +               insn = RVC_RS2S(insn) << SH_RD;
>         } else {
>                 uptrap.epc = regs->mepc;
>                 uptrap.cause = CAUSE_MISALIGNED_LOAD;
> @@ -237,6 +244,9 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
>                 val.data_ulong = GET_F32_RS2C(insn, regs);
>  #endif
>  #endif
> +       } else if ((insn & INSN_MASK_C_SH) == INSN_MATCH_C_SH) {
> +               len             = 2;
> +               val.data_ulong = GET_RS2S(insn, regs);
>         } else {
>                 uptrap.epc = regs->mepc;
>                 uptrap.cause = CAUSE_MISALIGNED_STORE;
> --
> 2.34.1
>
>
> --
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