From amanieu at gmail.com  Sun Oct  1 02:12:02 2023
From: amanieu at gmail.com (Amanieu d'Antras)
Date: Sun,  1 Oct 2023 10:12:02 +0100
Subject: [PATCH] lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP
Message-ID: <20231001091226.592084-1-amanieu@gmail.com>

Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
register, so checking that the rs2 field is non-zero is unnecessary.

Additionally, the previous check was incorrect since it was checking the
immediate field of the instruction instead of the rs2 field.

Signed-off-by: Amanieu d'Antras <amanieu at gmail.com>
---
 lib/sbi/sbi_misaligned_ldst.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c
index 4b91e07..aa512de 100644
--- a/lib/sbi/sbi_misaligned_ldst.c
+++ b/lib/sbi/sbi_misaligned_ldst.c
@@ -211,16 +211,14 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
 	} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
 		len	       = 8;
 		val.data_ulong = GET_RS2S(insn, regs);
-	} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
-		   ((insn >> SH_RD) & 0x1f)) {
+	} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {
 		len	       = 8;
 		val.data_ulong = GET_RS2C(insn, regs);
 #endif
 	} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
 		len	       = 4;
 		val.data_ulong = GET_RS2S(insn, regs);
-	} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
-		   ((insn >> SH_RD) & 0x1f)) {
+	} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {
 		len	       = 4;
 		val.data_ulong = GET_RS2C(insn, regs);
 #ifdef __riscv_flen
-- 
2.42.0



From wxjstz at 126.com  Wed Oct  4 04:48:20 2023
From: wxjstz at 126.com (Xiang W)
Date: Wed, 04 Oct 2023 19:48:20 +0800
Subject: [PATCH v2 1/1] lib: utils: Simplify SET_ISA_EXT_MAP()
In-Reply-To: <20230928121720.41669-1-heinrich.schuchardt@canonical.com>
References: <20230928121720.41669-1-heinrich.schuchardt@canonical.com>
Message-ID: <fc00fd7b82fd5013065ad9526a7a26cc0634cdb4.camel@126.com>

? 2023-09-28???? 14:17 +0200?Heinrich Schuchardt???
> The define is hard to read. The continue statement does not do what was
> intended.
> 
> * Remove do {} while (false);
> * Change the name to set_multi_letter_ext
> ? - Other local macros are lower case too.
> ? - Refer to the fact that this is only used for multi-letter extensions.
> 
> Addresses-Coverity-ID: 1568359 Unexpected control flow
> Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA string in FDT")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> 	keep continue statement
> 	rename macro
> ---
> ?lib/utils/fdt/fdt_helper.c | 13 ++++++-------
> ?1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index c97f09d..b97ff74 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -369,16 +369,15 @@ static int fdt_parse_isa_one_hart(const char *isa, unsigned long *extensions)
> ?		if (!j)
> ?			continue;
> ?
> -#define SET_ISA_EXT_MAP(name, bit)				\
> -		do {						\
> -			if (!strcmp(mstr, name)) {		\
> +#define set_multi_letter_ext(name, bit)				\
> +		{						\
> +			if (!strcmp(mstr, name))		\
> ?				__set_bit(bit, extensions);	\
> ?				continue;			\
> -			}					\
> -		} while (false)					\
> +		}						\
> ?
> -		SET_ISA_EXT_MAP("smepmp", SBI_HART_EXT_SMEPMP);
> -#undef SET_ISA_EXT_MAP
> +		set_multi_letter_ext("smepmp", SBI_HART_EXT_SMEPMP);
> +#undef set_multi_letter_ext
> ?	}
> ?
> ?	return 0;
> -- 
> 2.40.1
> 
> 



From anup at brainfault.org  Wed Oct  4 07:57:43 2023
From: anup at brainfault.org (Anup Patel)
Date: Wed, 4 Oct 2023 20:27:43 +0530
Subject: [PATCH v2] platform: generic: thead: fix stale TLB entries for th1520/sg2042
In-Reply-To: <IA1PR20MB495365BF4F1FFA74C7CCEA9CBBF6A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495365BF4F1FFA74C7CCEA9CBBF6A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAAhSdy0ZKWKA34_+AFCU6kYK9YOPkSR3ZzqFLuhuNY3oLOpZWA@mail.gmail.com>

On Fri, Sep 15, 2023 at 3:10?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> The TLB entries remain functional all the time once added in T-HEAD th1520
> and Sophgo sg2042 (even if the MMU is then disabled afterwards). If there
> are some stale TLB entries that contains the address of SBI, it will cause
> unexpected memory access and issue a illegal instruction error. To avoid
> this, a TLB flush is needed to drop these TLB entries before any memory
> access in the trap handler.
>
> To handle this workaroud, add a custom trap handler with executing TLB flush
> first in the T-HEAD platform to fix affected socs.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> Changed from v1:
> 1. remove stale code in RFC v2;
> 2. change quirk and function name to "TLB_FLUSH_FIXUP" for clear meaning.
>
> Changed from RFC v2:
> 1. rollback the moving of trap helper macro to sbi_trap.h
> 2. use direct jump in custom trap handler to access _trap_handler
>
> Changed from RFC:
> 1. use custom trap handler instead of asm alternative.
> 2. change description
> ---
>  platform/generic/Kconfig                    |  4 ++
>  platform/generic/configs/defconfig          |  1 +
>  platform/generic/thead/objects.mk           | 10 +++++
>  platform/generic/thead/thead-generic.c      | 50 +++++++++++++++++++++
>  platform/generic/thead/thead-trap-handler.S | 13 ++++++
>  5 files changed, 78 insertions(+)
>  create mode 100644 platform/generic/thead/objects.mk
>  create mode 100644 platform/generic/thead/thead-generic.c
>  create mode 100644 platform/generic/thead/thead-trap-handler.S
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 72768ed..68dd58c 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -52,6 +52,10 @@ config PLATFORM_STARFIVE_JH7110
>         bool "StarFive JH7110 support"
>         default n
>
> +config PLATFORM_THEAD_GENERIC
> +       bool "THEAD C9xx generic platform support"
> +       default n
> +

No need to add "_GENERIC" suffix to kconfig name. I have
taken care of this at the time of merging this patch.

>  source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
>
>  endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 634d410..26f0874 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -4,6 +4,7 @@ CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
>  CONFIG_PLATFORM_STARFIVE_JH7110=y
> +CONFIG_PLATFORM_THEAD_GENERIC=y
>  CONFIG_FDT_GPIO=y
>  CONFIG_FDT_GPIO_DESIGNWARE=y
>  CONFIG_FDT_GPIO_SIFIVE=y
> diff --git a/platform/generic/thead/objects.mk b/platform/generic/thead/objects.mk
> new file mode 100644
> index 0000000..cbbab18
> --- /dev/null
> +++ b/platform/generic/thead/objects.mk
> @@ -0,0 +1,10 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
> +# Copyright (C) 2023 Alibaba Group Holding Limited.
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD_GENERIC) += thead_generic
> +platform-objs-$(CONFIG_PLATFORM_THEAD_GENERIC) += thead/thead-generic.o
> +platform-objs-$(CONFIG_PLATFORM_THEAD_GENERIC) += thead/thead-trap-handler.o
> diff --git a/platform/generic/thead/thead-generic.c b/platform/generic/thead/thead-generic.c
> new file mode 100644
> index 0000000..8120f6f
> --- /dev/null
> +++ b/platform/generic/thead/thead-generic.c
> @@ -0,0 +1,50 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Authors:
> + *   Inochi Amaoto <inochiama at outlook.com>
> + *
> + */
> +
> +#include <platform_override.h>
> +#include <sbi/riscv_barrier.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_string.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +/**
> + * T-HEAD board with this quirk need to execute sfence.vma to flush
> + * stale entrie avoid incorrect memory access.
> + */
> +#define THEAD_QUIRK_TLB_FLUSH_FIXUP            BIT(0)
> +
> +void _thead_tlb_flush_fixup_trap_handler(void);
> +
> +void thead_register_tlb_flush_trap_handler(void)
> +{
> +       csr_write(CSR_MTVEC, &_thead_tlb_flush_fixup_trap_handler);
> +}
> +
> +static int thead_generic_early_init(bool cold_boot,
> +                                   const struct fdt_match *match)
> +{
> +       unsigned long quirks = (unsigned long)match->data;
> +
> +       if (quirks & THEAD_QUIRK_TLB_FLUSH_FIXUP)
> +               thead_register_tlb_flush_trap_handler();
> +
> +       return 0;
> +}
> +
> +static const struct fdt_match thead_generic_match[] = {
> +       { .compatible = "thead,th1520",
> +         .data = (void*)THEAD_QUIRK_TLB_FLUSH_FIXUP },
> +       { },
> +};
> +
> +const struct platform_override thead_generic = {
> +       .match_table    = thead_generic_match,
> +       .early_init     = thead_generic_early_init,
> +};
> diff --git a/platform/generic/thead/thead-trap-handler.S b/platform/generic/thead/thead-trap-handler.S
> new file mode 100644
> index 0000000..861c029
> --- /dev/null
> +++ b/platform/generic/thead/thead-trap-handler.S
> @@ -0,0 +1,13 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Authors:
> + *   Inochi Amaoto <inochiama at outlook.com>
> + *
> + */
> +       .section .entry, "ax", %progbits
> +       .align 3
> +       .globl _thead_tlb_flush_fixup_trap_handler
> +_thead_tlb_flush_fixup_trap_handler:
> +       sfence.vma t0, zero
> +       j _trap_handler
> --
> 2.42.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From inochiama at outlook.com  Wed Oct  4 23:57:44 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu,  5 Oct 2023 14:57:44 +0800
Subject: [PATCH v2 0/4] platform: generic: add T-HEAD th1520 soc support
Message-ID: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>

As the tlb workaround is fixed, now it is a time to add T-HEAD th1520 soc
PMU support.

We also move the tlb flush errata to a separate file, so the furthur
platform can reused it. e.g. the Sophgo sg2042.

Changed from v1:
1. rebase for the master

Inochi Amaoto (4):
  platform: generic: thead: move to thead c9xx header to vendor specific
    postion
  platform: generic: thead: separate implement of T-HEAD c9xx pmu
  platform: generic: thead: separate implement of T-HEAD c9xx errata
  platform: generic: thead: initialize PMU by default in thead generic
    platform

 platform/generic/Kconfig                      |  4 ++
 platform/generic/allwinner/sun20i-d1.c        | 53 +-------------
 .../{thead_c9xx.h => thead/c9xx_encoding.h}   |  4 +-
 platform/generic/include/thead/c9xx_errata.h  | 14 ++++
 platform/generic/include/thead/c9xx_pmu.h     |  7 ++
 platform/generic/thead/Kconfig                |  9 +++
 platform/generic/thead/objects.mk             |  6 +-
 platform/generic/thead/thead-generic.c        | 41 ++++++-----
 .../thead/thead_c9xx_errata_tlb_flush.c       | 17 +++++
 platform/generic/thead/thead_c9xx_pmu.c       | 69 +++++++++++++++++++
 ...andler.S => thead_c9xx_tlb_trap_handler.S} |  0
 11 files changed, 152 insertions(+), 72 deletions(-)
 rename platform/generic/include/{thead_c9xx.h => thead/c9xx_encoding.h} (98%)
 create mode 100644 platform/generic/include/thead/c9xx_errata.h
 create mode 100644 platform/generic/include/thead/c9xx_pmu.h
 create mode 100644 platform/generic/thead/Kconfig
 create mode 100644 platform/generic/thead/thead_c9xx_errata_tlb_flush.c
 create mode 100644 platform/generic/thead/thead_c9xx_pmu.c
 rename platform/generic/thead/{thead-trap-handler.S => thead_c9xx_tlb_trap_handler.S} (100%)

--
2.42.0



From inochiama at outlook.com  Wed Oct  4 23:58:40 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu,  5 Oct 2023 14:58:40 +0800
Subject: [PATCH v2 1/4] platform: generic: thead: move to thead c9xx header to vendor specific postion
In-Reply-To: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB495315D187896E99EF4A8747BBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>

The CSR encoding for t-head c9xx cores is shared across all the
platforms with these cores. So move header thead_c9xx.h to the
thead subdir.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/allwinner/sun20i-d1.c                        | 2 +-
 .../generic/include/{thead_c9xx.h => thead/c9xx_encoding.h}   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename platform/generic/include/{thead_c9xx.h => thead/c9xx_encoding.h} (98%)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index a9a7e47..b960284 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -5,7 +5,7 @@
  */
 
 #include <platform_override.h>
-#include <thead_c9xx.h>
+#include <thead/c9xx_encoding.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_io.h>
 #include <sbi/sbi_bitops.h>
diff --git a/platform/generic/include/thead_c9xx.h b/platform/generic/include/thead/c9xx_encoding.h
similarity index 98%
rename from platform/generic/include/thead_c9xx.h
rename to platform/generic/include/thead/c9xx_encoding.h
index bab0408..58adbef 100644
--- a/platform/generic/include/thead_c9xx.h
+++ b/platform/generic/include/thead/c9xx_encoding.h
@@ -1,5 +1,5 @@
-#ifndef __RISCV_THEAD_C9XX_H____
-#define __RISCV_THEAD_C9XX_H____
+#ifndef __RISCV_THEAD_C9XX_ENCODING_H____
+#define __RISCV_THEAD_C9XX_ENCODING_H____
 
 /* T-HEAD C9xx M mode CSR.  */
 #define THEAD_C9XX_CSR_MXSTATUS		0x7c0
-- 
2.42.0



From inochiama at outlook.com  Wed Oct  4 23:58:41 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu,  5 Oct 2023 14:58:41 +0800
Subject: [PATCH v2 2/4] platform: generic: thead: separate implement of T-HEAD c9xx pmu
In-Reply-To: <20231005065843.239501-1-inochiama@outlook.com>
References: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231005065843.239501-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB4953F08770A3C489E3413567BBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>

Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig                  |  2 +
 platform/generic/allwinner/sun20i-d1.c    | 51 +----------------
 platform/generic/include/thead/c9xx_pmu.h |  7 +++
 platform/generic/thead/Kconfig            |  5 ++
 platform/generic/thead/objects.mk         |  2 +
 platform/generic/thead/thead_c9xx_pmu.c   | 69 +++++++++++++++++++++++
 6 files changed, 87 insertions(+), 49 deletions(-)
 create mode 100644 platform/generic/include/thead/c9xx_pmu.h
 create mode 100644 platform/generic/thead/Kconfig
 create mode 100644 platform/generic/thead/thead_c9xx_pmu.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index e7bd94e..ea3b5cf 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -26,6 +26,7 @@ config PLATFORM_GENERIC_MINOR_VER
 config PLATFORM_ALLWINNER_D1
 	bool "Allwinner D1 support"
 	depends on FDT_IRQCHIP_PLIC
+	select THEAD_C9XX_PMU
 	default n
 
 config PLATFORM_ANDES_AE350
@@ -57,5 +58,6 @@ config PLATFORM_THEAD
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
+source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
 
 endif
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index b960284..e9388db 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -6,6 +6,7 @@
 
 #include <platform_override.h>
 #include <thead/c9xx_encoding.h>
+#include <thead/c9xx_pmu.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_io.h>
 #include <sbi/sbi_bitops.h>
@@ -223,58 +224,10 @@ static int sun20i_d1_fdt_fixup(void *fdt, const struct fdt_match *match)
 	return fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
 }
 
-static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
-{
-	if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
-		return;
-
-	/**
-	 * Clear out the OF bit so that next interrupt can be enabled.
-	 * This should be done before starting interrupt to avoid unexcepted
-	 * overflow interrupt.
-	 */
-	csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
-
-	/**
-	 * This register is described in C9xx document as the control register
-	 * for enabling writes to the superuser state counter. However, if the
-	 * corresponding bit is not set to 1, scounterof will always read as 0
-	 * when the counter register overflows.
-	 */
-	csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
-
-	/**
-	 * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
-	 * while the C9XX has designated enable bits.
-	 * So enable per-counter interrupt on C9xx here.
-	 */
-	csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
-}
-
-static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
-{
-	/**
-	 * There is no need to clear the bit of mcounterwen, it will expire
-	 * after setting the csr mcountinhibit.
-	 */
-	csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
-}
-
-static int thead_c9xx_pmu_irq_bit(void)
-{
-	return THEAD_C9XX_MIP_MOIP;
-}
-
-const struct sbi_pmu_device thead_c9xx_pmu_device = {
-	.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
-	.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
-	.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
-};
-
 static int sun20i_d1_extensions_init(const struct fdt_match *match,
 				     struct sbi_hart_features *hfeatures)
 {
-	sbi_pmu_set_device(&thead_c9xx_pmu_device);
+	thead_c9xx_register_pmu_device();
 
 	/* auto-detection doesn't work on t-head c9xx cores */
 	/* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
diff --git a/platform/generic/include/thead/c9xx_pmu.h b/platform/generic/include/thead/c9xx_pmu.h
new file mode 100644
index 0000000..bb1d831
--- /dev/null
+++ b/platform/generic/include/thead/c9xx_pmu.h
@@ -0,0 +1,7 @@
+
+#ifndef __RISCV_THEAD_C9XX_PMU_H____
+#define __RISCV_THEAD_C9XX_PMU_H____
+
+void thead_c9xx_register_pmu_device(void);
+
+#endif // __RISCV_THEAD_C9XX_PMU_H____
diff --git a/platform/generic/thead/Kconfig b/platform/generic/thead/Kconfig
new file mode 100644
index 0000000..e54e621
--- /dev/null
+++ b/platform/generic/thead/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+config THEAD_C9XX_PMU
+	bool "T-HEAD c9xx M-mode PMU support"
+	default n
diff --git a/platform/generic/thead/objects.mk b/platform/generic/thead/objects.mk
index 854bfbd..df2c61b 100644
--- a/platform/generic/thead/objects.mk
+++ b/platform/generic/thead/objects.mk
@@ -5,6 +5,8 @@
 # Copyright (C) 2023 Alibaba Group Holding Limited.
 #
 
+platform-objs-$(CONFIG_THEAD_C9XX_PMU) += thead/thead_c9xx_pmu.o
+
 carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD) += thead_generic
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-generic.o
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-trap-handler.o
diff --git a/platform/generic/thead/thead_c9xx_pmu.c b/platform/generic/thead/thead_c9xx_pmu.c
new file mode 100644
index 0000000..d205802
--- /dev/null
+++ b/platform/generic/thead/thead_c9xx_pmu.c
@@ -0,0 +1,69 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *   Haijiao Liu <haijiao.liu at sophgo.com>
+ *
+ */
+
+#include <thead/c9xx_encoding.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_pmu.h>
+
+static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
+{
+	if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+		return;
+
+	/**
+	 * Clear out the OF bit so that next interrupt can be enabled.
+	 * This should be done before starting interrupt to avoid unexcepted
+	 * overflow interrupt.
+	 */
+	csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
+
+	/**
+	 * This register is described in C9xx document as the control register
+	 * for enabling writes to the superuser state counter. However, if the
+	 * corresponding bit is not set to 1, scounterof will always read as 0
+	 * when the counter register overflows.
+	 */
+	csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
+
+	/**
+	 * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
+	 * while the C9XX has designated enable bits.
+	 * So enable per-counter interrupt on C9xx here.
+	 */
+	csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
+{
+	/**
+	 * There is no need to clear the bit of mcounterwen, it will expire
+	 * after setting the csr mcountinhibit.
+	 */
+	csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static int thead_c9xx_pmu_irq_bit(void)
+{
+	return THEAD_C9XX_MIP_MOIP;
+}
+
+static const struct sbi_pmu_device thead_c9xx_pmu_device = {
+	.name = "thead,c900-pmu",
+	.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
+	.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
+	.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
+};
+
+void thead_c9xx_register_pmu_device(void)
+{
+	sbi_pmu_set_device(&thead_c9xx_pmu_device);
+}
-- 
2.42.0



From inochiama at outlook.com  Wed Oct  4 23:58:42 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu,  5 Oct 2023 14:58:42 +0800
Subject: [PATCH v2 3/4] platform: generic: thead: separate implement of T-HEAD c9xx errata
In-Reply-To: <20231005065843.239501-1-inochiama@outlook.com>
References: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231005065843.239501-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB495386DC04E588A3869ADD69BBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>

Separate the implement of T-HEAD c9xx errata to allow any platform
with bug related to c9xx cores can use it.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig                      |  1 +
 platform/generic/include/thead/c9xx_errata.h  | 14 ++++++++++
 platform/generic/thead/Kconfig                |  4 +++
 platform/generic/thead/objects.mk             |  4 ++-
 platform/generic/thead/thead-generic.c        | 28 ++++++++-----------
 .../thead/thead_c9xx_errata_tlb_flush.c       | 17 +++++++++++
 ...andler.S => thead_c9xx_tlb_trap_handler.S} |  0
 7 files changed, 50 insertions(+), 18 deletions(-)
 create mode 100644 platform/generic/include/thead/c9xx_errata.h
 create mode 100644 platform/generic/thead/thead_c9xx_errata_tlb_flush.c
 rename platform/generic/thead/{thead-trap-handler.S => thead_c9xx_tlb_trap_handler.S} (100%)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index ea3b5cf..3be75cf 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -55,6 +55,7 @@ config PLATFORM_STARFIVE_JH7110
 
 config PLATFORM_THEAD
 	bool "THEAD C9xx support"
+	select THEAD_C9XX_ERRATA
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
diff --git a/platform/generic/include/thead/c9xx_errata.h b/platform/generic/include/thead/c9xx_errata.h
new file mode 100644
index 0000000..b617762
--- /dev/null
+++ b/platform/generic/include/thead/c9xx_errata.h
@@ -0,0 +1,14 @@
+
+#ifndef __RISCV_THEAD_C9XX_ERRATA_H____
+#define __RISCV_THEAD_C9XX_ERRATA_H____
+
+/**
+ * T-HEAD board with this quirk need to execute sfence.vma to flush
+ * stale entrie avoid incorrect memory access.
+ */
+#define THEAD_QUIRK_ERRATA_TLB_FLUSH		BIT(0)
+
+void thead_register_tlb_flush_trap_handler(void);
+
+#endif // __RISCV_THEAD_C9XX_ERRATA_H____
+
diff --git a/platform/generic/thead/Kconfig b/platform/generic/thead/Kconfig
index e54e621..c50d38e 100644
--- a/platform/generic/thead/Kconfig
+++ b/platform/generic/thead/Kconfig
@@ -3,3 +3,7 @@
 config THEAD_C9XX_PMU
 	bool "T-HEAD c9xx M-mode PMU support"
 	default n
+
+config THEAD_C9XX_ERRATA
+	bool "T-HEAD c9xx errata support"
+	default n
diff --git a/platform/generic/thead/objects.mk b/platform/generic/thead/objects.mk
index df2c61b..84f9faf 100644
--- a/platform/generic/thead/objects.mk
+++ b/platform/generic/thead/objects.mk
@@ -7,6 +7,8 @@
 
 platform-objs-$(CONFIG_THEAD_C9XX_PMU) += thead/thead_c9xx_pmu.o
 
+platform-objs-$(CONFIG_THEAD_C9XX_ERRATA) += thead/thead_c9xx_tlb_trap_handler.o
+platform-objs-$(CONFIG_THEAD_C9XX_ERRATA) += thead/thead_c9xx_errata_tlb_flush.o
+
 carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD) += thead_generic
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-generic.o
-platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-trap-handler.o
diff --git a/platform/generic/thead/thead-generic.c b/platform/generic/thead/thead-generic.c
index 8120f6f..c77140c 100644
--- a/platform/generic/thead/thead-generic.c
+++ b/platform/generic/thead/thead-generic.c
@@ -7,40 +7,34 @@
  */
 
 #include <platform_override.h>
-#include <sbi/riscv_barrier.h>
+#include <thead/c9xx_errata.h>
 #include <sbi/sbi_const.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_string.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
-/**
- * T-HEAD board with this quirk need to execute sfence.vma to flush
- * stale entrie avoid incorrect memory access.
- */
-#define THEAD_QUIRK_TLB_FLUSH_FIXUP		BIT(0)
-
-void _thead_tlb_flush_fixup_trap_handler(void);
-
-void thead_register_tlb_flush_trap_handler(void)
-{
-	csr_write(CSR_MTVEC, &_thead_tlb_flush_fixup_trap_handler);
-}
+struct thead_generic_quirks {
+	u64	errata;
+};
 
 static int thead_generic_early_init(bool cold_boot,
 				    const struct fdt_match *match)
 {
-	unsigned long quirks = (unsigned long)match->data;
+	struct thead_generic_quirks *quirks = (void *)match->data;
 
-	if (quirks & THEAD_QUIRK_TLB_FLUSH_FIXUP)
+	if (quirks->errata & THEAD_QUIRK_ERRATA_TLB_FLUSH)
 		thead_register_tlb_flush_trap_handler();
 
 	return 0;
 }
 
+static struct thead_generic_quirks thead_th1520_quirks = {
+	.errata = THEAD_QUIRK_ERRATA_TLB_FLUSH,
+};
+
 static const struct fdt_match thead_generic_match[] = {
-	{ .compatible = "thead,th1520",
-	  .data = (void*)THEAD_QUIRK_TLB_FLUSH_FIXUP },
+	{ .compatible = "thead,th1520", .data = &thead_th1520_quirks },
 	{ },
 };
 
diff --git a/platform/generic/thead/thead_c9xx_errata_tlb_flush.c b/platform/generic/thead/thead_c9xx_errata_tlb_flush.c
new file mode 100644
index 0000000..755899a
--- /dev/null
+++ b/platform/generic/thead/thead_c9xx_errata_tlb_flush.c
@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+
+void _thead_tlb_flush_fixup_trap_handler(void);
+
+void thead_register_tlb_flush_trap_handler(void)
+{
+	csr_write(CSR_MTVEC, &_thead_tlb_flush_fixup_trap_handler);
+}
diff --git a/platform/generic/thead/thead-trap-handler.S b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
similarity index 100%
rename from platform/generic/thead/thead-trap-handler.S
rename to platform/generic/thead/thead_c9xx_tlb_trap_handler.S
-- 
2.42.0



From inochiama at outlook.com  Wed Oct  4 23:58:43 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu,  5 Oct 2023 14:58:43 +0800
Subject: [PATCH v2 4/4] platform: generic: thead: initialize PMU by default in thead generic platform
In-Reply-To: <20231005065843.239501-1-inochiama@outlook.com>
References: <IA1PR20MB4953287B7688E0F5058984BDBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231005065843.239501-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB49536C4C0A19D97FA8E288CBBBCAA@IA1PR20MB4953.namprd20.prod.outlook.com>

Since all the SoC with thead c9xx cores need this initialization at now,
initialize the c9xx pmu in the thead generic platform by default.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig               |  1 +
 platform/generic/thead/thead-generic.c | 13 +++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 3be75cf..f9e7ed2 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -56,6 +56,7 @@ config PLATFORM_STARFIVE_JH7110
 config PLATFORM_THEAD
 	bool "THEAD C9xx support"
 	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
diff --git a/platform/generic/thead/thead-generic.c b/platform/generic/thead/thead-generic.c
index c77140c..72f4aaa 100644
--- a/platform/generic/thead/thead-generic.c
+++ b/platform/generic/thead/thead-generic.c
@@ -8,6 +8,7 @@
 
 #include <platform_override.h>
 #include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
 #include <sbi/sbi_const.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
@@ -29,6 +30,13 @@ static int thead_generic_early_init(bool cold_boot,
 	return 0;
 }
 
+static int thead_generic_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
 static struct thead_generic_quirks thead_th1520_quirks = {
 	.errata = THEAD_QUIRK_ERRATA_TLB_FLUSH,
 };
@@ -39,6 +47,7 @@ static const struct fdt_match thead_generic_match[] = {
 };
 
 const struct platform_override thead_generic = {
-	.match_table	= thead_generic_match,
-	.early_init	= thead_generic_early_init,
+	.match_table		= thead_generic_match,
+	.early_init		= thead_generic_early_init,
+	.extensions_init	= thead_generic_extensions_init,
 };
-- 
2.42.0



From anup at brainfault.org  Thu Oct  5 21:14:27 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 09:44:27 +0530
Subject: [PATCH 1/3] firmware: Remove ALIGN in .rela.dyn in linker script
In-Reply-To: <TYYP286MB143994BAD3D130B072AB4105C6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
References: <TYYP286MB1439495D0B19A0ECFD89BDABC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
 <TYYP286MB143994BAD3D130B072AB4105C6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy1F0dNjXJS9JA+kZmYhREKkhW7YA0Wfd4NAF3C4zU=5ng@mail.gmail.com>

On Sun, Sep 17, 2023 at 11:23?PM Vivian Wang <dramforever at live.com> wrote:
>
> The .rela.dyn section should be exactly the size of the relocations,
> without padding. On RV64, .rela* sections are already aligned and
> there's no need for padding. On RV32, this adds padding up to 4 bytes,
> which, if present, confuses the relocation loop into processing an extra
> entry past the end of .rela*, and it crashes with an invalid memory
> access.
>
> Fixes: 0f20e8adcf42 ("firmware: Support position independent execution")
> Signed-off-by: Vivian Wang <dramforever at live.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Thanks,
Anup

> ---
>  firmware/fw_base.ldS | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 3d68484..88b8dfd 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -49,7 +49,6 @@
>         .rela.dyn : {
>                 PROVIDE(__rel_dyn_start = .);
>                 *(.rela*)
> -               . = ALIGN(8);
>                 PROVIDE(__rel_dyn_end = .);
>         }
>
> --
> 2.41.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Oct  5 21:14:44 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 09:44:44 +0530
Subject: [PATCH 2/3] firmware: Remove handling of R_RISCV_{32,64}
In-Reply-To: <TYYP286MB14392A606EEDABFB7734CB88C6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
References: <TYYP286MB1439495D0B19A0ECFD89BDABC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
 <TYYP286MB14392A606EEDABFB7734CB88C6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy3Dmu7+DYZg8DcT9Y2QH-cRhYcfV4uLcvSDqeVBgsun=A@mail.gmail.com>

On Sun, Sep 17, 2023 at 11:23?PM Vivian Wang <dramforever at live.com> wrote:
>
> Since everything is statically linked, we won't actually have
> R_RISCV_{32,64} relocations. No need to handle these.
>
> Fixes: 0f20e8adcf42 ("firmware: Support position independent execution")
> Signed-off-by: Vivian Wang <dramforever at live.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Thanks,
Anup

> ---
>  firmware/fw_base.S      | 22 ----------------------
>  firmware/fw_base.ldS    |  6 ------
>  include/sbi/riscv_elf.h |  8 --------
>  3 files changed, 36 deletions(-)
>
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index ca34b4c..42b03fe 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -88,30 +88,8 @@ _try_lottery:
>         add     t5, t5, t2
>         add     t3, t3, t2
>         REG_S   t5, 0(t3)               /* store runtime address to the GOT entry */
> -       j       5f
>
>  3:
> -       lla     t4, __dyn_sym_start
> -
> -4:
> -       srli    t6, t5, SYM_INDEX       /* t6 <--- sym table index */
> -       andi    t5, t5, 0xFF            /* t5 <--- relocation type */
> -       li      t3, RELOC_TYPE
> -       bne     t5, t3, 5f
> -
> -       /* address R_RISCV_64 or R_RISCV_32 cases*/
> -       REG_L   t3, 0(t0)
> -       li      t5, SYM_SIZE
> -       mul     t6, t6, t5
> -       add     s5, t4, t6
> -       REG_L   t6, (REGBYTES * 2)(t0)  /* t0 <-- addend */
> -       REG_L   t5, REGBYTES(s5)
> -       add     t5, t5, t6
> -       add     t5, t5, t2              /* t5 <-- location to fix up in RAM */
> -       add     t3, t3, t2              /* t3 <-- location to fix up in RAM */
> -       REG_S   t5, 0(t3)               /* store runtime address to the variable */
> -
> -5:
>         addi    t0, t0, (REGBYTES * 3)
>         blt     t0, t1, 2b
>         j       _relocate_done
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 88b8dfd..c15ccdb 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -40,12 +40,6 @@
>
>         . = ALIGN(0x1000); /* Ensure next section is page aligned */
>
> -       .dynsym : {
> -               PROVIDE(__dyn_sym_start = .);
> -               *(.dynsym)
> -               PROVIDE(__dyn_sym_end = .);
> -       }
> -
>         .rela.dyn : {
>                 PROVIDE(__rel_dyn_start = .);
>                 *(.rela*)
> diff --git a/include/sbi/riscv_elf.h b/include/sbi/riscv_elf.h
> index 3b62c38..ed361e3 100644
> --- a/include/sbi/riscv_elf.h
> +++ b/include/sbi/riscv_elf.h
> @@ -1,14 +1,6 @@
>  #ifndef __RISCV_ELF_H__
>  #define __RISCV_ELF_H__
>
> -#include <sbi/riscv_asm.h>
> -
> -#define R_RISCV_32             1
> -#define R_RISCV_64             2
>  #define R_RISCV_RELATIVE       3
>
> -#define RELOC_TYPE             __REG_SEL(R_RISCV_64, R_RISCV_32)
> -#define SYM_INDEX              __REG_SEL(0x20, 0x8)
> -#define SYM_SIZE               __REG_SEL(0x18,0x10)
> -
>  #endif
> --
> 2.41.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Oct  5 21:14:59 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 09:44:59 +0530
Subject: [PATCH 3/3] Makefile: Add --exclude-libs ALL to avoid .dynsym
In-Reply-To: <TYYP286MB1439270F179A98FEE6178EDEC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
References: <TYYP286MB1439495D0B19A0ECFD89BDABC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
 <TYYP286MB1439270F179A98FEE6178EDEC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy05ccHLrv4iwq_p6BkHn+wkbwRbRNhmb02p+NxvazFkTA@mail.gmail.com>

On Sun, Sep 17, 2023 at 11:23?PM Vivian Wang <dramforever at live.com> wrote:
>
> Since everything is statically linked, we don't need to expose symbols
> for dynamic linking.
>
> For a default build this saves about 2 KiB of useless read only data in
> .dynsym, .dynstr, .hash, .gnu.hash sections.
>
> Signed-off-by: Vivian Wang <dramforever at live.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Thanks,
Anup

> ---
>  Makefile | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Makefile b/Makefile
> index ca70949..de4e73a 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -375,6 +375,7 @@ ASFLAGS             +=      $(firmware-asflags-y)
>  ARFLAGS                =       rcs
>
>  ELFFLAGS       +=      $(USE_LD_FLAG)
> +ELFFLAGS       +=      -Wl,--exclude-libs,ALL
>  ELFFLAGS       +=      -Wl,--build-id=none
>  ELFFLAGS       +=      $(platform-ldflags-y)
>  ELFFLAGS       +=      $(firmware-ldflags-y)
> --
> 2.41.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Oct  5 21:18:48 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 09:48:48 +0530
Subject: [PATCH 0/3] Relocation-related fixes
In-Reply-To: <TYYP286MB1439495D0B19A0ECFD89BDABC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
References: <TYYP286MB1439495D0B19A0ECFD89BDABC6F4A@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy0zezBg40dXY-S7FdtwZpRuZ4ukTKdmpGAaS-Y+OK=_gw@mail.gmail.com>

On Sun, Sep 17, 2023 at 11:22?PM Vivian Wang <dramforever at live.com> wrote:
>
> I was looking into various implementations of "DIY" runtime relocations.
> One thing led to another, and here are three patches.
>
> This area does seem fairly obscure, so advice on proper/better ways to
> do things are definitely needed. Thanks in advance for any help.
>
> Patch 1 fixes a crash on RV32 that happens to 50% of built binaries
> essentially randomly.
>
> Patch 2 removes handling of R_RISCV_{32,64}. Why they have been added in
> the first place is a complete mystery to me, since these are for dynamic
> linking only, which is simply not a thing here. I've also never seen a
> toolchain generate these for *static*-pie. And yes the generated binary
> boots fine.
>
> From what I can tell, Linux, musl, glibc all only handle
> R_RISCV_RELATIVE for static-pie. (Okay, also IRELATIVE, but just don't
> use ifuncs.) The only other place I can find that does anything with
> .dynsym is U-Boot's RISC-V relocation code [1], and the code is there
> without explanation either.
>
> Maybe some ancient toolchains generated R_RISCV_{32,64} for static
> linking? I have no idea.
>
> Since we don't need .dynsym, I went ahead and did patch 3. I tried
> fiddling around with -fvisibility= but it seems that, given that OpenSBI
> is built as a static library, --exclude-libs ALL looked liked the
> simplest solution. Or should we just /DISCARD/ .dynsym etc. instead?
>
> Cc'd Vincent Chen - Since you're the author of 0f20e8adcf42 "firmware:
> Support position independent execution" I'm hope you can give some
> insight. Thanks in advance.
>
> [1]: https://github.com/u-boot/u-boot/commit/e8e39597a33cc53aacbaf4ef5cae60ed86d6a20a
>
> Vivian Wang (3):
>   firmware: Remove ALIGN in .rela.dyn in linker script
>   firmware: Remove handling of R_RISCV_{32,64}
>   Makefile: Add --exclude-libs ALL to avoid .dynsym

I quickly tried this series with both GCC 12.2.0 and CLANG 14.0.0
on the RV64 virt machine and RV32 virt machine. It worked fine
at my end.

Applied this series to the riscv/opensbi repo.

Thanks,
Anup

>
>  Makefile                |  1 +
>  firmware/fw_base.S      | 22 ----------------------
>  firmware/fw_base.ldS    |  7 -------
>  include/sbi/riscv_elf.h |  8 --------
>  4 files changed, 1 insertion(+), 37 deletions(-)
>
> --
> 2.41.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Oct  5 21:35:30 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 10:05:30 +0530
Subject: [PATCH 0/3] Sparse HART id improvements
In-Reply-To: <20230924155745.1753120-1-wxjstz@126.com>
References: <20230924155745.1753120-1-wxjstz@126.com>
Message-ID: <CAAhSdy2iZruS48CqB9UDiaqL57KD7zX+DxsC-M8ArmxX8soWzg@mail.gmail.com>

On Sun, Sep 24, 2023 at 9:28?PM Xiang W <wxjstz at 126.com> wrote:
>
> Modify last_hartindex_having_scratch/hartindex_to_hartid_table
> /hartindex_to_scratch_table as static variables to prevent accidental
> modification and reduce memory consumption
>
> Xiang W (3):
>   lib: sbi: Refactor sbi_scratch_last_hartindex as a function
>   lib: sbi: Refactor sbi_hartindex_to_hartid as a function
>   lib: sbi: Refactor sbi_hartindex_to_scratch as a function

All these are in hot-path at various places so introducing a
function is certainly not helping.

Also, if some buggy code is accidentally modifying global data
then that buggy code should be fixed rather than papering over
the problem by introducing these functions.

Regards,
Anup

>
>  include/sbi/sbi_scratch.h | 35 ++++++++++++-----------------------
>  lib/sbi/sbi_scratch.c     | 30 ++++++++++++++++++++++++++----
>  2 files changed, 38 insertions(+), 27 deletions(-)
>
> --
> 2.40.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Oct  5 21:38:53 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 10:08:53 +0530
Subject: [PATCH] doc: Fix fw_payload.md
In-Reply-To: <20230924214823.2789366-1-hn@hnpl.org>
References: <20230924214823.2789366-1-hn@hnpl.org>
Message-ID: <CAAhSdy0ZaV7vDn-EA+7d+eRO8nhRteFe=UA-P+rUbQsYZ2KjPA@mail.gmail.com>

On Mon, Sep 25, 2023 at 3:19?AM Hoa Nguyen <hn at hnpl.org> wrote:
>
> The base of .text is defined by `FW_TEXT_START`, not `FW_TEXT_BASE`.
>
> Signed-off-by: Hoa Nguyen <hn at hnpl.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/firmware/fw_payload.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/firmware/fw_payload.md b/docs/firmware/fw_payload.md
> index 3d50ddc..113604a 100644
> --- a/docs/firmware/fw_payload.md
> +++ b/docs/firmware/fw_payload.md
> @@ -36,7 +36,7 @@ options. These configuration parameters can be defined using either the top
>  level `make` command line or the target platform *objects.mk* configuration
>  file. The parameters currently defined are as follows:
>
> -* **FW_PAYLOAD_OFFSET** - Offset from *FW_TEXT_BASE* where the payload binary
> +* **FW_PAYLOAD_OFFSET** - Offset from *FW_TEXT_START* where the payload binary
>    will be linked in the final *FW_PAYLOAD* firmware binary image. This
>    configuration parameter is mandatory if *FW_PAYLOAD_ALIGN* is not defined.
>    Compilation errors will result from an incorrect definition of
> --
> 2.25.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Oct  6 04:29:07 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 16:59:07 +0530
Subject: [PATCH] lib: utils/serial: Ensure proper allocation of PMP
 entries for uart8250
In-Reply-To: <20230925122426.1667314-1-peterlin@andestech.com>
References: <20230925122426.1667314-1-peterlin@andestech.com>
Message-ID: <CAAhSdy3LQckFHYw=LPArg4FJ+5=na4GDsfx2R8tNJS=dqpGU-w@mail.gmail.com>

On Mon, Sep 25, 2023 at 5:56?PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> The added memory region should start from the base address.
> Otherwise, the range will be shifted by reg_offset and not
> able to merge consecutive NAPOT regions in the root domain,
> resulting in wasted PMP entries.
>
> Fixes: e8bc1621 ("lib: utils/serial: Add shared regions for
> serial drivers")
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/serial/uart8250.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/lib/utils/serial/uart8250.c b/lib/utils/serial/uart8250.c
> index 4d158d3..1fe053f 100644
> --- a/lib/utils/serial/uart8250.c
> +++ b/lib/utils/serial/uart8250.c
> @@ -135,8 +135,7 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
>
>         sbi_console_set_device(&uart8250_console);
>
> -       return sbi_domain_root_add_memrange(base + reg_offset, PAGE_SIZE,
> -                                           PAGE_SIZE,
> +       return sbi_domain_root_add_memrange(base, PAGE_SIZE, PAGE_SIZE,
>                                             (SBI_DOMAIN_MEMREGION_MMIO |
>                                             SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
>  }
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Oct  6 04:29:29 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 16:59:29 +0530
Subject: [PATCH] lib: utils: timer/ipi: Update memregion flags for PLMT
 and PLICSW
In-Reply-To: <20230927100831.1119170-1-peterlin@andestech.com>
References: <20230927100831.1119170-1-peterlin@andestech.com>
Message-ID: <CAAhSdy0heLNZhdQGX8EWErprwnMJZxzPjUTpy+Z9r1fFbKfXcA@mail.gmail.com>

On Wed, Sep 27, 2023 at 3:39?PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> This patch adds unspecified permission flags for the PLICSW region
> and updates the permission of the PLMT region.
>
> With this update, both regions will become M-mode only read/write
> regions in the root domain.
>
>   Domain0 Region00: 0x00000000f0300000-0x00000000f0300fff M: (I,R,W) S/U: (R,W)
>   Domain0 Region01: 0x0000000000040000-0x000000000005ffff M: (R,W) S/U: ()
>   Domain0 Region02: 0x0000000000000000-0x000000000003ffff M: (R,X) S/U: ()
> > Domain0 Region03: 0x00000000e6000000-0x00000000e60fffff M: (I,R,W) S/U: ()
> > Domain0 Region04: 0x00000000e6400000-0x00000000e67fffff M: (I,R,W) S/U: ()
>   Domain0 Region05: 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
>
> The PMP rules of AE350-AX65 (single-core) w/ Smepmp:
>
>   p/x $pmpcfg0
>   $1 = {0x1f9b9b9d9b1e00,
>   pmp0cfg = {0x0},
>                     L--AAXWR
>   pmp1cfg = {0x1e} (00011110), pmpaddr1: 0xf0300000 ~   0xf0300fff  (UART1)
>   pmp2cfg = {0x9b} (10011011), pmpaddr2:    0x40000 ~      0x5ffff
>   pmp3cfg = {0x9d} (10011101), pmpaddr3:        0x0 ~      0x3ffff
>   pmp4cfg = {0x9b} (10011011), pmpaddr4: 0xe6000000 ~   0xe60fffff  (PLMT)
>   pmp5cfg = {0x9b} (10011011), pmpaddr5: 0xe6400000 ~   0xe67fffff  (PLICSW)
>   pmp6cfg = {0x1f} (00011111), pmpaddr6:        0x0 ~ 0xffffffffff
>   pmp7cfg = {0x0 }}
>
> The PMP rules of AE350-AX45MP (qual-core) w/o Smepmp:
>
>   p/x $pmpcfg0
>   $1 = {0x1f181818181b,
>                      L--AAXWR
>   pmp0cfg = {0x1b}, (00011011), pmpaddr0: 0xf0300000 ~  0xf0300fff  (UART1)
>   pmp1cfg = {0x18}, (00011000), pmpaddr1:    0x40000 ~     0x5ffff
>   pmp2cfg = {0x18}, (00011000), pmpaddr2:        0x0 ~     0x3ffff
>   pmp3cfg = {0x18}, (00011000), pmpaddr3: 0xe6000000 ~  0xe60fffff  (PLMT)
>   pmp4cfg = {0x18}, (00011000), pmpaddr4: 0xe6400000 ~  0xe67fffff  (PLICSW)
>   pmp5cfg = {0x1f}, (00011111), pmpaddr5:        0x0 ~ 0x1ffffffff
>   pmp6cfg = {0x0 }}
>
> Note that starting from this patch, we restrict the S/U-mode read
> permission to the PLMT region, since we should read the TIME CSR
> in a lower privilege mode.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> This patch is based on the fix [1] to UART8250
>
> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20230925122426.1667314-1-peterlin at andestech.com/
> ---
>  lib/utils/ipi/andes_plicsw.c | 4 +++-
>  lib/utils/timer/andes_plmt.c | 7 +++++--
>  2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/lib/utils/ipi/andes_plicsw.c b/lib/utils/ipi/andes_plicsw.c
> index dde39c0..5693efb 100644
> --- a/lib/utils/ipi/andes_plicsw.c
> +++ b/lib/utils/ipi/andes_plicsw.c
> @@ -131,7 +131,9 @@ int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
>         /* Add PLICSW region to the root domain */
>         rc = sbi_domain_root_add_memrange(plicsw->addr, plicsw->size,
>                                           PLICSW_REGION_ALIGN,
> -                                         SBI_DOMAIN_MEMREGION_MMIO);
> +                                         SBI_DOMAIN_MEMREGION_MMIO |
> +                                         SBI_DOMAIN_MEMREGION_M_READABLE |
> +                                         SBI_DOMAIN_MEMREGION_M_WRITABLE);
>         if (rc)
>                 return rc;
>
> diff --git a/lib/utils/timer/andes_plmt.c b/lib/utils/timer/andes_plmt.c
> index 94a86cc..6e4bfaf 100644
> --- a/lib/utils/timer/andes_plmt.c
> +++ b/lib/utils/timer/andes_plmt.c
> @@ -81,8 +81,11 @@ int plmt_cold_timer_init(struct plmt_data *plmt)
>
>         /* Add PLMT region to the root domain */
>         rc = sbi_domain_root_add_memrange(
> -               (unsigned long)plmt->time_val, plmt->size, PLMT_REGION_ALIGN,
> -               SBI_DOMAIN_MEMREGION_MMIO | SBI_DOMAIN_MEMREGION_READABLE);
> +               (unsigned long)plmt->time_val, plmt->size,
> +               PLMT_REGION_ALIGN,
> +               SBI_DOMAIN_MEMREGION_MMIO |
> +               SBI_DOMAIN_MEMREGION_M_READABLE |
> +               SBI_DOMAIN_MEMREGION_M_WRITABLE);
>         if (rc)
>                 return rc;
>
> --
> 2.34.1
>


From anup at brainfault.org  Fri Oct  6 04:36:01 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:06:01 +0530
Subject: [PATCH 1/1] lib: sbi: fix sbi_domain_get_assigned_hartmask()
In-Reply-To: <20230927141451.51052-1-heinrich.schuchardt@canonical.com>
References: <20230927141451.51052-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy1O7XVowJ6KmAXCxqqq9sXpq6rO1U_1xCv09st+s=1vUw@mail.gmail.com>

On Wed, Sep 27, 2023 at 7:45?PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> '1' is a 32 bit integer. When shifting it by more than 31 bits it becomes
> zero and we get an incorrect return value.
>
> Addresses-Coverity-ID: 1568356 Bad bit shift operation
> Fixes: 296e70d69da7 ("lib: sbi: Extend sbi_hartmask to support both hartid and hartindex")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_domain.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index b1f485d..fd4a296 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -76,7 +76,7 @@ ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
>         ulong ret = 0;
>         for (int i = 0; i < 8 * sizeof(ret); i++) {
>                 if (sbi_domain_is_assigned_hart(dom, hbase + i))
> -                       ret |= 1 << i;
> +                       ret |= 1UL << i;
>         }
>
>         return ret;
> --
> 2.40.1
>


From anup at brainfault.org  Fri Oct  6 04:43:25 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:13:25 +0530
Subject: [PATCH 1/1] lib: utils/fdt: simplify dt_parse_isa_extensions
In-Reply-To: <20230927141912.51591-1-heinrich.schuchardt@canonical.com>
References: <20230927141912.51591-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy2VCbXpmCZHPoN=a-O2yPV+ZB4aaN1VF1sBGdaFCeKNyg@mail.gmail.com>

On Wed, Sep 27, 2023 at 7:49?PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> hart_exts == NULL can only occur if offset and node address lead to an
> overflow resulting in exactly NULL. As we don't catch other values of
> overflow it does not make sense to treat this one as special.
>
> Addresses-Coverity-ID: 1568355 Logically dead code
> Addresses-Coverity-ID: 1568358 Logically dead code
> Fixes: 6259b2ec2d09 ("lib: utils/fdt: Fix fdt_parse_isa_extensions() implementation")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/fdt/fdt_helper.c | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index c97f09d..13e79b9 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -417,8 +417,6 @@ static int fdt_parse_isa_all_harts(void *fdt)
>
>                 hart_exts = sbi_scratch_offset_ptr(scratch,
>                                                    fdt_isa_bitmap_offset);
> -               if (!hart_exts)
> -                       return SBI_ENOENT;
>
>                 err = fdt_parse_isa_one_hart((const char *)val, hart_exts);
>                 if (err)
> @@ -452,8 +450,6 @@ int fdt_parse_isa_extensions(void *fdt, unsigned int hartid,
>                 return SBI_ENOENT;
>
>         hart_exts = sbi_scratch_offset_ptr(scratch, fdt_isa_bitmap_offset);
> -       if (!hart_exts)
> -               return SBI_ENOENT;
>
>         for (i = 0; i < BITS_TO_LONGS(SBI_HART_EXT_MAX); i++)
>                 extensions[i] |= hart_exts[i];
> --
> 2.40.1
>


From anup at brainfault.org  Fri Oct  6 05:02:21 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:32:21 +0530
Subject: [PATCH v2 1/1] lib: utils: Simplify SET_ISA_EXT_MAP()
In-Reply-To: <20230928121720.41669-1-heinrich.schuchardt@canonical.com>
References: <20230928121720.41669-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy2-PLPTtNr06MP6_wj0yJQ6VmwPEHEjUAbUexT1bwK45Q@mail.gmail.com>

On Thu, Sep 28, 2023 at 5:47?PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> The define is hard to read. The continue statement does not do what was
> intended.
>
> * Remove do {} while (false);
> * Change the name to set_multi_letter_ext
>   - Other local macros are lower case too.
>   - Refer to the fact that this is only used for multi-letter extensions.
>
> Addresses-Coverity-ID: 1568359 Unexpected control flow
> Fixes: d72f5f17478d ("lib: utils: Add detection of Smepmp from ISA string in FDT")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> v2:
>         keep continue statement
>         rename macro
> ---
>  lib/utils/fdt/fdt_helper.c | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index c97f09d..b97ff74 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -369,16 +369,15 @@ static int fdt_parse_isa_one_hart(const char *isa, unsigned long *extensions)
>                 if (!j)
>                         continue;
>
> -#define SET_ISA_EXT_MAP(name, bit)                             \
> -               do {                                            \
> -                       if (!strcmp(mstr, name)) {              \
> +#define set_multi_letter_ext(name, bit)                                \
> +               {                                               \
> +                       if (!strcmp(mstr, name))                \
>                                 __set_bit(bit, extensions);     \
>                                 continue;                       \
> -                       }                                       \

The braces around "if ()" are still required otherwise it fails to compile.

I have taken care of this at the time of merging this patch.

> -               } while (false)                                 \
> +               }                                               \
>
> -               SET_ISA_EXT_MAP("smepmp", SBI_HART_EXT_SMEPMP);
> -#undef SET_ISA_EXT_MAP
> +               set_multi_letter_ext("smepmp", SBI_HART_EXT_SMEPMP);
> +#undef set_multi_letter_ext
>         }
>
>         return 0;
> --
> 2.40.1
>

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From anup at brainfault.org  Fri Oct  6 05:02:45 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:32:45 +0530
Subject: [PATCH v2] lib: sbi_pmu: check for index overflows
In-Reply-To: <20230928130357.46224-1-heinrich.schuchardt@canonical.com>
References: <20230928130357.46224-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy1DbjcOdrHeLyHig0fCZud6-a_U0WAe32-2QMBz1iZcHg@mail.gmail.com>

On Thu, Sep 28, 2023 at 6:34?PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> sbi_pmu_ctr_cfg_match() receives data from a lower privilege level mode.
> We must catch maliciously wrong values.
>
> We already check against total_ctrs. But we do not check that total_ctrs is
> less than SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX.
>
> Check that the number of hardware counters is in the valid range.
>
> Addresses-Coverity-ID: 1566114 Out-of-bounds write
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> v2:
>         check num_hw_ctrs
> ---
>  lib/sbi/sbi_pmu.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index 9694aae..f4c8fc4 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -981,6 +981,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
>                 else
>                         num_hw_ctrs = hpm_count + 1;
>
> +               if (num_hw_ctrs > SBI_PMU_HW_CTR_MAX)
> +                       return SBI_EINVAL;
> +
>                 total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX;
>         }
>
> --
> 2.40.1
>


From anup at brainfault.org  Fri Oct  6 05:04:13 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:34:13 +0530
Subject: [PATCH 1/1] gpio/starfive: redundant readl() call
In-Reply-To: <20230929215355.18985-1-heinrich.schuchardt@canonical.com>
References: <20230929215355.18985-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy0WczXTJiFNLXuyr1bksJx-Q3rgdCm=0EYAOgvko53-=Q@mail.gmail.com>

On Sat, Sep 30, 2023 at 3:24?AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> In starfive_gpio_direction_output() readl() is called twice to read the
> gpio direction register. The result of the first read is discarded.
>
> Remove the redundant read.
>
> Fixes: 908be1b85c8f ("gpio/starfive: add gpio driver and support gpio reset")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/gpio/fdt_gpio_starfive.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/lib/utils/gpio/fdt_gpio_starfive.c b/lib/utils/gpio/fdt_gpio_starfive.c
> index f430b13..bd2a9f2 100644
> --- a/lib/utils/gpio/fdt_gpio_starfive.c
> +++ b/lib/utils/gpio/fdt_gpio_starfive.c
> @@ -37,7 +37,6 @@ static int starfive_gpio_direction_output(struct gpio_pin *gp, int value)
>         reg_addr = chip->addr + gp->offset;
>         reg_addr &= ~(STARFIVE_GPIO_REG_SHIFT_MASK);
>
> -       val = readl((void *)(reg_addr));
>         shift_bits = (gp->offset & STARFIVE_GPIO_REG_SHIFT_MASK)
>                 << STARFIVE_GPIO_SHIFT_BITS;
>         bit_mask = STARFIVE_GPIO_MASK << shift_bits;
> --
> 2.40.1
>


From anup at brainfault.org  Fri Oct  6 05:17:16 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:47:16 +0530
Subject: [PATCH 0/6] Add Andes PMU extension support
In-Reply-To: <20230906094051.3957564-1-peterlin@andestech.com>
References: <20230906094051.3957564-1-peterlin@andestech.com>
Message-ID: <CAAhSdy1iUKOKkp3Z8ybL8ubcF7Y+YZEyMN232HYogE4ToTH+hw@mail.gmail.com>

Hi Yu Chien Peter Lin,

On Wed, Sep 6, 2023 at 3:12?PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> This patch series enables perf tool to utilize Andes PMU
> extension via PMU SBI calls, provides PMU device callbacks
> for event sampling and mode filtering.
>
> We also provide a PMU node example of AX45MP in the last
> patch.
>
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support
> - https://github.com/andestech/linux/commits/andes-pmu-support
>
> Yu Chien Peter Lin (6):
>   sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
>   platform: include: andes45: Add PMU related CSR defines
>   platform: andes: Add Andes custom PMU support
>   platform: andes: Enable Andes PMU for AE350
>   platform: rzfive: Enable Andes PMU for RZ/Five
>   docs: pmu: Add Andes PMU node example

I assume there is going to be a v2 due to comments on PATCH3 ?

Regards,
Anup

>
>  docs/pmu_support.md                        | 87 ++++++++++++++++++++++
>  include/sbi/sbi_pmu.h                      |  6 ++
>  lib/sbi/sbi_pmu.c                          |  5 +-
>  platform/generic/Kconfig                   |  2 +
>  platform/generic/andes/Kconfig             |  4 +
>  platform/generic/andes/ae350.c             |  2 +
>  platform/generic/andes/andes_pmu.c         | 85 +++++++++++++++++++++
>  platform/generic/andes/objects.mk          |  1 +
>  platform/generic/include/andes/andes45.h   | 26 +++++++
>  platform/generic/include/andes/andes_pmu.h | 12 +++
>  platform/generic/renesas/rzfive/rzfive.c   |  2 +
>  11 files changed, 231 insertions(+), 1 deletion(-)
>  create mode 100644 platform/generic/andes/andes_pmu.c
>  create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> --
> 2.34.1
>


From prabhakar.csengg at gmail.com  Fri Oct  6 05:20:27 2023
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Fri, 6 Oct 2023 13:20:27 +0100
Subject: [PATCH 0/6] Add Andes PMU extension support
In-Reply-To: <20230906111455.4161641-1-peterlin@andestech.com>
References: <20230906111455.4161641-1-peterlin@andestech.com>
Message-ID: <CA+V-a8uDWwyf51ZTyi3_wGu8_9JNqudDTAQ2pS95oBa+VcYYdg@mail.gmail.com>

Hi Lin-san,

On Wed, Sep 6, 2023 at 12:17?PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> This patch series enables perf tool to utilize Andes PMU
> extension via PMU SBI calls, provides PMU device callbacks
> for event sampling and mode filtering.
>
> We also provide a PMU node example of AX45MP in the last
> patch.
>
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support
> - https://github.com/andestech/linux/commits/andes-pmu-support
>
> Yu Chien Peter Lin (6):
>   sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
>   platform: include: andes45: Add PMU related CSR defines
>   platform: andes: Add Andes custom PMU support
>   platform: andes: Enable Andes PMU for AE350
>   platform: rzfive: Enable Andes PMU for RZ/Five
>   docs: pmu: Add Andes PMU node example
>
>  docs/pmu_support.md                        | 87 ++++++++++++++++++++++
>  include/sbi/sbi_pmu.h                      |  6 ++
>  lib/sbi/sbi_pmu.c                          |  5 +-
>  platform/generic/Kconfig                   |  2 +
>  platform/generic/andes/Kconfig             |  4 +
>  platform/generic/andes/ae350.c             |  2 +
>  platform/generic/andes/andes_pmu.c         | 85 +++++++++++++++++++++
>  platform/generic/andes/objects.mk          |  1 +
>  platform/generic/include/andes/andes45.h   | 26 +++++++
>  platform/generic/include/andes/andes_pmu.h | 12 +++
>  platform/generic/renesas/rzfive/rzfive.c   |  2 +
>  11 files changed, 231 insertions(+), 1 deletion(-)
>  create mode 100644 platform/generic/andes/andes_pmu.c
>  create mode 100644 platform/generic/include/andes/andes_pmu.h
>
I tried these patches on the RZ/Five SMARC EVK and I am seeing kernel
freeze when trying to quit perf.

Cheers,
Prabhakar


From anup at brainfault.org  Fri Oct  6 05:21:44 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:51:44 +0530
Subject: [PATCH 4/4] lib: sbi: detect extensions from menvcfg
In-Reply-To: <CAMWQL2jdMwV=g5PNz26kk=w9dPHQQR-X5U_cOp+0JmHqEcb7xQ@mail.gmail.com>
References: <20230907092729.11200-1-yongxuan.wang@sifive.com>
 <20230907092729.11200-5-yongxuan.wang@sifive.com> <CAAhSdy2afU0UuO6H52Z9wryehPMk7rifP=dpQdOm9p88K05pvw@mail.gmail.com>
 <CAMWQL2jdMwV=g5PNz26kk=w9dPHQQR-X5U_cOp+0JmHqEcb7xQ@mail.gmail.com>
Message-ID: <CAAhSdy0DYx=uKK7KmSSGV5t4_WzgwvMA3tvUo-Ta--Hh8o1PuQ@mail.gmail.com>

On Wed, Sep 27, 2023 at 4:07?PM Yong-Xuan Wang <yongxuan.wang at sifive.com> wrote:
>
> Hi Anup,
>
>
> On Fri, Sep 22, 2023 at 4:59?PM Anup Patel <anup at brainfault.org> wrote:
> >
> > On Thu, Sep 7, 2023 at 2:57?PM Yong-Xuan Wang <yongxuan.wang at sifive.com> wrote:
> > >
> > > Currently "Boot HART ISA Extensions" only shows extensions which can be
> > > detected by test and set their CSRs. We can expand this functionality to
> > > detect additional extensions from menvcfg that do not introduce new CSRs
> > > but are controlled through menvcfg settings.
> >
> > To detect extensions this way, we have to write the CSR and some of the
> > CSR fields can have side effects. For example, the MML bit is a sticky bit
> > and enables ePMP mode.
> >
> > Instead, I suggest detecting extensions from the ISA string provided in the
> > DT. We have already done this for Smepmp extension so it should be easy
> > to extend.
>
> Thank you! I will update it in patch v2.
>
> And at present, OpenSBI employs two mechanisms for extension detection:
> one is parsing ISA string in fdt_parse_isa_extensions(), the other one
> is by testing CSRs in hart_detect_features(). Maybe we can delete the
> CSR testing method and only detect extensions from DT?

Instead of totally abandoning the CSR testing mechanism, I suggest keep
it but for future extensions prefer ISA string parsing (i.e. discover extensions
from DT passed by previous booting stage).

Regards,
Anup

>
> Regards,
> Yong-Xuan
>
>
> >
> > Regards,
> > Anup
> >
> > >
> > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
> > > ---
> > >  include/sbi/sbi_hart.h |  8 +++++++
> > >  lib/sbi/sbi_hart.c     | 49 ++++++++++++++++++++++++++++++++++++++++++
> > >  2 files changed, 57 insertions(+)
> > >
> > > diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> > > index e60f415..a0e5f58 100644
> > > --- a/include/sbi/sbi_hart.h
> > > +++ b/include/sbi/sbi_hart.h
> > > @@ -42,6 +42,14 @@ enum sbi_hart_extensions {
> > >         SBI_HART_EXT_ZIHPM,
> > >         /** Hart has Smcntrpmf extension */
> > >         SBI_HART_EXT_SMCNTRPMF,
> > > +       /** Hart has Smcntrpmf extension */
> > > +       SBI_HART_EXT_ZICBOZ,
> > > +       /** Hart has Smcntrpmf extension */
> > > +       SBI_HART_EXT_ZICBOM,
> > > +       /** Hart has Smcntrpmf extension */
> > > +       SBI_HART_EXT_SVPBMT,
> > > +       /** Hart has Svadu extension */
> > > +       SBI_HART_EXT_SVADU,
> > >
> > >         /** Maximum index of Hart extension */
> > >         SBI_HART_EXT_MAX,
> > > diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> > > index b7ca0e6..9a0572e 100644
> > > --- a/lib/sbi/sbi_hart.c
> > > +++ b/lib/sbi/sbi_hart.c
> > > @@ -604,6 +604,18 @@ static inline char *sbi_hart_extension_id2string(int ext)
> > >         case SBI_HART_EXT_SMCNTRPMF:
> > >                 estr = "smcntrpmf";
> > >                 break;
> > > +       case SBI_HART_EXT_ZICBOZ:
> > > +               estr = "zicboz";
> > > +               break;
> > > +       case SBI_HART_EXT_ZICBOM:
> > > +               estr = "zicbom";
> > > +               break;
> > > +       case SBI_HART_EXT_SVPBMT:
> > > +               estr = "svpbmt";
> > > +               break;
> > > +       case SBI_HART_EXT_SVADU:
> > > +               estr = "svadu";
> > > +               break;
> > >         default:
> > >                 break;
> > >         }
> > > @@ -875,6 +887,43 @@ __pmp_skip:
> > >                 __sbi_hart_update_extension(hfeatures,
> > >                                         SBI_HART_EXT_ZIHPM, true);
> > >
> > > +       if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) {
> > > +               unsigned long orig_menvcfg_val, menvcfg_val;
> > > +
> > > +               orig_menvcfg_val = csr_read(CSR_MENVCFG);
> > > +               csr_write(CSR_MENVCFG, ~0);
> > > +               menvcfg_val = csr_read(CSR_MENVCFG);
> > > +
> > > +#if __riscv_xlen == 32
> > > +               orig_menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
> > > +               csr_write(CSR_MENVCFGH, ~0);
> > > +               menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
> > > +#endif
> > > +
> > > +#define __check_ext_menvcfg(__bit, __ext)                              \
> > > +               if (menvcfg_val & (__bit))                              \
> > > +                       __sbi_hart_update_extension(hfeatures,          \
> > > +                                                   __ext, true);       \
> > > +
> > > +               /* If the extension is not implemented, the related fields in
> > > +                * menvcfg are read-only zero.
> > > +                */
> > > +               __check_ext_menvcfg(ENVCFG_CBZE, SBI_HART_EXT_ZICBOZ);
> > > +               __check_ext_menvcfg(ENVCFG_CBCFE |
> > > +                                   (ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT),
> > > +                                   SBI_HART_EXT_ZICBOM);
> > > +               __check_ext_menvcfg(ENVCFG_PBMTE, SBI_HART_EXT_SVPBMT);
> > > +               __check_ext_menvcfg(ENVCFG_HADE, SBI_HART_EXT_SVADU);
> > > +
> > > +#undef __check_ext_menvcfg
> > > +
> > > +               csr_write(CSR_MENVCFG, orig_menvcfg_val);
> > > +#if __riscv_xlen == 32
> > > +               csr_write(CSR_MENVCFGH, orig_menvcfg_val >> 32);
> > > +#endif
> > > +
> > > +       }
> > > +
> > >         /* Mark hart feature detection done */
> > >         hfeatures->detected = true;
> > >
> > > --
> > > 2.17.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Oct  6 05:26:38 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 17:56:38 +0530
Subject: [PATCH] docs: platform: update platform_requirements.md
In-Reply-To: <TYWP286MB29878C4D4202EBC98937326BA5C1A@TYWP286MB2987.JPNP286.PROD.OUTLOOK.COM>
References: <TYWP286MB29878C4D4202EBC98937326BA5C1A@TYWP286MB2987.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy0=rfPor_o6ZOUMbVZxgyeVW689OCUm3GWsow9pi3RPAQ@mail.gmail.com>

On Thu, Sep 28, 2023 at 1:55?PM <jay1273062855 at outlook.com> wrote:
>
> From: Yangjie Zhang <jay1273062855 at outlook.com>
>
> "Zicsr" isa extension has been separated from "I" extension.
> This patch add the isa requirement of "Zicsr" extension in
> platform requirements documentation.
>
> Signed-off-by: Yangjie Zhang <jay1273062855 at outlook.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/platform_requirements.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/docs/platform_requirements.md b/docs/platform_requirements.md
> index 8735adb..a843feb 100644
> --- a/docs/platform_requirements.md
> +++ b/docs/platform_requirements.md
> @@ -18,7 +18,7 @@ Base Platform Requirements
>
>  The base RISC-V platform requirements for OpenSBI are as follows:
>
> -1. At least rv32ima or rv64ima required on all HARTs
> +1. At least rv32ima_zicsr or rv64ima_zicsr required on all HARTs
>  2. At least one HART should have S-mode support because:
>
>       * SBI calls are meant for RISC-V S-mode (Supervisor mode)
> @@ -33,7 +33,7 @@ The base RISC-V platform requirements for OpenSBI are as follows:
>  6. Hardware support for injecting M-mode software interrupts on
>     a multi-HART platform
>
> -The RISC-V extensions not covered by rv32ima or rv64ima are optional
> +The RISC-V extensions not covered by rv32ima_zicsr or rv64ima_zicsr are optional
>  for OpenSBI. Although, OpenSBI will detect and handle some of these
>  optional RISC-V extensions at runtime.
>
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Oct  6 05:35:34 2023
From: anup at brainfault.org (Anup Patel)
Date: Fri, 6 Oct 2023 18:05:34 +0530
Subject: [PATCH] lib: sbi: Add support for mconfigptr
In-Reply-To: <TYWP286MB2987DF5FDABB17DF166C2588A5C1A@TYWP286MB2987.JPNP286.PROD.OUTLOOK.COM>
References: <TYWP286MB2987DF5FDABB17DF166C2588A5C1A@TYWP286MB2987.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy3y_AqQFRm60LWVV1EbO73+feRbQCjabWLtyGRnDv68UQ@mail.gmail.com>

On Thu, Sep 28, 2023 at 1:58?PM <jay1273062855 at outlook.com> wrote:
>
> From: Yangjie Zhang <jay1273062855 at outlook.com>
>
> RISC-V privileged specification v1.12 introduced the mconfigptr CSR
> which will hold the physical address of a configuration data
> structure.
>
> Signed-off-by: Yangjie Zhang <jay1273062855 at outlook.com>

Although, we don't use the mconfigptr CSR at the moment but it
does not hurt to have CSR define.

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/riscv_encoding.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index d137bf8..d7a000f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -430,6 +430,7 @@
>  #define CSR_MARCHID                    0xf12
>  #define CSR_MIMPID                     0xf13
>  #define CSR_MHARTID                    0xf14
> +#define CSR_MCONFIGPTR         0xf15
>
>  /* Machine Trap Setup */
>  #define CSR_MSTATUS                    0x300
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From heinrich.schuchardt at canonical.com  Fri Oct  6 13:59:26 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri,  6 Oct 2023 22:59:26 +0200
Subject: [PATCH 1/1] lib: sbi: simplify sanitize_domain()
Message-ID: <20231006205926.26599-1-heinrich.schuchardt@canonical.com>

Since commit 112daa2e647c ("lib: sbi: Maximize the use of HART index in
sbi_domain") the platform parameter is unused.

Fixes: 112daa2e647c ("lib: sbi: Maximize the use of HART index in sbi_domain")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/sbi/sbi_domain.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index fd4a296..4d248d0 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -256,8 +256,7 @@ static const struct sbi_domain_memregion *find_next_subset_region(
 	return ret;
 }
 
-static int sanitize_domain(const struct sbi_platform *plat,
-			   struct sbi_domain *dom)
+static int sanitize_domain(struct sbi_domain *dom)
 {
 	u32 i, j, count;
 	struct sbi_domain_memregion treg, *reg, *reg1;
@@ -494,7 +493,6 @@ int sbi_domain_register(struct sbi_domain *dom,
 	int rc;
 	struct sbi_domain *tdom;
 	u32 cold_hartid = current_hartid();
-	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
 
 	/* Sanity checks */
 	if (!dom || !assign_mask || domain_finalized)
@@ -517,7 +515,7 @@ int sbi_domain_register(struct sbi_domain *dom,
 	}
 
 	/* Sanitize discovered domain */
-	rc = sanitize_domain(plat, dom);
+	rc = sanitize_domain(dom);
 	if (rc) {
 		sbi_printf("%s: sanity checks failed for"
 			   " %s (error %d)\n", __func__,
@@ -564,7 +562,6 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
 	int rc;
 	bool reg_merged;
 	struct sbi_domain_memregion *nreg, *nreg1, *nreg2;
-	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
 
 	/* Sanity checks */
 	if (!reg || domain_finalized || !root.regions ||
@@ -590,7 +587,7 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
 	/* Sort and optimize root regions */
 	do {
 		/* Sanitize the root domain so that memregions are sorted */
-		rc = sanitize_domain(plat, &root);
+		rc = sanitize_domain(&root);
 		if (rc) {
 			sbi_printf("%s: sanity checks failed for"
 				   " %s (error %d)\n", __func__,
-- 
2.40.1



From atishp at atishpatra.org  Fri Oct  6 15:44:34 2023
From: atishp at atishpatra.org (Atish Patra)
Date: Fri, 6 Oct 2023 15:44:34 -0700
Subject: Public Review: Supervisor Binary Interface(SBI) v2.0
Message-ID: <CAOnJCUK_-svfBV2q3Sjc7T1PiDDzwMEjLWRr2hhB41vC1_4ORw@mail.gmail.com>

We're excited to kick off the public review for SBI v2.0.

Review Dates: 10/06/2023 to 11/06/2023

Specification Details:

PDF Version: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/commit-fe4562532a9cc57e5743b6466946c5e5c98c73ca/riscv-sbi.pdf

Source Code: https://github.com/riscv-non-isa/riscv-sbi-doc

How to Give Feedback:

Email your comments to the public isa-dev mailing
list(isa-dev at groups.riscv.org) or PRS mailing list
(tech-prs at lists.riscv.org).
Or, add issues/pull requests to our GitHub repository.

All feedback will be evaluated by the Platform Runtime Services Task
Group. Minor corrections and straightforward changes will be directly
implemented. Any other proposed changes will be discussed in a summary
report after the review period. If no major changes are required, the
updated specifications will be recommended for approval by the RISC-V
Technical Steering Committee and Board of Directors.

Contact:

Group: https://lists.riscv.org/g/tech-prs

Task Group Chair: Atish Patra (atishp at rivosinc.com)
Task Group Vice-chair: Sunil V L (sunilvl at ventanamicro.com)


-- 
Regards,
Atish


From atishp at atishpatra.org  Fri Oct  6 15:44:37 2023
From: atishp at atishpatra.org (Atish Patra)
Date: Fri, 6 Oct 2023 15:44:37 -0700
Subject: Public Review: Advanced Configuration and Power Interface -
 Functional Fixed Hardware
Message-ID: <CAOnJCU+BdTMQSxaXChUBLiiz71yx5e6mqngOxvD+cXNxSabzSQ@mail.gmail.com>

We're excited to kick off the public review for ACPI FFH v1.0.0.

Review Dates: 10/06/2023 to 11/06/2023

Specification Details:

PDF Version: https://github.com/riscv-non-isa/riscv-acpi-ffh/releases/download/v1.0.0-rc7/riscv-ffh.pdf

Source Code: https://github.com/riscv-non-isa/riscv-acpi-ffh

How to Give Feedback:

Email your comments to the public isa-dev mailing
list(isa-dev at groups.riscv.org) or PRS mailing list
(tech-prs at lists.riscv.org).
Or, add issues/pull requests to our GitHub repository.

All feedback will be evaluated by the Platform Runtime Services Task
Group. Minor corrections and straightforward changes will be directly
implemented. Any other proposed changes will be discussed in a summary
report after the review period. If no major changes are required, the
updated specifications will be recommended for approval by the RISC-V
Technical Steering Committee and Board of Directors.

Contact:

Group: https://lists.riscv.org/g/tech-prs

Task Group Chair: Atish Patra (atishp at rivosinc.com)
Task Group Vice-chair: Sunil V L (sunilvl at ventanamicro.com)

-- 
Regards,
Atish


From inochiama at outlook.com  Fri Oct  6 19:55:37 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 10:55:37 +0800
Subject: [PATCH 0/3] platform: generic Add Sophgo sg2042 support
Message-ID: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

As the dts of sg2042 in the mainline kernel is considered as stable, it is
time to port sg2042 soc.

This patch depends other two series:
1. platform: generic: add T-HEAD th1520 soc support
2. lib: sbi: Add sub-regions check for sanitizing domain

Link: https://lore.kernel.org/linux-riscv/cover.1696433229.git.unicorn_wang at outlook.com/

Inochi Amaoto (3):
  lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer
    compatible
  lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
  platform: generic: Add Sophgo sg2042 soc support

 lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
 lib/utils/timer/fdt_timer_mtimer.c |  2 +
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/sophgo/objects.mk |  9 ++++
 platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
 6 files changed, 90 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

--
2.42.0



From inochiama at outlook.com  Fri Oct  6 19:57:26 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 10:57:26 +0800
Subject: [PATCH 1/3] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953CFE8E06B92EC9BC25E74BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/timer/fdt_timer_mtimer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 9eaa11d..0ac9aed 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -146,6 +146,8 @@ static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
+	{ .compatible = "thead,c900-aclint-mtimer",
+	  .data = &thead_clint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Fri Oct  6 19:57:27 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 10:57:27 +0800
Subject: [PATCH 2/3] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
In-Reply-To: <20231007025727.99904-1-inochiama@outlook.com>
References: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231007025727.99904-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB4953857B6A80EA537CC4C0A7BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
string to avoid misuse.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index e3a6378..f4b2de4 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
 	{ .compatible = "thead,c900-clint", .data = &clint_offset },
+	{ .compatible = "thead,c900-aclint-mswi", .data = &clint_offset },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Fri Oct  6 19:58:06 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 10:58:06 +0800
Subject: [PATCH 3/3] platform: generic: Add Sophgo sg2042 soc support
In-Reply-To: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953D273C377C504C5EA8B4FBBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

Add Sophgo sg2042 platform support

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/sophgo/objects.mk |  9 ++++
 platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
 4 files changed, 87 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index f9e7ed2..a902cf3 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_SOPHGO_SG2042
+	bool "Sophgo sg2042 support"
+	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
+	default n
+
 config PLATFORM_STARFIVE_JH7110
 	bool "StarFive JH7110 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c432bc2..e1b76c8 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_SOPHGO_SG2042=y
 CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_PLATFORM_THEAD=y
 CONFIG_FDT_GPIO=y
diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
new file mode 100644
index 0000000..3d2908a
--- /dev/null
+++ b/platform/generic/sophgo/objects.mk
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
+# Copyright (C) 2023 Alibaba Group Holding Limited.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
+platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
new file mode 100644
index 0000000..df841bd
--- /dev/null
+++ b/platform/generic/sophgo/sg2042.c
@@ -0,0 +1,71 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <platform_override.h>
+#include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/timer/aclint_mtimer.h>
+
+#define SOPHGO_SG2042_TIMER_BASE	0x70ac000000UL
+#define SOPHGO_SG2042_TIMER_SIZE	0x10000UL
+
+
+static int sophgo_sg2042_early_init(bool cold_boot,
+				    const struct fdt_match *match)
+{
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+
+	thead_register_tlb_flush_trap_handler();
+
+	/*
+	 * Sophgo sg2042 soc use seperate 16 timers while initiating,
+	 * merge them as a single domain to avoid wasting.
+	 */
+	if (cold_boot)
+		return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
+						SOPHGO_SG2042_TIMER_SIZE *
+						sbi_platform_hart_count(plat),
+						MTIMER_REGION_ALIGN,
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
+
+
+	return 0;
+}
+
+static u32 sophgo_sg2042_tlb_num_entries(const struct fdt_match *match)
+{
+	unsigned long num_tlb_entries = (unsigned long)match->data;
+	return num_tlb_entries;
+}
+
+static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
+static const struct fdt_match sophgo_sg2042_match[] = {
+	{ .compatible = "sophgo,sg2042", .data = (void*)64 },
+	{ },
+};
+
+const struct platform_override sophgo_sg2042 = {
+	.match_table		= sophgo_sg2042_match,
+	.tlb_num_entries	= sophgo_sg2042_tlb_num_entries,
+	.early_init		= sophgo_sg2042_early_init,
+	.extensions_init	= sophgo_sg2042_extensions_init,
+};
-- 
2.42.0



From inochiama at outlook.com  Fri Oct  6 20:05:51 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 11:05:51 +0800
Subject: [PATCH v3 0/4] platform: generic: add T-HEAD th1520 soc support
Message-ID: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

As the tlb workaround is fixed, now it is a time to add T-HEAD th1520 soc
PMU support.

We also move the tlb flush errata to a separate file, so the furthur
platform can reused it. e.g. the Sophgo sg2042.

Changed from v2:
1. fix for empty line error when patching.
2. add the missing ack.

Changed from v1:
1. rebase for the master.

Inochi Amaoto (4):
  platform: generic: thead: move to thead c9xx header to vendor specific
    postion
  platform: generic: thead: separate implement of T-HEAD c9xx pmu
  platform: generic: thead: separate implement of T-HEAD c9xx errata
  platform: generic: thead: initialize PMU by default in thead generic
    platform

 platform/generic/Kconfig                      |  4 ++
 platform/generic/allwinner/sun20i-d1.c        | 53 +-------------
 .../{thead_c9xx.h => thead/c9xx_encoding.h}   |  4 +-
 platform/generic/include/thead/c9xx_errata.h  | 13 ++++
 platform/generic/include/thead/c9xx_pmu.h     |  7 ++
 platform/generic/thead/Kconfig                |  9 +++
 platform/generic/thead/objects.mk             |  6 +-
 platform/generic/thead/thead-generic.c        | 41 ++++++-----
 .../thead/thead_c9xx_errata_tlb_flush.c       | 17 +++++
 platform/generic/thead/thead_c9xx_pmu.c       | 69 +++++++++++++++++++
 ...andler.S => thead_c9xx_tlb_trap_handler.S} |  0
 11 files changed, 151 insertions(+), 72 deletions(-)
 rename platform/generic/include/{thead_c9xx.h => thead/c9xx_encoding.h} (98%)
 create mode 100644 platform/generic/include/thead/c9xx_errata.h
 create mode 100644 platform/generic/include/thead/c9xx_pmu.h
 create mode 100644 platform/generic/thead/Kconfig
 create mode 100644 platform/generic/thead/thead_c9xx_errata_tlb_flush.c
 create mode 100644 platform/generic/thead/thead_c9xx_pmu.c
 rename platform/generic/thead/{thead-trap-handler.S => thead_c9xx_tlb_trap_handler.S} (100%)

--
2.42.0



From inochiama at outlook.com  Fri Oct  6 20:06:28 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 11:06:28 +0800
Subject: [PATCH v3 1/4] platform: generic: thead: move to thead c9xx header to vendor specific postion
In-Reply-To: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953402F2CEAEA2038B7A8F7BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

The CSR encoding for t-head c9xx cores is shared across all the
platforms with these cores. So move header thead_c9xx.h to the
thead subdir.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Acked-by: Guo Ren <guoren at kernel.org>
---
 platform/generic/allwinner/sun20i-d1.c                        | 2 +-
 .../generic/include/{thead_c9xx.h => thead/c9xx_encoding.h}   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename platform/generic/include/{thead_c9xx.h => thead/c9xx_encoding.h} (98%)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index a9a7e47..b960284 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -5,7 +5,7 @@
  */

 #include <platform_override.h>
-#include <thead_c9xx.h>
+#include <thead/c9xx_encoding.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_io.h>
 #include <sbi/sbi_bitops.h>
diff --git a/platform/generic/include/thead_c9xx.h b/platform/generic/include/thead/c9xx_encoding.h
similarity index 98%
rename from platform/generic/include/thead_c9xx.h
rename to platform/generic/include/thead/c9xx_encoding.h
index bab0408..58adbef 100644
--- a/platform/generic/include/thead_c9xx.h
+++ b/platform/generic/include/thead/c9xx_encoding.h
@@ -1,5 +1,5 @@
-#ifndef __RISCV_THEAD_C9XX_H____
-#define __RISCV_THEAD_C9XX_H____
+#ifndef __RISCV_THEAD_C9XX_ENCODING_H____
+#define __RISCV_THEAD_C9XX_ENCODING_H____

 /* T-HEAD C9xx M mode CSR.  */
 #define THEAD_C9XX_CSR_MXSTATUS		0x7c0
--
2.42.0



From inochiama at outlook.com  Fri Oct  6 20:06:29 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 11:06:29 +0800
Subject: [PATCH v3 2/4] platform: generic: thead: separate implement of T-HEAD c9xx pmu
In-Reply-To: <20231007030631.101073-1-inochiama@outlook.com>
References: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231007030631.101073-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB49531384A849F05A47A17539BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

Separate the implement of T-HEAD c9xx pmu to allow any platform with
c9xx cores can use it.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig                  |  2 +
 platform/generic/allwinner/sun20i-d1.c    | 51 +----------------
 platform/generic/include/thead/c9xx_pmu.h |  7 +++
 platform/generic/thead/Kconfig            |  5 ++
 platform/generic/thead/objects.mk         |  2 +
 platform/generic/thead/thead_c9xx_pmu.c   | 69 +++++++++++++++++++++++
 6 files changed, 87 insertions(+), 49 deletions(-)
 create mode 100644 platform/generic/include/thead/c9xx_pmu.h
 create mode 100644 platform/generic/thead/Kconfig
 create mode 100644 platform/generic/thead/thead_c9xx_pmu.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index e7bd94e..ea3b5cf 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -26,6 +26,7 @@ config PLATFORM_GENERIC_MINOR_VER
 config PLATFORM_ALLWINNER_D1
 	bool "Allwinner D1 support"
 	depends on FDT_IRQCHIP_PLIC
+	select THEAD_C9XX_PMU
 	default n
 
 config PLATFORM_ANDES_AE350
@@ -57,5 +58,6 @@ config PLATFORM_THEAD
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
+source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
 
 endif
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index b960284..e9388db 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -6,6 +6,7 @@
 
 #include <platform_override.h>
 #include <thead/c9xx_encoding.h>
+#include <thead/c9xx_pmu.h>
 #include <sbi/riscv_asm.h>
 #include <sbi/riscv_io.h>
 #include <sbi/sbi_bitops.h>
@@ -223,58 +224,10 @@ static int sun20i_d1_fdt_fixup(void *fdt, const struct fdt_match *match)
 	return fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
 }
 
-static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
-{
-	if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
-		return;
-
-	/**
-	 * Clear out the OF bit so that next interrupt can be enabled.
-	 * This should be done before starting interrupt to avoid unexcepted
-	 * overflow interrupt.
-	 */
-	csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
-
-	/**
-	 * This register is described in C9xx document as the control register
-	 * for enabling writes to the superuser state counter. However, if the
-	 * corresponding bit is not set to 1, scounterof will always read as 0
-	 * when the counter register overflows.
-	 */
-	csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
-
-	/**
-	 * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
-	 * while the C9XX has designated enable bits.
-	 * So enable per-counter interrupt on C9xx here.
-	 */
-	csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
-}
-
-static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
-{
-	/**
-	 * There is no need to clear the bit of mcounterwen, it will expire
-	 * after setting the csr mcountinhibit.
-	 */
-	csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
-}
-
-static int thead_c9xx_pmu_irq_bit(void)
-{
-	return THEAD_C9XX_MIP_MOIP;
-}
-
-const struct sbi_pmu_device thead_c9xx_pmu_device = {
-	.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
-	.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
-	.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
-};
-
 static int sun20i_d1_extensions_init(const struct fdt_match *match,
 				     struct sbi_hart_features *hfeatures)
 {
-	sbi_pmu_set_device(&thead_c9xx_pmu_device);
+	thead_c9xx_register_pmu_device();
 
 	/* auto-detection doesn't work on t-head c9xx cores */
 	/* D1 has 29 mhpmevent csrs, but only 3-9,13-17 have valid value */
diff --git a/platform/generic/include/thead/c9xx_pmu.h b/platform/generic/include/thead/c9xx_pmu.h
new file mode 100644
index 0000000..bb1d831
--- /dev/null
+++ b/platform/generic/include/thead/c9xx_pmu.h
@@ -0,0 +1,7 @@
+
+#ifndef __RISCV_THEAD_C9XX_PMU_H____
+#define __RISCV_THEAD_C9XX_PMU_H____
+
+void thead_c9xx_register_pmu_device(void);
+
+#endif // __RISCV_THEAD_C9XX_PMU_H____
diff --git a/platform/generic/thead/Kconfig b/platform/generic/thead/Kconfig
new file mode 100644
index 0000000..e54e621
--- /dev/null
+++ b/platform/generic/thead/Kconfig
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+config THEAD_C9XX_PMU
+	bool "T-HEAD c9xx M-mode PMU support"
+	default n
diff --git a/platform/generic/thead/objects.mk b/platform/generic/thead/objects.mk
index 854bfbd..df2c61b 100644
--- a/platform/generic/thead/objects.mk
+++ b/platform/generic/thead/objects.mk
@@ -5,6 +5,8 @@
 # Copyright (C) 2023 Alibaba Group Holding Limited.
 #
 
+platform-objs-$(CONFIG_THEAD_C9XX_PMU) += thead/thead_c9xx_pmu.o
+
 carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD) += thead_generic
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-generic.o
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-trap-handler.o
diff --git a/platform/generic/thead/thead_c9xx_pmu.c b/platform/generic/thead/thead_c9xx_pmu.c
new file mode 100644
index 0000000..d205802
--- /dev/null
+++ b/platform/generic/thead/thead_c9xx_pmu.c
@@ -0,0 +1,69 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *   Haijiao Liu <haijiao.liu at sophgo.com>
+ *
+ */
+
+#include <thead/c9xx_encoding.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_pmu.h>
+
+static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
+{
+	if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+		return;
+
+	/**
+	 * Clear out the OF bit so that next interrupt can be enabled.
+	 * This should be done before starting interrupt to avoid unexcepted
+	 * overflow interrupt.
+	 */
+	csr_clear(THEAD_C9XX_CSR_MCOUNTEROF, BIT(ctr_idx));
+
+	/**
+	 * This register is described in C9xx document as the control register
+	 * for enabling writes to the superuser state counter. However, if the
+	 * corresponding bit is not set to 1, scounterof will always read as 0
+	 * when the counter register overflows.
+	 */
+	csr_set(THEAD_C9XX_CSR_MCOUNTERWEN, BIT(ctr_idx));
+
+	/**
+	 * SSCOFPMF uses the OF bit for enabling/disabling the interrupt,
+	 * while the C9XX has designated enable bits.
+	 * So enable per-counter interrupt on C9xx here.
+	 */
+	csr_set(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void thead_c9xx_pmu_ctr_disable_irq(uint32_t ctr_idx)
+{
+	/**
+	 * There is no need to clear the bit of mcounterwen, it will expire
+	 * after setting the csr mcountinhibit.
+	 */
+	csr_clear(THEAD_C9XX_CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static int thead_c9xx_pmu_irq_bit(void)
+{
+	return THEAD_C9XX_MIP_MOIP;
+}
+
+static const struct sbi_pmu_device thead_c9xx_pmu_device = {
+	.name = "thead,c900-pmu",
+	.hw_counter_enable_irq = thead_c9xx_pmu_ctr_enable_irq,
+	.hw_counter_disable_irq = thead_c9xx_pmu_ctr_disable_irq,
+	.hw_counter_irq_bit = thead_c9xx_pmu_irq_bit,
+};
+
+void thead_c9xx_register_pmu_device(void)
+{
+	sbi_pmu_set_device(&thead_c9xx_pmu_device);
+}
-- 
2.42.0



From inochiama at outlook.com  Fri Oct  6 20:06:30 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 11:06:30 +0800
Subject: [PATCH v3 3/4] platform: generic: thead: separate implement of T-HEAD c9xx errata
In-Reply-To: <20231007030631.101073-1-inochiama@outlook.com>
References: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231007030631.101073-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB495399EC057D782C694A6A27BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

Separate the implement of T-HEAD c9xx errata to allow any platform
with bug related to c9xx cores can use it.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig                      |  1 +
 platform/generic/include/thead/c9xx_errata.h  | 13 +++++++++
 platform/generic/thead/Kconfig                |  4 +++
 platform/generic/thead/objects.mk             |  4 ++-
 platform/generic/thead/thead-generic.c        | 28 ++++++++-----------
 .../thead/thead_c9xx_errata_tlb_flush.c       | 17 +++++++++++
 ...andler.S => thead_c9xx_tlb_trap_handler.S} |  0
 7 files changed, 49 insertions(+), 18 deletions(-)
 create mode 100644 platform/generic/include/thead/c9xx_errata.h
 create mode 100644 platform/generic/thead/thead_c9xx_errata_tlb_flush.c
 rename platform/generic/thead/{thead-trap-handler.S => thead_c9xx_tlb_trap_handler.S} (100%)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index ea3b5cf..3be75cf 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -55,6 +55,7 @@ config PLATFORM_STARFIVE_JH7110
 
 config PLATFORM_THEAD
 	bool "THEAD C9xx support"
+	select THEAD_C9XX_ERRATA
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
diff --git a/platform/generic/include/thead/c9xx_errata.h b/platform/generic/include/thead/c9xx_errata.h
new file mode 100644
index 0000000..bf97938
--- /dev/null
+++ b/platform/generic/include/thead/c9xx_errata.h
@@ -0,0 +1,13 @@
+
+#ifndef __RISCV_THEAD_C9XX_ERRATA_H____
+#define __RISCV_THEAD_C9XX_ERRATA_H____
+
+/**
+ * T-HEAD board with this quirk need to execute sfence.vma to flush
+ * stale entrie avoid incorrect memory access.
+ */
+#define THEAD_QUIRK_ERRATA_TLB_FLUSH		BIT(0)
+
+void thead_register_tlb_flush_trap_handler(void);
+
+#endif // __RISCV_THEAD_C9XX_ERRATA_H____
diff --git a/platform/generic/thead/Kconfig b/platform/generic/thead/Kconfig
index e54e621..c50d38e 100644
--- a/platform/generic/thead/Kconfig
+++ b/platform/generic/thead/Kconfig
@@ -3,3 +3,7 @@
 config THEAD_C9XX_PMU
 	bool "T-HEAD c9xx M-mode PMU support"
 	default n
+
+config THEAD_C9XX_ERRATA
+	bool "T-HEAD c9xx errata support"
+	default n
diff --git a/platform/generic/thead/objects.mk b/platform/generic/thead/objects.mk
index df2c61b..84f9faf 100644
--- a/platform/generic/thead/objects.mk
+++ b/platform/generic/thead/objects.mk
@@ -7,6 +7,8 @@
 
 platform-objs-$(CONFIG_THEAD_C9XX_PMU) += thead/thead_c9xx_pmu.o
 
+platform-objs-$(CONFIG_THEAD_C9XX_ERRATA) += thead/thead_c9xx_tlb_trap_handler.o
+platform-objs-$(CONFIG_THEAD_C9XX_ERRATA) += thead/thead_c9xx_errata_tlb_flush.o
+
 carray-platform_override_modules-$(CONFIG_PLATFORM_THEAD) += thead_generic
 platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-generic.o
-platform-objs-$(CONFIG_PLATFORM_THEAD) += thead/thead-trap-handler.o
diff --git a/platform/generic/thead/thead-generic.c b/platform/generic/thead/thead-generic.c
index 8120f6f..c77140c 100644
--- a/platform/generic/thead/thead-generic.c
+++ b/platform/generic/thead/thead-generic.c
@@ -7,40 +7,34 @@
  */
 
 #include <platform_override.h>
-#include <sbi/riscv_barrier.h>
+#include <thead/c9xx_errata.h>
 #include <sbi/sbi_const.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
 #include <sbi/sbi_string.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
-/**
- * T-HEAD board with this quirk need to execute sfence.vma to flush
- * stale entrie avoid incorrect memory access.
- */
-#define THEAD_QUIRK_TLB_FLUSH_FIXUP		BIT(0)
-
-void _thead_tlb_flush_fixup_trap_handler(void);
-
-void thead_register_tlb_flush_trap_handler(void)
-{
-	csr_write(CSR_MTVEC, &_thead_tlb_flush_fixup_trap_handler);
-}
+struct thead_generic_quirks {
+	u64	errata;
+};
 
 static int thead_generic_early_init(bool cold_boot,
 				    const struct fdt_match *match)
 {
-	unsigned long quirks = (unsigned long)match->data;
+	struct thead_generic_quirks *quirks = (void *)match->data;
 
-	if (quirks & THEAD_QUIRK_TLB_FLUSH_FIXUP)
+	if (quirks->errata & THEAD_QUIRK_ERRATA_TLB_FLUSH)
 		thead_register_tlb_flush_trap_handler();
 
 	return 0;
 }
 
+static struct thead_generic_quirks thead_th1520_quirks = {
+	.errata = THEAD_QUIRK_ERRATA_TLB_FLUSH,
+};
+
 static const struct fdt_match thead_generic_match[] = {
-	{ .compatible = "thead,th1520",
-	  .data = (void*)THEAD_QUIRK_TLB_FLUSH_FIXUP },
+	{ .compatible = "thead,th1520", .data = &thead_th1520_quirks },
 	{ },
 };
 
diff --git a/platform/generic/thead/thead_c9xx_errata_tlb_flush.c b/platform/generic/thead/thead_c9xx_errata_tlb_flush.c
new file mode 100644
index 0000000..755899a
--- /dev/null
+++ b/platform/generic/thead/thead_c9xx_errata_tlb_flush.c
@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+
+void _thead_tlb_flush_fixup_trap_handler(void);
+
+void thead_register_tlb_flush_trap_handler(void)
+{
+	csr_write(CSR_MTVEC, &_thead_tlb_flush_fixup_trap_handler);
+}
diff --git a/platform/generic/thead/thead-trap-handler.S b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
similarity index 100%
rename from platform/generic/thead/thead-trap-handler.S
rename to platform/generic/thead/thead_c9xx_tlb_trap_handler.S
-- 
2.42.0



From inochiama at outlook.com  Fri Oct  6 20:06:31 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat,  7 Oct 2023 11:06:31 +0800
Subject: [PATCH v3 4/4] platform: generic: thead: initialize PMU by default in thead generic platform
In-Reply-To: <20231007030631.101073-1-inochiama@outlook.com>
References: <IA1PR20MB49534E329372B295663B2153BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231007030631.101073-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB49536E28A3FC24C353A8DC04BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>

Since all the SoC with thead c9xx cores need this initialization at now,
initialize the c9xx pmu in the thead generic platform by default.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig               |  1 +
 platform/generic/thead/thead-generic.c | 13 +++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 3be75cf..f9e7ed2 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -56,6 +56,7 @@ config PLATFORM_STARFIVE_JH7110
 config PLATFORM_THEAD
 	bool "THEAD C9xx support"
 	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
 	default n
 
 source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
diff --git a/platform/generic/thead/thead-generic.c b/platform/generic/thead/thead-generic.c
index c77140c..72f4aaa 100644
--- a/platform/generic/thead/thead-generic.c
+++ b/platform/generic/thead/thead-generic.c
@@ -8,6 +8,7 @@
 
 #include <platform_override.h>
 #include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
 #include <sbi/sbi_const.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
@@ -29,6 +30,13 @@ static int thead_generic_early_init(bool cold_boot,
 	return 0;
 }
 
+static int thead_generic_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
 static struct thead_generic_quirks thead_th1520_quirks = {
 	.errata = THEAD_QUIRK_ERRATA_TLB_FLUSH,
 };
@@ -39,6 +47,7 @@ static const struct fdt_match thead_generic_match[] = {
 };
 
 const struct platform_override thead_generic = {
-	.match_table	= thead_generic_match,
-	.early_init	= thead_generic_early_init,
+	.match_table		= thead_generic_match,
+	.early_init		= thead_generic_early_init,
+	.extensions_init	= thead_generic_extensions_init,
 };
-- 
2.42.0



From wxjstz at 126.com  Fri Oct  6 20:48:50 2023
From: wxjstz at 126.com (Xiang W)
Date: Sat, 07 Oct 2023 11:48:50 +0800
Subject: [PATCH 0/3] Sparse HART id improvements
In-Reply-To: <CAAhSdy2iZruS48CqB9UDiaqL57KD7zX+DxsC-M8ArmxX8soWzg@mail.gmail.com>
References: <20230924155745.1753120-1-wxjstz@126.com>
	 <CAAhSdy2iZruS48CqB9UDiaqL57KD7zX+DxsC-M8ArmxX8soWzg@mail.gmail.com>
Message-ID: <6ce921ad7d4ff85737d4605163e70abb451f910c.camel@126.com>

? 2023-10-06???? 10:05 +0530?Anup Patel???
> On Sun, Sep 24, 2023 at 9:28?PM Xiang W <wxjstz at 126.com> wrote:
> > 
> > Modify last_hartindex_having_scratch/hartindex_to_hartid_table
> > /hartindex_to_scratch_table as static variables to prevent accidental
> > modification and reduce memory consumption
> > 
> > Xiang W (3):
> > ? lib: sbi: Refactor sbi_scratch_last_hartindex as a function
> > ? lib: sbi: Refactor sbi_hartindex_to_hartid as a function
> > ? lib: sbi: Refactor sbi_hartindex_to_scratch as a function
> 
> All these are in hot-path at various places so introducing a
> function is certainly not helping.
> 
> Also, if some buggy code is accidentally modifying global data
> then that buggy code should be fixed rather than papering over
> the problem by introducing these functions.
PATCH1:
The original code is a bit strange in that there is already a global variable
last_hartindex_having_scratch, but instead of using it outside of sbi_scratch.c,
the macro sbi_scratch_last_hartindex is used. If don't want to modify this macro
into a function, why not just change the name of the last_hartindex_having_scratch
renamed to sbi_scratch_last_hartindex and then remove the macro?

PATCH2:
The arrays hartindex_to_hartid_table and plat->hart_index2id store similar content,
and the extra length of the hartindex_to_hartid_table array is not used because
there is a determination of whether the index is less than sbi_scratch_last_ hartindex.
the array can be removed by adding just a little bit of checking.

Regards,
Xiang W
> 
> Regards,
> Anup
> 
> > 
> > ?include/sbi/sbi_scratch.h | 35 ++++++++++++-----------------------
> > ?lib/sbi/sbi_scratch.c???? | 30 ++++++++++++++++++++++++++----
> > ?2 files changed, 38 insertions(+), 27 deletions(-)
> > 
> > --
> > 2.40.1
> > 
> > 
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi



From peterlin at andestech.com  Fri Oct  6 23:04:43 2023
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Sat, 7 Oct 2023 14:04:43 +0800
Subject: [PATCH 0/6] Add Andes PMU extension support
In-Reply-To: <CAAhSdy1iUKOKkp3Z8ybL8ubcF7Y+YZEyMN232HYogE4ToTH+hw@mail.gmail.com>
References: <20230906094051.3957564-1-peterlin@andestech.com>
 <CAAhSdy1iUKOKkp3Z8ybL8ubcF7Y+YZEyMN232HYogE4ToTH+hw@mail.gmail.com>
Message-ID: <ZSD0-_n7QLr_vKQI@APC323>

Hi Anup,

On Fri, Oct 06, 2023 at 05:47:16PM +0530, Anup Patel wrote:
> Hi Yu Chien Peter Lin,
> 
> On Wed, Sep 6, 2023 at 3:12?PM Yu Chien Peter Lin
> <peterlin at andestech.com> wrote:
> >
> > This patch series enables perf tool to utilize Andes PMU
> > extension via PMU SBI calls, provides PMU device callbacks
> > for event sampling and mode filtering.
> >
> > We also provide a PMU node example of AX45MP in the last
> > patch.
> >
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support
> > - https://github.com/andestech/linux/commits/andes-pmu-support
> >
> > Yu Chien Peter Lin (6):
> >   sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> >   platform: include: andes45: Add PMU related CSR defines
> >   platform: andes: Add Andes custom PMU support
> >   platform: andes: Enable Andes PMU for AE350
> >   platform: rzfive: Enable Andes PMU for RZ/Five
> >   docs: pmu: Add Andes PMU node example
> 
> I assume there is going to be a v2 due to comments on PATCH3 ?

Yes we are working on this.

Thanks.
Peter Lin

> Regards,
> Anup
> 
> >
> >  docs/pmu_support.md                        | 87 ++++++++++++++++++++++
> >  include/sbi/sbi_pmu.h                      |  6 ++
> >  lib/sbi/sbi_pmu.c                          |  5 +-
> >  platform/generic/Kconfig                   |  2 +
> >  platform/generic/andes/Kconfig             |  4 +
> >  platform/generic/andes/ae350.c             |  2 +
> >  platform/generic/andes/andes_pmu.c         | 85 +++++++++++++++++++++
> >  platform/generic/andes/objects.mk          |  1 +
> >  platform/generic/include/andes/andes45.h   | 26 +++++++
> >  platform/generic/include/andes/andes_pmu.h | 12 +++
> >  platform/generic/renesas/rzfive/rzfive.c   |  2 +
> >  11 files changed, 231 insertions(+), 1 deletion(-)
> >  create mode 100644 platform/generic/andes/andes_pmu.c
> >  create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > --
> > 2.34.1
> >


From guoren at kernel.org  Sat Oct  7 23:58:18 2023
From: guoren at kernel.org (Guo Ren)
Date: Sun, 8 Oct 2023 14:58:18 +0800
Subject: [PATCH 3/3] platform: generic: Add Sophgo sg2042 soc support
In-Reply-To: <IA1PR20MB4953D273C377C504C5EA8B4FBBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49531BBE4BAA82B82316FFC1BBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <IA1PR20MB4953D273C377C504C5EA8B4FBBC8A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTSAoddJkSSZyWuCK2FpzTfKZ5hDCeKR40vrX4erZ6CM9w@mail.gmail.com>

On Sat, Oct 7, 2023 at 10:58?AM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Add Sophgo sg2042 platform support
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  platform/generic/Kconfig           |  6 +++
>  platform/generic/configs/defconfig |  1 +
>  platform/generic/sophgo/objects.mk |  9 ++++
>  platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
>  4 files changed, 87 insertions(+)
>  create mode 100644 platform/generic/sophgo/objects.mk
>  create mode 100644 platform/generic/sophgo/sg2042.c
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index f9e7ed2..a902cf3 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
>         depends on FDT_RESET && FDT_I2C
>         default n
>
> +config PLATFORM_SOPHGO_SG2042
> +       bool "Sophgo sg2042 support"
> +       select THEAD_C9XX_ERRATA
> +       select THEAD_C9XX_PMU
> +       default n
> +
>  config PLATFORM_STARFIVE_JH7110
>         bool "StarFive JH7110 support"
>         default n
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index c432bc2..e1b76c8 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_SOPHGO_SG2042=y
>  CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_PLATFORM_THEAD=y
>  CONFIG_FDT_GPIO=y
> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
> new file mode 100644
> index 0000000..3d2908a
> --- /dev/null
> +++ b/platform/generic/sophgo/objects.mk
> @@ -0,0 +1,9 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
> +# Copyright (C) 2023 Alibaba Group Holding Limited.
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
> new file mode 100644
> index 0000000..df841bd
> --- /dev/null
> +++ b/platform/generic/sophgo/sg2042.c
> @@ -0,0 +1,71 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Authors:
> + *   Inochi Amaoto <inochiama at outlook.com>
> + *
> + */
> +
> +#include <platform_override.h>
> +#include <thead/c9xx_errata.h>
> +#include <thead/c9xx_pmu.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_string.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/timer/aclint_mtimer.h>
> +
> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
> +
> +
> +static int sophgo_sg2042_early_init(bool cold_boot,
> +                                   const struct fdt_match *match)
> +{
> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
> +
> +       thead_register_tlb_flush_trap_handler();
> +
> +       /*
> +        * Sophgo sg2042 soc use seperate 16 timers while initiating,
> +        * merge them as a single domain to avoid wasting.
> +        */
> +       if (cold_boot)
> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
> +                                               SOPHGO_SG2042_TIMER_SIZE *
> +                                               sbi_platform_hart_count(plat),
> +                                               MTIMER_REGION_ALIGN,
> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
> +
> +
> +       return 0;
> +}
> +
> +static u32 sophgo_sg2042_tlb_num_entries(const struct fdt_match *match)
> +{
> +       unsigned long num_tlb_entries = (unsigned long)match->data;
> +       return num_tlb_entries;
why not return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES or 64?

> +}
> +
> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
> +                                        struct sbi_hart_features *hfeatures)
> +{
> +       thead_c9xx_register_pmu_device();
> +       return 0;
> +}
> +
> +static const struct fdt_match sophgo_sg2042_match[] = {
> +       { .compatible = "sophgo,sg2042", .data = (void*)64 },
The .data seems not to be set appropriately.

> +       { },
> +};
> +
> +const struct platform_override sophgo_sg2042 = {
> +       .match_table            = sophgo_sg2042_match,
> +       .tlb_num_entries        = sophgo_sg2042_tlb_num_entries,
> +       .early_init             = sophgo_sg2042_early_init,
> +       .extensions_init        = sophgo_sg2042_extensions_init,
> +};
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From inochiama at outlook.com  Sun Oct  8 00:42:59 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 15:42:59 +0800
Subject: [PATCH 3/3] platform: generic: Add Sophgo sg2042 soc support
In-Reply-To: <CAJF2gTSAoddJkSSZyWuCK2FpzTfKZ5hDCeKR40vrX4erZ6CM9w@mail.gmail.com>
References: <CAJF2gTSAoddJkSSZyWuCK2FpzTfKZ5hDCeKR40vrX4erZ6CM9w@mail.gmail.com>
Message-ID: <IA1PR20MB49537F790BFB6FD99E29067ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

>On Sat, Oct 7, 2023 at 10:58?AM Inochi Amaoto <inochiama at outlook.com> wrote:
>>
>> Add Sophgo sg2042 platform support
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> ---
>>  platform/generic/Kconfig           |  6 +++
>>  platform/generic/configs/defconfig |  1 +
>>  platform/generic/sophgo/objects.mk |  9 ++++
>>  platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
>>  4 files changed, 87 insertions(+)
>>  create mode 100644 platform/generic/sophgo/objects.mk
>>  create mode 100644 platform/generic/sophgo/sg2042.c
>>
>> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
>> index f9e7ed2..a902cf3 100644
>> --- a/platform/generic/Kconfig
>> +++ b/platform/generic/Kconfig
>> @@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
>>         depends on FDT_RESET && FDT_I2C
>>         default n
>>
>> +config PLATFORM_SOPHGO_SG2042
>> +       bool "Sophgo sg2042 support"
>> +       select THEAD_C9XX_ERRATA
>> +       select THEAD_C9XX_PMU
>> +       default n
>> +
>>  config PLATFORM_STARFIVE_JH7110
>>         bool "StarFive JH7110 support"
>>         default n
>> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
>> index c432bc2..e1b76c8 100644
>> --- a/platform/generic/configs/defconfig
>> +++ b/platform/generic/configs/defconfig
>> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>>  CONFIG_PLATFORM_SIFIVE_FU540=y
>>  CONFIG_PLATFORM_SIFIVE_FU740=y
>> +CONFIG_PLATFORM_SOPHGO_SG2042=y
>>  CONFIG_PLATFORM_STARFIVE_JH7110=y
>>  CONFIG_PLATFORM_THEAD=y
>>  CONFIG_FDT_GPIO=y
>> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
>> new file mode 100644
>> index 0000000..3d2908a
>> --- /dev/null
>> +++ b/platform/generic/sophgo/objects.mk
>> @@ -0,0 +1,9 @@
>> +#
>> +# SPDX-License-Identifier: BSD-2-Clause
>> +#
>> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
>> +# Copyright (C) 2023 Alibaba Group Holding Limited.
>> +#
>> +
>> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
>> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
>> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
>> new file mode 100644
>> index 0000000..df841bd
>> --- /dev/null
>> +++ b/platform/generic/sophgo/sg2042.c
>> @@ -0,0 +1,71 @@
>> +/*
>> + * SPDX-License-Identifier: BSD-2-Clause
>> + *
>> + * Authors:
>> + *   Inochi Amaoto <inochiama at outlook.com>
>> + *
>> + */
>> +
>> +#include <platform_override.h>
>> +#include <thead/c9xx_errata.h>
>> +#include <thead/c9xx_pmu.h>
>> +#include <sbi/sbi_const.h>
>> +#include <sbi/sbi_domain.h>
>> +#include <sbi/sbi_platform.h>
>> +#include <sbi/sbi_scratch.h>
>> +#include <sbi/sbi_string.h>
>> +#include <sbi_utils/fdt/fdt_helper.h>
>> +#include <sbi_utils/timer/aclint_mtimer.h>
>> +
>> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
>> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
>> +
>> +
>> +static int sophgo_sg2042_early_init(bool cold_boot,
>> +                                   const struct fdt_match *match)
>> +{
>> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
>> +
>> +       thead_register_tlb_flush_trap_handler();
>> +
>> +       /*
>> +        * Sophgo sg2042 soc use seperate 16 timers while initiating,
>> +        * merge them as a single domain to avoid wasting.
>> +        */
>> +       if (cold_boot)
>> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
>> +                                               SOPHGO_SG2042_TIMER_SIZE *
>> +                                               sbi_platform_hart_count(plat),
>> +                                               MTIMER_REGION_ALIGN,
>> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
>> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
>> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
>> +
>> +
>> +       return 0;
>> +}
>> +
>> +static u32 sophgo_sg2042_tlb_num_entries(const struct fdt_match *match)
>> +{
>> +       unsigned long num_tlb_entries = (unsigned long)match->data;
>> +       return num_tlb_entries;
>why not return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES or 64?
>

AFAIK, use SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES may gain performance impact
on sg2042. So the default value needs to be changed.
I just left this number as a quirk, so 64 is OK for me. But I think using
max(SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES, hart_count) in generic platform
code maybe a better idea.

>> +}
>> +
>> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
>> +                                        struct sbi_hart_features *hfeatures)
>> +{
>> +       thead_c9xx_register_pmu_device();
>> +       return 0;
>> +}
>> +
>> +static const struct fdt_match sophgo_sg2042_match[] = {
>> +       { .compatible = "sophgo,sg2042", .data = (void*)64 },
>The .data seems not to be set appropriately.
>
>> +       { },
>> +};
>> +
>> +const struct platform_override sophgo_sg2042 = {
>> +       .match_table            = sophgo_sg2042_match,
>> +       .tlb_num_entries        = sophgo_sg2042_tlb_num_entries,
>> +       .early_init             = sophgo_sg2042_early_init,
>> +       .extensions_init        = sophgo_sg2042_extensions_init,
>> +};
>> --
>> 2.42.0
>>
>
>
>--
>Best Regards
> Guo Ren
>
>


From guoren at kernel.org  Sun Oct  8 01:36:54 2023
From: guoren at kernel.org (Guo Ren)
Date: Sun, 8 Oct 2023 16:36:54 +0800
Subject: [PATCH 3/3] platform: generic: Add Sophgo sg2042 soc support
In-Reply-To: <IA1PR20MB49537F790BFB6FD99E29067ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <CAJF2gTSAoddJkSSZyWuCK2FpzTfKZ5hDCeKR40vrX4erZ6CM9w@mail.gmail.com>
 <IA1PR20MB49537F790BFB6FD99E29067ABBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTQOcODbzU3HWe=Mk2BiktLEr4emA2=BeZmb1ExgoSvsvw@mail.gmail.com>

On Sun, Oct 8, 2023 at 3:43?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> >On Sat, Oct 7, 2023 at 10:58?AM Inochi Amaoto <inochiama at outlook.com> wrote:
> >>
> >> Add Sophgo sg2042 platform support
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> >> ---
> >>  platform/generic/Kconfig           |  6 +++
> >>  platform/generic/configs/defconfig |  1 +
> >>  platform/generic/sophgo/objects.mk |  9 ++++
> >>  platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
> >>  4 files changed, 87 insertions(+)
> >>  create mode 100644 platform/generic/sophgo/objects.mk
> >>  create mode 100644 platform/generic/sophgo/sg2042.c
> >>
> >> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> >> index f9e7ed2..a902cf3 100644
> >> --- a/platform/generic/Kconfig
> >> +++ b/platform/generic/Kconfig
> >> @@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
> >>         depends on FDT_RESET && FDT_I2C
> >>         default n
> >>
> >> +config PLATFORM_SOPHGO_SG2042
> >> +       bool "Sophgo sg2042 support"
> >> +       select THEAD_C9XX_ERRATA
> >> +       select THEAD_C9XX_PMU
> >> +       default n
> >> +
> >>  config PLATFORM_STARFIVE_JH7110
> >>         bool "StarFive JH7110 support"
> >>         default n
> >> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> >> index c432bc2..e1b76c8 100644
> >> --- a/platform/generic/configs/defconfig
> >> +++ b/platform/generic/configs/defconfig
> >> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> >>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
> >>  CONFIG_PLATFORM_SIFIVE_FU540=y
> >>  CONFIG_PLATFORM_SIFIVE_FU740=y
> >> +CONFIG_PLATFORM_SOPHGO_SG2042=y
> >>  CONFIG_PLATFORM_STARFIVE_JH7110=y
> >>  CONFIG_PLATFORM_THEAD=y
> >>  CONFIG_FDT_GPIO=y
> >> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
> >> new file mode 100644
> >> index 0000000..3d2908a
> >> --- /dev/null
> >> +++ b/platform/generic/sophgo/objects.mk
> >> @@ -0,0 +1,9 @@
> >> +#
> >> +# SPDX-License-Identifier: BSD-2-Clause
> >> +#
> >> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
> >> +# Copyright (C) 2023 Alibaba Group Holding Limited.
> >> +#
> >> +
> >> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
> >> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
> >> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
> >> new file mode 100644
> >> index 0000000..df841bd
> >> --- /dev/null
> >> +++ b/platform/generic/sophgo/sg2042.c
> >> @@ -0,0 +1,71 @@
> >> +/*
> >> + * SPDX-License-Identifier: BSD-2-Clause
> >> + *
> >> + * Authors:
> >> + *   Inochi Amaoto <inochiama at outlook.com>
> >> + *
> >> + */
> >> +
> >> +#include <platform_override.h>
> >> +#include <thead/c9xx_errata.h>
> >> +#include <thead/c9xx_pmu.h>
> >> +#include <sbi/sbi_const.h>
> >> +#include <sbi/sbi_domain.h>
> >> +#include <sbi/sbi_platform.h>
> >> +#include <sbi/sbi_scratch.h>
> >> +#include <sbi/sbi_string.h>
> >> +#include <sbi_utils/fdt/fdt_helper.h>
> >> +#include <sbi_utils/timer/aclint_mtimer.h>
> >> +
> >> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
> >> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
> >> +
> >> +
> >> +static int sophgo_sg2042_early_init(bool cold_boot,
> >> +                                   const struct fdt_match *match)
> >> +{
> >> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
> >> +
> >> +       thead_register_tlb_flush_trap_handler();
> >> +
> >> +       /*
> >> +        * Sophgo sg2042 soc use seperate 16 timers while initiating,
> >> +        * merge them as a single domain to avoid wasting.
> >> +        */
> >> +       if (cold_boot)
> >> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
> >> +                                               SOPHGO_SG2042_TIMER_SIZE *
> >> +                                               sbi_platform_hart_count(plat),
> >> +                                               MTIMER_REGION_ALIGN,
> >> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
> >> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
> >> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
> >> +
> >> +
> >> +       return 0;
> >> +}
> >> +
> >> +static u32 sophgo_sg2042_tlb_num_entries(const struct fdt_match *match)
> >> +{
> >> +       unsigned long num_tlb_entries = (unsigned long)match->data;
> >> +       return num_tlb_entries;
> >why not return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES or 64?
> >
>
> AFAIK, use SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES may gain performance impact
> on sg2042. So the default value needs to be changed.
Okay, so we need to increase the number of entries.

> I just left this number as a quirk, so 64 is OK for me. But I think using
> max(SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES, hart_count) in generic platform
> code maybe a better idea.
I mean, why do you use match->data? (void *) data is for complex
struct. You could return 64 directly here.

>
> >> +}
> >> +
> >> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
> >> +                                        struct sbi_hart_features *hfeatures)
> >> +{
> >> +       thead_c9xx_register_pmu_device();
> >> +       return 0;
> >> +}
> >> +
> >> +static const struct fdt_match sophgo_sg2042_match[] = {
> >> +       { .compatible = "sophgo,sg2042", .data = (void*)64 },
> >The .data seems not to be set appropriately.
> >
> >> +       { },
> >> +};
> >> +
> >> +const struct platform_override sophgo_sg2042 = {
> >> +       .match_table            = sophgo_sg2042_match,
> >> +       .tlb_num_entries        = sophgo_sg2042_tlb_num_entries,
> >> +       .early_init             = sophgo_sg2042_early_init,
> >> +       .extensions_init        = sophgo_sg2042_extensions_init,
> >> +};
> >> --
> >> 2.42.0
> >>
> >
> >
> >--
> >Best Regards
> > Guo Ren
> >
> >



-- 
Best Regards
 Guo Ren


From inochiama at outlook.com  Sun Oct  8 01:45:55 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 16:45:55 +0800
Subject: [PATCH 3/3] platform: generic: Add Sophgo sg2042 soc support
In-Reply-To: <CAJF2gTQOcODbzU3HWe=Mk2BiktLEr4emA2=BeZmb1ExgoSvsvw@mail.gmail.com>
References: <CAJF2gTQOcODbzU3HWe=Mk2BiktLEr4emA2=BeZmb1ExgoSvsvw@mail.gmail.com>
Message-ID: <IA1PR20MB4953D4AD87BF2E2EB693CE77BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

>On Sun, Oct 8, 2023 at 3:43?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>>
>>> On Sat, Oct 7, 2023 at 10:58?AM Inochi Amaoto <inochiama at outlook.com> wrote:
>>>>
>>>> Add Sophgo sg2042 platform support
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>>>> ---
>>>>  platform/generic/Kconfig           |  6 +++
>>>>  platform/generic/configs/defconfig |  1 +
>>>>  platform/generic/sophgo/objects.mk |  9 ++++
>>>>  platform/generic/sophgo/sg2042.c   | 71 ++++++++++++++++++++++++++++++
>>>>  4 files changed, 87 insertions(+)
>>>>  create mode 100644 platform/generic/sophgo/objects.mk
>>>>  create mode 100644 platform/generic/sophgo/sg2042.c
>>>>
>>>> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
>>>> index f9e7ed2..a902cf3 100644
>>>> --- a/platform/generic/Kconfig
>>>> +++ b/platform/generic/Kconfig
>>>> @@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
>>>>         depends on FDT_RESET && FDT_I2C
>>>>         default n
>>>>
>>>> +config PLATFORM_SOPHGO_SG2042
>>>> +       bool "Sophgo sg2042 support"
>>>> +       select THEAD_C9XX_ERRATA
>>>> +       select THEAD_C9XX_PMU
>>>> +       default n
>>>> +
>>>>  config PLATFORM_STARFIVE_JH7110
>>>>         bool "StarFive JH7110 support"
>>>>         default n
>>>> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
>>>> index c432bc2..e1b76c8 100644
>>>> --- a/platform/generic/configs/defconfig
>>>> +++ b/platform/generic/configs/defconfig
>>>> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>>>>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>>>>  CONFIG_PLATFORM_SIFIVE_FU540=y
>>>>  CONFIG_PLATFORM_SIFIVE_FU740=y
>>>> +CONFIG_PLATFORM_SOPHGO_SG2042=y
>>>>  CONFIG_PLATFORM_STARFIVE_JH7110=y
>>>>  CONFIG_PLATFORM_THEAD=y
>>>>  CONFIG_FDT_GPIO=y
>>>> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
>>>> new file mode 100644
>>>> index 0000000..3d2908a
>>>> --- /dev/null
>>>> +++ b/platform/generic/sophgo/objects.mk
>>>> @@ -0,0 +1,9 @@
>>>> +#
>>>> +# SPDX-License-Identifier: BSD-2-Clause
>>>> +#
>>>> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
>>>> +# Copyright (C) 2023 Alibaba Group Holding Limited.
>>>> +#
>>>> +
>>>> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
>>>> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
>>>> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
>>>> new file mode 100644
>>>> index 0000000..df841bd
>>>> --- /dev/null
>>>> +++ b/platform/generic/sophgo/sg2042.c
>>>> @@ -0,0 +1,71 @@
>>>> +/*
>>>> + * SPDX-License-Identifier: BSD-2-Clause
>>>> + *
>>>> + * Authors:
>>>> + *   Inochi Amaoto <inochiama at outlook.com>
>>>> + *
>>>> + */
>>>> +
>>>> +#include <platform_override.h>
>>>> +#include <thead/c9xx_errata.h>
>>>> +#include <thead/c9xx_pmu.h>
>>>> +#include <sbi/sbi_const.h>
>>>> +#include <sbi/sbi_domain.h>
>>>> +#include <sbi/sbi_platform.h>
>>>> +#include <sbi/sbi_scratch.h>
>>>> +#include <sbi/sbi_string.h>
>>>> +#include <sbi_utils/fdt/fdt_helper.h>
>>>> +#include <sbi_utils/timer/aclint_mtimer.h>
>>>> +
>>>> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
>>>> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
>>>> +
>>>> +
>>>> +static int sophgo_sg2042_early_init(bool cold_boot,
>>>> +                                   const struct fdt_match *match)
>>>> +{
>>>> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
>>>> +
>>>> +       thead_register_tlb_flush_trap_handler();
>>>> +
>>>> +       /*
>>>> +        * Sophgo sg2042 soc use seperate 16 timers while initiating,
>>>> +        * merge them as a single domain to avoid wasting.
>>>> +        */
>>>> +       if (cold_boot)
>>>> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
>>>> +                                               SOPHGO_SG2042_TIMER_SIZE *
>>>> +                                               sbi_platform_hart_count(plat),
>>>> +                                               MTIMER_REGION_ALIGN,
>>>> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
>>>> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
>>>> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
>>>> +
>>>> +
>>>> +       return 0;
>>>> +}
>>>> +
>>>> +static u32 sophgo_sg2042_tlb_num_entries(const struct fdt_match *match)
>>>> +{
>>>> +       unsigned long num_tlb_entries = (unsigned long)match->data;
>>>> +       return num_tlb_entries;
>>> why not return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES or 64?
>>>
>>
>> AFAIK, use SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES may gain performance impact
>> on sg2042. So the default value needs to be changed.
>Okay, so we need to increase the number of entries.
>
>> I just left this number as a quirk, so 64 is OK for me. But I think using
>> max(SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES, hart_count) in generic platform
>> code maybe a better idea.
>I mean, why do you use match->data? (void *) data is for complex
>struct. You could return 64 directly here.
>

Yeah, I just use them to carry data for chips different in future.
I agree with you for the direct number. Anyway, I will prepare a new
patch with dynamic detected tlb entries as I mentioned, that will solve
this problem.

>>
>>>> +}
>>>> +
>>>> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
>>>> +                                        struct sbi_hart_features *hfeatures)
>>>> +{
>>>> +       thead_c9xx_register_pmu_device();
>>>> +       return 0;
>>>> +}
>>>> +
>>>> +static const struct fdt_match sophgo_sg2042_match[] = {
>>>> +       { .compatible = "sophgo,sg2042", .data = (void*)64 },
>>> The .data seems not to be set appropriately.
>>>
>>>> +       { },
>>>> +};
>>>> +
>>>> +const struct platform_override sophgo_sg2042 = {
>>>> +       .match_table            = sophgo_sg2042_match,
>>>> +       .tlb_num_entries        = sophgo_sg2042_tlb_num_entries,
>>>> +       .early_init             = sophgo_sg2042_early_init,
>>>> +       .extensions_init        = sophgo_sg2042_extensions_init,
>>>> +};
>>>> --
>>>> 2.42.0
>>>>
>>>
>>>
>>> --
>>> Best Regards
>>> Guo Ren
>>>
>>>
>
>
>
>--
>Best Regards
> Guo Ren
>
>


From inochiama at outlook.com  Sun Oct  8 05:15:52 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 20:15:52 +0800
Subject: [PATCH v2 0/4] platform: generic: Add Sophgo sg2042 support
Message-ID: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

As the dts of sg2042 in the mainline kernel is considered as stable, it is
time to port sg2042 soc.

This patch depends other two series:
1. platform: generic: add T-HEAD th1520 soc support
2. lib: sbi: Add sub-regions check for sanitizing domain

Link: https://lore.kernel.org/linux-riscv/cover.1696433229.git.unicorn_wang at outlook.com/

Changed from v1:
1. make number of entries in tlb fifo auto deteted.

Inochi Amaoto (4):
  lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer
    compatible
  lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
  platform: Allow platform uses hart count as the size of tlb info
  platform: generic: Add Sophgo sg2042 platform support

 lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
 lib/utils/timer/fdt_timer_mtimer.c |  2 +
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/platform.c        |  7 ++++
 platform/generic/sophgo/objects.mk |  9 +++++
 platform/generic/sophgo/sg2042.c   | 64 ++++++++++++++++++++++++++++++
 7 files changed, 90 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

--
2.42.0



From inochiama at outlook.com  Sun Oct  8 05:16:44 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 20:16:44 +0800
Subject: [PATCH v2 1/4] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953A405684C03B289FED6E6BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/timer/fdt_timer_mtimer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 9eaa11d..0ac9aed 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -146,6 +146,8 @@ static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
+	{ .compatible = "thead,c900-aclint-mtimer",
+	  .data = &thead_clint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Sun Oct  8 05:16:45 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 20:16:45 +0800
Subject: [PATCH v2 2/4] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
In-Reply-To: <20231008121645.329797-1-inochiama@outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231008121645.329797-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB49532F228F940A375F963BC8BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
string to avoid misuse.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index e3a6378..f4b2de4 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
 	{ .compatible = "thead,c900-clint", .data = &clint_offset },
+	{ .compatible = "thead,c900-aclint-mswi", .data = &clint_offset },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Sun Oct  8 05:17:41 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 20:17:41 +0800
Subject: [PATCH v2 3/4] platform: Allow platform uses hart count as the size of tlb info
In-Reply-To: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953F3CC7ED87825F69B50CEBBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

For platform with high number of harts, it is better to auto detect a
suitable number of entries in tlb fifo. Since allocating tlb entry for
all online harts can reduce the wait time significantly, using the
number of the online harts can make most platforms happy. This auto
detection can avoid most duplicate code for setting tlb fifo size if
the hart count of platform is big.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/platform.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..9397afc 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -258,8 +258,15 @@ static u64 generic_tlbr_flush_limit(void)
 
 static u32 generic_tlb_num_entries(void)
 {
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+	u32 hart_count = sbi_platform_hart_count(plat);
+
 	if (generic_plat && generic_plat->tlb_num_entries)
 		return generic_plat->tlb_num_entries(generic_plat_match);
+
+	/* for platform with too many harts, use hart count instead */
+	if (hart_count > SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES)
+		return hart_count;
 	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
 }
 
-- 
2.42.0



From inochiama at outlook.com  Sun Oct  8 05:17:42 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sun,  8 Oct 2023 20:17:42 +0800
Subject: [PATCH v2 4/4] platform: generic: Add Sophgo sg2042 platform support
In-Reply-To: <20231008121742.330012-1-inochiama@outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231008121742.330012-1-inochiama@outlook.com>
Message-ID: <IA1PR20MB4953994C9AA1CAE023E84E00BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>

Add Sophgo sg2042 soc support

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/sophgo/objects.mk |  9 +++++
 platform/generic/sophgo/sg2042.c   | 64 ++++++++++++++++++++++++++++++
 4 files changed, 80 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index f9e7ed2..a902cf3 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_SOPHGO_SG2042
+	bool "Sophgo sg2042 support"
+	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
+	default n
+
 config PLATFORM_STARFIVE_JH7110
 	bool "StarFive JH7110 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c432bc2..e1b76c8 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_SOPHGO_SG2042=y
 CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_PLATFORM_THEAD=y
 CONFIG_FDT_GPIO=y
diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
new file mode 100644
index 0000000..3d2908a
--- /dev/null
+++ b/platform/generic/sophgo/objects.mk
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
+# Copyright (C) 2023 Alibaba Group Holding Limited.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
+platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
new file mode 100644
index 0000000..af36eb2
--- /dev/null
+++ b/platform/generic/sophgo/sg2042.c
@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <platform_override.h>
+#include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/timer/aclint_mtimer.h>
+
+#define SOPHGO_SG2042_TIMER_BASE	0x70ac000000UL
+#define SOPHGO_SG2042_TIMER_SIZE	0x10000UL
+
+
+static int sophgo_sg2042_early_init(bool cold_boot,
+				    const struct fdt_match *match)
+{
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+
+	thead_register_tlb_flush_trap_handler();
+
+	/*
+	 * Sophgo sg2042 soc use seperate 16 timers while initiating,
+	 * merge them as a single domain to avoid wasting.
+	 */
+	if (cold_boot)
+		return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
+						SOPHGO_SG2042_TIMER_SIZE *
+						sbi_platform_hart_count(plat),
+						MTIMER_REGION_ALIGN,
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
+
+
+	return 0;
+}
+
+static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
+static const struct fdt_match sophgo_sg2042_match[] = {
+	{ .compatible = "sophgo,sg2042" },
+	{ },
+};
+
+const struct platform_override sophgo_sg2042 = {
+	.match_table		= sophgo_sg2042_match,
+	.early_init		= sophgo_sg2042_early_init,
+	.extensions_init	= sophgo_sg2042_extensions_init,
+};
-- 
2.42.0



From wxjstz at 126.com  Sun Oct  8 09:20:28 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 09 Oct 2023 00:20:28 +0800
Subject: [PATCH v2 3/4] platform: Allow platform uses hart count as the
 size of tlb info
In-Reply-To: <IA1PR20MB4953F3CC7ED87825F69B50CEBBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
	 <IA1PR20MB4953F3CC7ED87825F69B50CEBBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <8e44a0ba88a2cc25d5ad5254ec7db33b8e37cab8.camel@126.com>

? 2023-10-08???? 20:17 +0800?Inochi Amaoto???
> For platform with high number of harts, it is better to auto detect a
> suitable number of entries in tlb fifo. Since allocating tlb entry for
> all online harts can reduce the wait time significantly, using the
> number of the online harts can make most platforms happy. This auto
> detection can avoid most duplicate code for setting tlb fifo size if
> the hart count of platform is big.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> ?platform/generic/platform.c | 7 +++++++
> ?1 file changed, 7 insertions(+)
> 
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 66a0b77..9397afc 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -258,8 +258,15 @@ static u64 generic_tlbr_flush_limit(void)
> ?
> ?static u32 generic_tlb_num_entries(void)
> ?{
> +	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
> +	u32 hart_count = sbi_platform_hart_count(plat);
The two lines above can be replaced with:
	u32 hart_count = sbi_scratch_last_hartindex() + 1;

If returning hart_count directly is appropriate, is it possible to remove
SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES and generic_plat->tlb_num_entries?

This patch does not seem to belong to sg2042 and should be sent separately.

Regards,
Xiang W

> +
> ?	if (generic_plat && generic_plat->tlb_num_entries)
> ?		return generic_plat->tlb_num_entries(generic_plat_match);
> +
> +	/* for platform with too many harts, use hart count instead */
> +	if (hart_count > SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES)
> +		return hart_count;
> ?	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> ?}
> ?



From samuel.holland at sifive.com  Sun Oct  8 12:36:46 2023
From: samuel.holland at sifive.com (Samuel Holland)
Date: Sun, 8 Oct 2023 14:36:46 -0500
Subject: [PATCH v2 1/4] lib: utils/timer: mtimer: add separate T-Head C9xx
 CLINT mtimer compatible
In-Reply-To: <IA1PR20MB4953A405684C03B289FED6E6BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <IA1PR20MB4953A405684C03B289FED6E6BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <10dad8bc-e333-42ee-a594-e56e7c5e1e34@sifive.com>

On 2023-10-08 7:16 AM, Inochi Amaoto wrote:
> T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
> different address, which may cause a misuse if use the same compatible
> string, add a new timer compatible string to avoid this.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
> ---
>  lib/utils/timer/fdt_timer_mtimer.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index 9eaa11d..0ac9aed 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -146,6 +146,8 @@ static const struct fdt_match timer_mtimer_match[] = {
>  	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
>  	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
>  	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
> +	{ .compatible = "thead,c900-aclint-mtimer",
> +	  .data = &thead_clint_quirks },

This is wrong. When using separate mtimer/mswi nodes, there is no MMIO offset.
So you need a new quirks structure for this compatible string.

Regards,
Samuel

>  	{ .compatible = "riscv,aclint-mtimer" },
>  	{ },
>  };



From samuel.holland at sifive.com  Sun Oct  8 12:40:26 2023
From: samuel.holland at sifive.com (Samuel Holland)
Date: Sun, 8 Oct 2023 14:40:26 -0500
Subject: [PATCH v2 2/4] lib: utils/ipi: mswi: add separate T-Head C9xx
 CLINT mswi compatible
In-Reply-To: <IA1PR20MB49532F228F940A375F963BC8BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231008121645.329797-1-inochiama@outlook.com>
 <IA1PR20MB49532F228F940A375F963BC8BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <1e9653aa-d618-4ea8-b6e0-c0f458822e50@sifive.com>

On 2023-10-08 7:16 AM, Inochi Amaoto wrote:
> Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
> string to avoid misuse.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
> ---
>  lib/utils/ipi/fdt_ipi_mswi.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
> index e3a6378..f4b2de4 100644
> --- a/lib/utils/ipi/fdt_ipi_mswi.c
> +++ b/lib/utils/ipi/fdt_ipi_mswi.c
> @@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
>  	{ .compatible = "riscv,clint0", .data = &clint_offset },
>  	{ .compatible = "sifive,clint0", .data = &clint_offset },
>  	{ .compatible = "thead,c900-clint", .data = &clint_offset },
> +	{ .compatible = "thead,c900-aclint-mswi", .data = &clint_offset },

This should omit .data, like for riscv,aclint-mswi below, so it gets the MMIO
region base and size directly from the DT node.

Regards,
Samuel

>  	{ .compatible = "riscv,aclint-mswi" },
>  	{ },
>  };



From inochiama at outlook.com  Sun Oct  8 17:19:06 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Mon,  9 Oct 2023 08:19:06 +0800
Subject: [PATCH v2 2/4] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
In-Reply-To: <1e9653aa-d618-4ea8-b6e0-c0f458822e50@sifive.com>
References: <1e9653aa-d618-4ea8-b6e0-c0f458822e50@sifive.com>
Message-ID: <IA1PR20MB49531F8F9DB5B02BAA3ADA80BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>

>On 2023-10-08 7:16 AM, Inochi Amaoto wrote:
>> Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
>> string to avoid misuse.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
>> ---
>>  lib/utils/ipi/fdt_ipi_mswi.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
>> index e3a6378..f4b2de4 100644
>> --- a/lib/utils/ipi/fdt_ipi_mswi.c
>> +++ b/lib/utils/ipi/fdt_ipi_mswi.c
>> @@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
>>  	{ .compatible = "riscv,clint0", .data = &clint_offset },
>>  	{ .compatible = "sifive,clint0", .data = &clint_offset },
>>  	{ .compatible = "thead,c900-clint", .data = &clint_offset },
>> +	{ .compatible = "thead,c900-aclint-mswi", .data = &clint_offset },
>
>This should omit .data, like for riscv,aclint-mswi below, so it gets the MMIO
>region base and size directly from the DT node.
>
>Regards,
>Samuel
>

Yes, I will omit it. It seems I have misunderstand the aclint.

>>  	{ .compatible = "riscv,aclint-mswi" },
>>  	{ },
>>  };
>


From inochiama at outlook.com  Sun Oct  8 17:20:30 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Mon,  9 Oct 2023 08:20:30 +0800
Subject: [PATCH v2 1/4] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <10dad8bc-e333-42ee-a594-e56e7c5e1e34@sifive.com>
References: <10dad8bc-e333-42ee-a594-e56e7c5e1e34@sifive.com>
Message-ID: <IA1PR20MB4953B602556F31EC2EFDCAA4BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>

>On 2023-10-08 7:16 AM, Inochi Amaoto wrote:
>> T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
>> different address, which may cause a misuse if use the same compatible
>> string, add a new timer compatible string to avoid this.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
>> ---
>>  lib/utils/timer/fdt_timer_mtimer.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
>> index 9eaa11d..0ac9aed 100644
>> --- a/lib/utils/timer/fdt_timer_mtimer.c
>> +++ b/lib/utils/timer/fdt_timer_mtimer.c
>> @@ -146,6 +146,8 @@ static const struct fdt_match timer_mtimer_match[] = {
>>  	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
>>  	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
>>  	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
>> +	{ .compatible = "thead,c900-aclint-mtimer",
>> +	  .data = &thead_clint_quirks },
>
>This is wrong. When using separate mtimer/mswi nodes, there is no MMIO offset.
>So you need a new quirks structure for this compatible string.
>
>Regards,
>Samuel
>

Ok, I will add a new one.

>>  	{ .compatible = "riscv,aclint-mtimer" },
>>  	{ },
>>  };
>
>


From inochiama at outlook.com  Sun Oct  8 17:23:10 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Mon,  9 Oct 2023 08:23:10 +0800
Subject: [PATCH v2 1/4] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <IA1PR20MB4953B602556F31EC2EFDCAA4BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953B602556F31EC2EFDCAA4BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953CD4AE893CBB129A3F7AABBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>

>>On 2023-10-08 7:16 AM, Inochi Amaoto wrote:
>>> T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
>>> different address, which may cause a misuse if use the same compatible
>>> string, add a new timer compatible string to avoid this.
>>>
>>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>>> Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
>>> ---
>>>  lib/utils/timer/fdt_timer_mtimer.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
>>> index 9eaa11d..0ac9aed 100644
>>> --- a/lib/utils/timer/fdt_timer_mtimer.c
>>> +++ b/lib/utils/timer/fdt_timer_mtimer.c
>>> @@ -146,6 +146,8 @@ static const struct fdt_match timer_mtimer_match[] = {
>>>  	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
>>>  	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
>>>  	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
>>> +	{ .compatible = "thead,c900-aclint-mtimer",
>>> +	  .data = &thead_clint_quirks },
>>
>>This is wrong. When using separate mtimer/mswi nodes, there is no MMIO offset.
>>So you need a new quirks structure for this compatible string.
>>
>>Regards,
>>Samuel
>>
>
>Ok, I will add a new one.
>

Fix this may need to change the kernel dt-binding and dt.
FYI, Chen Wang.

>>>  	{ .compatible = "riscv,aclint-mtimer" },
>>>  	{ },
>>>  };
>>
>>


From inochiama at outlook.com  Sun Oct  8 17:24:57 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Mon,  9 Oct 2023 08:24:57 +0800
Subject: [PATCH v2 3/4] platform: Allow platform uses hart count as the size of tlb info
In-Reply-To: <8e44a0ba88a2cc25d5ad5254ec7db33b8e37cab8.camel@126.com>
References: <8e44a0ba88a2cc25d5ad5254ec7db33b8e37cab8.camel@126.com>
Message-ID: <IA1PR20MB4953025C9298EF3306D61100BBCEA@IA1PR20MB4953.namprd20.prod.outlook.com>

>? 2023-10-08???? 20:17 +0800?Inochi Amaoto???
>> For platform with high number of harts, it is better to auto detect a
>> suitable number of entries in tlb fifo. Since allocating tlb entry for
>> all online harts can reduce the wait time significantly, using the
>> number of the online harts can make most platforms happy. This auto
>> detection can avoid most duplicate code for setting tlb fifo size if
>> the hart count of platform is big.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> ---
>>  platform/generic/platform.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
>> index 66a0b77..9397afc 100644
>> --- a/platform/generic/platform.c
>> +++ b/platform/generic/platform.c
>> @@ -258,8 +258,15 @@ static u64 generic_tlbr_flush_limit(void)
>>
>>  static u32 generic_tlb_num_entries(void)
>>  {
>> +	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
>> +	u32 hart_count = sbi_platform_hart_count(plat);
>The two lines above can be replaced with:
>	u32 hart_count = sbi_scratch_last_hartindex() + 1;
>

Thx.

>If returning hart_count directly is appropriate, is it possible to remove
>SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES and generic_plat->tlb_num_entries?
>

I think replacing SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES with hart_count is
reasonable.
For the override functions, it gives a chance for platform to setting up
a new entry number. I suggest to perserve it, so the platform can define
its own if needed.

>This patch does not seem to belong to sg2042 and should be sent separately.
>

Yes, The only reason I added it is that sg2042 require the new default
value.

I will send it separately.

>Regards,
>Xiang W
>
>> +
>>  	if (generic_plat && generic_plat->tlb_num_entries)
>>  		return generic_plat->tlb_num_entries(generic_plat_match);
>> +
>> +	/* for platform with too many harts, use hart count instead */
>> +	if (hart_count > SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES)
>> +		return hart_count;
>>  	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
>>  }
>>


From guoren at kernel.org  Sun Oct  8 17:36:51 2023
From: guoren at kernel.org (Guo Ren)
Date: Mon, 9 Oct 2023 08:36:51 +0800
Subject: [PATCH v2 4/4] platform: generic: Add Sophgo sg2042 platform support
In-Reply-To: <IA1PR20MB4953994C9AA1CAE023E84E00BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953CAA2C31F07F9A1157EF7BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20231008121742.330012-1-inochiama@outlook.com> <IA1PR20MB4953994C9AA1CAE023E84E00BBCFA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTTWuMO5MVpieUQE=wvUSspLS_Md82T+GOvg-LoMrLphaQ@mail.gmail.com>

On Sun, Oct 8, 2023 at 8:17?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Add Sophgo sg2042 soc support
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  platform/generic/Kconfig           |  6 +++
>  platform/generic/configs/defconfig |  1 +
>  platform/generic/sophgo/objects.mk |  9 +++++
>  platform/generic/sophgo/sg2042.c   | 64 ++++++++++++++++++++++++++++++
>  4 files changed, 80 insertions(+)
>  create mode 100644 platform/generic/sophgo/objects.mk
>  create mode 100644 platform/generic/sophgo/sg2042.c
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index f9e7ed2..a902cf3 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
>         depends on FDT_RESET && FDT_I2C
>         default n
>
> +config PLATFORM_SOPHGO_SG2042
> +       bool "Sophgo sg2042 support"
> +       select THEAD_C9XX_ERRATA
> +       select THEAD_C9XX_PMU
> +       default n
> +
>  config PLATFORM_STARFIVE_JH7110
>         bool "StarFive JH7110 support"
>         default n
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index c432bc2..e1b76c8 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_SOPHGO_SG2042=y
>  CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_PLATFORM_THEAD=y
>  CONFIG_FDT_GPIO=y
> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
> new file mode 100644
> index 0000000..3d2908a
> --- /dev/null
> +++ b/platform/generic/sophgo/objects.mk
> @@ -0,0 +1,9 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
> +# Copyright (C) 2023 Alibaba Group Holding Limited.
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
> new file mode 100644
> index 0000000..af36eb2
> --- /dev/null
> +++ b/platform/generic/sophgo/sg2042.c
> @@ -0,0 +1,64 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Authors:
> + *   Inochi Amaoto <inochiama at outlook.com>
> + *
> + */
> +
> +#include <platform_override.h>
> +#include <thead/c9xx_errata.h>
> +#include <thead/c9xx_pmu.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_string.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/timer/aclint_mtimer.h>
> +
> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
> +
> +
> +static int sophgo_sg2042_early_init(bool cold_boot,
> +                                   const struct fdt_match *match)
> +{
> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
> +
> +       thead_register_tlb_flush_trap_handler();
> +
> +       /*
> +        * Sophgo sg2042 soc use seperate 16 timers while initiating,
Typo: separate

After fixed:

Reviewed-by: Guo Ren <guoren at kernel.org>

> +        * merge them as a single domain to avoid wasting.
> +        */
> +       if (cold_boot)
> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
> +                                               SOPHGO_SG2042_TIMER_SIZE *
> +                                               sbi_platform_hart_count(plat),
> +                                               MTIMER_REGION_ALIGN,
> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
> +
> +
> +       return 0;
> +}
> +
> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
> +                                        struct sbi_hart_features *hfeatures)
> +{
> +       thead_c9xx_register_pmu_device();
> +       return 0;
> +}
> +
> +static const struct fdt_match sophgo_sg2042_match[] = {
> +       { .compatible = "sophgo,sg2042" },
> +       { },
> +};
> +
> +const struct platform_override sophgo_sg2042 = {
> +       .match_table            = sophgo_sg2042_match,
> +       .early_init             = sophgo_sg2042_early_init,
> +       .extensions_init        = sophgo_sg2042_extensions_init,
> +};
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From anup at brainfault.org  Mon Oct  9 01:25:47 2023
From: anup at brainfault.org (Anup Patel)
Date: Mon, 9 Oct 2023 13:55:47 +0530
Subject: [PATCH] lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP
In-Reply-To: <20231001091226.592084-1-amanieu@gmail.com>
References: <20231001091226.592084-1-amanieu@gmail.com>
Message-ID: <CAAhSdy0Ut=A2T02FauaH=fZqpX8XosUt_fCMXbm0WhAW2sECPw@mail.gmail.com>

On Sun, Oct 1, 2023 at 2:43?PM Amanieu d'Antras <amanieu at gmail.com> wrote:
>
> Unlike C.LWSP/C.LDSP, these encodings can be used with the zero
> register, so checking that the rs2 field is non-zero is unnecessary.
>
> Additionally, the previous check was incorrect since it was checking the
> immediate field of the instruction instead of the rs2 field.
>
> Signed-off-by: Amanieu d'Antras <amanieu at gmail.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Regards,
Anup

> ---
>  lib/sbi/sbi_misaligned_ldst.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c
> index 4b91e07..aa512de 100644
> --- a/lib/sbi/sbi_misaligned_ldst.c
> +++ b/lib/sbi/sbi_misaligned_ldst.c
> @@ -211,16 +211,14 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
>         } else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
>                 len            = 8;
>                 val.data_ulong = GET_RS2S(insn, regs);
> -       } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
> -                  ((insn >> SH_RD) & 0x1f)) {
> +       } else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {
>                 len            = 8;
>                 val.data_ulong = GET_RS2C(insn, regs);
>  #endif
>         } else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
>                 len            = 4;
>                 val.data_ulong = GET_RS2S(insn, regs);
> -       } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
> -                  ((insn >> SH_RD) & 0x1f)) {
> +       } else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {
>                 len            = 4;
>                 val.data_ulong = GET_RS2C(insn, regs);
>  #ifdef __riscv_flen
> --
> 2.42.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Oct  9 01:36:52 2023
From: anup at brainfault.org (Anup Patel)
Date: Mon, 9 Oct 2023 14:06:52 +0530
Subject: [PATCH 0/3] Sparse HART id improvements
In-Reply-To: <6ce921ad7d4ff85737d4605163e70abb451f910c.camel@126.com>
References: <20230924155745.1753120-1-wxjstz@126.com> <CAAhSdy2iZruS48CqB9UDiaqL57KD7zX+DxsC-M8ArmxX8soWzg@mail.gmail.com>
 <6ce921ad7d4ff85737d4605163e70abb451f910c.camel@126.com>
Message-ID: <CAAhSdy119qy6zksV6ofVf_iy1nTJsGTwNNhKEUiFqNYjaL+fEw@mail.gmail.com>

On Sat, Oct 7, 2023 at 9:19?AM Xiang W <wxjstz at 126.com> wrote:
>
> ? 2023-10-06???? 10:05 +0530?Anup Patel???
> > On Sun, Sep 24, 2023 at 9:28?PM Xiang W <wxjstz at 126.com> wrote:
> > >
> > > Modify last_hartindex_having_scratch/hartindex_to_hartid_table
> > > /hartindex_to_scratch_table as static variables to prevent accidental
> > > modification and reduce memory consumption
> > >
> > > Xiang W (3):
> > >   lib: sbi: Refactor sbi_scratch_last_hartindex as a function
> > >   lib: sbi: Refactor sbi_hartindex_to_hartid as a function
> > >   lib: sbi: Refactor sbi_hartindex_to_scratch as a function
> >
> > All these are in hot-path at various places so introducing a
> > function is certainly not helping.
> >
> > Also, if some buggy code is accidentally modifying global data
> > then that buggy code should be fixed rather than papering over
> > the problem by introducing these functions.
> PATCH1:
> The original code is a bit strange in that there is already a global variable
> last_hartindex_having_scratch, but instead of using it outside of sbi_scratch.c,
> the macro sbi_scratch_last_hartindex is used. If don't want to modify this macro
> into a function, why not just change the name of the last_hartindex_having_scratch
> renamed to sbi_scratch_last_hartindex and then remove the macro?

The sbi_scratch_last_hartindex() macro allows adding instrumentation
code for debugging purposes. The caller of sbi_scratch_last_hartindex()
should not care about how it is implemented.

>
> PATCH2:
> The arrays hartindex_to_hartid_table and plat->hart_index2id store similar content,
> and the extra length of the hartindex_to_hartid_table array is not used because
> there is a determination of whether the index is less than sbi_scratch_last_ hartindex.
> the array can be removed by adding just a little bit of checking.

The "plat->hart_index2id" is optional and can be NULL as well so
we have to always use "if ()" before accessing "plat->hart_index2id".

Also, we always have to access "hart_index2id[]" via "plat" pointer
which is slower compared to a global array like "hartindex_to_hartid_table[]".

Regards,
Anup

>
> Regards,
> Xiang W
> >
> > Regards,
> > Anup
> >
> > >
> > >  include/sbi/sbi_scratch.h | 35 ++++++++++++-----------------------
> > >  lib/sbi/sbi_scratch.c     | 30 ++++++++++++++++++++++++++----
> > >  2 files changed, 38 insertions(+), 27 deletions(-)
> > >
> > > --
> > > 2.40.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
>


From anup at brainfault.org  Mon Oct  9 01:53:01 2023
From: anup at brainfault.org (Anup Patel)
Date: Mon, 9 Oct 2023 14:23:01 +0530
Subject: [PATCH] lib: sbi: Add sub-regions check for sanitizing domain
In-Reply-To: <IA1PR20MB4953ECE2BD5CA00E14EFE892BBF1A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953ECE2BD5CA00E14EFE892BBF1A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAAhSdy1hGgvXQ4HNxYcHd56vT2sXqYNuQXFyVk7GUksgDFukHg@mail.gmail.com>

On Tue, Sep 12, 2023 at 5:42?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> As the domain will reject a new memory region which has a sub-regions
> already in the domain, even the new region is bigger and has the same
> flags. This problem can be solved by relaxing region restriction and
> rechecking when adding and sanitizing domains.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  lib/sbi/sbi_domain.c | 86 ++++++++++++++++++++++++++++++--------------
>  1 file changed, 59 insertions(+), 27 deletions(-)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index acd0f74..8c6cbfe 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -193,20 +193,19 @@ static bool is_region_subset(const struct sbi_domain_memregion *regA,
>         ulong regB_end = regB->base + (BIT(regB->order) - 1);
>
>         if ((regB_start <= regA_start) &&
> -           (regA_start < regB_end) &&
> -           (regB_start < regA_end) &&
> +           (regB_start <= regA_end) &&
> +           (regA_start <= regB_end) &&
>             (regA_end <= regB_end))

The above needs to be a separate patch since it is improving
is_region_subset().

>                 return true;
>
>         return false;
>  }
>
> -/** Check if regionA conflicts regionB */
> -static bool is_region_conflict(const struct sbi_domain_memregion *regA,
> -                               const struct sbi_domain_memregion *regB)
> +/** Check if regionA can be replaced by regionB */
> +static bool is_region_compatible(const struct sbi_domain_memregion *regA,
> +                                const struct sbi_domain_memregion *regB)
>  {
> -       if ((is_region_subset(regA, regB) || is_region_subset(regB, regA)) &&
> -           regA->flags == regB->flags)
> +       if (is_region_subset(regA, regB) && regA->flags == regB->flags)
>                 return true;
>
>         return false;
> @@ -264,11 +263,26 @@ static const struct sbi_domain_memregion *find_next_subset_region(
>         return ret;
>  }
>
> +static void swap_region(struct sbi_domain_memregion* reg1,
> +                       struct sbi_domain_memregion* reg2)
> +{
> +       struct sbi_domain_memregion treg;
> +
> +       sbi_memcpy(&treg, reg1, sizeof(treg));
> +       sbi_memcpy(reg1, reg2, sizeof(treg));
> +       sbi_memcpy(reg2, &treg, sizeof(treg));
> +}

Introducing swap_region() should also be a separate patch.

> +
> +static void clear_region(struct sbi_domain_memregion* reg)
> +{
> +       sbi_memset(reg, 0x0, sizeof(*reg));
> +}
> +
>  static int sanitize_domain(const struct sbi_platform *plat,
>                            struct sbi_domain *dom)
>  {
>         u32 i, j, count;
> -       struct sbi_domain_memregion treg, *reg, *reg1;
> +       struct sbi_domain_memregion *reg, *reg1;
>
>         /* Check possible HARTs */
>         if (!dom->possible_harts) {
> @@ -312,28 +326,50 @@ static int sanitize_domain(const struct sbi_platform *plat,
>                 return SBI_EINVAL;
>         }
>
> +       /* Remove covered regions */
> +       while(i < (count - 1)) {
> +               reg = &dom->regions[i];
> +               j = i + 1;
> +               while (j < count) {
> +                       reg1 = &dom->regions[j];
> +
> +                       /* reg1 is sub-region of reg, remove reg1 */
> +                       if (is_region_compatible(reg1, reg)) {
> +                               swap_region(reg1, &dom->regions[count - 1]);
> +                               clear_region(&dom->regions[count - 1]);
> +                               count--;
> +                               continue;
> +                       }
> +
> +                       /*
> +                        * reg is sub-region of reg1, replace reg with reg1
> +                        * and recheck all other regions.
> +                        */
> +                       if (is_region_compatible(reg, reg1)) {
> +                               swap_region(reg, reg1);
> +                               swap_region(reg1, &dom->regions[count - 1]);
> +                               clear_region(&dom->regions[count - 1]);
> +                               count--;
> +                               goto regions_recheck;
> +                       }
> +
> +                       j++;
> +               }
> +
> +               i++;
> +regions_recheck:
> +       }
> +
>         /* Sort the memory regions */
>         for (i = 0; i < (count - 1); i++) {
>                 reg = &dom->regions[i];
>                 for (j = i + 1; j < count; j++) {
>                         reg1 = &dom->regions[j];
>
> -                       if (is_region_conflict(reg1, reg)) {
> -                               sbi_printf("%s: %s conflict between regions "
> -                                       "(base=0x%lx order=%lu flags=0x%lx) and "
> -                                       "(base=0x%lx order=%lu flags=0x%lx)\n",
> -                                       __func__, dom->name,
> -                                       reg->base, reg->order, reg->flags,
> -                                       reg1->base, reg1->order, reg1->flags);
> -                               return SBI_EINVAL;
> -                       }
> -
>                         if (!is_region_before(reg1, reg))
>                                 continue;
>
> -                       sbi_memcpy(&treg, reg1, sizeof(treg));
> -                       sbi_memcpy(reg1, reg, sizeof(treg));
> -                       sbi_memcpy(reg, &treg, sizeof(treg));
> +                       swap_region(reg, reg1);
>                 }
>         }
>
> @@ -578,12 +614,8 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
>
>         /* Check for conflicts */
>         sbi_domain_for_each_memregion(&root, nreg) {
> -               if (is_region_conflict(reg, nreg)) {
> -                       sbi_printf("%s: is_region_conflict check failed"
> -                       " 0x%lx conflicts existing 0x%lx\n", __func__,
> -                                  reg->base, nreg->base);
> -                       return SBI_EALREADY;
> -               }
> +               if (is_region_compatible(reg, nreg))
> +                       return 0;
>         }
>
>         /* Append the memregion to root memregions */
> --
> 2.42.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

The remaining changes should be a separate patch itself.

Please convert this patch into a small series as suggested above.

Regards,
Anup


From wxjstz at 126.com  Mon Oct  9 02:22:02 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon,  9 Oct 2023 17:22:02 +0800
Subject: [PATCH] lib: sbi: Improve hartindex_to_hartid_table
Message-ID: <20231009092202.267633-1-wxjstz@126.com>

Modify hartindex_to_hartid_table point to plat->hart_index2id to
save memory. This slows down sbi_hartindex_to_hartid slightly
because it needs to determine whether hartindex_to_hartid_table is
NULL. This will also improve the speed of sbi_hartid_to_hartindex
when plat->hart_index2id is NULL, since there is no need to iterate
through the array.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_scratch.h | 13 ++++++++-----
 lib/sbi/sbi_scratch.c     |  7 +++++--
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index e6a33ba..02db224 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -213,13 +213,16 @@ extern u32 last_hartindex_having_scratch;
 (((__hartindex) <= sbi_scratch_last_hartindex()) ? true : false)
 
 /** HART index to HART id table */
-extern u32 hartindex_to_hartid_table[];
+extern const u32* hartindex_to_hartid_table;
 
 /** Get sbi_scratch from HART index */
-#define sbi_hartindex_to_hartid(__hartindex)		\
-({							\
-	((__hartindex) <= sbi_scratch_last_hartindex()) ?\
-	hartindex_to_hartid_table[__hartindex] : -1U;	\
+#define sbi_hartindex_to_hartid(__hartindex)			\
+({								\
+	((__hartindex) <= sbi_scratch_last_hartindex()) ?	\
+		(hartindex_to_hartid_table ?			\
+			hartindex_to_hartid_table[__hartindex] :\
+			__hartindex) :				\
+		-1U;						\
 })
 
 /** HART index to scratch table */
diff --git a/lib/sbi/sbi_scratch.c b/lib/sbi/sbi_scratch.c
index ccbbc68..e097077 100644
--- a/lib/sbi/sbi_scratch.c
+++ b/lib/sbi/sbi_scratch.c
@@ -15,7 +15,7 @@
 #include <sbi/sbi_string.h>
 
 u32 last_hartindex_having_scratch = 0;
-u32 hartindex_to_hartid_table[SBI_HARTMASK_MAX_BITS + 1] = { -1U };
+const u32 *hartindex_to_hartid_table;
 struct sbi_scratch *hartindex_to_scratch_table[SBI_HARTMASK_MAX_BITS + 1] = { 0 };
 
 static spinlock_t extra_lock = SPIN_LOCK_INITIALIZER;
@@ -25,6 +25,9 @@ u32 sbi_hartid_to_hartindex(u32 hartid)
 {
 	u32 i;
 
+	if (hartindex_to_hartid_table == NULL)
+		return hartid;
+
 	for (i = 0; i <= last_hartindex_having_scratch; i++)
 		if (hartindex_to_hartid_table[i] == hartid)
 			return i;
@@ -41,11 +44,11 @@ int sbi_scratch_init(struct sbi_scratch *scratch)
 
 	for (i = 0; i < plat->hart_count; i++) {
 		h = (plat->hart_index2id) ? plat->hart_index2id[i] : i;
-		hartindex_to_hartid_table[i] = h;
 		hartindex_to_scratch_table[i] =
 			((hartid2scratch)scratch->hartid_to_scratch)(h, i);
 	}
 
+	hartindex_to_hartid_table = plat->hart_index2id;
 	last_hartindex_having_scratch = plat->hart_count - 1;
 
 	return 0;
-- 
2.40.1



From wxjstz at 126.com  Mon Oct  9 02:25:09 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 09 Oct 2023 17:25:09 +0800
Subject: [PATCH 0/3] Sparse HART id improvements
In-Reply-To: <CAAhSdy119qy6zksV6ofVf_iy1nTJsGTwNNhKEUiFqNYjaL+fEw@mail.gmail.com>
References: <20230924155745.1753120-1-wxjstz@126.com>
	 <CAAhSdy2iZruS48CqB9UDiaqL57KD7zX+DxsC-M8ArmxX8soWzg@mail.gmail.com>
	 <6ce921ad7d4ff85737d4605163e70abb451f910c.camel@126.com>
	 <CAAhSdy119qy6zksV6ofVf_iy1nTJsGTwNNhKEUiFqNYjaL+fEw@mail.gmail.com>
Message-ID: <dee74ff21f4e73f7394d541361a3f65cc35adebe.camel@126.com>

? 2023-10-09???? 14:06 +0530?Anup Patel???
> On Sat, Oct 7, 2023 at 9:19?AM Xiang W <wxjstz at 126.com> wrote:
> > 
> > ? 2023-10-06???? 10:05 +0530?Anup Patel???
> > > On Sun, Sep 24, 2023 at 9:28?PM Xiang W <wxjstz at 126.com> wrote:
> > > > 
> > > > Modify last_hartindex_having_scratch/hartindex_to_hartid_table
> > > > /hartindex_to_scratch_table as static variables to prevent accidental
> > > > modification and reduce memory consumption
> > > > 
> > > > Xiang W (3):
> > > > ? lib: sbi: Refactor sbi_scratch_last_hartindex as a function
> > > > ? lib: sbi: Refactor sbi_hartindex_to_hartid as a function
> > > > ? lib: sbi: Refactor sbi_hartindex_to_scratch as a function
> > > 
> > > All these are in hot-path at various places so introducing a
> > > function is certainly not helping.
> > > 
> > > Also, if some buggy code is accidentally modifying global data
> > > then that buggy code should be fixed rather than papering over
> > > the problem by introducing these functions.
> > PATCH1:
> > The original code is a bit strange in that there is already a global variable
> > last_hartindex_having_scratch, but instead of using it outside of sbi_scratch.c,
> > the macro sbi_scratch_last_hartindex is used. If don't want to modify this macro
> > into a function, why not just change the name of the last_hartindex_having_scratch
> > renamed to sbi_scratch_last_hartindex and then remove the macro?
> 
> The sbi_scratch_last_hartindex() macro allows adding instrumentation
> code for debugging purposes. The caller of sbi_scratch_last_hartindex()
> should not care about how it is implemented.
> 
> > 
> > PATCH2:
> > The arrays hartindex_to_hartid_table and plat->hart_index2id store similar content,
> > and the extra length of the hartindex_to_hartid_table array is not used because
> > there is a determination of whether the index is less than sbi_scratch_last_ hartindex.
> > the array can be removed by adding just a little bit of checking.
> 
> The "plat->hart_index2id" is optional and can be NULL as well so
> we have to always use "if ()" before accessing "plat->hart_index2id".
> 
> Also, we always have to access "hart_index2id[]" via "plat" pointer
> which is slower compared to a global array like "hartindex_to_hartid_table[]".
My expression may not be very accurate, please review my code.
https://lists.infradead.org/pipermail/opensbi/2023-October/005703.html

Regards,
Xiang W
> 
> Regards,
> Anup
> 
> > 
> > Regards,
> > Xiang W
> > > 
> > > Regards,
> > > Anup
> > > 
> > > > 
> > > > ?include/sbi/sbi_scratch.h | 35 ++++++++++++-----------------------
> > > > ?lib/sbi/sbi_scratch.c???? | 30 ++++++++++++++++++++++++++----
> > > > ?2 files changed, 38 insertions(+), 27 deletions(-)
> > > > 
> > > > --
> > > > 2.40.1
> > > > 
> > > > 
> > > > --
> > > > opensbi mailing list
> > > > opensbi at lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/opensbi
> > 



From inochiama at outlook.com  Mon Oct  9 17:59:22 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Tue, 10 Oct 2023 08:59:22 +0800
Subject: [PATCH v2 0/3] lib: sbi: Add sub-regions check for sanitizing domain
Message-ID: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>

As the domain will reject a new memory region which has a sub-regions
already in the domain, even the new region is bigger and has the same
flags.

To resolve this problem, just relax restriction of memory region when
adding it, and merge the region into the existed domain regions when
sorting regions.

Changed from v1:
1. separate the patch into three parts.

Inochi Amaoto (3):
  lib: sbi: separate the swap operation of domain region
  lib: sbi: add more restriction to domain region subset check
  lib: sbi: Add regions merging when sanitizing domain region

 lib/sbi/sbi_domain.c | 86 ++++++++++++++++++++++++++++++--------------
 1 file changed, 59 insertions(+), 27 deletions(-)

--
2.42.0



From inochiama at outlook.com  Mon Oct  9 18:00:23 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Tue, 10 Oct 2023 09:00:23 +0800
Subject: [PATCH v2 1/3] lib: sbi: separate the swap operation of domain region
In-Reply-To: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB49533CD1EAD7784957CF4361BBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>

Swapping domain region is a common operation when sorting domain region,
so separate it as a function to make code clean.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/sbi/sbi_domain.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index fd4a296..283b598 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -256,11 +256,21 @@ static const struct sbi_domain_memregion *find_next_subset_region(
 	return ret;
 }
 
+static void swap_region(struct sbi_domain_memregion* reg1,
+			struct sbi_domain_memregion* reg2)
+{
+	struct sbi_domain_memregion treg;
+
+	sbi_memcpy(&treg, reg1, sizeof(treg));
+	sbi_memcpy(reg1, reg2, sizeof(treg));
+	sbi_memcpy(reg2, &treg, sizeof(treg));
+}
+
 static int sanitize_domain(const struct sbi_platform *plat,
 			   struct sbi_domain *dom)
 {
 	u32 i, j, count;
-	struct sbi_domain_memregion treg, *reg, *reg1;
+	struct sbi_domain_memregion *reg, *reg1;
 
 	/* Check possible HARTs */
 	if (!dom->possible_harts) {
@@ -324,9 +334,7 @@ static int sanitize_domain(const struct sbi_platform *plat,
 			if (!is_region_before(reg1, reg))
 				continue;
 
-			sbi_memcpy(&treg, reg1, sizeof(treg));
-			sbi_memcpy(reg1, reg, sizeof(treg));
-			sbi_memcpy(reg, &treg, sizeof(treg));
+			swap_region(reg, reg1);
 		}
 	}
 
-- 
2.42.0



From inochiama at outlook.com  Mon Oct  9 18:00:24 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Tue, 10 Oct 2023 09:00:24 +0800
Subject: [PATCH v2 2/3] lib: sbi: add more restriction to domain region subset check
In-Reply-To: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB495351E19560D833EAC11BC8BBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>

make is_region_subset() check the bound of the domain region, so it can
handle the domain region with the same base and length.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/sbi/sbi_domain.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 283b598..2b9d16f 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -185,8 +185,8 @@ static bool is_region_subset(const struct sbi_domain_memregion *regA,
 	ulong regB_end = regB->base + (BIT(regB->order) - 1);
 
 	if ((regB_start <= regA_start) &&
-	    (regA_start < regB_end) &&
-	    (regB_start < regA_end) &&
+	    (regB_start <= regA_end) &&
+	    (regA_start <= regB_end) &&
 	    (regA_end <= regB_end))
 		return true;
 
-- 
2.42.0



From inochiama at outlook.com  Mon Oct  9 18:00:25 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Tue, 10 Oct 2023 09:00:25 +0800
Subject: [PATCH v2 3/3] lib: sbi: Add regions merging when sanitizing domain region
In-Reply-To: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533A7AB5888E0117F7799BBBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953272F8B5C9000CDA69F02BBCDA@IA1PR20MB4953.namprd20.prod.outlook.com>

As the domain will reject a new memory region which has a sub-regions
already in the domain, even the new region is bigger and has the same
flags. This problem can be solved by relaxing region restriction and
rechecking when adding and sanitizing domains.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/sbi/sbi_domain.c | 66 ++++++++++++++++++++++++++++++--------------
 1 file changed, 45 insertions(+), 21 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 2b9d16f..9e9cdad 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -193,12 +193,11 @@ static bool is_region_subset(const struct sbi_domain_memregion *regA,
 	return false;
 }
 
-/** Check if regionA conflicts regionB */
-static bool is_region_conflict(const struct sbi_domain_memregion *regA,
-				const struct sbi_domain_memregion *regB)
+/** Check if regionA can be replaced by regionB */
+static bool is_region_compatible(const struct sbi_domain_memregion *regA,
+				 const struct sbi_domain_memregion *regB)
 {
-	if ((is_region_subset(regA, regB) || is_region_subset(regB, regA)) &&
-	    regA->flags == regB->flags)
+	if (is_region_subset(regA, regB) && regA->flags == regB->flags)
 		return true;
 
 	return false;
@@ -266,6 +265,11 @@ static void swap_region(struct sbi_domain_memregion* reg1,
 	sbi_memcpy(reg2, &treg, sizeof(treg));
 }
 
+static void clear_region(struct sbi_domain_memregion* reg)
+{
+	sbi_memset(reg, 0x0, sizeof(*reg));
+}
+
 static int sanitize_domain(const struct sbi_platform *plat,
 			   struct sbi_domain *dom)
 {
@@ -315,22 +319,46 @@ static int sanitize_domain(const struct sbi_platform *plat,
 		return SBI_EINVAL;
 	}
 
+	/* Remove covered regions */
+	while(i < (count - 1)) {
+		reg = &dom->regions[i];
+		j = i + 1;
+		while (j < count) {
+			reg1 = &dom->regions[j];
+
+			/* reg1 is sub-region of reg, remove reg1 */
+			if (is_region_compatible(reg1, reg)) {
+				swap_region(reg1, &dom->regions[count - 1]);
+				clear_region(&dom->regions[count - 1]);
+				count--;
+				continue;
+			}
+
+			/*
+			 * reg is sub-region of reg1, replace reg with reg1
+			 * and recheck all other regions.
+			 */
+			if (is_region_compatible(reg, reg1)) {
+				swap_region(reg, reg1);
+				swap_region(reg1, &dom->regions[count - 1]);
+				clear_region(&dom->regions[count - 1]);
+				count--;
+				goto regions_recheck;
+			}
+
+			j++;
+		}
+
+		i++;
+regions_recheck:
+	}
+
 	/* Sort the memory regions */
 	for (i = 0; i < (count - 1); i++) {
 		reg = &dom->regions[i];
 		for (j = i + 1; j < count; j++) {
 			reg1 = &dom->regions[j];
 
-			if (is_region_conflict(reg1, reg)) {
-				sbi_printf("%s: %s conflict between regions "
-					"(base=0x%lx order=%lu flags=0x%lx) and "
-					"(base=0x%lx order=%lu flags=0x%lx)\n",
-					__func__, dom->name,
-					reg->base, reg->order, reg->flags,
-					reg1->base, reg1->order, reg1->flags);
-				return SBI_EINVAL;
-			}
-
 			if (!is_region_before(reg1, reg))
 				continue;
 
@@ -581,12 +609,8 @@ int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg)
 
 	/* Check for conflicts */
 	sbi_domain_for_each_memregion(&root, nreg) {
-		if (is_region_conflict(reg, nreg)) {
-			sbi_printf("%s: is_region_conflict check failed"
-			" 0x%lx conflicts existing 0x%lx\n", __func__,
-				   reg->base, nreg->base);
-			return SBI_EALREADY;
-		}
+		if (is_region_compatible(reg, nreg))
+			return 0;
 	}
 
 	/* Append the memregion to root memregions */
-- 
2.42.0



From peterlin at andestech.com  Mon Oct  9 23:09:47 2023
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Tue, 10 Oct 2023 14:09:47 +0800
Subject: [PATCH 0/6] Add Andes PMU extension support
In-Reply-To: <CA+V-a8uDWwyf51ZTyi3_wGu8_9JNqudDTAQ2pS95oBa+VcYYdg@mail.gmail.com>
References: <20230906111455.4161641-1-peterlin@andestech.com>
 <CA+V-a8uDWwyf51ZTyi3_wGu8_9JNqudDTAQ2pS95oBa+VcYYdg@mail.gmail.com>
Message-ID: <ZSTqq-lncdC31iPw@APC323>

On Fri, Oct 06, 2023 at 01:20:27PM +0100, Lad, Prabhakar wrote:
> Hi Lin-san,
> 
> On Wed, Sep 6, 2023 at 12:17?PM Yu Chien Peter Lin
> <peterlin at andestech.com> wrote:
> >
> > This patch series enables perf tool to utilize Andes PMU
> > extension via PMU SBI calls, provides PMU device callbacks
> > for event sampling and mode filtering.
> >
> > We also provide a PMU node example of AX45MP in the last
> > patch.
> >
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support
> > - https://github.com/andestech/linux/commits/andes-pmu-support
> >
> > Yu Chien Peter Lin (6):
> >   sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> >   platform: include: andes45: Add PMU related CSR defines
> >   platform: andes: Add Andes custom PMU support
> >   platform: andes: Enable Andes PMU for AE350
> >   platform: rzfive: Enable Andes PMU for RZ/Five
> >   docs: pmu: Add Andes PMU node example
> >
> >  docs/pmu_support.md                        | 87 ++++++++++++++++++++++
> >  include/sbi/sbi_pmu.h                      |  6 ++
> >  lib/sbi/sbi_pmu.c                          |  5 +-
> >  platform/generic/Kconfig                   |  2 +
> >  platform/generic/andes/Kconfig             |  4 +
> >  platform/generic/andes/ae350.c             |  2 +
> >  platform/generic/andes/andes_pmu.c         | 85 +++++++++++++++++++++
> >  platform/generic/andes/objects.mk          |  1 +
> >  platform/generic/include/andes/andes45.h   | 26 +++++++
> >  platform/generic/include/andes/andes_pmu.h | 12 +++
> >  platform/generic/renesas/rzfive/rzfive.c   |  2 +
> >  11 files changed, 231 insertions(+), 1 deletion(-)
> >  create mode 100644 platform/generic/andes/andes_pmu.c
> >  create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> I tried these patches on the RZ/Five SMARC EVK and I am seeing kernel
> freeze when trying to quit perf.

Thanks for reporting, this happens on my Tinker-V board as well.
I will look into this issue.

Thanks,
Peter Lin

> Cheers,
> Prabhakar


From apatel at ventanamicro.com  Tue Oct 10 03:21:25 2023
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 10 Oct 2023 15:51:25 +0530
Subject: [PATCH] include: sbi: Change spec version to 2.0
Message-ID: <20231010102125.603343-1-apatel@ventanamicro.com>

Now that SBI v2.0 specification is frozen, we change spec verion
implemented by OpenSBI to v2.0.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_ecall.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/sbi/sbi_ecall.h b/include/sbi/sbi_ecall.h
index 90f33ba..027213c 100644
--- a/include/sbi/sbi_ecall.h
+++ b/include/sbi/sbi_ecall.h
@@ -13,7 +13,7 @@
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_list.h>
 
-#define SBI_ECALL_VERSION_MAJOR		1
+#define SBI_ECALL_VERSION_MAJOR		2
 #define SBI_ECALL_VERSION_MINOR		0
 #define SBI_OPENSBI_IMPID		1
 
-- 
2.34.1



From inochiama at outlook.com  Wed Oct 11 16:25:08 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 07:25:08 +0800
Subject: [PATCH] lib: utils/fdt: Allow zero length mtime when parsing ACLINT
Message-ID: <IA1PR20MB4953C5601F0B167904D68D5FBBCCA@IA1PR20MB4953.namprd20.prod.outlook.com>

Currently, the fdt_parse_aclint_node() does not allow the first reg to
be zero length. This may cause the parser to fail when the ACLINT does
not support mtime.

To be robust, delay the check of first reg in fdt_parse_aclint_node()
so the parser can handle ACLINT without mtime support.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/utils/fdt/fdt_helper.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index c97f09d..6b4ef38 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -897,8 +897,10 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !reg_size)
+	if (rc < 0)
 		return SBI_ENODEV;
+	if (!reg_size)
+		reg_addr = reg_size = 0;
 	*out_addr1 = reg_addr;
 	*out_size1 = reg_size;
 
@@ -906,6 +908,8 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
 				    &reg_addr, &reg_size);
 	if (rc < 0 || !reg_size)
 		reg_addr = reg_size = 0;
+	if (!reg_addr && *out_size1 == 0)
+		return SBI_ENODEV;
 	if (out_addr2)
 		*out_addr2 = reg_addr;
 	if (out_size2)
-- 
2.42.0



From inochiama at outlook.com  Wed Oct 11 18:54:18 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 09:54:18 +0800
Subject: [PATCH] platform: generic: thead: improve tlb flush errata
Message-ID: <IA1PR20MB49530A123B23DFFED0CC3E06BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

Flushing the tlb entries can solve the thead tlb problem, but flushing
it by address will miss something and lead to a exception in some rare
cases, and this is more common for sg2042.

To solve this problem, flush the tlb entries by asid in the custom trap
handler to ensure it is refreshed.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
This patch based on the th1520 series patch.
---
 platform/generic/thead/thead_c9xx_tlb_trap_handler.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/platform/generic/thead/thead_c9xx_tlb_trap_handler.S b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
index 861c029..120daa7 100644
--- a/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
+++ b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
@@ -9,5 +9,5 @@
 	.align 3
 	.globl _thead_tlb_flush_fixup_trap_handler
 _thead_tlb_flush_fixup_trap_handler:
-	sfence.vma t0, zero
+	sfence.vma zero, t0
 	j _trap_handler
--
2.42.0



From wxjstz at 126.com  Wed Oct 11 20:27:07 2023
From: wxjstz at 126.com (Xiang W)
Date: Thu, 12 Oct 2023 11:27:07 +0800
Subject: [PATCH] lib: utils/fdt: Allow zero length mtime when parsing
 ACLINT
In-Reply-To: <IA1PR20MB4953C5601F0B167904D68D5FBBCCA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953C5601F0B167904D68D5FBBCCA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <77f4664efaa5f974e70f2b7f5be46eb37aad2750.camel@126.com>

? 2023-10-12???? 07:25 +0800?Inochi Amaoto???
> Currently, the fdt_parse_aclint_node() does not allow the first reg to
> be zero length. This may cause the parser to fail when the ACLINT does
> not support mtime.
> 
> To be robust, delay the check of first reg in fdt_parse_aclint_node()
> so the parser can handle ACLINT without mtime support.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> ?lib/utils/fdt/fdt_helper.c | 6 +++++-
> ?1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index c97f09d..6b4ef38 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -897,8 +897,10 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
> ?
> ?	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
> ?				??? &reg_addr, &reg_size);
> -	if (rc < 0 || !reg_size)
> +	if (rc < 0)
> ?		return SBI_ENODEV;
> +	if (!reg_size)
> +		reg_addr = reg_size = 0;
If abandon checking reg_size here, should add a check where this function
is called. Because reg_size=0 is only legal under without_mtime.

Regards,
Xiang W
> ?	*out_addr1 = reg_addr;
> ?	*out_size1 = reg_size;
> ?
> @@ -906,6 +908,8 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
> ?				??? &reg_addr, &reg_size);
> ?	if (rc < 0 || !reg_size)
> ?		reg_addr = reg_size = 0;
> +	if (!reg_addr && *out_size1 == 0)
> +		return SBI_ENODEV;

> ?	if (out_addr2)
> ?		*out_addr2 = reg_addr;
> ?	if (out_size2)
> -- 
> 2.42.0
> 
> 



From inochiama at outlook.com  Wed Oct 11 20:29:29 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 11:29:29 +0800
Subject: [PATCH] platform: Uses hart count as the default size of tlb info
Message-ID: <IA1PR20MB4953569FCD95E4E40FC6A4CABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

For platform with high number of harts, it is better to auto detect a
suitable number of entries in tlb fifo. Since allocating tlb entry for
all online harts can reduce the wait time significantly, using the
number of the online harts can make most platforms happy. This auto
detection can avoid most duplicate code for setting tlb fifo size.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 platform/generic/platform.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..4246efd 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -260,7 +260,7 @@ static u32 generic_tlb_num_entries(void)
 {
 	if (generic_plat && generic_plat->tlb_num_entries)
 		return generic_plat->tlb_num_entries(generic_plat_match);
-	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
+	return sbi_scratch_last_hartindex() + 1;
 }
 
 static int generic_pmu_init(void)
-- 
2.42.0



From wxjstz at 126.com  Wed Oct 11 20:59:39 2023
From: wxjstz at 126.com (Xiang W)
Date: Thu, 12 Oct 2023 11:59:39 +0800
Subject: [PATCH] platform: Uses hart count as the default size of tlb
 info
In-Reply-To: <IA1PR20MB4953569FCD95E4E40FC6A4CABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953569FCD95E4E40FC6A4CABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <6397376c06e557760bfa0e383058ca08e3bd812c.camel@126.com>

? 2023-10-12???? 11:29 +0800?Inochi Amaoto???
> For platform with high number of harts, it is better to auto detect a
> suitable number of entries in tlb fifo. Since allocating tlb entry for
> all online harts can reduce the wait time significantly, using the
> number of the online harts can make most platforms happy. This auto
> detection can avoid most duplicate code for setting tlb fifo size.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Missing fix for sbi_platform_tlb_fifo_num_entries. Then remove?
SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES.

Regards,
Xiang W

> ---
> ?platform/generic/platform.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 66a0b77..4246efd 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -260,7 +260,7 @@ static u32 generic_tlb_num_entries(void)
> ?{
> ?	if (generic_plat && generic_plat->tlb_num_entries)
> ?		return generic_plat->tlb_num_entries(generic_plat_match);
> -	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> +	return sbi_scratch_last_hartindex() + 1;
> ?}
> ?
> ?static int generic_pmu_init(void)
> -- 
> 2.42.0
> 
> 



From guoren at kernel.org  Wed Oct 11 23:23:32 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 14:23:32 +0800
Subject: [PATCH] platform: generic: thead: improve tlb flush errata
In-Reply-To: <IA1PR20MB49530A123B23DFFED0CC3E06BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49530A123B23DFFED0CC3E06BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTT1CCQjzz8YkApucHuvnv+bFuK+3hDy-SCO3E7zgGTgHQ@mail.gmail.com>

On Thu, Oct 12, 2023 at 9:54?AM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Flushing the tlb entries can solve the thead tlb problem, but flushing
> it by address will miss something and lead to a exception in some rare
> cases, and this is more common for sg2042.
>
> To solve this problem, flush the tlb entries by asid in the custom trap
> handler to ensure it is refreshed.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> This patch based on the th1520 series patch.
> ---
>  platform/generic/thead/thead_c9xx_tlb_trap_handler.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/platform/generic/thead/thead_c9xx_tlb_trap_handler.S b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
> index 861c029..120daa7 100644
> --- a/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
> +++ b/platform/generic/thead/thead_c9xx_tlb_trap_handler.S
> @@ -9,5 +9,5 @@
>         .align 3
>         .globl _thead_tlb_flush_fixup_trap_handler
>  _thead_tlb_flush_fixup_trap_handler:
> -       sfence.vma t0, zero
> +       sfence.vma zero, t0
Reviewed-by: Guo Ren <guoren at kernel.org>

>         j _trap_handler
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From inochiama at outlook.com  Thu Oct 12 01:23:48 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 16:23:48 +0800
Subject: [PATCH] lib: utils/fdt: Allow zero length mtime when parsing ACLINT
In-Reply-To: <77f4664efaa5f974e70f2b7f5be46eb37aad2750.camel@126.com>
References: <77f4664efaa5f974e70f2b7f5be46eb37aad2750.camel@126.com>
Message-ID: <IA1PR20MB49539F83A28A3651F47CCCBDBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

>? 2023-10-12???? 07:25 +0800?Inochi Amaoto???
>> Currently, the fdt_parse_aclint_node() does not allow the first reg to
>> be zero length. This may cause the parser to fail when the ACLINT does
>> not support mtime.
>>
>> To be robust, delay the check of first reg in fdt_parse_aclint_node()
>> so the parser can handle ACLINT without mtime support.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> ---
>>  lib/utils/fdt/fdt_helper.c | 6 +++++-
>>  1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
>> index c97f09d..6b4ef38 100644
>> --- a/lib/utils/fdt/fdt_helper.c
>> +++ b/lib/utils/fdt/fdt_helper.c
>> @@ -897,8 +897,10 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
>>
>>  	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
>>  				    &reg_addr, &reg_size);
>> -	if (rc < 0 || !reg_size)
>> +	if (rc < 0)
>>  		return SBI_ENODEV;
>> +	if (!reg_size)
>> +		reg_addr = reg_size = 0;
>If abandon checking reg_size here, should add a check where this function
>is called. Because reg_size=0 is only legal under without_mtime.
>

This check is not abandoned, but delayed.

>Regards,
>Xiang W
>>  	*out_addr1 = reg_addr;
>>  	*out_size1 = reg_size;
>>
>> @@ -906,6 +908,8 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
>>  				    &reg_addr, &reg_size);
>>  	if (rc < 0 || !reg_size)
>>  		reg_addr = reg_size = 0;
>> +	if (!reg_addr && *out_size1 == 0)
>> +		return SBI_ENODEV;
>

The reg_size of the first pair is checked here.
It seems I should check reg_size here, will fix.

>>  	if (out_addr2)
>>  		*out_addr2 = reg_addr;
>>  	if (out_size2)
>> --
>> 2.42.0
>>
>>
>
>


From inochiama at outlook.com  Thu Oct 12 01:29:36 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 16:29:36 +0800
Subject: [PATCH v2] lib: utils/fdt: Allow zero length mtime when parsing ACLINT
Message-ID: <IA1PR20MB49534DA3EEF05A947D5EF6EABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

Currently, the fdt_parse_aclint_node() does not allow the first reg to
be zero length. This may cause the parser to fail when the ACLINT does
not support mtime.

To be robust, delay the check of first reg in fdt_parse_aclint_node()
so the parser can handle ACLINT without mtime support.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/utils/fdt/fdt_helper.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 9ae7f09..972e529 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -891,8 +891,10 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !reg_size)
+	if (rc < 0)
 		return SBI_ENODEV;
+	if (!reg_size)
+		reg_addr = reg_size = 0;
 	*out_addr1 = reg_addr;
 	*out_size1 = reg_size;
 
@@ -900,6 +902,8 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
 				    &reg_addr, &reg_size);
 	if (rc < 0 || !reg_size)
 		reg_addr = reg_size = 0;
+	if (!reg_size && *out_size1 == 0)
+		return SBI_ENODEV;
 	if (out_addr2)
 		*out_addr2 = reg_addr;
 	if (out_size2)
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 01:33:28 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 16:33:28 +0800
Subject: [PATCH v2] platform: Uses hart count as the default size of tlb info
Message-ID: <IA1PR20MB495379709E66871C21333296BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

For platform with high number of harts, it is better to auto detect a
suitable number of entries in tlb fifo. Since allocating tlb entry for
all online harts can reduce the wait time significantly, using the
number of the online harts can make most platforms happy. This auto
detection can avoid most duplicate code for setting tlb fifo size.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
Changed from v1:
1. replace SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES with hart count in all cases.

---
 include/sbi/sbi_platform.h  | 3 +--
 platform/generic/platform.c | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 389203b..58b9069 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -41,7 +41,6 @@
 #define SBI_PLATFORM_HART_INDEX2ID_OFFSET (0x60 + (__SIZEOF_POINTER__ * 2))

 #define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT		(1UL << 12)
-#define SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES				8

 #ifndef __ASSEMBLER__

@@ -330,7 +329,7 @@ static inline u32 sbi_platform_tlb_fifo_num_entries(const struct sbi_platform *p
 {
 	if (plat && sbi_platform_ops(plat)->get_tlb_num_entries)
 		return sbi_platform_ops(plat)->get_tlb_num_entries();
-	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
+	return sbi_scratch_last_hartindex() + 1;
 }

 /**
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..4246efd 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -260,7 +260,7 @@ static u32 generic_tlb_num_entries(void)
 {
 	if (generic_plat && generic_plat->tlb_num_entries)
 		return generic_plat->tlb_num_entries(generic_plat_match);
-	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
+	return sbi_scratch_last_hartindex() + 1;
 }

 static int generic_pmu_init(void)
--
2.42.0



From guoren at kernel.org  Thu Oct 12 01:59:13 2023
From: guoren at kernel.org (guoren at kernel.org)
Date: Thu, 12 Oct 2023 04:59:13 -0400
Subject: [PATCH] utils/reset: Remove fdt_reset_thead
Message-ID: <20231012085913.1679067-1-guoren@kernel.org>

From: Guo Ren <guoren at linux.alibaba.com>

In the past, we used fdt_reset_thead to help customers with prototype
verification. However, with the emergence of the Big-little SoC system,
it can no longer meet the demand. Therefore, we use zero_stage_boot
instead of fdt_reset_thead. It cleans up the opensbi code and ends the
disputation of reset_sample's dts.

This patch removes the fdt_reset_thead component and updates the related
doc.

Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
Signed-off-by: Guo Ren <guoren at kernel.org>
---
 docs/platform/thead-c9xx.md           | 183 +-------------------------
 lib/utils/reset/Kconfig               |   4 -
 lib/utils/reset/fdt_reset_thead.c     | 134 -------------------
 lib/utils/reset/fdt_reset_thead.h     |  23 ----
 lib/utils/reset/fdt_reset_thead_asm.S |  47 -------
 lib/utils/reset/objects.mk            |   4 -
 platform/generic/configs/defconfig    |   1 -
 7 files changed, 7 insertions(+), 389 deletions(-)
 delete mode 100644 lib/utils/reset/fdt_reset_thead.c
 delete mode 100644 lib/utils/reset/fdt_reset_thead.h
 delete mode 100644 lib/utils/reset/fdt_reset_thead_asm.S

diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md
index 8bb9e91f1a9b..cc05b58ca6b6 100644
--- a/docs/platform/thead-c9xx.md
+++ b/docs/platform/thead-c9xx.md
@@ -1,7 +1,7 @@
 T-HEAD C9xx Series Processors
 =============================
 
-The **C9xx** series processors are high-performance RISC-V architecture
+The C9xx series processors are high-performance RISC-V architecture
 multi-core processors with AI vector acceleration engine.
 
 For more details, refer [T-HEAD.CN](https://www.t-head.cn/)
@@ -12,185 +12,16 @@ To build the platform-specific library and firmware images, provide the
 Platform Options
 ----------------
 
-The *T-HEAD C9xx* does not have any platform-specific compile options
+The T-HEAD C9xx does not have any platform-specific compile options
 because it uses generic platform.
 
 ```
-CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic /usr/bin/make
+CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic make
 ```
 
-The *T-HEAD C9xx* DTB provided to OpenSBI generic firmwares will usually have
-"riscv,clint0", "riscv,plic0", "thead,reset-sample" compatible strings.
+Here is the simplest boot flow for a fpga prototype:
 
-DTS Example1: (Single core, eg: Allwinner D1 - c906)
-----------------------------------------------------
+ (Jtag gdbinit) -> (zsb) -> (opensbi) -> (linux)
 
-```
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <3000000>;
-		cpu at 0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdcv";
-			mmu-type = "riscv,sv39";
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		clint0: clint at 14000000 {
-			compatible = "allwinner,sun20i-d1-clint";
-			interrupts-extended = <
-				&cpu0_intc  3 &cpu0_intc  7
-				>;
-			reg = <0x0 0x14000000 0x0 0x04000000>;
-		};
-
-		intc: interrupt-controller at 10000000 {
-			#interrupt-cells = <1>;
-			compatible = "allwinner,sun20i-d1-plic",
-				     "thead,c900-plic";
-			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc  0xffffffff &cpu0_intc  9
-				>;
-			reg = <0x0 0x10000000 0x0 0x04000000>;
-			reg-names = "control";
-			riscv,max-priority = <7>;
-			riscv,ndev = <200>;
-		};
-	}
-```
-
-DTS Example2: (Multi cores with soc reset-regs)
------------------------------------------------
-
-```
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		timebase-frequency = <3000000>;
-		cpu at 0 {
-			device_type = "cpu";
-			reg = <0>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			mmu-type = "riscv,sv39";
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu at 1 {
-			device_type = "cpu";
-			reg = <1>;
-			status = "fail";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			mmu-type = "riscv,sv39";
-			cpu1_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu at 2 {
-			device_type = "cpu";
-			reg = <2>;
-			status = "fail";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			mmu-type = "riscv,sv39";
-			cpu2_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-		cpu at 3 {
-			device_type = "cpu";
-			reg = <3>;
-			status = "fail";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdc";
-			mmu-type = "riscv,sv39";
-			cpu3_intc: interrupt-controller {
-				#interrupt-cells = <1>;
-				compatible = "riscv,cpu-intc";
-				interrupt-controller;
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		compatible = "simple-bus";
-		ranges;
-
-		reset: reset-sample {
-			compatible = "thead,reset-sample";
-			entry-reg = <0xff 0xff019050>;
-			entry-cnt = <4>;
-			control-reg = <0xff 0xff015004>;
-			control-val = <0x1c>;
-			csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
-		};
-
-		clint0: clint at ffdc000000 {
-			compatible = "riscv,clint0";
-			interrupts-extended = <
-				&cpu0_intc  3 &cpu0_intc  7
-				&cpu1_intc  3 &cpu1_intc  7
-				&cpu2_intc  3 &cpu2_intc  7
-				&cpu3_intc  3 &cpu3_intc  7
-				&cpu4_intc  3 &cpu4_intc  7
-				>;
-			reg = <0xff 0xdc000000 0x0 0x04000000>;
-		};
-
-		intc: interrupt-controller at ffd8000000 {
-			#interrupt-cells = <1>;
-			compatible = "thead,c900-plic";
-			interrupt-controller;
-			interrupts-extended = <
-				&cpu0_intc  0xffffffff &cpu0_intc  9
-				&cpu1_intc  0xffffffff &cpu1_intc  9
-				&cpu2_intc  0xffffffff &cpu2_intc  9
-				&cpu3_intc  0xffffffff &cpu3_intc  9
-				>;
-			reg = <0xff 0xd8000000 0x0 0x04000000>;
-			reg-names = "control";
-			riscv,max-priority = <7>;
-			riscv,ndev = <80>;
-		};
-	}
-```
-
-DTS Example2: (Multi cores with old reset csrs)
------------------------------------------------
-```
-	reset: reset-sample {
-		compatible = "thead,reset-sample";
-		using-csr-reset;
-		csr-copy = <0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc
-			    0x3b0 0x3b1 0x3b2 0x3b3
-			    0x3b4 0x3b5 0x3b6 0x3b7
-			    0x3a0>;
-	};
-```
+For more details, refer:
+ [zero stage boot](https://github.com/c-sky/zero_stage_boot)
diff --git a/lib/utils/reset/Kconfig b/lib/utils/reset/Kconfig
index 23f50c4dfe40..b26260db1678 100644
--- a/lib/utils/reset/Kconfig
+++ b/lib/utils/reset/Kconfig
@@ -33,10 +33,6 @@ config FDT_RESET_SYSCON
 	depends on FDT_REGMAP
 	default n
 
-config FDT_RESET_THEAD
-	bool "T-HEAD FDT reset driver"
-	default n
-
 endif
 
 endmenu
diff --git a/lib/utils/reset/fdt_reset_thead.c b/lib/utils/reset/fdt_reset_thead.c
deleted file mode 100644
index e1d6885debae..000000000000
--- a/lib/utils/reset/fdt_reset_thead.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#include <libfdt.h>
-#include <sbi/riscv_io.h>
-#include <sbi/sbi_bitops.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_scratch.h>
-#include <sbi/sbi_system.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/reset/fdt_reset.h>
-
-#include "fdt_reset_thead.h"
-
-struct custom_csr custom_csr[MAX_CUSTOM_CSR];
-
-#define CSR_OPCODE 0x39073
-static void clone_csrs(int cnt)
-{
-	unsigned long i;
-
-	for (i = 0; i < cnt; i++) {
-		/* Write csr BIT[31 - 20] to stub */
-		__reset_thead_csr_stub[3*i + 1] =
-				CSR_OPCODE | (custom_csr[i].index << 20);
-
-		/* Mask csr BIT[31 - 20] */
-		*(u32 *)&__fdt_reset_thead_csrr &= BIT(20) - 1;
-		smp_mb();
-
-		/* Write csr BIT[31 - 20] to __fdt_reset_thead_csrr */
-		*(u32 *)&__fdt_reset_thead_csrr |= custom_csr[i].index << 20;
-		smp_mb();
-
-		RISCV_FENCE_I;
-
-		custom_csr[i].value = __fdt_reset_thead_csrr();
-	}
-}
-
-static int thead_system_reset_check(u32 type, u32 reason)
-{
-	return 1;
-}
-
-static void thead_system_reset(u32 type, u32 reason)
-{
-	ebreak();
-}
-
-static struct sbi_system_reset_device thead_reset = {
-	.name = "thead_reset",
-	.system_reset_check = thead_system_reset_check,
-	.system_reset = thead_system_reset
-};
-
-extern void __thead_pre_start_warm(void);
-static int thead_reset_init(void *fdt, int nodeoff,
-				 const struct fdt_match *match)
-{
-	char *p;
-	const fdt64_t *val;
-	const fdt32_t *val_w;
-	int len, i;
-	u32 t, tmp = 0;
-
-	/* Prepare clone csrs */
-	val_w = fdt_getprop(fdt, nodeoff, "csr-copy", &len);
-	if (len > 0 && val_w) {
-		int cnt;
-
-		cnt = len / sizeof(fdt32_t);
-		if (cnt > MAX_CUSTOM_CSR)
-			sbi_hart_hang();
-
-		for (i = 0; i < cnt; i++) {
-			custom_csr[i].index = fdt32_to_cpu(val_w[i]);
-		}
-
-		if (cnt)
-			clone_csrs(cnt);
-	}
-
-	/* Old reset method for secondary harts */
-	if (fdt_getprop(fdt, nodeoff, "using-csr-reset", &len)) {
-		csr_write(0x7c7, (ulong)&__thead_pre_start_warm);
-		csr_write(0x7c6, -1);
-	}
-
-	/* Custom reset method for secondary harts */
-	val = fdt_getprop(fdt, nodeoff, "entry-reg", &len);
-	if (len > 0 && val) {
-          p = (char *)(ulong)fdt64_to_cpu(*val);
-
-		val_w = fdt_getprop(fdt, nodeoff, "entry-cnt", &len);
-		if (len > 0 && val_w) {
-			tmp = fdt32_to_cpu(*val_w);
-
-			for (i = 0; i < tmp; i++) {
-				t = (ulong)&__thead_pre_start_warm;
-				writel(t, p + (8 * i));
-				t = (u64)(ulong)&__thead_pre_start_warm >> 32;
-				writel(t, p + (8 * i) + 4);
-			}
-		}
-
-		val = fdt_getprop(fdt, nodeoff, "control-reg", &len);
-		if (len > 0 && val) {
-			p = (void *)(ulong)fdt64_to_cpu(*val);
-
-			val_w = fdt_getprop(fdt, nodeoff, "control-val", &len);
-			if (len > 0 && val_w) {
-				tmp = fdt32_to_cpu(*val_w);
-				tmp |= readl(p);
-				writel(tmp, p);
-			}
-		}
-	}
-
-	sbi_system_reset_add_device(&thead_reset);
-
-	return 0;
-}
-
-static const struct fdt_match thead_reset_match[] = {
-	{ .compatible = "thead,reset-sample" },
-	{ },
-};
-
-struct fdt_reset fdt_reset_thead = {
-	.match_table = thead_reset_match,
-	.init = thead_reset_init
-};
diff --git a/lib/utils/reset/fdt_reset_thead.h b/lib/utils/reset/fdt_reset_thead.h
deleted file mode 100644
index d7a686ec9317..000000000000
--- a/lib/utils/reset/fdt_reset_thead.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#ifndef __FDT_RESET_THEAD_H__
-#define __FDT_RESET_THEAD_H__
-
-#define MAX_CUSTOM_CSR	32
-
-#ifndef __ASSEMBLER__
-struct custom_csr {
-	unsigned long index;
-	unsigned long value;
-};
-
-u64  __fdt_reset_thead_csrr(void);
-
-extern struct custom_csr custom_csr[MAX_CUSTOM_CSR];
-extern u32 __reset_thead_csr_stub[];
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __FDT_RESET_THEAD_H__ */
diff --git a/lib/utils/reset/fdt_reset_thead_asm.S b/lib/utils/reset/fdt_reset_thead_asm.S
deleted file mode 100644
index 8237951fd82d..000000000000
--- a/lib/utils/reset/fdt_reset_thead_asm.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- */
-
-#include <sbi/riscv_asm.h>
-#include "fdt_reset_thead.h"
-
-/*
- * csrrs rd, csr, rs1
- * |31   20|19   15|14   12|11  7|6       0|
- *    csr     rs1     010     rd   1110011
- */
-#define CSR_STUB	addi    x0, x0, 0
-
-	.option norvc
-	.align 3
-	.global __fdt_reset_thead_csrr
-__fdt_reset_thead_csrr:
-	csrrs a0, 0, x0
-	ret
-
-	.align 3
-	.global __thead_pre_start_warm
-__thead_pre_start_warm:
-	/*
-	 * Clear L1 cache & BTB & BHT ...
-	 */
-	li	t1, 0x70013
-	csrw	0x7c2, t1
-	fence rw,rw
-
-	lla	t1, custom_csr
-
-	.global __reset_thead_csr_stub
-__reset_thead_csr_stub:
-.rept	MAX_CUSTOM_CSR
-	REG_L	t2, 8(t1)
-	CSR_STUB
-	addi	t1, t1, 16
-.endr
-	/*
-	 * Clear L1 cache & BTB & BHT ...
-	 */
-	li	t1, 0x70013
-	csrw	0x7c2, t1
-	fence rw,rw
-	j _start_warm
diff --git a/lib/utils/reset/objects.mk b/lib/utils/reset/objects.mk
index ea9cedcd8002..b5222347b213 100644
--- a/lib/utils/reset/objects.mk
+++ b/lib/utils/reset/objects.mk
@@ -26,7 +26,3 @@ libsbiutils-objs-$(CONFIG_FDT_RESET_SUNXI_WDT) += reset/fdt_reset_sunxi_wdt.o
 carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_SYSCON) += fdt_syscon_poweroff
 carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_SYSCON) += fdt_syscon_reboot
 libsbiutils-objs-$(CONFIG_FDT_RESET_SYSCON) += reset/fdt_reset_syscon.o
-
-carray-fdt_reset_drivers-$(CONFIG_FDT_RESET_THEAD) += fdt_reset_thead
-libsbiutils-objs-$(CONFIG_FDT_RESET_THEAD) += reset/fdt_reset_thead.o
-libsbiutils-objs-$(CONFIG_FDT_RESET_THEAD) += reset/fdt_reset_thead_asm.o
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c432bc2f8936..95bab61ea5d9 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -27,7 +27,6 @@ CONFIG_FDT_RESET_GPIO=y
 CONFIG_FDT_RESET_HTIF=y
 CONFIG_FDT_RESET_SUNXI_WDT=y
 CONFIG_FDT_RESET_SYSCON=y
-CONFIG_FDT_RESET_THEAD=y
 CONFIG_FDT_SERIAL=y
 CONFIG_FDT_SERIAL_CADENCE=y
 CONFIG_FDT_SERIAL_GAISLER=y
-- 
2.36.1



From inochiama at outlook.com  Thu Oct 12 02:00:24 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 17:00:24 +0800
Subject: [PATCH 0/3] lib: utils: Add T-HEAD C900 ACLINT
Message-ID: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

Add T-HEAD C900 ACLINT driver for sg2042

The timer quirks need the following patch to parse thead mtime:
lib: utils/fdt: Allow zero length mtime when parsing ACLINT

Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/

Changed from sg2042 v2:
1. Allow ACLINT has its own quirks
2. add new quirks for thead,c900-aclint-mtimer

This patch is moved from the patch series of supporting sg2042 as it
became complex.
The original patch: platform: generic: Add Sophgo sg2042 support

Inochi Amaoto (3):
  lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
  lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer
    compatible
  lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible

 lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
 lib/utils/timer/fdt_timer_mtimer.c | 23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

--
2.42.0



From inochiama at outlook.com  Thu Oct 12 02:01:36 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 17:01:36 +0800
Subject: [PATCH 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953BFAB68230DF0B1360FF4BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs a quirks.

Add more check to ensure the timer is CLINT before applying quirks.
And now apply the general quirks after applying CLINT specific quirks.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 9eaa11d..cd14f75 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
 
 static struct aclint_mtimer_data *mt_reference = NULL;
 
+static int timer_is_clint(const void *data)
+{
+	const struct timer_mtimer_quirks *quirks = data;
+	return quirks && quirks->mtime_offset;
+}
+
 static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 				  const struct fdt_match *match)
 {
@@ -58,7 +64,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		return rc;
 	}
 
-	if (match->data) { /* SiFive CLINT */
+	if (timer_is_clint(match->data)) { /* SiFive CLINT */
 		const struct timer_mtimer_quirks *quirks = match->data;
 
 		/* Set CLINT addresses */
@@ -74,8 +80,6 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 			mt->mtime_addr = mt->mtime_size = 0;
 		}
 		mt->mtimecmp_addr += quirks->mtime_offset;
-		/* Apply additional CLINT quirks */
-		mt->has_64bit_mmio = quirks->has_64bit_mmio;
 	} else { /* RISC-V ACLINT MTIMER */
 		/* Set ACLINT MTIMER addresses */
 		mt->mtime_addr = addr[0];
@@ -84,6 +88,13 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		mt->mtimecmp_size = size[1];
 	}
 
+	/* Apply additional quirks for CLINT and ACLINT */
+	if (match->data) {
+		const struct timer_mtimer_quirks *quirks = match->data;
+
+		mt->has_64bit_mmio = quirks->has_64bit_mmio;
+	}
+
 	/* Check if MTIMER device has shared MTIME address */
 	if (mt->mtime_size) {
 		mt->has_shared_mtime = false;
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 02:01:37 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 17:01:37 +0800
Subject: [PATCH 2/3] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB49536237AE535BE87D81558DBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index cd14f75..8c45fdf 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -153,10 +153,16 @@ static const struct timer_mtimer_quirks thead_clint_quirks = {
 	.without_mtime  = true,
 };
 
+static const struct timer_mtimer_quirks thead_aclint_quirks = {
+	.has_64bit_mmio	= false,
+};
+
 static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
+	{ .compatible = "thead,c900-aclint-mtimer",
+	  .data = &thead_aclint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 02:01:38 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 17:01:38 +0800
Subject: [PATCH 3/3] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
In-Reply-To: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB49537E385424B60FEFF948E2BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
string to avoid misuse.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
---
 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index e3a6378..5432db6 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
 	{ .compatible = "thead,c900-clint", .data = &clint_offset },
+	{ .compatible = "thead,c900-aclint-mswi" },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 02:04:01 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 17:04:01 +0800
Subject: [PATCH v3] platform: generic: Add Sophgo sg2042 platform support
Message-ID: <IA1PR20MB4953405DEDABE27D1B60B2BFBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

Add Sophgo sg2042 soc support

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
This patch depends these patchs:
1. platform: generic: add T-HEAD th1520 soc support
2. lib: sbi: Add sub-regions check for sanitizing domain
3. lib: utils: Add T-HEAD C900 ACLINT
4. platform: generic: thead: improve tlb flush errata

Link: https://lore.kernel.org/linux-riscv/cover.1696433229.git.unicorn_wang at outlook.com/

Changed from v2:
1. replace hart count with number 16 when calculating the timer area.
   The sg2042 have a fixed number of timer, see the kernel dt in the link.
2. fix typo
3. move the c900 aclint patch out of this series.
4. move the tlb size change patch out of this series.

Changed from v1:
1. make number of entries in tlb fifo auto deteted.
---
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/sophgo/objects.mk |  9 +++++
 platform/generic/sophgo/sg2042.c   | 64 ++++++++++++++++++++++++++++++
 4 files changed, 80 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index e7bd94e..e440cb7 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -48,6 +48,12 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n

+config PLATFORM_SOPHGO_SG2042
+	bool "Sophgo sg2042 support"
+	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
+	default n
+
 config PLATFORM_STARFIVE_JH7110
 	bool "StarFive JH7110 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c432bc2..e1b76c8 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_SOPHGO_SG2042=y
 CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_PLATFORM_THEAD=y
 CONFIG_FDT_GPIO=y
diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
new file mode 100644
index 0000000..3d2908a
--- /dev/null
+++ b/platform/generic/sophgo/objects.mk
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
+# Copyright (C) 2023 Alibaba Group Holding Limited.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
+platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
new file mode 100644
index 0000000..fc198c7
--- /dev/null
+++ b/platform/generic/sophgo/sg2042.c
@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <platform_override.h>
+#include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/timer/aclint_mtimer.h>
+
+#define SOPHGO_SG2042_TIMER_BASE	0x70ac000000UL
+#define SOPHGO_SG2042_TIMER_SIZE	0x10000UL
+#define SOPHGO_SG2042_TIMER_NUM		16
+
+static int sophgo_sg2042_early_init(bool cold_boot,
+				    const struct fdt_match *match)
+{
+	const struct sbi_platform *plat = sbi_platform_thishart_ptr();
+
+	thead_register_tlb_flush_trap_handler();
+
+	/*
+	 * Sophgo sg2042 soc use separate 16 timers while initiating,
+	 * merge them as a single domain to avoid wasting.
+	 */
+	if (cold_boot)
+		return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
+						SOPHGO_SG2042_TIMER_SIZE *
+						SOPHGO_SG2042_TIMER_NUM,
+						MTIMER_REGION_ALIGN,
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
+
+
+	return 0;
+}
+
+static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
+static const struct fdt_match sophgo_sg2042_match[] = {
+	{ .compatible = "sophgo,sg2042" },
+	{ },
+};
+
+const struct platform_override sophgo_sg2042 = {
+	.match_table		= sophgo_sg2042_match,
+	.early_init		= sophgo_sg2042_early_init,
+	.extensions_init	= sophgo_sg2042_extensions_init,
+};
--
2.42.0



From guoren at kernel.org  Thu Oct 12 02:06:46 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:06:46 +0800
Subject: [PATCH 3/3] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT
 mswi compatible
In-Reply-To: <IA1PR20MB49537E385424B60FEFF948E2BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <IA1PR20MB49537E385424B60FEFF948E2BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTR1c3QSdVLxkK_LdOEDKiiY16N=3QA2yaxWAUGPuN0f+A@mail.gmail.com>

On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
> string to avoid misuse.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
> ---
>  lib/utils/ipi/fdt_ipi_mswi.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
> index e3a6378..5432db6 100644
> --- a/lib/utils/ipi/fdt_ipi_mswi.c
> +++ b/lib/utils/ipi/fdt_ipi_mswi.c
> @@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
>         { .compatible = "riscv,clint0", .data = &clint_offset },
>         { .compatible = "sifive,clint0", .data = &clint_offset },
>         { .compatible = "thead,c900-clint", .data = &clint_offset },
> +       { .compatible = "thead,c900-aclint-mswi" },
>         { .compatible = "riscv,aclint-mswi" },
>         { },
>  };
> --
> 2.42.0
>
Reviewed-by: Guo Ren <guoren at kernel.org>

-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Thu Oct 12 02:11:19 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:11:19 +0800
Subject: [PATCH v3] platform: generic: Add Sophgo sg2042 platform support
In-Reply-To: <IA1PR20MB4953405DEDABE27D1B60B2BFBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB4953405DEDABE27D1B60B2BFBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTTtBPUfLOcfeQc+zKSr56PfhJR=CMt3McLzV_cBxjCQNQ@mail.gmail.com>

On Thu, Oct 12, 2023 at 5:04?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Add Sophgo sg2042 soc support
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> This patch depends these patchs:
> 1. platform: generic: add T-HEAD th1520 soc support
> 2. lib: sbi: Add sub-regions check for sanitizing domain
> 3. lib: utils: Add T-HEAD C900 ACLINT
> 4. platform: generic: thead: improve tlb flush errata
>
> Link: https://lore.kernel.org/linux-riscv/cover.1696433229.git.unicorn_wang at outlook.com/
>
> Changed from v2:
> 1. replace hart count with number 16 when calculating the timer area.
>    The sg2042 have a fixed number of timer, see the kernel dt in the link.
> 2. fix typo
> 3. move the c900 aclint patch out of this series.
> 4. move the tlb size change patch out of this series.
>
> Changed from v1:
> 1. make number of entries in tlb fifo auto deteted.
> ---
>  platform/generic/Kconfig           |  6 +++
>  platform/generic/configs/defconfig |  1 +
>  platform/generic/sophgo/objects.mk |  9 +++++
>  platform/generic/sophgo/sg2042.c   | 64 ++++++++++++++++++++++++++++++
>  4 files changed, 80 insertions(+)
>  create mode 100644 platform/generic/sophgo/objects.mk
>  create mode 100644 platform/generic/sophgo/sg2042.c
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index e7bd94e..e440cb7 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -48,6 +48,12 @@ config PLATFORM_SIFIVE_FU740
>         depends on FDT_RESET && FDT_I2C
>         default n
>
> +config PLATFORM_SOPHGO_SG2042
> +       bool "Sophgo sg2042 support"
> +       select THEAD_C9XX_ERRATA
> +       select THEAD_C9XX_PMU
> +       default n
> +
>  config PLATFORM_STARFIVE_JH7110
>         bool "StarFive JH7110 support"
>         default n
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index c432bc2..e1b76c8 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_SOPHGO_SG2042=y
>  CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_PLATFORM_THEAD=y
>  CONFIG_FDT_GPIO=y
> diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
> new file mode 100644
> index 0000000..3d2908a
> --- /dev/null
> +++ b/platform/generic/sophgo/objects.mk
> @@ -0,0 +1,9 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
> +# Copyright (C) 2023 Alibaba Group Holding Limited.
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
> +platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
> diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
> new file mode 100644
> index 0000000..fc198c7
> --- /dev/null
> +++ b/platform/generic/sophgo/sg2042.c
> @@ -0,0 +1,64 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Authors:
> + *   Inochi Amaoto <inochiama at outlook.com>
> + *
> + */
> +
> +#include <platform_override.h>
> +#include <thead/c9xx_errata.h>
> +#include <thead/c9xx_pmu.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_string.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/timer/aclint_mtimer.h>
> +
> +#define SOPHGO_SG2042_TIMER_BASE       0x70ac000000UL
> +#define SOPHGO_SG2042_TIMER_SIZE       0x10000UL
> +#define SOPHGO_SG2042_TIMER_NUM                16
> +
> +static int sophgo_sg2042_early_init(bool cold_boot,
> +                                   const struct fdt_match *match)
> +{
> +       const struct sbi_platform *plat = sbi_platform_thishart_ptr();
> +
> +       thead_register_tlb_flush_trap_handler();
> +
> +       /*
> +        * Sophgo sg2042 soc use separate 16 timers while initiating,
> +        * merge them as a single domain to avoid wasting.
> +        */
> +       if (cold_boot)
> +               return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
> +                                               SOPHGO_SG2042_TIMER_SIZE *
> +                                               SOPHGO_SG2042_TIMER_NUM,
> +                                               MTIMER_REGION_ALIGN,
> +                                               (SBI_DOMAIN_MEMREGION_MMIO |
> +                                                SBI_DOMAIN_MEMREGION_M_READABLE |
> +                                                SBI_DOMAIN_MEMREGION_M_WRITABLE));
> +
> +
> +       return 0;
> +}
> +
> +static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
> +                                        struct sbi_hart_features *hfeatures)
> +{
> +       thead_c9xx_register_pmu_device();
> +       return 0;
> +}
> +
> +static const struct fdt_match sophgo_sg2042_match[] = {
> +       { .compatible = "sophgo,sg2042" },
> +       { },
> +};
> +
> +const struct platform_override sophgo_sg2042 = {
> +       .match_table            = sophgo_sg2042_match,
> +       .early_init             = sophgo_sg2042_early_init,
> +       .extensions_init        = sophgo_sg2042_extensions_init,
> +};
> --
> 2.42.0
>
LGTM

Reviewed-by: Guo Ren <guoren at kernel.org>

-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Thu Oct 12 02:20:38 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:20:38 +0800
Subject: [PATCH 2/3] lib: utils/timer: mtimer: add separate T-Head C9xx
 CLINT mtimer compatible
In-Reply-To: <IA1PR20MB49536237AE535BE87D81558DBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <IA1PR20MB49536237AE535BE87D81558DBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTRx7PTjZPjpugoqtVG+y-BvHDxoWsiKFTRoNQayVR9ytg@mail.gmail.com>

On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
> different address, which may cause a misuse if use the same compatible
> string, add a new timer compatible string to avoid this.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
> ---
>  lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index cd14f75..8c45fdf 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -153,10 +153,16 @@ static const struct timer_mtimer_quirks thead_clint_quirks = {
>         .without_mtime  = true,
>  };
>
> +static const struct timer_mtimer_quirks thead_aclint_quirks = {
> +       .has_64bit_mmio = false,
> +};
Yes, split mtimer & mswi of clint.

Reviewed-by: Guo Ren <guoren at kernel.org>

> +
>  static const struct fdt_match timer_mtimer_match[] = {
>         { .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
>         { .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
>         { .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
> +       { .compatible = "thead,c900-aclint-mtimer",
> +         .data = &thead_aclint_quirks },
>         { .compatible = "riscv,aclint-mtimer" },
>         { },
>  };
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Thu Oct 12 02:34:41 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:34:41 +0800
Subject: [PATCH 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <IA1PR20MB4953BFAB68230DF0B1360FF4BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495316CD19B4976D3BF5AA8BBBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <IA1PR20MB4953BFAB68230DF0B1360FF4BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTSwKx6T9YmKN8i+R_VZ9H9MTVs9NygUiDhRBip_bjDdwQ@mail.gmail.com>

On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> The quirks checking will cause ACLINT step into a CLINT code path, this
> is not expected when ACLINT needs a quirks.
>
> Add more check to ensure the timer is CLINT before applying quirks.
> And now apply the general quirks after applying CLINT specific quirks.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index 9eaa11d..cd14f75 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
>
>  static struct aclint_mtimer_data *mt_reference = NULL;
>
> +static int timer_is_clint(const void *data)

The timer is not clint, the timer is in the clint, right?
How about timer_in_clint?

> +{
> +       const struct timer_mtimer_quirks *quirks = data;
> +       return quirks && quirks->mtime_offset;
> +}
> +
>  static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                                   const struct fdt_match *match)
>  {
> @@ -58,7 +64,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                 return rc;
>         }
>
> -       if (match->data) { /* SiFive CLINT */
> +       if (timer_is_clint(match->data)) { /* SiFive CLINT */
The comment is confusing. So, how about deleting it:
if (timer_in_clint(match->data)) {

>                 const struct timer_mtimer_quirks *quirks = match->data;
>
>                 /* Set CLINT addresses */
> @@ -74,8 +80,6 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                         mt->mtime_addr = mt->mtime_size = 0;
>                 }
>                 mt->mtimecmp_addr += quirks->mtime_offset;
> -               /* Apply additional CLINT quirks */
> -               mt->has_64bit_mmio = quirks->has_64bit_mmio;
>         } else { /* RISC-V ACLINT MTIMER */
>                 /* Set ACLINT MTIMER addresses */
>                 mt->mtime_addr = addr[0];
> @@ -84,6 +88,13 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                 mt->mtimecmp_size = size[1];
>         }
>
> +       /* Apply additional quirks for CLINT and ACLINT */
> +       if (match->data) {
> +               const struct timer_mtimer_quirks *quirks = match->data;
> +
> +               mt->has_64bit_mmio = quirks->has_64bit_mmio;
> +       }
> +
>         /* Check if MTIMER device has shared MTIME address */
>         if (mt->mtime_size) {
>                 mt->has_shared_mtime = false;
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Thu Oct 12 02:38:21 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:38:21 +0800
Subject: [PATCH v2] platform: Uses hart count as the default size of tlb info
In-Reply-To: <IA1PR20MB495379709E66871C21333296BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495379709E66871C21333296BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTQsXeLz13GudQrMO4NvqH8CxhQusrxBK_Oq7uD13R0mFQ@mail.gmail.com>

On Thu, Oct 12, 2023 at 4:34?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> For platform with high number of harts, it is better to auto detect a
> suitable number of entries in tlb fifo. Since allocating tlb entry for
> all online harts can reduce the wait time significantly, using the
> number of the online harts can make most platforms happy. This auto
> detection can avoid most duplicate code for setting tlb fifo size.
I agree to allocate tlb fifo by the number of harts.

Acked-by: Guo Ren <guoren at kernel.org>

>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
> Changed from v1:
> 1. replace SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES with hart count in all cases.
>
> ---
>  include/sbi/sbi_platform.h  | 3 +--
>  platform/generic/platform.c | 2 +-
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 389203b..58b9069 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -41,7 +41,6 @@
>  #define SBI_PLATFORM_HART_INDEX2ID_OFFSET (0x60 + (__SIZEOF_POINTER__ * 2))
>
>  #define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT             (1UL << 12)
> -#define SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES                              8
>
>  #ifndef __ASSEMBLER__
>
> @@ -330,7 +329,7 @@ static inline u32 sbi_platform_tlb_fifo_num_entries(const struct sbi_platform *p
>  {
>         if (plat && sbi_platform_ops(plat)->get_tlb_num_entries)
>                 return sbi_platform_ops(plat)->get_tlb_num_entries();
> -       return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> +       return sbi_scratch_last_hartindex() + 1;
>  }
>
>  /**
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 66a0b77..4246efd 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -260,7 +260,7 @@ static u32 generic_tlb_num_entries(void)
>  {
>         if (generic_plat && generic_plat->tlb_num_entries)
>                 return generic_plat->tlb_num_entries(generic_plat_match);
> -       return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> +       return sbi_scratch_last_hartindex() + 1;
>  }
>
>  static int generic_pmu_init(void)
> --
> 2.42.0
>


-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Thu Oct 12 02:46:39 2023
From: guoren at kernel.org (Guo Ren)
Date: Thu, 12 Oct 2023 17:46:39 +0800
Subject: [PATCH v2] lib: utils/fdt: Allow zero length mtime when parsing ACLINT
In-Reply-To: <IA1PR20MB49534DA3EEF05A947D5EF6EABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49534DA3EEF05A947D5EF6EABBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTRPCvOV3j4jyeNX4tgcSjAK8L3_FW4njdZZq6ye-OVQ6Q@mail.gmail.com>

On Thu, Oct 12, 2023 at 4:29?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> Currently, the fdt_parse_aclint_node() does not allow the first reg to
> be zero length. This may cause the parser to fail when the ACLINT does
> not support mtime.
>
> To be robust, delay the check of first reg in fdt_parse_aclint_node()
> so the parser can handle ACLINT without mtime support.
>
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> ---
>  lib/utils/fdt/fdt_helper.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 9ae7f09..972e529 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -891,8 +891,10 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
>
>         rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
>                                     &reg_addr, &reg_size);
> -       if (rc < 0 || !reg_size)
> +       if (rc < 0)
>                 return SBI_ENODEV;
> +       if (!reg_size)
> +               reg_addr = reg_size = 0;
>         *out_addr1 = reg_addr;
>         *out_size1 = reg_size;
>
> @@ -900,6 +902,8 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
>                                     &reg_addr, &reg_size);
>         if (rc < 0 || !reg_size)
>                 reg_addr = reg_size = 0;
> +       if (!reg_size && *out_size1 == 0)
> +               return SBI_ENODEV;
>         if (out_addr2)
>                 *out_addr2 = reg_addr;
>         if (out_size2)
> --
> 2.42.0
>
 Reviewed-by: Guo Ren <guoren at kernel.org>

-- 
Best Regards
 Guo Ren


From inochiama at outlook.com  Thu Oct 12 04:19:58 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Thu, 12 Oct 2023 19:19:58 +0800
Subject: [PATCH 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <CAJF2gTSwKx6T9YmKN8i+R_VZ9H9MTVs9NygUiDhRBip_bjDdwQ@mail.gmail.com>
References: <CAJF2gTSwKx6T9YmKN8i+R_VZ9H9MTVs9NygUiDhRBip_bjDdwQ@mail.gmail.com>
Message-ID: <IA1PR20MB4953FF9940A6522ADDB18AC3BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>

>On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>>
>> The quirks checking will cause ACLINT step into a CLINT code path, this
>> is not expected when ACLINT needs a quirks.
>>
>> Add more check to ensure the timer is CLINT before applying quirks.
>> And now apply the general quirks after applying CLINT specific quirks.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> ---
>>  lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
>>  1 file changed, 14 insertions(+), 3 deletions(-)
>>
>> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
>> index 9eaa11d..cd14f75 100644
>> --- a/lib/utils/timer/fdt_timer_mtimer.c
>> +++ b/lib/utils/timer/fdt_timer_mtimer.c
>> @@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
>>
>>  static struct aclint_mtimer_data *mt_reference = NULL;
>>
>> +static int timer_is_clint(const void *data)
>
>The timer is not clint, the timer is in the clint, right?

I have no idea about what you mean.
I think your meaning is that this is for clint timer, right?0
For this function, it just checks whether the quirk is for clint.

>How about timer_in_clint?
>

This name make me confused, maybe is_clint_quirk is better?

>> +{
>> +       const struct timer_mtimer_quirks *quirks = data;
>> +       return quirks && quirks->mtime_offset;
>> +}
>> +
>>  static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>>                                   const struct fdt_match *match)
>>  {
>> @@ -58,7 +64,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>>                 return rc;
>>         }
>>
>> -       if (match->data) { /* SiFive CLINT */
>> +       if (timer_is_clint(match->data)) { /* SiFive CLINT */
>The comment is confusing. So, how about deleting it:
>if (timer_in_clint(match->data)) {
>

I think this is ok, the code can be comment.

>>                 const struct timer_mtimer_quirks *quirks = match->data;
>>
>>                 /* Set CLINT addresses */
>> @@ -74,8 +80,6 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>>                         mt->mtime_addr = mt->mtime_size = 0;
>>                 }
>>                 mt->mtimecmp_addr += quirks->mtime_offset;
>> -               /* Apply additional CLINT quirks */
>> -               mt->has_64bit_mmio = quirks->has_64bit_mmio;
>>         } else { /* RISC-V ACLINT MTIMER */
>>                 /* Set ACLINT MTIMER addresses */
>>                 mt->mtime_addr = addr[0];
>> @@ -84,6 +88,13 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>>                 mt->mtimecmp_size = size[1];
>>         }
>>
>> +       /* Apply additional quirks for CLINT and ACLINT */
>> +       if (match->data) {
>> +               const struct timer_mtimer_quirks *quirks = match->data;
>> +
>> +               mt->has_64bit_mmio = quirks->has_64bit_mmio;
>> +       }
>> +
>>         /* Check if MTIMER device has shared MTIME address */
>>         if (mt->mtime_size) {
>>                 mt->has_shared_mtime = false;
>> --
>> 2.42.0
>>
>
>
>--
>Best Regards
> Guo Ren
>
>


From wxjstz at 126.com  Thu Oct 12 06:15:53 2023
From: wxjstz at 126.com (Xiang W)
Date: Thu, 12 Oct 2023 21:15:53 +0800
Subject: [PATCH v2] platform: Uses hart count as the default size of tlb
 info
In-Reply-To: <IA1PR20MB495379709E66871C21333296BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB495379709E66871C21333296BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <e7d9ee2f117fdb87ab073e229188e336e0203a46.camel@126.com>

? 2023-10-12???? 16:33 +0800?Inochi Amaoto???
> For platform with high number of harts, it is better to auto detect a
> suitable number of entries in tlb fifo. Since allocating tlb entry for
> all online harts can reduce the wait time significantly, using the
> number of the online harts can make most platforms happy. This auto
> detection can avoid most duplicate code for setting tlb fifo size.
> 
> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> Changed from v1:
> 1. replace SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES with hart count in all cases.
> 
> ---
> ?include/sbi/sbi_platform.h? | 3 +--
> ?platform/generic/platform.c | 2 +-
> ?2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 389203b..58b9069 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -41,7 +41,6 @@
> ?#define SBI_PLATFORM_HART_INDEX2ID_OFFSET (0x60 + (__SIZEOF_POINTER__ * 2))
> 
> ?#define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT		(1UL << 12)
> -#define SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES				8
> 
> ?#ifndef __ASSEMBLER__
> 
> @@ -330,7 +329,7 @@ static inline u32 sbi_platform_tlb_fifo_num_entries(const struct sbi_platform *p
> ?{
> ?	if (plat && sbi_platform_ops(plat)->get_tlb_num_entries)
> ?		return sbi_platform_ops(plat)->get_tlb_num_entries();
> -	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> +	return sbi_scratch_last_hartindex() + 1;
> ?}
> 
> ?/**
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 66a0b77..4246efd 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -260,7 +260,7 @@ static u32 generic_tlb_num_entries(void)
> ?{
> ?	if (generic_plat && generic_plat->tlb_num_entries)
> ?		return generic_plat->tlb_num_entries(generic_plat_match);
> -	return SBI_PLATFORM_TLB_FIFO_NUM_ENTRIES;
> +	return sbi_scratch_last_hartindex() + 1;
> ?}
> 
> ?static int generic_pmu_init(void)
> --
> 2.42.0



From guoren at kernel.org  Thu Oct 12 18:05:28 2023
From: guoren at kernel.org (Guo Ren)
Date: Fri, 13 Oct 2023 09:05:28 +0800
Subject: [PATCH 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <IA1PR20MB4953FF9940A6522ADDB18AC3BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <CAJF2gTSwKx6T9YmKN8i+R_VZ9H9MTVs9NygUiDhRBip_bjDdwQ@mail.gmail.com>
 <IA1PR20MB4953FF9940A6522ADDB18AC3BBD3A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <CAJF2gTStYzrYon2xuq3TFPLVkH=mS_-weNV9xM9r25p2xTsevA@mail.gmail.com>

On Thu, Oct 12, 2023 at 7:19?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>
> >On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
> >>
> >> The quirks checking will cause ACLINT step into a CLINT code path, this
> >> is not expected when ACLINT needs a quirks.
> >>
> >> Add more check to ensure the timer is CLINT before applying quirks.
> >> And now apply the general quirks after applying CLINT specific quirks.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
> >> ---
> >>  lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
> >>  1 file changed, 14 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> >> index 9eaa11d..cd14f75 100644
> >> --- a/lib/utils/timer/fdt_timer_mtimer.c
> >> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> >> @@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
> >>
> >>  static struct aclint_mtimer_data *mt_reference = NULL;
> >>
> >> +static int timer_is_clint(const void *data)
> >
> >The timer is not clint, the timer is in the clint, right?
>
> I have no idea about what you mean.
> I think your meaning is that this is for clint timer, right?0
> For this function, it just checks whether the quirk is for clint.
>
> >How about timer_in_clint?
> >
>
> This name make me confused, maybe is_clint_quirk is better?
In timer_is_clint, you detect mtime_offset, if "mtime_offset != 0"
means the clint address contains a timer, we add an offset for it.
Otherwise, clint & timer are separated.

That's my suggestion of timer_in_clint's meaning. The is_clint_quirk
didn't give the correct meaning because the quirk is always there.

Here are many options:
!timer_is_separate(data)/clint_contains_timer(data)/!clint_is_separate(data)/!clint_is_split(data)/...

>
> >> +{
> >> +       const struct timer_mtimer_quirks *quirks = data;
> >> +       return quirks && quirks->mtime_offset;
> >> +}
> >> +
> >>  static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> >>                                   const struct fdt_match *match)
> >>  {
> >> @@ -58,7 +64,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> >>                 return rc;
> >>         }
> >>
> >> -       if (match->data) { /* SiFive CLINT */
> >> +       if (timer_is_clint(match->data)) { /* SiFive CLINT */
> >The comment is confusing. So, how about deleting it:
> >if (timer_in_clint(match->data)) {
> >
>
> I think this is ok, the code can be comment.
>
> >>                 const struct timer_mtimer_quirks *quirks = match->data;
> >>
> >>                 /* Set CLINT addresses */
> >> @@ -74,8 +80,6 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> >>                         mt->mtime_addr = mt->mtime_size = 0;
> >>                 }
> >>                 mt->mtimecmp_addr += quirks->mtime_offset;
> >> -               /* Apply additional CLINT quirks */
> >> -               mt->has_64bit_mmio = quirks->has_64bit_mmio;
> >>         } else { /* RISC-V ACLINT MTIMER */
> >>                 /* Set ACLINT MTIMER addresses */
> >>                 mt->mtime_addr = addr[0];
> >> @@ -84,6 +88,13 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> >>                 mt->mtimecmp_size = size[1];
> >>         }
> >>
> >> +       /* Apply additional quirks for CLINT and ACLINT */
> >> +       if (match->data) {
> >> +               const struct timer_mtimer_quirks *quirks = match->data;
> >> +
> >> +               mt->has_64bit_mmio = quirks->has_64bit_mmio;
> >> +       }
> >> +
> >>         /* Check if MTIMER device has shared MTIME address */
> >>         if (mt->mtime_size) {
> >>                 mt->has_shared_mtime = false;
> >> --
> >> 2.42.0
> >>
> >
> >
> >--
> >Best Regards
> > Guo Ren
> >
> >



-- 
Best Regards
 Guo Ren


From inochiama at outlook.com  Thu Oct 12 23:45:35 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 13 Oct 2023 14:45:35 +0800
Subject: [PATCH 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <CAJF2gTStYzrYon2xuq3TFPLVkH=mS_-weNV9xM9r25p2xTsevA@mail.gmail.com>
References: <CAJF2gTStYzrYon2xuq3TFPLVkH=mS_-weNV9xM9r25p2xTsevA@mail.gmail.com>
Message-ID: <IA1PR20MB4953FDDA2BC139F71DEC19C7BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>

>On Thu, Oct 12, 2023 at 7:19?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>>
>>> On Thu, Oct 12, 2023 at 5:01?PM Inochi Amaoto <inochiama at outlook.com> wrote:
>>>>
>>>> The quirks checking will cause ACLINT step into a CLINT code path, this
>>>> is not expected when ACLINT needs a quirks.
>>>>
>>>> Add more check to ensure the timer is CLINT before applying quirks.
>>>> And now apply the general quirks after applying CLINT specific quirks.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>>>> ---
>>>>  lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
>>>>  1 file changed, 14 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
>>>> index 9eaa11d..cd14f75 100644
>>>> --- a/lib/utils/timer/fdt_timer_mtimer.c
>>>> +++ b/lib/utils/timer/fdt_timer_mtimer.c
>>>> @@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
>>>>
>>>>  static struct aclint_mtimer_data *mt_reference = NULL;
>>>>
>>>> +static int timer_is_clint(const void *data)
>>>
>>> The timer is not clint, the timer is in the clint, right?
>>
>> I have no idea about what you mean.
>> I think your meaning is that this is for clint timer, right?0
>> For this function, it just checks whether the quirk is for clint.
>>
>>> How about timer_in_clint?
>>>
>>
>> This name make me confused, maybe is_clint_quirk is better?
>In timer_is_clint, you detect mtime_offset, if "mtime_offset != 0"
>means the clint address contains a timer, we add an offset for it.
>Otherwise, clint & timer are separated.
>

OK, I take it.

>That's my suggestion of timer_in_clint's meaning. The is_clint_quirk
>didn't give the correct meaning because the quirk is always there.
>

In fact, the quirk for aclint is confusing. IIRC, both the quirks for
aclint and quirks for clint are in the same struct. The quirk struct may
need a split, but this is not the thing this patch should care about.

>Here are many options:
>!timer_is_separate(data)/clint_contains_timer(data)/!clint_is_separate(data)/!clint_is_split(data)/...
>
I will take clint_contains_timer for this action, it is better to describe
the thing we are talking about.


From inochiama at outlook.com  Thu Oct 12 23:46:02 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 13 Oct 2023 14:46:02 +0800
Subject: [PATCH v2 0/3] lib: utils: Add T-HEAD C900 ACLINT
Message-ID: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>

Add T-HEAD C900 ACLINT driver for sg2042

The timer quirks need the following patch to parse thead mtime:
lib: utils/fdt: Allow zero length mtime when parsing ACLINT

Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/

Changed from v1:
1. function fix and comment cleanup.

Changed from sg2042 v2:
1. Allow ACLINT has its own quirks
2. add new quirks for thead,c900-aclint-mtimer

This patch is moved from the patch series of supporting sg2042 as it
became complex.
The original patch: platform: generic: Add Sophgo sg2042 support

Inochi Amaoto (3):
  lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
  lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer
    compatible
  lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible

 lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
 lib/utils/timer/fdt_timer_mtimer.c | 23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

--
2.42.0



From inochiama at outlook.com  Thu Oct 12 23:46:59 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 13 Oct 2023 14:46:59 +0800
Subject: [PATCH v2 1/3] lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
In-Reply-To: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953107FD516BD3BF45704C6BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>

The quirks checking will cause ACLINT step into a CLINT code path, this
is not expected when ACLINT needs a quirks.

Add more check to ensure the timer is CLINT before applying quirks.
And now apply the general quirks after applying CLINT specific quirks.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
---
 lib/utils/timer/fdt_timer_mtimer.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 9eaa11d..fb5917f 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -29,6 +29,12 @@ static SBI_LIST_HEAD(mtn_list);
 
 static struct aclint_mtimer_data *mt_reference = NULL;
 
+static int clint_contains_timer(const void *data)
+{
+	const struct timer_mtimer_quirks *quirks = data;
+	return quirks && quirks->mtime_offset;
+}
+
 static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 				  const struct fdt_match *match)
 {
@@ -58,7 +64,7 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		return rc;
 	}
 
-	if (match->data) { /* SiFive CLINT */
+	if (clint_contains_timer(match->data)) {
 		const struct timer_mtimer_quirks *quirks = match->data;
 
 		/* Set CLINT addresses */
@@ -74,8 +80,6 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 			mt->mtime_addr = mt->mtime_size = 0;
 		}
 		mt->mtimecmp_addr += quirks->mtime_offset;
-		/* Apply additional CLINT quirks */
-		mt->has_64bit_mmio = quirks->has_64bit_mmio;
 	} else { /* RISC-V ACLINT MTIMER */
 		/* Set ACLINT MTIMER addresses */
 		mt->mtime_addr = addr[0];
@@ -84,6 +88,13 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		mt->mtimecmp_size = size[1];
 	}
 
+	/* Apply additional quirks for CLINT and ACLINT */
+	if (match->data) {
+		const struct timer_mtimer_quirks *quirks = match->data;
+
+		mt->has_64bit_mmio = quirks->has_64bit_mmio;
+	}
+
 	/* Check if MTIMER device has shared MTIME address */
 	if (mt->mtime_size) {
 		mt->has_shared_mtime = false;
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 23:47:00 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 13 Oct 2023 14:47:00 +0800
Subject: [PATCH v2 2/3] lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer compatible
In-Reply-To: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB4953AD97529FD723312F6C43BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>

T-HEAD allows soc vendor to map the mtimer and mswi of C9xx clint on
different address, which may cause a misuse if use the same compatible
string, add a new timer compatible string to avoid this.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang at outlook.com/
Reviewed-by: Guo Ren <guoren at kernel.org>
---
 lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index fb5917f..a873f1e 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -153,10 +153,16 @@ static const struct timer_mtimer_quirks thead_clint_quirks = {
 	.without_mtime  = true,
 };
 
+static const struct timer_mtimer_quirks thead_aclint_quirks = {
+	.has_64bit_mmio	= false,
+};
+
 static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
+	{ .compatible = "thead,c900-aclint-mtimer",
+	  .data = &thead_aclint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.42.0



From inochiama at outlook.com  Thu Oct 12 23:47:01 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 13 Oct 2023 14:47:01 +0800
Subject: [PATCH v2 3/3] lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
In-Reply-To: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <IA1PR20MB49533BA0170E1F1A025EBF99BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <IA1PR20MB49534DF6838E0801E267A8C2BBD2A@IA1PR20MB4953.namprd20.prod.outlook.com>

Like the mtimer of T-HEAD C9xx clint, the mswi also needs new compatible
string to avoid misuse.

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Link: https://lore.kernel.org/linux-riscv/1f6b82a1864477a51db33d3f295889ff985b497b.1696433229.git.unicorn_wang at outlook.com/
Reviewed-by: Guo Ren <guoren at kernel.org>
---
 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index e3a6378..5432db6 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
 	{ .compatible = "thead,c900-clint", .data = &clint_offset },
+	{ .compatible = "thead,c900-aclint-mswi" },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.42.0



From cp0613 at linux.alibaba.com  Tue Oct 17 04:53:12 2023
From: cp0613 at linux.alibaba.com (cp0613 at linux.alibaba.com)
Date: Tue, 17 Oct 2023 19:53:12 +0800
Subject: [PATCH] lib: utils/serial: Optimize semihosting_putc implementation
Message-ID: <20231017115312.268-1-cp0613@linux.alibaba.com>

From: Chen Pei <cp0613 at linux.alibaba.com>

For some debuggers that do not implement SYSWRITEC and SYSREADC
operations, we can use SYSWRITE and SYSREAD instead like the
implementation of semihosting_getc().

Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
---
 lib/utils/serial/semihosting.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index ce65887..9bbf2e2 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -162,7 +162,10 @@ static long semihosting_write(long fd, const void *memp, size_t len)
 
 static void semihosting_putc(char ch)
 {
-	semihosting_trap(SYSWRITEC, &ch);
+	if (semihosting_outfd < 0)
+		semihosting_trap(SYSWRITEC, &ch);
+	else
+		semihosting_write(semihosting_outfd, &ch, 1);
 }
 
 static unsigned long semihosting_puts(const char *str, unsigned long len)
-- 
2.25.1



From wxjstz at 126.com  Tue Oct 17 09:57:27 2023
From: wxjstz at 126.com (Xiang W)
Date: Wed, 18 Oct 2023 00:57:27 +0800
Subject: [PATCH] lib: utils/serial: Optimize semihosting_putc
 implementation
In-Reply-To: <20231017115312.268-1-cp0613@linux.alibaba.com>
References: <20231017115312.268-1-cp0613@linux.alibaba.com>
Message-ID: <1bafdb31530fe5264f232dd2539b5cd2b718344a.camel@126.com>

? 2023-10-17???? 19:53 +0800?cp0613 at linux.alibaba.com???
> From: Chen Pei <cp0613 at linux.alibaba.com>
> 
> For some debuggers that do not implement SYSWRITEC and SYSREADC
> operations, we can use SYSWRITE and SYSREAD instead like the
> implementation of semihosting_getc().
> 
> Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> ---
> ?lib/utils/serial/semihosting.c | 5 ++++-
> ?1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index ce65887..9bbf2e2 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -162,7 +162,10 @@ static long semihosting_write(long fd, const void *memp, size_t len)
> ?
> ?static void semihosting_putc(char ch)
> ?{
> -	semihosting_trap(SYSWRITEC, &ch);
> +	if (semihosting_outfd < 0)
> +		semihosting_trap(SYSWRITEC, &ch);
> +	else
> +		semihosting_write(semihosting_outfd, &ch, 1);
The code can be simplified by calling semihosting_puts directly, otherwise look good to me.

Reviewed-by: Xiang W <wxjstz at 126.com>
> ?}
> ?
> ?static unsigned long semihosting_puts(const char *str, unsigned long len)
> -- 
> 2.25.1
> 
> 



From samuel.holland at sifive.com  Tue Oct 17 15:20:19 2023
From: samuel.holland at sifive.com (Samuel Holland)
Date: Tue, 17 Oct 2023 15:20:19 -0700
Subject: [PATCH] lib: sbi: Correctly limit flushes to a single ASID/VMID
Message-ID: <20231017222027.3668468-1-samuel.holland@sifive.com>

Per the SBI specification, the effects of these functions are limited to
a specific ASID and/or VMID. This applies even when flushing the entire
address space.

Signed-off-by: Samuel Holland <samuel.holland at sifive.com>
---
The SBI spec doesn't say anything about this `start == 0 && size == 0`
exception, so I wonder if it should be removed entirely.

 lib/sbi/sbi_tlb.c | 21 +++------------------
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/lib/sbi/sbi_tlb.c b/lib/sbi/sbi_tlb.c
index ced2854..dad9508 100644
--- a/lib/sbi/sbi_tlb.c
+++ b/lib/sbi/sbi_tlb.c
@@ -111,12 +111,7 @@ void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
 	hgatp = csr_swap(CSR_HGATP,
 			 (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
 
-	if (start == 0 && size == 0) {
-		__sbi_hfence_vvma_all();
-		goto done;
-	}
-
-	if (size == SBI_TLB_FLUSH_ALL) {
+	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_hfence_vvma_asid(asid);
 		goto done;
 	}
@@ -138,12 +133,7 @@ void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD);
 
-	if (start == 0 && size == 0) {
-		__sbi_hfence_gvma_all();
-		return;
-	}
-
-	if (size == SBI_TLB_FLUSH_ALL) {
+	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__sbi_hfence_gvma_vmid(vmid);
 		return;
 	}
@@ -162,13 +152,8 @@ void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo)
 
 	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD);
 
-	if (start == 0 && size == 0) {
-		tlb_flush_all();
-		return;
-	}
-
 	/* Flush entire MM context for a given ASID */
-	if (size == SBI_TLB_FLUSH_ALL) {
+	if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
 		__asm__ __volatile__("sfence.vma x0, %0"
 				     :
 				     : "r"(asid)
-- 
2.41.0



From cp0613 at linux.alibaba.com  Tue Oct 17 19:42:05 2023
From: cp0613 at linux.alibaba.com (cp0613 at linux.alibaba.com)
Date: Wed, 18 Oct 2023 10:42:05 +0800
Subject: [PATCH v2] lib: utils/serial: Optimize semihosting_putc implementation
Message-ID: <20231018024205.270-1-cp0613@linux.alibaba.com>

From: Chen Pei <cp0613 at linux.alibaba.com>

For some debuggers that do not implement SYSWRITEC and SYSREADC
operations, we can use SYSWRITE and SYSREAD instead like the
implementation of semihosting_getc().

Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
Reviewed-by: Xiang W <wxjstz at 126.com>

Changed from v1:
1. simplified by calling semihosting_puts directly.

---
 lib/utils/serial/semihosting.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index ce65887..a27c69e 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
 
 /* clang-format on */
 
-static void semihosting_putc(char ch)
-{
-	semihosting_trap(SYSWRITEC, &ch);
-}
-
 static unsigned long semihosting_puts(const char *str, unsigned long len)
 {
 	char ch;
@@ -183,6 +178,11 @@ static unsigned long semihosting_puts(const char *str, unsigned long len)
 	return (ret < 0) ? 0 : ret;
 }
 
+static void semihosting_putc(char ch)
+{
+	semihosting_puts(&ch, 1);
+}
+
 static int semihosting_getc(void)
 {
 	char ch = 0;
-- 
2.25.1



From ajones at ventanamicro.com  Thu Oct 19 01:43:06 2023
From: ajones at ventanamicro.com (Andrew Jones)
Date: Thu, 19 Oct 2023 10:43:06 +0200
Subject: [PATCH] include: sbi: Change spec version to 2.0
In-Reply-To: <20231010102125.603343-1-apatel@ventanamicro.com>
References: <20231010102125.603343-1-apatel@ventanamicro.com>
Message-ID: <20231019-1a0cc8a5a3643dbf4d4d51f6@orel>

On Tue, Oct 10, 2023 at 03:51:25PM +0530, Anup Patel wrote:
> Now that SBI v2.0 specification is frozen, we change spec verion
> implemented by OpenSBI to v2.0.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_ecall.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/sbi/sbi_ecall.h b/include/sbi/sbi_ecall.h
> index 90f33ba..027213c 100644
> --- a/include/sbi/sbi_ecall.h
> +++ b/include/sbi/sbi_ecall.h
> @@ -13,7 +13,7 @@
>  #include <sbi/sbi_types.h>
>  #include <sbi/sbi_list.h>
>  
> -#define SBI_ECALL_VERSION_MAJOR		1
> +#define SBI_ECALL_VERSION_MAJOR		2
>  #define SBI_ECALL_VERSION_MINOR		0
>  #define SBI_OPENSBI_IMPID		1
>  
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones at ventanamicro.com>


It'd be good to get this merged and also build a new version of opensbi
which can be incorporated into QEMU. Without this change several new SBI
extensions won't be usable by Linux, even though the implementations are
present, because Linux checks that the SBI implementation version is at
least as big as the spec version where the extensions were frozen.

Thanks,
drew


From guoren at kernel.org  Thu Oct 19 02:27:34 2023
From: guoren at kernel.org (guoren at kernel.org)
Date: Thu, 19 Oct 2023 05:27:34 -0400
Subject: [PATCH] fw_base.S: Fix boot hart status synchronization
Message-ID: <20231019092734.2554798-1-guoren@kernel.org>

From: Guo Ren <guoren at linux.alibaba.com>

It's wrong to put the fence after setting the boot status flag because
all relocation operations must be finished before setting the status
flag. So, this fence must be put before the setting status flag, and
there is no use in putting a fence between _start_warm and setting
status flag.

Also, nop can't delay other harts too much, so use div instead, just
like Linux cpu_relax. Current opensbi force enables ?M? Standard
Extension, and mul instructions have been used in the fw_base.S.

After the above two fixes, the boot hart index param of the
fw_dynamic_info could be guaranteed properly for all platforms.

Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
Signed-off-by: Guo Ren <guoren at kernel.org>
---
 firmware/fw_base.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index 42b03fe890f0..f7763f4d9e56 100644
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -399,8 +399,8 @@ _fdt_reloc_done:
 	/* mark boot hart done */
 	li	t0, BOOT_STATUS_BOOT_HART_DONE
 	lla	t1, _boot_status
-	REG_S	t0, 0(t1)
 	fence	rw, rw
+	REG_S	t0, 0(t1)
 	j	_start_warm
 
 	/* waiting for boot hart to be done (_boot_status == 2) */
@@ -409,9 +409,9 @@ _wait_for_boot_hart:
 	lla	t1, _boot_status
 	REG_L	t1, 0(t1)
 	/* Reduce the bus traffic so that boot hart may proceed faster */
-	nop
-	nop
-	nop
+	div	t2, t2, zero
+	div	t2, t2, zero
+	div	t2, t2, zero
 	bne	t0, t1, _wait_for_boot_hart
 
 _start_warm:
-- 
2.36.1



From peterlin at andestech.com  Thu Oct 19 04:37:04 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:04 +0800
Subject: [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-3-peterlin@andestech.com>

Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - No change
---
 include/sbi/sbi_pmu.h | 6 ++++++
 lib/sbi/sbi_pmu.c     | 5 ++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
index 16f6877..d63149c 100644
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -89,6 +89,12 @@ struct sbi_pmu_device {
 	 * Custom function returning the machine-specific irq-bit.
 	 */
 	int (*hw_counter_irq_bit)(void);
+
+	/**
+	 * Custom function to inhibit counting of events while in
+	 * specified mode.
+	 */
+	void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
 };
 
 /** Get the PMU platform device */
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 3cbd4ff..7e3723f 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
 		pmu_dev->hw_counter_disable_irq(ctr_idx);
 
 	/* Update the inhibit flags based on inhibit flags received from supervisor */
-	pmu_update_inhibit_flags(flags, &mhpmevent_val);
+	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+		pmu_update_inhibit_flags(flags, &mhpmevent_val);
+	if (pmu_dev && pmu_dev->hw_counter_filter_mode)
+		pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
 
 #if __riscv_xlen == 32
 	csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:02 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:02 +0800
Subject: [PATCH v2 00/11] Add Andes PMU extension support
Message-ID: <20231019113713.3508153-1-peterlin@andestech.com>

This patch series enables perf tool to utilize Andes PMU
extension via PMU SBI calls, provides PMU device callbacks
to achieve event sampling and mode filtering.

This version also introduces a platform override fdt_add_pmu_mappings()
to create event mappings before PMU setup if a valid PMU node
is missing.

The last patch provides a PMU node example used on AX45MP cores.

The OpenSBI and Linux patches can be found on Andes Technology GitHub
- https://github.com/andestech/opensbi/commits/andes-pmu-support-v2
- https://github.com/andestech/linux/commits/andes-pmu-support-v2

Yu Chien Peter Lin (11):
  sbi: sbi_pmu: Improve sbi_pmu_init() error handling
  sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
  platform: include: andes45: Add PMU related CSR defines
  platform: andes: Add Andes custom PMU support
  platform: andes: Enable Andes PMU for AE350
  platform: rzfive: Enable Andes PMU for RZ/Five
  lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
  lib: utils: fdt_fixup: Allow preserving PMU properties
  platform: andes: Factor out is_andes() helper
  platform: andes: Implement andes_fdt_add_pmu_mappings platform
    override
  docs: pmu: Add Andes PMU node example

 docs/pmu_support.md                          |  82 ++++
 include/sbi/sbi_ecall_interface.h            |   5 +
 include/sbi/sbi_pmu.h                        |   6 +
 include/sbi/sbi_scratch.h                    |   2 +
 include/sbi_utils/fdt/fdt_fixup.h            |  48 +++
 lib/sbi/sbi_pmu.c                            |  10 +-
 lib/utils/fdt/fdt_fixup.c                    | 101 ++++-
 lib/utils/fdt/fdt_pmu.c                      |   2 +-
 platform/generic/Kconfig                     |   4 +
 platform/generic/andes/Kconfig               |  11 +
 platform/generic/andes/ae350.c               |  31 +-
 platform/generic/andes/andes_hpm.c           | 381 +++++++++++++++++++
 platform/generic/andes/andes_pmu.c           |  81 ++++
 platform/generic/andes/objects.mk            |   2 +
 platform/generic/include/andes/andes45.h     |  32 ++
 platform/generic/include/andes/andes_hpm.h   |  83 ++++
 platform/generic/include/andes/andes_pmu.h   |   8 +
 platform/generic/include/platform_override.h |   1 +
 platform/generic/platform.c                  |  16 +-
 platform/generic/renesas/rzfive/rzfive.c     |  18 +-
 20 files changed, 909 insertions(+), 15 deletions(-)
 create mode 100644 platform/generic/andes/andes_hpm.c
 create mode 100644 platform/generic/andes/andes_pmu.c
 create mode 100644 platform/generic/include/andes/andes_hpm.h
 create mode 100644 platform/generic/include/andes/andes_pmu.h

-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:03 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:03 +0800
Subject: [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-2-peterlin@andestech.com>

This patch makes the following changes:

- As sbi_platform_pmu_init() returns a negative error code on
  failure, let sbi_pmu_init() to hang by propagating the error
  code.

- In order to distinguish the SBI_EFAIL error returned by
  sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
  that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
  generic_pmu_init() ignores such case.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 lib/sbi/sbi_pmu.c           | 5 ++++-
 lib/utils/fdt/fdt_pmu.c     | 2 +-
 platform/generic/platform.c | 8 +++++++-
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index f4c8fc4..3cbd4ff 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
 	int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
 	struct sbi_pmu_hart_state *phs;
 	const struct sbi_platform *plat;
+	int rc;
 
 	if (cold_boot) {
 		hw_event_map = sbi_calloc(sizeof(*hw_event_map),
@@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
 
 		plat = sbi_platform_ptr(scratch);
 		/* Initialize hw pmu events */
-		sbi_platform_pmu_init(plat);
+		rc = sbi_platform_pmu_init(plat);
+		if (rc)
+			return rc;
 
 		/* mcycle & minstret is available always */
 		if (!hpm_count)
diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
index 83301bb..a8d7648 100644
--- a/lib/utils/fdt/fdt_pmu.c
+++ b/lib/utils/fdt/fdt_pmu.c
@@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
 
 	pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
 	if (pmu_offset < 0)
-		return SBI_EFAIL;
+		return SBI_ENOENT;
 
 	event_ctr_map = fdt_getprop(fdt, pmu_offset,
 				    "riscv,event-to-mhpmcounters", &len);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..cb9270d 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
 
 static int generic_pmu_init(void)
 {
-	return fdt_pmu_setup(fdt_get_address());
+	int rc;
+
+	rc = fdt_pmu_setup(fdt_get_address());
+	if (rc && rc != SBI_ENOENT)
+		return rc;
+
+	return 0;
 }
 
 static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:05 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:05 +0800
Subject: [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-4-peterlin@andestech.com>

This patch adds CSR for Andes PMU extension.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - Rename andes_pmu() -> has_andes_pmu()
---
 platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index f570994..ce31617 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -12,6 +12,17 @@
 #define CSR_MDCM_CFG		0xfc1
 #define CSR_MMSC_CFG		0xfc2
 
+/* Machine Trap Related Registers */
+#define CSR_MSLIDELEG		0x7d5
+
+/* Counter Related Registers */
+#define CSR_MCOUNTERWEN		0x7ce
+#define CSR_MCOUNTERINTEN	0x7cf
+#define CSR_MCOUNTERMASK_M	0x7d1
+#define CSR_MCOUNTERMASK_S	0x7d2
+#define CSR_MCOUNTERMASK_U	0x7d3
+#define CSR_MCOUNTEROVF		0x7d4
+
 #define MICM_CFG_ISZ_OFFSET		6
 #define MICM_CFG_ISZ_MASK		(0x7  << MICM_CFG_ISZ_OFFSET)
 
@@ -26,4 +37,19 @@
 #define MCACHE_CTL_CCTL_SUEN_OFFSET	8
 #define MCACHE_CTL_CCTL_SUEN_MASK	(0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
 
+/* Performance monitor */
+#define MMSC_CFG_PMNDS_MASK		(1 << 15)
+#define MIP_PMOVI			(1 << 18)
+
+#ifndef __ASSEMBLER__
+
+#define has_andes_pmu()					\
+({							\
+	(((csr_read(CSR_MMSC_CFG) &			\
+	   MMSC_CFG_PMNDS_MASK)				\
+	  && misa_extension('S')) ? true : false);	\
+})
+
+#endif /* __ASSEMBLER__ */
+
 #endif /* _RISCV_ANDES45_H */
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:06 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:06 +0800
Subject: [PATCH v2 04/11] platform: andes: Add Andes custom PMU support
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-5-peterlin@andestech.com>

Before the ratification of Sscofpmf, the Andes PMU extension
was designed to support the sampling and filtering with hardware
performance counters, it works with the current SBI PMU extension
and Linux SBI PMU driver.

This patch implements the PMU device callbacks that update the
corresponding bits on custom CSRs.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - Fix mode filtering in andes_hw_counter_filter_mode()
  - Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
  - Don't grant write permissions via CSR_MCOUNTERWEN as not needed
---
 platform/generic/andes/Kconfig             |  4 ++
 platform/generic/andes/andes_pmu.c         | 81 ++++++++++++++++++++++
 platform/generic/andes/objects.mk          |  1 +
 platform/generic/include/andes/andes_pmu.h |  8 +++
 4 files changed, 94 insertions(+)
 create mode 100644 platform/generic/andes/andes_pmu.c
 create mode 100644 platform/generic/include/andes/andes_pmu.h

diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index a91fb9c..555e4fe 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -7,3 +7,7 @@ config ANDES45_PMA
 config ANDES_SBI
 	bool "Andes SBI support"
 	default n
+
+config ANDES_PMU
+	bool "Andes custom PMU extension support"
+	default n
diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
new file mode 100644
index 0000000..0f6ecc0
--- /dev/null
+++ b/platform/generic/andes/andes_pmu.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#include <andes/andes45.h>
+#include <andes/andes_pmu.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_pmu.h>
+#include <sbi/sbi_scratch.h>
+
+static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
+{
+	unsigned long mip_val;
+
+	if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+		return;
+
+	mip_val = csr_read(CSR_MIP);
+	if (!(mip_val & MIP_PMOVI))
+		csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
+
+	csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
+{
+	csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
+{
+	if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
+		csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+	else
+		csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+
+	if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
+		csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+	else
+		csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+}
+
+static struct sbi_pmu_device andes_pmu = {
+	.name = "andes_pmu",
+	.hw_counter_enable_irq  = andes_hw_counter_enable_irq,
+	.hw_counter_disable_irq = andes_hw_counter_disable_irq,
+	/*
+	 * We set delegation of supervisor local interrupts via
+	 * 18th bit on mslideleg instead of mideleg, so leave
+	 * hw_counter_irq_bit() callback unimplemented.
+	 */
+	.hw_counter_irq_bit     = NULL,
+	.hw_counter_filter_mode = andes_hw_counter_filter_mode
+};
+
+int andes_pmu_init(void)
+{
+	if (!has_andes_pmu())
+		return SBI_ENOTSUPP;
+
+	/*
+	 * It is not reasonable for an Andes CPU to support
+	 * both Andes PMU and standard Sscofpmf, as they
+	 * serve the same purpose.
+	 */
+	if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+				   SBI_HART_EXT_SSCOFPMF))
+		sbi_hart_hang();
+
+	/* Inhibit HPM counter in M-mode */
+	csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
+	/* Delegate S-mode local interrupt to S-mode */
+	csr_write(CSR_MSLIDELEG, MIP_PMOVI);
+
+	sbi_pmu_set_device(&andes_pmu);
+
+	return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index e8f86ea..6a8c66c 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
 
 platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
 platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
+platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h
new file mode 100644
index 0000000..70b3a12
--- /dev/null
+++ b/platform/generic/include/andes/andes_pmu.h
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: BSD-2-Clause
+
+#ifndef _RISCV_ANDES_PMU_H
+#define _RISCV_ANDES_PMU_H
+
+int andes_pmu_init(void);
+
+#endif /* _RISCV_ANDES_PMU_H */
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:07 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:07 +0800
Subject: [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-6-peterlin@andestech.com>

Enable Andes PMU extension support for AE350 platforms.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - Implement ae350_extensions_init()
---
 platform/generic/Kconfig       |  1 +
 platform/generic/andes/ae350.c | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index e7bd94e..9b2f9c7 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
 config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
 	select SYS_ATCSMU
+	select ANDES_PMU
 	default n
 
 config PLATFORM_RENESAS_RZFIVE
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 80eca05..c3f280d 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -8,6 +8,7 @@
  */
 
 #include <platform_override.h>
+#include <andes/andes_pmu.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/fdt/fdt_fixup.h>
 #include <sbi_utils/sys/atcsmu.h>
@@ -110,6 +111,17 @@ static int ae350_final_init(bool cold_boot, const struct fdt_match *match)
 	return 0;
 }
 
+static int ae350_extensions_init(const struct fdt_match *match,
+			  struct sbi_hart_features *hfeatures)
+{
+	int rc;
+	rc = andes_pmu_init();
+	if (rc && rc != SBI_ENOTSUPP)
+		return rc;
+
+	return 0;
+}
+
 static const struct fdt_match andes_ae350_match[] = {
 	{ .compatible = "andestech,ae350" },
 	{ },
@@ -118,4 +130,5 @@ static const struct fdt_match andes_ae350_match[] = {
 const struct platform_override andes_ae350 = {
 	.match_table = andes_ae350_match,
 	.final_init  = ae350_final_init,
+	.extensions_init = ae350_extensions_init,
 };
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:08 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:08 +0800
Subject: [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-7-peterlin@andestech.com>

Enable Andes PMU extension support for RZ/Five.
This patch also staticize renesas_rzfive_early_init() as
it is not used outside of this unit.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - Implement renesas_rzfive_extensions_init()
  - staticize renesas_rzfive_early_init()
---
 platform/generic/Kconfig                 |  1 +
 platform/generic/renesas/rzfive/rzfive.c | 16 +++++++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 9b2f9c7..d6dafef 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -38,6 +38,7 @@ config PLATFORM_RENESAS_RZFIVE
 	bool "Renesas RZ/Five support"
 	select ANDES45_PMA
 	select ANDES_SBI
+	select ANDES_PMU
 	default n
 
 config PLATFORM_SIFIVE_FU540
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index a69797b..2f772c8 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,9 +5,11 @@
  */
 
 #include <andes/andes45_pma.h>
+#include <andes/andes_pmu.h>
 #include <andes/andes_sbi.h>
 #include <platform_override.h>
 #include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
 static const struct andes45_pma_region renesas_rzfive_pma_regions[] = {
@@ -29,7 +31,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
 					 array_size(renesas_rzfive_pma_regions));
 }
 
-int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
+static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
 {
 	/*
 	 * Renesas RZ/Five RISC-V SoC has Instruction local memory and
@@ -47,6 +49,17 @@ int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
 					    SBI_DOMAIN_MEMREGION_M_RWX);
 }
 
+static int renesas_rzfive_extensions_init(const struct fdt_match *match,
+			  struct sbi_hart_features *hfeatures)
+{
+	int rc;
+	rc = andes_pmu_init();
+	if (rc && rc != SBI_ENOTSUPP)
+		return rc;
+
+	return 0;
+}
+
 static const struct fdt_match renesas_rzfive_match[] = {
 	{ .compatible = "renesas,r9a07g043f01" },
 	{ /* sentinel */ }
@@ -57,4 +70,5 @@ const struct platform_override renesas_rzfive = {
 	.early_init = renesas_rzfive_early_init,
 	.final_init = renesas_rzfive_final_init,
 	.vendor_ext_provider = andes_sbi_vendor_ext_provider,
+	.extensions_init = renesas_rzfive_extensions_init,
 };
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:09 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:09 +0800
Subject: [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-8-peterlin@andestech.com>

Add fdt_add_pmu_mappings() that creates entries of riscv,*event-to-mhpm*
property from arrays right before fdt_pmu_setup() populating the mapping
tables (i.e. hw_event_map[] and fdt_pmu_evt_select[]).

The helper function will skip the creation of those properties if a
"/pmu" node with "riscv,pmu" compatible string is provided.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 include/sbi_utils/fdt/fdt_fixup.h            | 48 ++++++++++
 lib/utils/fdt/fdt_fixup.c                    | 95 ++++++++++++++++++++
 platform/generic/include/platform_override.h |  1 +
 platform/generic/platform.c                  | 10 ++-
 4 files changed, 153 insertions(+), 1 deletion(-)

diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
index ecd55a7..9b72df8 100644
--- a/include/sbi_utils/fdt/fdt_fixup.h
+++ b/include/sbi_utils/fdt/fdt_fixup.h
@@ -19,6 +19,54 @@ struct sbi_cpu_idle_state {
 	uint32_t wakeup_latency_us;
 };
 
+struct sbi_pmu_event_select_map {
+	/**
+	 * The description of an entry in
+	 * riscv,event-to-mhpmevent property
+	 */
+	uint32_t eidx;
+	uint64_t select;
+};
+
+struct sbi_pmu_event_counter_map {
+	/**
+	 * The description of an entry in
+	 * riscv,event-to-mhpmcounters property
+	 */
+	uint32_t eidx_start;
+	uint32_t eidx_end;
+	uint32_t ctr_map;
+};
+
+struct sbi_pmu_raw_event_counter_map {
+	/**
+	 * The description of an entry in
+	 * riscv,raw-event-to-mhpmcounters property
+	 */
+	uint64_t select;
+	uint64_t select_mask;
+	uint32_t ctr_map;
+};
+
+/**
+ * Add PMU properties in the DT
+ *
+ * Add information about event to selector/counter mappings to the
+ * devicetree.
+ *
+ * @param fdt: device tree blob
+ * @param selects: array of event index to selector value mapping
+ *                 descriptions, ending with empty element
+ * @param counters: array of event indexes to counters mapping
+ *                  descriptions, ending with empty element
+ * @param rcounters: array of raw events to counters mapping
+ *                   descriptions, ending with empty element
+ * @return zero on success and -ve on failure
+ */
+int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
+		const struct sbi_pmu_event_counter_map *counters,
+		const struct sbi_pmu_raw_event_counter_map *rcounters);
+
 /**
  * Add CPU idle states to cpu nodes in the DT
  *
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index e213ded..67e2e2e 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -20,6 +20,101 @@
 #include <sbi_utils/fdt/fdt_pmu.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
+int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
+		const struct sbi_pmu_event_counter_map *counters,
+		const struct sbi_pmu_raw_event_counter_map *rcounters)
+{
+	int i, err, pmu_noff, root_noff;
+	const char *comp;
+	fdt32_t evt_to_mhpmevent[3];
+	fdt32_t evt_to_mhpmcounters[3];
+	fdt32_t raw_evt_to_mhpmcounters[5];
+
+	/* Try to locate pmu node */
+	pmu_noff = fdt_path_offset(fdt, "/pmu");
+
+	if (pmu_noff > 0) {
+		/*
+		 * If compatible string is "riscv,pmu",
+		 * we assume a valid pmu node has been
+		 * provided.
+		 */
+		comp = fdt_getprop(fdt, pmu_noff, "compatible", NULL);
+		if (comp && !strcmp(comp, "riscv,pmu"))
+			return 0;
+		else
+			return -FDT_ERR_BADVALUE;
+	}
+
+	if (pmu_noff < 0 && pmu_noff != -FDT_ERR_NOTFOUND)
+		return pmu_noff;
+
+	/*
+	 * If "riscv,event-to-mhpmevent" is present, "riscv,event-to-mhpmcounters"
+	 * must be provided as well, but not vice versa (OpenSBI will direct mapping
+	 * event_idx as selector value).
+	 */
+	if (selects && !counters) {
+		sbi_printf("%s: ERR: riscv,event-to-mhpmcounters is mandatory if"
+			" riscv,event-to-mhpmevent is present.", __func__);
+		return SBI_EINVAL;
+	}
+
+	/*
+	 * Create pmu node based on given @selects, @counters
+	 * and @rcounters.
+	 */
+	root_noff = fdt_path_offset(fdt, "/");
+	pmu_noff = fdt_add_subnode(fdt, root_noff, "pmu");
+	if  (pmu_noff < 0)
+		return pmu_noff;
+
+	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
+	if (err < 0)
+		return err;
+
+	err = fdt_setprop_string(fdt, pmu_noff, "compatible", "riscv,pmu");
+	if (err)
+		return err;
+
+	/* Add riscv,event-to-mhpmevent */
+	for (i = 0; selects && selects[i].eidx; i++) {
+		evt_to_mhpmevent[0] = cpu_to_fdt32(selects[i].eidx);
+		evt_to_mhpmevent[1] = cpu_to_fdt32(selects[i].select >> 32);
+		evt_to_mhpmevent[2] = cpu_to_fdt32(selects[i].select & ~0UL);
+		err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmevent",
+				evt_to_mhpmevent, 3 * sizeof(fdt32_t));
+		if (err)
+			return err;
+	}
+
+	/* Add riscv,event-to-mhpmcounters */
+	for (i = 0; counters && counters[i].eidx_start; i++) {
+		evt_to_mhpmcounters[0] = cpu_to_fdt32(counters[i].eidx_start);
+		evt_to_mhpmcounters[1] = cpu_to_fdt32(counters[i].eidx_end);
+		evt_to_mhpmcounters[2] = cpu_to_fdt32(counters[i].ctr_map);
+		err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmcounters",
+				evt_to_mhpmcounters, 3 * sizeof(fdt32_t));
+		if (err)
+			return err;
+	}
+
+	/* Add riscv,raw-event-to-mhpmcounters */
+	for (i = 0; rcounters && rcounters[i].select; i++) {
+		raw_evt_to_mhpmcounters[0] = cpu_to_fdt32(rcounters[i].select >> 32);
+		raw_evt_to_mhpmcounters[1] = cpu_to_fdt32(rcounters[i].select & ~0UL);
+		raw_evt_to_mhpmcounters[2] = cpu_to_fdt32(rcounters[i].select_mask >> 32);
+		raw_evt_to_mhpmcounters[3] = cpu_to_fdt32(rcounters[i].select_mask & ~0UL);
+		raw_evt_to_mhpmcounters[4] = cpu_to_fdt32(rcounters[i].ctr_map);
+		err = fdt_appendprop(fdt, pmu_noff, "riscv,raw-event-to-mhpmcounters",
+				raw_evt_to_mhpmcounters, 5 * sizeof(fdt32_t));
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
 {
 	int cpu_node, cpus_node, err, idle_states_node;
diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index bf4b112..bd34d2a 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -19,6 +19,7 @@ struct platform_override {
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
 	u32 (*tlb_num_entries)(const struct fdt_match *match);
+	int (*fdt_add_pmu_mappings)(void *fdt, const struct fdt_match *match);
 	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index cb9270d..a48a8b7 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -265,9 +265,17 @@ static u32 generic_tlb_num_entries(void)
 
 static int generic_pmu_init(void)
 {
+	void *fdt = fdt_get_address();
 	int rc;
 
-	rc = fdt_pmu_setup(fdt_get_address());
+	if (generic_plat && generic_plat->fdt_add_pmu_mappings) {
+		rc = generic_plat->fdt_add_pmu_mappings(fdt,
+							generic_plat_match);
+		if (rc)
+			return rc;
+	}
+
+	rc = fdt_pmu_setup(fdt);
 	if (rc && rc != SBI_ENOENT)
 		return rc;
 
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:10 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:10 +0800
Subject: [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-9-peterlin@andestech.com>

Add a scratch option to control PMU fixup, so the next
stage software can dump the PMU node including event
mapping information for debugging purposes.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 include/sbi/sbi_scratch.h | 2 ++
 lib/utils/fdt/fdt_fixup.c | 6 +++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index e6a33ba..7914dfb 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -151,6 +151,8 @@ enum sbi_scratch_options {
 	SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
 	/** Enable runtime debug prints */
 	SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
+	/** Preserve PMU node properties */
+	SBI_SCRATCH_PRESERVE_PMU_PROP = (1 << 2),
 };
 
 /** Get pointer to sbi_scratch for current HART */
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index 67e2e2e..b0c885f 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -482,6 +482,8 @@ int fdt_reserved_memory_fixup(void *fdt)
 
 void fdt_fixups(void *fdt)
 {
+	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
 	fdt_aplic_fixup(fdt);
 
 	fdt_imsic_fixup(fdt);
@@ -489,5 +491,7 @@ void fdt_fixups(void *fdt)
 	fdt_plic_fixup(fdt);
 
 	fdt_reserved_memory_fixup(fdt);
-	fdt_pmu_fixup(fdt);
+
+	if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_PROP))
+		fdt_pmu_fixup(fdt);
 }
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:11 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:11 +0800
Subject: [PATCH v2 09/11] platform: andes: Factor out is_andes() helper
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-10-peterlin@andestech.com>

We will need is_andes(45) in the following patch,
so factor out the code that parses marchid to make
it reusable for checking any Andes CPU variants.

Also improves the comment in ae350_hart_start().

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 platform/generic/andes/ae350.c           | 16 +++++++---------
 platform/generic/include/andes/andes45.h |  6 ++++++
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index c3f280d..80cd294 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -24,16 +24,14 @@ static struct smu_data smu = { 0 };
 extern void __ae350_enable_coherency_warmboot(void);
 extern void __ae350_disable_coherency(void);
 
-static __always_inline bool is_andes25(void)
-{
-	ulong marchid = csr_read(CSR_MARCHID);
-	return !!(EXTRACT_FIELD(marchid, CSR_MARCHID_MICROID) == 0xa25);
-}
-
 static int ae350_hart_start(u32 hartid, ulong saddr)
 {
-	/* Don't send wakeup command at boot-time */
-	if (!sbi_init_count(hartid) || (is_andes25() && hartid == 0))
+	/*
+	 * Don't send wakeup command
+	 * 1) at boot-time
+	 * 2) the target hart is non-sleepable 25-series hart0
+	 */
+	if (!sbi_init_count(hartid) || (is_andes(25) && hartid == 0))
 		return sbi_ipi_raw_send(sbi_hartid_to_hartindex(hartid));
 
 	/* Write wakeup command to the sleep hart */
@@ -52,7 +50,7 @@ static int ae350_hart_stop(void)
 	 * L2-cache, instead of turning it off, it should fall
 	 * through and jump to warmboot_addr.
 	 */
-	if (is_andes25() && hartid == 0)
+	if (is_andes(25) && hartid == 0)
 		return SBI_ENOTSUPP;
 
 	if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index ce31617..01f63d4 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -43,6 +43,12 @@
 
 #ifndef __ASSEMBLER__
 
+#define is_andes(series)				\
+({							\
+	char value = csr_read(CSR_MARCHID) & 0xff;	\
+	(series) == (value >> 4) * 10 + (value & 0x0f);	\
+})
+
 #define has_andes_pmu()					\
 ({							\
 	(((csr_read(CSR_MMSC_CFG) &			\
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:12 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:12 +0800
Subject: [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-11-peterlin@andestech.com>

Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
node properties that will later be populated with mapping tables.

Currently we only support 45-series event mappings.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Changes v1 -> v2:
  - New patch
---
 include/sbi/sbi_ecall_interface.h          |   5 +
 platform/generic/Kconfig                   |   2 +
 platform/generic/andes/Kconfig             |   7 +
 platform/generic/andes/ae350.c             |   2 +
 platform/generic/andes/andes_hpm.c         | 381 +++++++++++++++++++++
 platform/generic/andes/objects.mk          |   1 +
 platform/generic/include/andes/andes_hpm.h |  83 +++++
 platform/generic/renesas/rzfive/rzfive.c   |   2 +
 8 files changed, 483 insertions(+)
 create mode 100644 platform/generic/andes/andes_hpm.c
 create mode 100644 platform/generic/include/andes/andes_hpm.h

diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index 1fe469e..89187e7 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
 	SBI_PMU_HW_CACHE_RESULT_MAX,
 };
 
+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
+	(SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
+	SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
+	SBI_PMU_HW_CACHE_RESULT_##res)
+
 /**
  * Special "firmware" events provided by the OpenSBI, even if the hardware
  * does not support performance events. These events are encoded as a raw
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index d6dafef..fbcd870 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
 config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
 	select SYS_ATCSMU
+	select ANDES_HPM
 	select ANDES_PMU
 	default n
 
@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
 	bool "Renesas RZ/Five support"
 	select ANDES45_PMA
 	select ANDES_SBI
+	select ANDES_HPM
 	select ANDES_PMU
 	default n
 
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index 555e4fe..8af2704 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -8,6 +8,13 @@ config ANDES_SBI
 	bool "Andes SBI support"
 	default n
 
+config ANDES_HPM
+	bool "Andes HPM support"
+	default n
+	help
+	  This provides Andes platform override for creating
+	  event to counter mappings in pmu node.
+
 config ANDES_PMU
 	bool "Andes custom PMU extension support"
 	default n
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 80cd294..28c187e 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -19,6 +19,7 @@
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_init.h>
 #include <andes/andes45.h>
+#include <andes/andes_hpm.h>
 
 static struct smu_data smu = { 0 };
 extern void __ae350_enable_coherency_warmboot(void);
@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
 const struct platform_override andes_ae350 = {
 	.match_table = andes_ae350_match,
 	.final_init  = ae350_final_init,
+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
 	.extensions_init = ae350_extensions_init,
 };
diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
new file mode 100644
index 0000000..f9e6d2e
--- /dev/null
+++ b/platform/generic/andes/andes_hpm.c
@@ -0,0 +1,381 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#include <andes/andes45.h>
+#include <andes/andes_hpm.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
+	/* Hardware general events (Type #0) */
+	{
+		/* perf: cycles (eidx: 0x1) */
+		.eidx = SBI_PMU_HW_CPU_CYCLES,
+		.select = ANDES_CYCLES
+	},
+	{
+		/* perf: instructions (eidx: 0x2) */
+		.eidx = SBI_PMU_HW_INSTRUCTIONS,
+		.select = ANDES_INSTRET
+	},
+	{
+		/* perf: cache-references (eidx: 0x3) */
+		.eidx = SBI_PMU_HW_CACHE_REFERENCES,
+		.select = ANDES_DCACHE_ACCESS
+	},
+	{
+		/* perf: cache-misses (eidx: 0x4) */
+		.eidx = SBI_PMU_HW_CACHE_MISSES,
+		.select = ANDES_DCACHE_MISS
+	},
+	{
+		/* perf: branches (eidx: 0x5) */
+		.eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
+		.select = ANDES_CONDITION_BR,
+	},
+	{
+		/* perf: branch-misses (eidx: 0x6) */
+		.eidx = SBI_PMU_HW_BRANCH_MISSES,
+		.select = ANDES_MISPREDICT_CONDITION_BR,
+	},
+	/* Hardware cache events (Type #1) */
+	{
+		/* perf: L1-dcache-loads (eidx: 0x10000) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+		.select = ANDES_DCACHE_LOAD_ACCESS
+	},
+	{
+		/* perf: L1-dcache-loads-misses (eidx: 0x10001) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
+		.select = ANDES_DCACHE_LOAD_MISS
+	},
+	{
+		/* perf: L1-dcache-stores (eidx: 0x10002) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
+		.select = ANDES_DCACHE_STORE_ACCESS
+	},
+	{
+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+		.select = ANDES_DCACHE_STORE_MISS
+	},
+	{
+		/* perf: L1-icache-load (eidx: 0x10008) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+		.select = ANDES_ICACHE_ACCESS
+	},
+	{
+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+		.select = ANDES_ICACHE_MISS
+	},
+	{ /* sentinel */ }
+};
+
+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
+	{
+		/* perf: cycles (eidx: 0x1) */
+		.eidx_start = SBI_PMU_HW_CPU_CYCLES,
+		/* perf: branch-misses (eidx: 0x6) */
+		.eidx_end = SBI_PMU_HW_BRANCH_MISSES,
+		.ctr_map = ANDES_MHPM_MAP,
+	},
+	{
+		/* perf: L1-dcache-loads (eidx: 0x10000) */
+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+		.ctr_map = ANDES_MHPM_MAP,
+	},
+	{
+		/* perf: L1-icache-load (eidx: 0x10008) */
+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+		.ctr_map = ANDES_MHPM_MAP,
+	},
+	{ /* sentinel */ }
+};
+
+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
+	{
+		.select = ANDES_CYCLES,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INSTRET,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_LOAD_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_STORE_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_ATOMIC_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_SYS_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_COMPUTE_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CONDITION_BR,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_TAKEN_CONDITION_BR,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_JAL_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_JALR_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_RET_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CONTROL_TRANS_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_EX9_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_MUL_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_DIV_REMAINDER_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_LOAD_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_STORE_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_ADD_SUB_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_MUL_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_FUSED_MULADD_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_OTHER_FLOAT_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_INT_MUL_AND_SUB_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_RETIRED_OP,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_ILM_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DLM_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_ICACHE_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_ICACHE_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_LOAD_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_LOAD_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_STORE_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_STORE_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_DCACHE_WB,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CYCLE_WAIT_ICACHE_FILL,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CYCLE_WAIT_DCACHE_FILL,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_UNCACHED_IFETCH_FROM_BUS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_UNCACHED_LOAD_FROM_BUS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MAIN_ITLB_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MAIN_ITLB_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MAIN_DTLB_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MAIN_DTLB_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_CYCLE_WAIT_ITLB_FILL,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_HW_PREFETCH_BUS_ACCESS,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MISPREDICT_CONDITION_BR,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{
+		.select = ANDES_MISPREDICT_TARGET_RET_INST,
+		.select_mask = ANDES_RAW_EVENT_MASK,
+		.ctr_map = ANDES_MHPM_MAP
+	},
+	{ /* sentinel */ }
+};
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
+{
+	/*
+	 * At the moment, simply create mapping for any 45-series core
+	 * based on marchid, we may check and differentiate the mapping
+	 * by mimpid.
+	 */
+	if (is_andes(45))
+		return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
+					    andes45_hw_evt_counters,
+					    andes45_raw_evt_counters);
+
+	return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index 6a8c66c..57caaf6 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
 platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
 platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
 platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
new file mode 100644
index 0000000..0f301db
--- /dev/null
+++ b/platform/generic/include/andes/andes_hpm.h
@@ -0,0 +1,83 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _ANDES_HPM_H_
+#define _ANDES_HPM_H_
+
+#include <sbi_utils/fdt/fdt_helper.h>
+
+#define ANDES_MHPM_MAP		0x78
+#define ANDES_RAW_EVENT_MASK	~0ULL
+
+/* Event code for instruction commit events */
+#define ANDES_CYCLES				0x10
+#define ANDES_INSTRET				0x20
+#define ANDES_INT_LOAD_INST			0x30
+#define ANDES_INT_STORE_INST			0x40
+#define ANDES_ATOMIC_INST			0x50
+#define ANDES_SYS_INST				0x60
+#define ANDES_INT_COMPUTE_INST			0x70
+#define ANDES_CONDITION_BR			0x80
+#define ANDES_TAKEN_CONDITION_BR		0x90
+#define ANDES_JAL_INST				0xA0
+#define ANDES_JALR_INST				0xB0
+#define ANDES_RET_INST				0xC0
+#define ANDES_CONTROL_TRANS_INST		0xD0
+#define ANDES_EX9_INST				0xE0
+#define ANDES_INT_MUL_INST			0xF0
+#define ANDES_INT_DIV_REMAINDER_INST		0x100
+#define ANDES_FLOAT_LOAD_INST			0x110
+#define ANDES_FLOAT_STORE_INST			0x120
+#define ANDES_FLOAT_ADD_SUB_INST		0x130
+#define ANDES_FLOAT_MUL_INST			0x140
+#define ANDES_FLOAT_FUSED_MULADD_INST		0x150
+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST	0x160
+#define ANDES_OTHER_FLOAT_INST			0x170
+#define ANDES_INT_MUL_AND_SUB_INST		0x180
+#define ANDES_RETIRED_OP			0x190
+
+/* Event code for memory system events */
+#define ANDES_ILM_ACCESS			0x01
+#define ANDES_DLM_ACCESS			0x11
+#define ANDES_ICACHE_ACCESS			0x21
+#define ANDES_ICACHE_MISS			0x31
+#define ANDES_DCACHE_ACCESS			0x41
+#define ANDES_DCACHE_MISS			0x51
+#define ANDES_DCACHE_LOAD_ACCESS		0x61
+#define ANDES_DCACHE_LOAD_MISS			0x71
+#define ANDES_DCACHE_STORE_ACCESS		0x81
+#define ANDES_DCACHE_STORE_MISS			0x91
+#define ANDES_DCACHE_WB				0xA1
+#define ANDES_CYCLE_WAIT_ICACHE_FILL		0xB1
+#define ANDES_CYCLE_WAIT_DCACHE_FILL		0xC1
+#define ANDES_UNCACHED_IFETCH_FROM_BUS		0xD1
+#define ANDES_UNCACHED_LOAD_FROM_BUS		0xE1
+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH	0xF1
+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD		0x101
+#define ANDES_MAIN_ITLB_ACCESS			0x111
+#define ANDES_MAIN_ITLB_MISS			0x121
+#define ANDES_MAIN_DTLB_ACCESS			0x131
+#define ANDES_MAIN_DTLB_MISS			0x141
+#define ANDES_CYCLE_WAIT_ITLB_FILL		0x151
+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS	0x161
+#define ANDES_HW_PREFETCH_BUS_ACCESS		0x171
+
+/* Event code for microarchitecture events */
+#define ANDES_MISPREDICT_CONDITION_BR		0x02
+#define ANDES_MISPREDICT_TAKE_CONDITION_BR	0x12
+#define ANDES_MISPREDICT_TARGET_RET_INST	0x22
+
+#ifdef CONFIG_ANDES_HPM
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
+
+#else
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
+
+#endif /* CONFIG_ANDES_HPM */
+
+#endif /* _ANDES_HPM_H_ */
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index 2f772c8..fafbff0 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,6 +5,7 @@
  */
 
 #include <andes/andes45_pma.h>
+#include <andes/andes_hpm.h>
 #include <andes/andes_pmu.h>
 #include <andes/andes_sbi.h>
 #include <platform_override.h>
@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
 	.match_table = renesas_rzfive_match,
 	.early_init = renesas_rzfive_early_init,
 	.final_init = renesas_rzfive_final_init,
+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
 	.vendor_ext_provider = andes_sbi_vendor_ext_provider,
 	.extensions_init = renesas_rzfive_extensions_init,
 };
-- 
2.34.1



From peterlin at andestech.com  Thu Oct 19 04:37:13 2023
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 19 Oct 2023 19:37:13 +0800
Subject: [PATCH v2 11/11] docs: pmu: Add Andes PMU node example
In-Reply-To: <20231019113713.3508153-1-peterlin@andestech.com>
References: <20231019113713.3508153-1-peterlin@andestech.com>
Message-ID: <20231019113713.3508153-12-peterlin@andestech.com>

Add PMU node example for event index to counter index mapping
and selector value translation of Andes' CPUs.

Currently, there are 4 HPM counters that can be used to monitor
all of the events for each hart.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Locus Wei-Han Chen <locus84 at andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
Changes v1 -> v2:
  - sync up with datasheet
---
 docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 8cfa08c..9b48f1e 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -125,3 +125,85 @@ pmu {
 					  <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
 };
 ```
+
+### Example 3
+
+```
+/*
+ * For Andes 45-series platforms. The encodings can be found in the
+ * "Machine Performance Monitoring Event Selector" section
+ * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ */
+pmu {
+	compatible 			= "riscv,pmu";
+	riscv,event-to-mhpmevent =
+					 <0x1 0x0000 0x10>, /* CPU_CYCLES          -> Cycle count */
+					 <0x2 0x0000 0x20>, /* INSTRUCTIONS        -> Retired instruction count */
+					 <0x3 0x0000 0x41>, /* CACHE_REFERENCES    -> D-Cache access */
+					 <0x4 0x0000 0x51>, /* CACHE_MISSES        -> D-Cache miss */
+					 <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
+					 <0x6 0x0000 0x02>, /* BRANCH_MISSES       -> Misprediction of conditional branches */
+					 <0x10000 0x0000 0x61>,  /* L1D_READ_ACCESS  -> D-Cache load access */
+					 <0x10001 0x0000 0x71>,  /* L1D_READ_MISS    -> D-Cache load miss */
+					 <0x10002 0x0000 0x81>,  /* L1D_WRITE_ACCESS -> D-Cache store access */
+					 <0x10003 0x0000 0x91>,  /* L1D_WRITE_MISS   -> D-Cache store miss */
+					 <0x10008 0x0000 0x21>,  /* L1I_READ_ACCESS  -> I-Cache access */
+					 <0x10009 0x0000 0x31>;  /* L1I_READ_MISS    -> I-Cache miss */
+	riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
+							<0x10000 0x10003 0x78>,
+							<0x10008 0x10009 0x78>;
+	riscv,raw-event-to-mhpmcounters =
+						<0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
+						<0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
+						<0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
+						<0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
+						<0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
+						<0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
+						<0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
+						<0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
+						<0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
+						<0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
+						<0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
+						<0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
+						<0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
+						<0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
+						<0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
+						<0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
+						<0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
+						<0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
+						<0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
+						<0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
+						<0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
+						<0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
+						<0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
+						<0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
+						<0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
+						<0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
+						<0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
+						<0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
+						<0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
+						<0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
+						<0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
+						<0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
+						<0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
+						<0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
+						<0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
+						<0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
+						<0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
+						<0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
+						<0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
+						<0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
+						<0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
+						<0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
+						<0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
+						<0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
+						<0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
+						<0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
+						<0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
+						<0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
+						<0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
+						<0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
+						<0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
+						<0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
+};
+```
-- 
2.34.1



From anup at brainfault.org  Thu Oct 19 04:51:13 2023
From: anup at brainfault.org (Anup Patel)
Date: Thu, 19 Oct 2023 17:21:13 +0530
Subject: [PATCH] include: sbi: Change spec version to 2.0
In-Reply-To: <20231010102125.603343-1-apatel@ventanamicro.com>
References: <20231010102125.603343-1-apatel@ventanamicro.com>
Message-ID: <CAAhSdy2urwZ1srodcXSYCNP7JcAgw+dCeXfSMEEAHCYBKmi5AQ@mail.gmail.com>

On Tue, Oct 10, 2023 at 3:51?PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> Now that SBI v2.0 specification is frozen, we change spec verion
> implemented by OpenSBI to v2.0.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/sbi_ecall.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_ecall.h b/include/sbi/sbi_ecall.h
> index 90f33ba..027213c 100644
> --- a/include/sbi/sbi_ecall.h
> +++ b/include/sbi/sbi_ecall.h
> @@ -13,7 +13,7 @@
>  #include <sbi/sbi_types.h>
>  #include <sbi/sbi_list.h>
>
> -#define SBI_ECALL_VERSION_MAJOR                1
> +#define SBI_ECALL_VERSION_MAJOR                2
>  #define SBI_ECALL_VERSION_MINOR                0
>  #define SBI_OPENSBI_IMPID              1
>
> --
> 2.34.1
>


From guoren at kernel.org  Thu Oct 19 16:33:23 2023
From: guoren at kernel.org (Guo Ren)
Date: Fri, 20 Oct 2023 07:33:23 +0800
Subject: [PATCH] fw_base.S: Fix boot hart status synchronization
In-Reply-To: <20231019092734.2554798-1-guoren@kernel.org>
References: <20231019092734.2554798-1-guoren@kernel.org>
Message-ID: <CAJF2gTSM5+j-iUd8-ucdZLi5YW8zcZCf4BdM2L94NkYcuZ5=qg@mail.gmail.com>

F.Y.I Drew

This patch is also needed for "zsb -> opensbi -> linux"


On Thu, Oct 19, 2023 at 5:27?PM <guoren at kernel.org> wrote:
>
> From: Guo Ren <guoren at linux.alibaba.com>
>
> It's wrong to put the fence after setting the boot status flag because
> all relocation operations must be finished before setting the status
> flag. So, this fence must be put before the setting status flag, and
> there is no use in putting a fence between _start_warm and setting
> status flag.
>
> Also, nop can't delay other harts too much, so use div instead, just
> like Linux cpu_relax. Current opensbi force enables ?M? Standard
> Extension, and mul instructions have been used in the fw_base.S.
>
> After the above two fixes, the boot hart index param of the
> fw_dynamic_info could be guaranteed properly for all platforms.
>
> Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren at kernel.org>
> ---
>  firmware/fw_base.S | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index 42b03fe890f0..f7763f4d9e56 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -399,8 +399,8 @@ _fdt_reloc_done:
>         /* mark boot hart done */
>         li      t0, BOOT_STATUS_BOOT_HART_DONE
>         lla     t1, _boot_status
> -       REG_S   t0, 0(t1)
>         fence   rw, rw
> +       REG_S   t0, 0(t1)
>         j       _start_warm
>
>         /* waiting for boot hart to be done (_boot_status == 2) */
> @@ -409,9 +409,9 @@ _wait_for_boot_hart:
>         lla     t1, _boot_status
>         REG_L   t1, 0(t1)
>         /* Reduce the bus traffic so that boot hart may proceed faster */
> -       nop
> -       nop
> -       nop
> +       div     t2, t2, zero
> +       div     t2, t2, zero
> +       div     t2, t2, zero
>         bne     t0, t1, _wait_for_boot_hart
>
>  _start_warm:
> --
> 2.36.1
>


--
Best Regards
 Guo Ren


From inochiama at outlook.com  Thu Oct 19 16:57:18 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Fri, 20 Oct 2023 07:57:18 +0800
Subject: [PATCH v4] platform: generic: Add Sophgo sg2042 platform support
Message-ID: <IA1PR20MB4953FC1436930F92BA765847BBD4A@IA1PR20MB4953.namprd20.prod.outlook.com>

Add Sophgo sg2042 soc support

Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
Reviewed-by: Guo Ren <guoren at kernel.org>
---
This patch depends these patchs:
1. platform: generic: add T-HEAD th1520 soc support
2. lib: sbi: Add sub-regions check for sanitizing domain
3. lib: utils: Add T-HEAD C900 ACLINT
4. platform: generic: thead: improve tlb flush errata

Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005676.html
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005705.html
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005736.html
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005712.html
Link: https://lore.kernel.org/linux-riscv/cover.1696433229.git.unicorn_wang at outlook.com/

Changed from v3:
1. remove unused variable to avoid compile failed

Changed from v2:
1. replace hart count with number 16 when calculating the timer area.
   The sg2042 have a fixed number of timer, see the kernel dt in the link.
2. fix typo
3. move the c900 aclint patch out of this series.
4. move the tlb size change patch out of this series.

Changed from v1:
1. make number of entries in tlb fifo auto deteted.

---
 platform/generic/Kconfig           |  6 +++
 platform/generic/configs/defconfig |  1 +
 platform/generic/sophgo/objects.mk |  9 +++++
 platform/generic/sophgo/sg2042.c   | 62 ++++++++++++++++++++++++++++++
 4 files changed, 78 insertions(+)
 create mode 100644 platform/generic/sophgo/objects.mk
 create mode 100644 platform/generic/sophgo/sg2042.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index f9e7ed2..a902cf3 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -49,6 +49,12 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n

+config PLATFORM_SOPHGO_SG2042
+	bool "Sophgo sg2042 support"
+	select THEAD_C9XX_ERRATA
+	select THEAD_C9XX_PMU
+	default n
+
 config PLATFORM_STARFIVE_JH7110
 	bool "StarFive JH7110 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c432bc2..e1b76c8 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_SOPHGO_SG2042=y
 CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_PLATFORM_THEAD=y
 CONFIG_FDT_GPIO=y
diff --git a/platform/generic/sophgo/objects.mk b/platform/generic/sophgo/objects.mk
new file mode 100644
index 0000000..3d2908a
--- /dev/null
+++ b/platform/generic/sophgo/objects.mk
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2023 Inochi Amaoto <inochiama at outlook.com>
+# Copyright (C) 2023 Alibaba Group Holding Limited.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo_sg2042
+platform-objs-$(CONFIG_PLATFORM_SOPHGO_SG2042) += sophgo/sg2042.o
diff --git a/platform/generic/sophgo/sg2042.c b/platform/generic/sophgo/sg2042.c
new file mode 100644
index 0000000..9c6acdb
--- /dev/null
+++ b/platform/generic/sophgo/sg2042.c
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Authors:
+ *   Inochi Amaoto <inochiama at outlook.com>
+ *
+ */
+
+#include <platform_override.h>
+#include <thead/c9xx_errata.h>
+#include <thead/c9xx_pmu.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/timer/aclint_mtimer.h>
+
+#define SOPHGO_SG2042_TIMER_BASE	0x70ac000000UL
+#define SOPHGO_SG2042_TIMER_SIZE	0x10000UL
+#define SOPHGO_SG2042_TIMER_NUM		16
+
+static int sophgo_sg2042_early_init(bool cold_boot,
+				    const struct fdt_match *match)
+{
+	thead_register_tlb_flush_trap_handler();
+
+	/*
+	 * Sophgo sg2042 soc use separate 16 timers while initiating,
+	 * merge them as a single domain to avoid wasting.
+	 */
+	if (cold_boot)
+		return sbi_domain_root_add_memrange(SOPHGO_SG2042_TIMER_BASE,
+						SOPHGO_SG2042_TIMER_SIZE *
+						SOPHGO_SG2042_TIMER_NUM,
+						MTIMER_REGION_ALIGN,
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
+
+
+	return 0;
+}
+
+static int sophgo_sg2042_extensions_init(const struct fdt_match *match,
+					 struct sbi_hart_features *hfeatures)
+{
+	thead_c9xx_register_pmu_device();
+	return 0;
+}
+
+static const struct fdt_match sophgo_sg2042_match[] = {
+	{ .compatible = "sophgo,sg2042" },
+	{ },
+};
+
+const struct platform_override sophgo_sg2042 = {
+	.match_table		= sophgo_sg2042_match,
+	.early_init		= sophgo_sg2042_early_init,
+	.extensions_init	= sophgo_sg2042_extensions_init,
+};
--
2.42.0



From inochiama at outlook.com  Sat Oct 21 05:25:30 2023
From: inochiama at outlook.com (Inochi Amaoto)
Date: Sat, 21 Oct 2023 20:25:30 +0800
Subject: [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
In-Reply-To: <20231019113713.3508153-8-peterlin@andestech.com>
References: <20231019113713.3508153-8-peterlin@andestech.com>
Message-ID: <IA1PR20MB4953B09D78D523D9E15B7D9CBBDAA@IA1PR20MB4953.namprd20.prod.outlook.com>

>Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
>node properties that will later be populated with mapping tables.
>
>Currently we only support 45-series event mappings.
>
>Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
>---
>Changes v1 -> v2:
>  - New patch
>---
> include/sbi/sbi_ecall_interface.h          |   5 +
> platform/generic/Kconfig                   |   2 +
> platform/generic/andes/Kconfig             |   7 +
> platform/generic/andes/ae350.c             |   2 +
> platform/generic/andes/andes_hpm.c         | 381 +++++++++++++++++++++
> platform/generic/andes/objects.mk          |   1 +
> platform/generic/include/andes/andes_hpm.h |  83 +++++
> platform/generic/renesas/rzfive/rzfive.c   |   2 +
> 8 files changed, 483 insertions(+)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
>
>diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
>index 1fe469e..89187e7 100644
>--- a/include/sbi/sbi_ecall_interface.h
>+++ b/include/sbi/sbi_ecall_interface.h
>@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> 	SBI_PMU_HW_CACHE_RESULT_MAX,
> };
>
>+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
>+	(SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
>+	SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
>+	SBI_PMU_HW_CACHE_RESULT_##res)
>+
> /**
>  * Special "firmware" events provided by the OpenSBI, even if the hardware
>  * does not support performance events. These events are encoded as a raw
>diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
>index d6dafef..fbcd870 100644
>--- a/platform/generic/Kconfig
>+++ b/platform/generic/Kconfig
>@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> 	bool "Andes AE350 support"
> 	select SYS_ATCSMU
>+	select ANDES_HPM
> 	select ANDES_PMU
> 	default n
>
>@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> 	bool "Renesas RZ/Five support"
> 	select ANDES45_PMA
> 	select ANDES_SBI
>+	select ANDES_HPM
> 	select ANDES_PMU
> 	default n
>
>diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
>index 555e4fe..8af2704 100644
>--- a/platform/generic/andes/Kconfig
>+++ b/platform/generic/andes/Kconfig
>@@ -8,6 +8,13 @@ config ANDES_SBI
> 	bool "Andes SBI support"
> 	default n
>
>+config ANDES_HPM
>+	bool "Andes HPM support"
>+	default n
>+	help
>+	  This provides Andes platform override for creating
>+	  event to counter mappings in pmu node.
>+
> config ANDES_PMU
> 	bool "Andes custom PMU extension support"
> 	default n
>diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
>index 80cd294..28c187e 100644
>--- a/platform/generic/andes/ae350.c
>+++ b/platform/generic/andes/ae350.c
>@@ -19,6 +19,7 @@
> #include <sbi/sbi_ipi.h>
> #include <sbi/sbi_init.h>
> #include <andes/andes45.h>
>+#include <andes/andes_hpm.h>
>
> static struct smu_data smu = { 0 };
> extern void __ae350_enable_coherency_warmboot(void);
>@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> 	.match_table = andes_ae350_match,
> 	.final_init  = ae350_final_init,
>+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> 	.extensions_init = ae350_extensions_init,
> };
>diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
>new file mode 100644
>index 0000000..f9e6d2e
>--- /dev/null
>+++ b/platform/generic/andes/andes_hpm.c
>@@ -0,0 +1,381 @@
>+/*
>+ * SPDX-License-Identifier: BSD-2-Clause
>+ *
>+ * Copyright (c) 2023 Andes Technology Corporation
>+ */
>+
>+#include <andes/andes45.h>
>+#include <andes/andes_hpm.h>
>+#include <sbi/riscv_asm.h>
>+#include <sbi/sbi_ecall_interface.h>
>+#include <sbi_utils/fdt/fdt_fixup.h>
>+
>+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
>+	/* Hardware general events (Type #0) */
>+	{
>+		/* perf: cycles (eidx: 0x1) */
>+		.eidx = SBI_PMU_HW_CPU_CYCLES,
>+		.select = ANDES_CYCLES
>+	},
>+	{
>+		/* perf: instructions (eidx: 0x2) */
>+		.eidx = SBI_PMU_HW_INSTRUCTIONS,
>+		.select = ANDES_INSTRET
>+	},
>+	{
>+		/* perf: cache-references (eidx: 0x3) */
>+		.eidx = SBI_PMU_HW_CACHE_REFERENCES,
>+		.select = ANDES_DCACHE_ACCESS
>+	},
>+	{
>+		/* perf: cache-misses (eidx: 0x4) */
>+		.eidx = SBI_PMU_HW_CACHE_MISSES,
>+		.select = ANDES_DCACHE_MISS
>+	},
>+	{
>+		/* perf: branches (eidx: 0x5) */
>+		.eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
>+		.select = ANDES_CONDITION_BR,
>+	},
>+	{
>+		/* perf: branch-misses (eidx: 0x6) */
>+		.eidx = SBI_PMU_HW_BRANCH_MISSES,
>+		.select = ANDES_MISPREDICT_CONDITION_BR,
>+	},
>+	/* Hardware cache events (Type #1) */
>+	{
>+		/* perf: L1-dcache-loads (eidx: 0x10000) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
>+		.select = ANDES_DCACHE_LOAD_ACCESS
>+	},
>+	{
>+		/* perf: L1-dcache-loads-misses (eidx: 0x10001) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
>+		.select = ANDES_DCACHE_LOAD_MISS
>+	},
>+	{
>+		/* perf: L1-dcache-stores (eidx: 0x10002) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
>+		.select = ANDES_DCACHE_STORE_ACCESS
>+	},
>+	{
>+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
>+		.select = ANDES_DCACHE_STORE_MISS
>+	},
>+	{
>+		/* perf: L1-icache-load (eidx: 0x10008) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
>+		.select = ANDES_ICACHE_ACCESS
>+	},
>+	{
>+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
>+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
>+		.select = ANDES_ICACHE_MISS
>+	},
>+	{ /* sentinel */ }
>+};
>+
>+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
>+	{
>+		/* perf: cycles (eidx: 0x1) */
>+		.eidx_start = SBI_PMU_HW_CPU_CYCLES,
>+		/* perf: branch-misses (eidx: 0x6) */
>+		.eidx_end = SBI_PMU_HW_BRANCH_MISSES,
>+		.ctr_map = ANDES_MHPM_MAP,
>+	},
>+	{
>+		/* perf: L1-dcache-loads (eidx: 0x10000) */
>+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
>+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
>+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
>+		.ctr_map = ANDES_MHPM_MAP,
>+	},
>+	{
>+		/* perf: L1-icache-load (eidx: 0x10008) */
>+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
>+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
>+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
>+		.ctr_map = ANDES_MHPM_MAP,
>+	},
>+	{ /* sentinel */ }
>+};
>+
>+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
>+	{
>+		.select = ANDES_CYCLES,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INSTRET,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_LOAD_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_STORE_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_ATOMIC_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_SYS_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_COMPUTE_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CONDITION_BR,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_TAKEN_CONDITION_BR,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_JAL_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_JALR_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_RET_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CONTROL_TRANS_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_EX9_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_MUL_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_DIV_REMAINDER_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_LOAD_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_STORE_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_ADD_SUB_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_MUL_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_FUSED_MULADD_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_OTHER_FLOAT_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_INT_MUL_AND_SUB_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_RETIRED_OP,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_ILM_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DLM_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_ICACHE_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_ICACHE_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_LOAD_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_LOAD_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_STORE_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_STORE_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_DCACHE_WB,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CYCLE_WAIT_ICACHE_FILL,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CYCLE_WAIT_DCACHE_FILL,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_UNCACHED_IFETCH_FROM_BUS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_UNCACHED_LOAD_FROM_BUS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MAIN_ITLB_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MAIN_ITLB_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MAIN_DTLB_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MAIN_DTLB_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_CYCLE_WAIT_ITLB_FILL,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_HW_PREFETCH_BUS_ACCESS,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MISPREDICT_CONDITION_BR,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{
>+		.select = ANDES_MISPREDICT_TARGET_RET_INST,
>+		.select_mask = ANDES_RAW_EVENT_MASK,
>+		.ctr_map = ANDES_MHPM_MAP
>+	},
>+	{ /* sentinel */ }
>+};

Why not use DT? I just see everything is fixed.

Adding fdt_add_pmu_mappings is not a good idea. Opensbi can use its own
DT by setting FW_FDT_PATH, so you do not need to add this mapping table.

>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
>+{
>+	/*
>+	 * At the moment, simply create mapping for any 45-series core
>+	 * based on marchid, we may check and differentiate the mapping
>+	 * by mimpid.
>+	 */
>+	if (is_andes(45))
>+		return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
>+					    andes45_hw_evt_counters,
>+					    andes45_raw_evt_counters);
>+
>+	return 0;
>+}
>diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
>index 6a8c66c..57caaf6 100644
>--- a/platform/generic/andes/objects.mk
>+++ b/platform/generic/andes/objects.mk
>@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
>+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
>diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
>new file mode 100644
>index 0000000..0f301db
>--- /dev/null
>+++ b/platform/generic/include/andes/andes_hpm.h
>@@ -0,0 +1,83 @@
>+/*
>+ * SPDX-License-Identifier: BSD-2-Clause
>+ *
>+ * Copyright (c) 2023 Andes Technology Corporation
>+ */
>+
>+#ifndef _ANDES_HPM_H_
>+#define _ANDES_HPM_H_
>+
>+#include <sbi_utils/fdt/fdt_helper.h>
>+
>+#define ANDES_MHPM_MAP		0x78
>+#define ANDES_RAW_EVENT_MASK	~0ULL
>+
>+/* Event code for instruction commit events */
>+#define ANDES_CYCLES				0x10
>+#define ANDES_INSTRET				0x20
>+#define ANDES_INT_LOAD_INST			0x30
>+#define ANDES_INT_STORE_INST			0x40
>+#define ANDES_ATOMIC_INST			0x50
>+#define ANDES_SYS_INST				0x60
>+#define ANDES_INT_COMPUTE_INST			0x70
>+#define ANDES_CONDITION_BR			0x80
>+#define ANDES_TAKEN_CONDITION_BR		0x90
>+#define ANDES_JAL_INST				0xA0
>+#define ANDES_JALR_INST				0xB0
>+#define ANDES_RET_INST				0xC0
>+#define ANDES_CONTROL_TRANS_INST		0xD0
>+#define ANDES_EX9_INST				0xE0
>+#define ANDES_INT_MUL_INST			0xF0
>+#define ANDES_INT_DIV_REMAINDER_INST		0x100
>+#define ANDES_FLOAT_LOAD_INST			0x110
>+#define ANDES_FLOAT_STORE_INST			0x120
>+#define ANDES_FLOAT_ADD_SUB_INST		0x130
>+#define ANDES_FLOAT_MUL_INST			0x140
>+#define ANDES_FLOAT_FUSED_MULADD_INST		0x150
>+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST	0x160
>+#define ANDES_OTHER_FLOAT_INST			0x170
>+#define ANDES_INT_MUL_AND_SUB_INST		0x180
>+#define ANDES_RETIRED_OP			0x190
>+
>+/* Event code for memory system events */
>+#define ANDES_ILM_ACCESS			0x01
>+#define ANDES_DLM_ACCESS			0x11
>+#define ANDES_ICACHE_ACCESS			0x21
>+#define ANDES_ICACHE_MISS			0x31
>+#define ANDES_DCACHE_ACCESS			0x41
>+#define ANDES_DCACHE_MISS			0x51
>+#define ANDES_DCACHE_LOAD_ACCESS		0x61
>+#define ANDES_DCACHE_LOAD_MISS			0x71
>+#define ANDES_DCACHE_STORE_ACCESS		0x81
>+#define ANDES_DCACHE_STORE_MISS			0x91
>+#define ANDES_DCACHE_WB				0xA1
>+#define ANDES_CYCLE_WAIT_ICACHE_FILL		0xB1
>+#define ANDES_CYCLE_WAIT_DCACHE_FILL		0xC1
>+#define ANDES_UNCACHED_IFETCH_FROM_BUS		0xD1
>+#define ANDES_UNCACHED_LOAD_FROM_BUS		0xE1
>+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH	0xF1
>+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD		0x101
>+#define ANDES_MAIN_ITLB_ACCESS			0x111
>+#define ANDES_MAIN_ITLB_MISS			0x121
>+#define ANDES_MAIN_DTLB_ACCESS			0x131
>+#define ANDES_MAIN_DTLB_MISS			0x141
>+#define ANDES_CYCLE_WAIT_ITLB_FILL		0x151
>+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS	0x161
>+#define ANDES_HW_PREFETCH_BUS_ACCESS		0x171
>+
>+/* Event code for microarchitecture events */
>+#define ANDES_MISPREDICT_CONDITION_BR		0x02
>+#define ANDES_MISPREDICT_TAKE_CONDITION_BR	0x12
>+#define ANDES_MISPREDICT_TARGET_RET_INST	0x22
>+
>+#ifdef CONFIG_ANDES_HPM
>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
>+
>+#else
>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
>+
>+#endif /* CONFIG_ANDES_HPM */
>+
>+#endif /* _ANDES_HPM_H_ */
>diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
>index 2f772c8..fafbff0 100644
>--- a/platform/generic/renesas/rzfive/rzfive.c
>+++ b/platform/generic/renesas/rzfive/rzfive.c
>@@ -5,6 +5,7 @@
>  */
>
> #include <andes/andes45_pma.h>
>+#include <andes/andes_hpm.h>
> #include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
>@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
> 	.match_table = renesas_rzfive_match,
> 	.early_init = renesas_rzfive_early_init,
> 	.final_init = renesas_rzfive_final_init,
>+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> 	.vendor_ext_provider = andes_sbi_vendor_ext_provider,
> 	.extensions_init = renesas_rzfive_extensions_init,
> };
>--
>2.34.1
>
>


From peterlin at andestech.com  Sat Oct 21 23:50:37 2023
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Sun, 22 Oct 2023 14:50:37 +0800
Subject: [PATCH v2 10/11] platform: andes: Implement
 andes_fdt_add_pmu_mappings platform override
In-Reply-To: <IA1PR20MB4953B09D78D523D9E15B7D9CBBDAA@IA1PR20MB4953.namprd20.prod.outlook.com>
References: <20231019113713.3508153-8-peterlin@andestech.com>
 <IA1PR20MB4953B09D78D523D9E15B7D9CBBDAA@IA1PR20MB4953.namprd20.prod.outlook.com>
Message-ID: <ZTTGPYnOsJo3jvdu@APC323>

Hi Inochi Amaoto,

On Sat, Oct 21, 2023 at 08:25:30PM +0800, Inochi Amaoto wrote:
> >Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
> >node properties that will later be populated with mapping tables.
> >
> >Currently we only support 45-series event mappings.
> >
> >Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> >---
> >Changes v1 -> v2:
> >  - New patch
> >---
> > include/sbi/sbi_ecall_interface.h          |   5 +
> > platform/generic/Kconfig                   |   2 +
> > platform/generic/andes/Kconfig             |   7 +
> > platform/generic/andes/ae350.c             |   2 +
> > platform/generic/andes/andes_hpm.c         | 381 +++++++++++++++++++++
> > platform/generic/andes/objects.mk          |   1 +
> > platform/generic/include/andes/andes_hpm.h |  83 +++++
> > platform/generic/renesas/rzfive/rzfive.c   |   2 +
> > 8 files changed, 483 insertions(+)
> > create mode 100644 platform/generic/andes/andes_hpm.c
> > create mode 100644 platform/generic/include/andes/andes_hpm.h
> >
> >diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> >index 1fe469e..89187e7 100644
> >--- a/include/sbi/sbi_ecall_interface.h
> >+++ b/include/sbi/sbi_ecall_interface.h
> >@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> > 	SBI_PMU_HW_CACHE_RESULT_MAX,
> > };
> >
> >+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
> >+	(SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
> >+	SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
> >+	SBI_PMU_HW_CACHE_RESULT_##res)
> >+
> > /**
> >  * Special "firmware" events provided by the OpenSBI, even if the hardware
> >  * does not support performance events. These events are encoded as a raw
> >diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> >index d6dafef..fbcd870 100644
> >--- a/platform/generic/Kconfig
> >+++ b/platform/generic/Kconfig
> >@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> > config PLATFORM_ANDES_AE350
> > 	bool "Andes AE350 support"
> > 	select SYS_ATCSMU
> >+	select ANDES_HPM
> > 	select ANDES_PMU
> > 	default n
> >
> >@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> > 	bool "Renesas RZ/Five support"
> > 	select ANDES45_PMA
> > 	select ANDES_SBI
> >+	select ANDES_HPM
> > 	select ANDES_PMU
> > 	default n
> >
> >diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> >index 555e4fe..8af2704 100644
> >--- a/platform/generic/andes/Kconfig
> >+++ b/platform/generic/andes/Kconfig
> >@@ -8,6 +8,13 @@ config ANDES_SBI
> > 	bool "Andes SBI support"
> > 	default n
> >
> >+config ANDES_HPM
> >+	bool "Andes HPM support"
> >+	default n
> >+	help
> >+	  This provides Andes platform override for creating
> >+	  event to counter mappings in pmu node.
> >+
> > config ANDES_PMU
> > 	bool "Andes custom PMU extension support"
> > 	default n
> >diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> >index 80cd294..28c187e 100644
> >--- a/platform/generic/andes/ae350.c
> >+++ b/platform/generic/andes/ae350.c
> >@@ -19,6 +19,7 @@
> > #include <sbi/sbi_ipi.h>
> > #include <sbi/sbi_init.h>
> > #include <andes/andes45.h>
> >+#include <andes/andes_hpm.h>
> >
> > static struct smu_data smu = { 0 };
> > extern void __ae350_enable_coherency_warmboot(void);
> >@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
> > const struct platform_override andes_ae350 = {
> > 	.match_table = andes_ae350_match,
> > 	.final_init  = ae350_final_init,
> >+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> > 	.extensions_init = ae350_extensions_init,
> > };
> >diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
> >new file mode 100644
> >index 0000000..f9e6d2e
> >--- /dev/null
> >+++ b/platform/generic/andes/andes_hpm.c
> >@@ -0,0 +1,381 @@
> >+/*
> >+ * SPDX-License-Identifier: BSD-2-Clause
> >+ *
> >+ * Copyright (c) 2023 Andes Technology Corporation
> >+ */
> >+
> >+#include <andes/andes45.h>
> >+#include <andes/andes_hpm.h>
> >+#include <sbi/riscv_asm.h>
> >+#include <sbi/sbi_ecall_interface.h>
> >+#include <sbi_utils/fdt/fdt_fixup.h>
> >+
> >+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
> >+	/* Hardware general events (Type #0) */
> >+	{
> >+		/* perf: cycles (eidx: 0x1) */
> >+		.eidx = SBI_PMU_HW_CPU_CYCLES,
> >+		.select = ANDES_CYCLES
> >+	},
> >+	{
> >+		/* perf: instructions (eidx: 0x2) */
> >+		.eidx = SBI_PMU_HW_INSTRUCTIONS,
> >+		.select = ANDES_INSTRET
> >+	},
> >+	{
> >+		/* perf: cache-references (eidx: 0x3) */
> >+		.eidx = SBI_PMU_HW_CACHE_REFERENCES,
> >+		.select = ANDES_DCACHE_ACCESS
> >+	},
> >+	{
> >+		/* perf: cache-misses (eidx: 0x4) */
> >+		.eidx = SBI_PMU_HW_CACHE_MISSES,
> >+		.select = ANDES_DCACHE_MISS
> >+	},
> >+	{
> >+		/* perf: branches (eidx: 0x5) */
> >+		.eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
> >+		.select = ANDES_CONDITION_BR,
> >+	},
> >+	{
> >+		/* perf: branch-misses (eidx: 0x6) */
> >+		.eidx = SBI_PMU_HW_BRANCH_MISSES,
> >+		.select = ANDES_MISPREDICT_CONDITION_BR,
> >+	},
> >+	/* Hardware cache events (Type #1) */
> >+	{
> >+		/* perf: L1-dcache-loads (eidx: 0x10000) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> >+		.select = ANDES_DCACHE_LOAD_ACCESS
> >+	},
> >+	{
> >+		/* perf: L1-dcache-loads-misses (eidx: 0x10001) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
> >+		.select = ANDES_DCACHE_LOAD_MISS
> >+	},
> >+	{
> >+		/* perf: L1-dcache-stores (eidx: 0x10002) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
> >+		.select = ANDES_DCACHE_STORE_ACCESS
> >+	},
> >+	{
> >+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> >+		.select = ANDES_DCACHE_STORE_MISS
> >+	},
> >+	{
> >+		/* perf: L1-icache-load (eidx: 0x10008) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> >+		.select = ANDES_ICACHE_ACCESS
> >+	},
> >+	{
> >+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
> >+		.eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> >+		.select = ANDES_ICACHE_MISS
> >+	},
> >+	{ /* sentinel */ }
> >+};
> >+
> >+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
> >+	{
> >+		/* perf: cycles (eidx: 0x1) */
> >+		.eidx_start = SBI_PMU_HW_CPU_CYCLES,
> >+		/* perf: branch-misses (eidx: 0x6) */
> >+		.eidx_end = SBI_PMU_HW_BRANCH_MISSES,
> >+		.ctr_map = ANDES_MHPM_MAP,
> >+	},
> >+	{
> >+		/* perf: L1-dcache-loads (eidx: 0x10000) */
> >+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> >+		/* perf: L1-dcache-store-misses (eidx: 0x10003) */
> >+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> >+		.ctr_map = ANDES_MHPM_MAP,
> >+	},
> >+	{
> >+		/* perf: L1-icache-load (eidx: 0x10008) */
> >+		.eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> >+		/* perf: L1-icache-load-misses (eidx: 0x10009) */
> >+		.eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> >+		.ctr_map = ANDES_MHPM_MAP,
> >+	},
> >+	{ /* sentinel */ }
> >+};
> >+
> >+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
> >+	{
> >+		.select = ANDES_CYCLES,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INSTRET,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_LOAD_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_STORE_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_ATOMIC_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_SYS_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_COMPUTE_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CONDITION_BR,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_TAKEN_CONDITION_BR,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_JAL_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_JALR_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_RET_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CONTROL_TRANS_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_EX9_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_MUL_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_DIV_REMAINDER_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_LOAD_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_STORE_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_ADD_SUB_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_MUL_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_FUSED_MULADD_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_OTHER_FLOAT_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_INT_MUL_AND_SUB_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_RETIRED_OP,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_ILM_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DLM_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_ICACHE_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_ICACHE_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_LOAD_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_LOAD_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_STORE_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_STORE_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_DCACHE_WB,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CYCLE_WAIT_ICACHE_FILL,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CYCLE_WAIT_DCACHE_FILL,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_UNCACHED_IFETCH_FROM_BUS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_UNCACHED_LOAD_FROM_BUS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MAIN_ITLB_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MAIN_ITLB_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MAIN_DTLB_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MAIN_DTLB_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_CYCLE_WAIT_ITLB_FILL,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_HW_PREFETCH_BUS_ACCESS,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MISPREDICT_CONDITION_BR,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{
> >+		.select = ANDES_MISPREDICT_TARGET_RET_INST,
> >+		.select_mask = ANDES_RAW_EVENT_MASK,
> >+		.ctr_map = ANDES_MHPM_MAP
> >+	},
> >+	{ /* sentinel */ }
> >+};
> 
> Why not use DT? I just see everything is fixed.
> 
> Adding fdt_add_pmu_mappings is not a good idea. Opensbi can use its own
> DT by setting FW_FDT_PATH, so you do not need to add this mapping table.

Thanks for the feedback.
We use this to ensure that a valid pmu node is available, but
if most people don't need this, I'm happy to drop this patch.

Best regards,
Peter Lin

> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
> >+{
> >+	/*
> >+	 * At the moment, simply create mapping for any 45-series core
> >+	 * based on marchid, we may check and differentiate the mapping
> >+	 * by mimpid.
> >+	 */
> >+	if (is_andes(45))
> >+		return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
> >+					    andes45_hw_evt_counters,
> >+					    andes45_raw_evt_counters);
> >+
> >+	return 0;
> >+}
> >diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> >index 6a8c66c..57caaf6 100644
> >--- a/platform/generic/andes/objects.mk
> >+++ b/platform/generic/andes/objects.mk
> >@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> > platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> > platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> > platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
> >+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
> >diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
> >new file mode 100644
> >index 0000000..0f301db
> >--- /dev/null
> >+++ b/platform/generic/include/andes/andes_hpm.h
> >@@ -0,0 +1,83 @@
> >+/*
> >+ * SPDX-License-Identifier: BSD-2-Clause
> >+ *
> >+ * Copyright (c) 2023 Andes Technology Corporation
> >+ */
> >+
> >+#ifndef _ANDES_HPM_H_
> >+#define _ANDES_HPM_H_
> >+
> >+#include <sbi_utils/fdt/fdt_helper.h>
> >+
> >+#define ANDES_MHPM_MAP		0x78
> >+#define ANDES_RAW_EVENT_MASK	~0ULL
> >+
> >+/* Event code for instruction commit events */
> >+#define ANDES_CYCLES				0x10
> >+#define ANDES_INSTRET				0x20
> >+#define ANDES_INT_LOAD_INST			0x30
> >+#define ANDES_INT_STORE_INST			0x40
> >+#define ANDES_ATOMIC_INST			0x50
> >+#define ANDES_SYS_INST				0x60
> >+#define ANDES_INT_COMPUTE_INST			0x70
> >+#define ANDES_CONDITION_BR			0x80
> >+#define ANDES_TAKEN_CONDITION_BR		0x90
> >+#define ANDES_JAL_INST				0xA0
> >+#define ANDES_JALR_INST				0xB0
> >+#define ANDES_RET_INST				0xC0
> >+#define ANDES_CONTROL_TRANS_INST		0xD0
> >+#define ANDES_EX9_INST				0xE0
> >+#define ANDES_INT_MUL_INST			0xF0
> >+#define ANDES_INT_DIV_REMAINDER_INST		0x100
> >+#define ANDES_FLOAT_LOAD_INST			0x110
> >+#define ANDES_FLOAT_STORE_INST			0x120
> >+#define ANDES_FLOAT_ADD_SUB_INST		0x130
> >+#define ANDES_FLOAT_MUL_INST			0x140
> >+#define ANDES_FLOAT_FUSED_MULADD_INST		0x150
> >+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST	0x160
> >+#define ANDES_OTHER_FLOAT_INST			0x170
> >+#define ANDES_INT_MUL_AND_SUB_INST		0x180
> >+#define ANDES_RETIRED_OP			0x190
> >+
> >+/* Event code for memory system events */
> >+#define ANDES_ILM_ACCESS			0x01
> >+#define ANDES_DLM_ACCESS			0x11
> >+#define ANDES_ICACHE_ACCESS			0x21
> >+#define ANDES_ICACHE_MISS			0x31
> >+#define ANDES_DCACHE_ACCESS			0x41
> >+#define ANDES_DCACHE_MISS			0x51
> >+#define ANDES_DCACHE_LOAD_ACCESS		0x61
> >+#define ANDES_DCACHE_LOAD_MISS			0x71
> >+#define ANDES_DCACHE_STORE_ACCESS		0x81
> >+#define ANDES_DCACHE_STORE_MISS			0x91
> >+#define ANDES_DCACHE_WB				0xA1
> >+#define ANDES_CYCLE_WAIT_ICACHE_FILL		0xB1
> >+#define ANDES_CYCLE_WAIT_DCACHE_FILL		0xC1
> >+#define ANDES_UNCACHED_IFETCH_FROM_BUS		0xD1
> >+#define ANDES_UNCACHED_LOAD_FROM_BUS		0xE1
> >+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH	0xF1
> >+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD		0x101
> >+#define ANDES_MAIN_ITLB_ACCESS			0x111
> >+#define ANDES_MAIN_ITLB_MISS			0x121
> >+#define ANDES_MAIN_DTLB_ACCESS			0x131
> >+#define ANDES_MAIN_DTLB_MISS			0x141
> >+#define ANDES_CYCLE_WAIT_ITLB_FILL		0x151
> >+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS	0x161
> >+#define ANDES_HW_PREFETCH_BUS_ACCESS		0x171
> >+
> >+/* Event code for microarchitecture events */
> >+#define ANDES_MISPREDICT_CONDITION_BR		0x02
> >+#define ANDES_MISPREDICT_TAKE_CONDITION_BR	0x12
> >+#define ANDES_MISPREDICT_TARGET_RET_INST	0x22
> >+
> >+#ifdef CONFIG_ANDES_HPM
> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
> >+
> >+#else
> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
> >+
> >+#endif /* CONFIG_ANDES_HPM */
> >+
> >+#endif /* _ANDES_HPM_H_ */
> >diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> >index 2f772c8..fafbff0 100644
> >--- a/platform/generic/renesas/rzfive/rzfive.c
> >+++ b/platform/generic/renesas/rzfive/rzfive.c
> >@@ -5,6 +5,7 @@
> >  */
> >
> > #include <andes/andes45_pma.h>
> >+#include <andes/andes_hpm.h>
> > #include <andes/andes_pmu.h>
> > #include <andes/andes_sbi.h>
> > #include <platform_override.h>
> >@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
> > 	.match_table = renesas_rzfive_match,
> > 	.early_init = renesas_rzfive_early_init,
> > 	.final_init = renesas_rzfive_final_init,
> >+	.fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> > 	.vendor_ext_provider = andes_sbi_vendor_ext_provider,
> > 	.extensions_init = renesas_rzfive_extensions_init,
> > };
> >--
> >2.34.1
> >
> >


From guoren at kernel.org  Sun Oct 22 23:35:19 2023
From: guoren at kernel.org (Guo Ren)
Date: Mon, 23 Oct 2023 14:35:19 +0800
Subject: [PATCH v2] lib: utils/serial: Optimize semihosting_putc implementation
In-Reply-To: <20231018024205.270-1-cp0613@linux.alibaba.com>
References: <20231018024205.270-1-cp0613@linux.alibaba.com>
Message-ID: <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com>

On Wed, Oct 18, 2023 at 10:42?AM <cp0613 at linux.alibaba.com> wrote:
>
> From: Chen Pei <cp0613 at linux.alibaba.com>
>
> For some debuggers that do not implement SYSWRITEC and SYSREADC
> operations, we can use SYSWRITE and SYSREAD instead like the
> implementation of semihosting_getc().
>
> Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> Reviewed-by: Xiang W <wxjstz at 126.com>
>
> Changed from v1:
> 1. simplified by calling semihosting_puts directly.
>
> ---
>  lib/utils/serial/semihosting.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index ce65887..a27c69e 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
>
>  /* clang-format on */
>
> -static void semihosting_putc(char ch)
> -{
> -       semihosting_trap(SYSWRITEC, &ch);
> -}
> -
>  static unsigned long semihosting_puts(const char *str, unsigned long len)
>  {
>         char ch;
> @@ -183,6 +178,11 @@ static unsigned long semihosting_puts(const char *str, unsigned long len)
>         return (ret < 0) ? 0 : ret;
>  }
>
> +static void semihosting_putc(char ch)
> +{
> +       semihosting_puts(&ch, 1);
> +}
> +
When console_puts() was introduced by commit c43903c4eae41 ("lib: sbi:
Add console_puts() callback in the console device"), sbi_putc() became
unnecessary and confusing. See below code:

void sbi_putc(char ch)
{
        if (console_dev && console_dev->console_putc) {
                if (ch == '\n')
                        console_dev->console_putc('\r');
                console_dev->console_putc(ch);
        }
}

static unsigned long nputs(const char *str, unsigned long len)
{
        unsigned long i, ret;

        if (console_dev && console_dev->console_puts) {
                ret = console_dev->console_puts(str, len);
        } else {
                for (i = 0; i < len; i++)
                        sbi_putc(str[i]);
                ret = len;
        }

        return ret;
}

Actually, sbi_putc() is duplicated from inputs(), and it's time to
remove sbi_putc to make the opensbi code clearer. Here are the
statistics of the work:

lib/utils/serial/uart8250.c-static struct sbi_console_device
uart8250_console = {
lib/utils/serial/uart8250.c-    .name = "uart8250",
lib/utils/serial/uart8250.c:    .console_putc = uart8250_putc,
lib/utils/serial/uart8250.c-    .console_getc = uart8250_getc
lib/utils/serial/uart8250.c-};
--
lib/utils/serial/renesas_scif.c-static struct sbi_console_device
renesas_scif_console = {
lib/utils/serial/renesas_scif.c-        .name           = "renesas_scif",
lib/utils/serial/renesas_scif.c:        .console_putc   = renesas_scif_putc,
lib/utils/serial/renesas_scif.c-};
--
lib/utils/serial/semihosting.c-static struct sbi_console_device
semihosting_console = {
lib/utils/serial/semihosting.c- .name = "semihosting",
lib/utils/serial/semihosting.c: .console_putc = semihosting_putc,
lib/utils/serial/semihosting.c- .console_puts = semihosting_puts,
lib/utils/serial/semihosting.c- .console_getc = semihosting_getc
lib/utils/serial/semihosting.c-};
--
lib/utils/serial/shakti-uart.c-static struct sbi_console_device
shakti_console = {
lib/utils/serial/shakti-uart.c- .name = "shakti_uart",
lib/utils/serial/shakti-uart.c: .console_putc = shakti_uart_putc,
lib/utils/serial/shakti-uart.c- .console_getc = shakti_uart_getc
lib/utils/serial/shakti-uart.c-};
--
lib/utils/serial/sifive-uart.c-static struct sbi_console_device
sifive_console = {
lib/utils/serial/sifive-uart.c- .name = "sifive_uart",
lib/utils/serial/sifive-uart.c: .console_putc = sifive_uart_putc,
lib/utils/serial/sifive-uart.c- .console_getc = sifive_uart_getc
lib/utils/serial/sifive-uart.c-};
--
lib/utils/serial/litex-uart.c-static struct sbi_console_device litex_console = {
lib/utils/serial/litex-uart.c-  .name = "litex_uart",
lib/utils/serial/litex-uart.c:  .console_putc = litex_uart_putc,
lib/utils/serial/litex-uart.c-  .console_getc = litex_uart_getc
lib/utils/serial/litex-uart.c-};
--
lib/utils/serial/gaisler-uart.c-static struct sbi_console_device
gaisler_console = {
lib/utils/serial/gaisler-uart.c-        .name         = "gaisler_uart",
lib/utils/serial/gaisler-uart.c:        .console_putc = gaisler_uart_putc,
lib/utils/serial/gaisler-uart.c-        .console_getc = gaisler_uart_getc
lib/utils/serial/gaisler-uart.c-};
--
lib/utils/serial/xlnx-uartlite.c-static struct sbi_console_device
xlnx_uartlite_console = {
lib/utils/serial/xlnx-uartlite.c-       .name = "xlnx-uartlite",
lib/utils/serial/xlnx-uartlite.c:       .console_putc = xlnx_uartlite_putc,
lib/utils/serial/xlnx-uartlite.c-       .console_getc = xlnx_uartlite_getc
lib/utils/serial/xlnx-uartlite.c-};
--
lib/utils/serial/cadence-uart.c-static struct sbi_console_device
cadence_console = {
lib/utils/serial/cadence-uart.c-        .name = "cadence_uart",
lib/utils/serial/cadence-uart.c:        .console_putc = cadence_uart_putc,
lib/utils/serial/cadence-uart.c-        .console_getc = cadence_uart_getc
lib/utils/serial/cadence-uart.c-};
--
lib/utils/sys/htif.c-static struct sbi_console_device htif_console = {
lib/utils/sys/htif.c-   .name = "htif",
lib/utils/sys/htif.c:   .console_putc = htif_putc,
lib/utils/sys/htif.c-   .console_getc = htif_getc
lib/utils/sys/htif.c-};

Is it worth removing .console_putc by implementing .console_puts.?

>  static int semihosting_getc(void)
>  {
>         char ch = 0;
> --
> 2.25.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren


From wxjstz at 126.com  Mon Oct 23 01:22:03 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 23 Oct 2023 16:22:03 +0800
Subject: [PATCH v2] lib: utils/serial: Optimize semihosting_putc
 implementation
In-Reply-To: <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com>
References: <20231018024205.270-1-cp0613@linux.alibaba.com>
	 <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com>
Message-ID: <fc823fb6c8d4c5b7906ef8f2fcbe2c9e628e6c14.camel@126.com>

? 2023-10-23???? 14:35 +0800?Guo Ren???
> On Wed, Oct 18, 2023 at 10:42?AM <cp0613 at linux.alibaba.com> wrote:
> > 
> > From: Chen Pei <cp0613 at linux.alibaba.com>
> > 
> > For some debuggers that do not implement SYSWRITEC and SYSREADC
> > operations, we can use SYSWRITE and SYSREAD instead like the
> > implementation of semihosting_getc().
> > 
> > Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> > Reviewed-by: Xiang W <wxjstz at 126.com>
> > 
> > Changed from v1:
> > 1. simplified by calling semihosting_puts directly.
> > 
> > ---
> > ?lib/utils/serial/semihosting.c | 10 +++++-----
> > ?1 file changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > index ce65887..a27c69e 100644
> > --- a/lib/utils/serial/semihosting.c
> > +++ b/lib/utils/serial/semihosting.c
> > @@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
> > 
> > ?/* clang-format on */
> > 
> > -static void semihosting_putc(char ch)
> > -{
> > -?????? semihosting_trap(SYSWRITEC, &ch);
> > -}
> > -
> > ?static unsigned long semihosting_puts(const char *str, unsigned long len)
> > ?{
> > ??????? char ch;
> > @@ -183,6 +178,11 @@ static unsigned long semihosting_puts(const char *str, unsigned long len)
> > ??????? return (ret < 0) ? 0 : ret;
> > ?}
> > 
> > +static void semihosting_putc(char ch)
> > +{
> > +?????? semihosting_puts(&ch, 1);
> > +}
> > +
> When console_puts() was introduced by commit c43903c4eae41 ("lib: sbi:
> Add console_puts() callback in the console device"), sbi_putc() became
> unnecessary and confusing. See below code:
> 
> void sbi_putc(char ch)
> {
> ??????? if (console_dev && console_dev->console_putc) {
> ??????????????? if (ch == '\n')
> ??????????????????????? console_dev->console_putc('\r');
> ??????????????? console_dev->console_putc(ch);
> ??????? }
> }
> 
> static unsigned long nputs(const char *str, unsigned long len)
> {
> ??????? unsigned long i, ret;
> 
> ??????? if (console_dev && console_dev->console_puts) {
> ??????????????? ret = console_dev->console_puts(str, len);
> ??????? } else {
> ??????????????? for (i = 0; i < len; i++)
> ??????????????????????? sbi_putc(str[i]);
> ??????????????? ret = len;
> ??????? }
> 
> ??????? return ret;
> }
> 
> Actually, sbi_putc() is duplicated from inputs(), and it's time to
> remove sbi_putc to make the opensbi code clearer. Here are the
> statistics of the work:
> 
> lib/utils/serial/uart8250.c-static struct sbi_console_device
> uart8250_console = {
> lib/utils/serial/uart8250.c-??? .name = "uart8250",
> lib/utils/serial/uart8250.c:??? .console_putc = uart8250_putc,
> lib/utils/serial/uart8250.c-??? .console_getc = uart8250_getc
> lib/utils/serial/uart8250.c-};
> --
> lib/utils/serial/renesas_scif.c-static struct sbi_console_device
> renesas_scif_console = {
> lib/utils/serial/renesas_scif.c-??????? .name?????????? = "renesas_scif",
> lib/utils/serial/renesas_scif.c:??????? .console_putc?? = renesas_scif_putc,
> lib/utils/serial/renesas_scif.c-};
> --
> lib/utils/serial/semihosting.c-static struct sbi_console_device
> semihosting_console = {
> lib/utils/serial/semihosting.c- .name = "semihosting",
> lib/utils/serial/semihosting.c: .console_putc = semihosting_putc,
> lib/utils/serial/semihosting.c- .console_puts = semihosting_puts,
> lib/utils/serial/semihosting.c- .console_getc = semihosting_getc
> lib/utils/serial/semihosting.c-};
> --
> lib/utils/serial/shakti-uart.c-static struct sbi_console_device
> shakti_console = {
> lib/utils/serial/shakti-uart.c- .name = "shakti_uart",
> lib/utils/serial/shakti-uart.c: .console_putc = shakti_uart_putc,
> lib/utils/serial/shakti-uart.c- .console_getc = shakti_uart_getc
> lib/utils/serial/shakti-uart.c-};
> --
> lib/utils/serial/sifive-uart.c-static struct sbi_console_device
> sifive_console = {
> lib/utils/serial/sifive-uart.c- .name = "sifive_uart",
> lib/utils/serial/sifive-uart.c: .console_putc = sifive_uart_putc,
> lib/utils/serial/sifive-uart.c- .console_getc = sifive_uart_getc
> lib/utils/serial/sifive-uart.c-};
> --
> lib/utils/serial/litex-uart.c-static struct sbi_console_device litex_console = {
> lib/utils/serial/litex-uart.c-? .name = "litex_uart",
> lib/utils/serial/litex-uart.c:? .console_putc = litex_uart_putc,
> lib/utils/serial/litex-uart.c-? .console_getc = litex_uart_getc
> lib/utils/serial/litex-uart.c-};
> --
> lib/utils/serial/gaisler-uart.c-static struct sbi_console_device
> gaisler_console = {
> lib/utils/serial/gaisler-uart.c-??????? .name???????? = "gaisler_uart",
> lib/utils/serial/gaisler-uart.c:??????? .console_putc = gaisler_uart_putc,
> lib/utils/serial/gaisler-uart.c-??????? .console_getc = gaisler_uart_getc
> lib/utils/serial/gaisler-uart.c-};
> --
> lib/utils/serial/xlnx-uartlite.c-static struct sbi_console_device
> xlnx_uartlite_console = {
> lib/utils/serial/xlnx-uartlite.c-?????? .name = "xlnx-uartlite",
> lib/utils/serial/xlnx-uartlite.c:?????? .console_putc = xlnx_uartlite_putc,
> lib/utils/serial/xlnx-uartlite.c-?????? .console_getc = xlnx_uartlite_getc
> lib/utils/serial/xlnx-uartlite.c-};
> --
> lib/utils/serial/cadence-uart.c-static struct sbi_console_device
> cadence_console = {
> lib/utils/serial/cadence-uart.c-??????? .name = "cadence_uart",
> lib/utils/serial/cadence-uart.c:??????? .console_putc = cadence_uart_putc,
> lib/utils/serial/cadence-uart.c-??????? .console_getc = cadence_uart_getc
> lib/utils/serial/cadence-uart.c-};
> --
> lib/utils/sys/htif.c-static struct sbi_console_device htif_console = {
> lib/utils/sys/htif.c-?? .name = "htif",
> lib/utils/sys/htif.c:?? .console_putc = htif_putc,
> lib/utils/sys/htif.c-?? .console_getc = htif_getc
> lib/utils/sys/htif.c-};
> 
> Is it worth removing .console_putc by implementing .console_puts.?
I think sbi_console.c can be modified to make console_putc unnecessary. Just
implement one of console_putc/console_puts. This can reduce modifications to
sbi_console_device.

Regards,
Xiang W
> 
> > ?static int semihosting_getc(void)
> > ?{
> > ??????? char ch = 0;
> > --
> > 2.25.1
> > 
> > 
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
> 
> 
> 
> -- 
> Best Regards
> ?Guo Ren
> 



From apatel at ventanamicro.com  Mon Oct 23 01:35:47 2023
From: apatel at ventanamicro.com (Anup Patel)
Date: Mon, 23 Oct 2023 14:05:47 +0530
Subject: [PATCH v2] lib: utils/serial: Optimize semihosting_putc implementation
In-Reply-To: <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com>
References: <20231018024205.270-1-cp0613@linux.alibaba.com> <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com>
Message-ID: <CAK9=C2XEY3VjQOjdjs6Y55JtNGE=-WAHA5Y6=+BQTraEqiSfig@mail.gmail.com>

On Mon, Oct 23, 2023 at 12:05?PM Guo Ren <guoren at kernel.org> wrote:
>
> On Wed, Oct 18, 2023 at 10:42?AM <cp0613 at linux.alibaba.com> wrote:
> >
> > From: Chen Pei <cp0613 at linux.alibaba.com>
> >
> > For some debuggers that do not implement SYSWRITEC and SYSREADC
> > operations, we can use SYSWRITE and SYSREAD instead like the
> > implementation of semihosting_getc().
> >
> > Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> > Reviewed-by: Xiang W <wxjstz at 126.com>
> >
> > Changed from v1:
> > 1. simplified by calling semihosting_puts directly.
> >
> > ---
> >  lib/utils/serial/semihosting.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > index ce65887..a27c69e 100644
> > --- a/lib/utils/serial/semihosting.c
> > +++ b/lib/utils/serial/semihosting.c
> > @@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
> >
> >  /* clang-format on */
> >
> > -static void semihosting_putc(char ch)
> > -{
> > -       semihosting_trap(SYSWRITEC, &ch);
> > -}
> > -
> >  static unsigned long semihosting_puts(const char *str, unsigned long len)
> >  {
> >         char ch;
> > @@ -183,6 +178,11 @@ static unsigned long semihosting_puts(const char *str, unsigned long len)
> >         return (ret < 0) ? 0 : ret;
> >  }
> >
> > +static void semihosting_putc(char ch)
> > +{
> > +       semihosting_puts(&ch, 1);
> > +}
> > +
> When console_puts() was introduced by commit c43903c4eae41 ("lib: sbi:
> Add console_puts() callback in the console device"), sbi_putc() became
> unnecessary and confusing. See below code:
>
> void sbi_putc(char ch)
> {
>         if (console_dev && console_dev->console_putc) {
>                 if (ch == '\n')
>                         console_dev->console_putc('\r');
>                 console_dev->console_putc(ch);
>         }
> }
>
> static unsigned long nputs(const char *str, unsigned long len)
> {
>         unsigned long i, ret;
>
>         if (console_dev && console_dev->console_puts) {
>                 ret = console_dev->console_puts(str, len);
>         } else {
>                 for (i = 0; i < len; i++)
>                         sbi_putc(str[i]);
>                 ret = len;
>         }
>
>         return ret;
> }
>
> Actually, sbi_putc() is duplicated from inputs(), and it's time to
> remove sbi_putc to make the opensbi code clearer. Here are the
> statistics of the work:
>
> lib/utils/serial/uart8250.c-static struct sbi_console_device
> uart8250_console = {
> lib/utils/serial/uart8250.c-    .name = "uart8250",
> lib/utils/serial/uart8250.c:    .console_putc = uart8250_putc,
> lib/utils/serial/uart8250.c-    .console_getc = uart8250_getc
> lib/utils/serial/uart8250.c-};
> --
> lib/utils/serial/renesas_scif.c-static struct sbi_console_device
> renesas_scif_console = {
> lib/utils/serial/renesas_scif.c-        .name           = "renesas_scif",
> lib/utils/serial/renesas_scif.c:        .console_putc   = renesas_scif_putc,
> lib/utils/serial/renesas_scif.c-};
> --
> lib/utils/serial/semihosting.c-static struct sbi_console_device
> semihosting_console = {
> lib/utils/serial/semihosting.c- .name = "semihosting",
> lib/utils/serial/semihosting.c: .console_putc = semihosting_putc,
> lib/utils/serial/semihosting.c- .console_puts = semihosting_puts,
> lib/utils/serial/semihosting.c- .console_getc = semihosting_getc
> lib/utils/serial/semihosting.c-};
> --
> lib/utils/serial/shakti-uart.c-static struct sbi_console_device
> shakti_console = {
> lib/utils/serial/shakti-uart.c- .name = "shakti_uart",
> lib/utils/serial/shakti-uart.c: .console_putc = shakti_uart_putc,
> lib/utils/serial/shakti-uart.c- .console_getc = shakti_uart_getc
> lib/utils/serial/shakti-uart.c-};
> --
> lib/utils/serial/sifive-uart.c-static struct sbi_console_device
> sifive_console = {
> lib/utils/serial/sifive-uart.c- .name = "sifive_uart",
> lib/utils/serial/sifive-uart.c: .console_putc = sifive_uart_putc,
> lib/utils/serial/sifive-uart.c- .console_getc = sifive_uart_getc
> lib/utils/serial/sifive-uart.c-};
> --
> lib/utils/serial/litex-uart.c-static struct sbi_console_device litex_console = {
> lib/utils/serial/litex-uart.c-  .name = "litex_uart",
> lib/utils/serial/litex-uart.c:  .console_putc = litex_uart_putc,
> lib/utils/serial/litex-uart.c-  .console_getc = litex_uart_getc
> lib/utils/serial/litex-uart.c-};
> --
> lib/utils/serial/gaisler-uart.c-static struct sbi_console_device
> gaisler_console = {
> lib/utils/serial/gaisler-uart.c-        .name         = "gaisler_uart",
> lib/utils/serial/gaisler-uart.c:        .console_putc = gaisler_uart_putc,
> lib/utils/serial/gaisler-uart.c-        .console_getc = gaisler_uart_getc
> lib/utils/serial/gaisler-uart.c-};
> --
> lib/utils/serial/xlnx-uartlite.c-static struct sbi_console_device
> xlnx_uartlite_console = {
> lib/utils/serial/xlnx-uartlite.c-       .name = "xlnx-uartlite",
> lib/utils/serial/xlnx-uartlite.c:       .console_putc = xlnx_uartlite_putc,
> lib/utils/serial/xlnx-uartlite.c-       .console_getc = xlnx_uartlite_getc
> lib/utils/serial/xlnx-uartlite.c-};
> --
> lib/utils/serial/cadence-uart.c-static struct sbi_console_device
> cadence_console = {
> lib/utils/serial/cadence-uart.c-        .name = "cadence_uart",
> lib/utils/serial/cadence-uart.c:        .console_putc = cadence_uart_putc,
> lib/utils/serial/cadence-uart.c-        .console_getc = cadence_uart_getc
> lib/utils/serial/cadence-uart.c-};
> --
> lib/utils/sys/htif.c-static struct sbi_console_device htif_console = {
> lib/utils/sys/htif.c-   .name = "htif",
> lib/utils/sys/htif.c:   .console_putc = htif_putc,
> lib/utils/sys/htif.c-   .console_getc = htif_getc
> lib/utils/sys/htif.c-};
>
> Is it worth removing .console_putc by implementing .console_puts.?

NACK, having console_puts in all serial drivers would mean
duplicating generic code into all drivers.

Regards,
Anup

>
> >  static int semihosting_getc(void)
> >  {
> >         char ch = 0;
> > --
> > 2.25.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
>
>
> --
> Best Regards
>  Guo Ren
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From guoren at kernel.org  Mon Oct 23 01:57:19 2023
From: guoren at kernel.org (Guo Ren)
Date: Mon, 23 Oct 2023 16:57:19 +0800
Subject: [PATCH v2] lib: utils/serial: Optimize semihosting_putc implementation
In-Reply-To: <CAK9=C2XEY3VjQOjdjs6Y55JtNGE=-WAHA5Y6=+BQTraEqiSfig@mail.gmail.com>
References: <20231018024205.270-1-cp0613@linux.alibaba.com>
 <CAJF2gTTop12wvxoZ7_M1r+mbrpihbfeNp1j=v1p=6Xtmx1PbYg@mail.gmail.com> <CAK9=C2XEY3VjQOjdjs6Y55JtNGE=-WAHA5Y6=+BQTraEqiSfig@mail.gmail.com>
Message-ID: <CAJF2gTQDN3Oqxy8CR98XAjYHGMUY8SFQRGsJWNeacHkUTJJrzQ@mail.gmail.com>

On Mon, Oct 23, 2023 at 4:36?PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> On Mon, Oct 23, 2023 at 12:05?PM Guo Ren <guoren at kernel.org> wrote:
> >
> > On Wed, Oct 18, 2023 at 10:42?AM <cp0613 at linux.alibaba.com> wrote:
> > >
> > > From: Chen Pei <cp0613 at linux.alibaba.com>
> > >
> > > For some debuggers that do not implement SYSWRITEC and SYSREADC
> > > operations, we can use SYSWRITE and SYSREAD instead like the
> > > implementation of semihosting_getc().
> > >
> > > Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> > > Reviewed-by: Xiang W <wxjstz at 126.com>
> > >
> > > Changed from v1:
> > > 1. simplified by calling semihosting_puts directly.
> > >
> > > ---
> > >  lib/utils/serial/semihosting.c | 10 +++++-----
> > >  1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > > index ce65887..a27c69e 100644
> > > --- a/lib/utils/serial/semihosting.c
> > > +++ b/lib/utils/serial/semihosting.c
> > > @@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
> > >
> > >  /* clang-format on */
> > >
> > > -static void semihosting_putc(char ch)
> > > -{
> > > -       semihosting_trap(SYSWRITEC, &ch);
> > > -}
> > > -
> > >  static unsigned long semihosting_puts(const char *str, unsigned long len)
> > >  {
> > >         char ch;
> > > @@ -183,6 +178,11 @@ static unsigned long semihosting_puts(const char *str, unsigned long len)
> > >         return (ret < 0) ? 0 : ret;
> > >  }
> > >
> > > +static void semihosting_putc(char ch)
> > > +{
> > > +       semihosting_puts(&ch, 1);
> > > +}
> > > +
> > When console_puts() was introduced by commit c43903c4eae41 ("lib: sbi:
> > Add console_puts() callback in the console device"), sbi_putc() became
> > unnecessary and confusing. See below code:
> >
> > void sbi_putc(char ch)
> > {
> >         if (console_dev && console_dev->console_putc) {
> >                 if (ch == '\n')
> >                         console_dev->console_putc('\r');
> >                 console_dev->console_putc(ch);
> >         }
> > }
> >
> > static unsigned long nputs(const char *str, unsigned long len)
> > {
> >         unsigned long i, ret;
> >
> >         if (console_dev && console_dev->console_puts) {
> >                 ret = console_dev->console_puts(str, len);
> >         } else {
> >                 for (i = 0; i < len; i++)
> >                         sbi_putc(str[i]);
> >                 ret = len;
> >         }
> >
> >         return ret;
> > }
> >
> > Actually, sbi_putc() is duplicated from inputs(), and it's time to
> > remove sbi_putc to make the opensbi code clearer. Here are the
> > statistics of the work:
> >
> > lib/utils/serial/uart8250.c-static struct sbi_console_device
> > uart8250_console = {
> > lib/utils/serial/uart8250.c-    .name = "uart8250",
> > lib/utils/serial/uart8250.c:    .console_putc = uart8250_putc,
> > lib/utils/serial/uart8250.c-    .console_getc = uart8250_getc
> > lib/utils/serial/uart8250.c-};
> > --
> > lib/utils/serial/renesas_scif.c-static struct sbi_console_device
> > renesas_scif_console = {
> > lib/utils/serial/renesas_scif.c-        .name           = "renesas_scif",
> > lib/utils/serial/renesas_scif.c:        .console_putc   = renesas_scif_putc,
> > lib/utils/serial/renesas_scif.c-};
> > --
> > lib/utils/serial/semihosting.c-static struct sbi_console_device
> > semihosting_console = {
> > lib/utils/serial/semihosting.c- .name = "semihosting",
> > lib/utils/serial/semihosting.c: .console_putc = semihosting_putc,
> > lib/utils/serial/semihosting.c- .console_puts = semihosting_puts,
> > lib/utils/serial/semihosting.c- .console_getc = semihosting_getc
> > lib/utils/serial/semihosting.c-};
> > --
> > lib/utils/serial/shakti-uart.c-static struct sbi_console_device
> > shakti_console = {
> > lib/utils/serial/shakti-uart.c- .name = "shakti_uart",
> > lib/utils/serial/shakti-uart.c: .console_putc = shakti_uart_putc,
> > lib/utils/serial/shakti-uart.c- .console_getc = shakti_uart_getc
> > lib/utils/serial/shakti-uart.c-};
> > --
> > lib/utils/serial/sifive-uart.c-static struct sbi_console_device
> > sifive_console = {
> > lib/utils/serial/sifive-uart.c- .name = "sifive_uart",
> > lib/utils/serial/sifive-uart.c: .console_putc = sifive_uart_putc,
> > lib/utils/serial/sifive-uart.c- .console_getc = sifive_uart_getc
> > lib/utils/serial/sifive-uart.c-};
> > --
> > lib/utils/serial/litex-uart.c-static struct sbi_console_device litex_console = {
> > lib/utils/serial/litex-uart.c-  .name = "litex_uart",
> > lib/utils/serial/litex-uart.c:  .console_putc = litex_uart_putc,
> > lib/utils/serial/litex-uart.c-  .console_getc = litex_uart_getc
> > lib/utils/serial/litex-uart.c-};
> > --
> > lib/utils/serial/gaisler-uart.c-static struct sbi_console_device
> > gaisler_console = {
> > lib/utils/serial/gaisler-uart.c-        .name         = "gaisler_uart",
> > lib/utils/serial/gaisler-uart.c:        .console_putc = gaisler_uart_putc,
> > lib/utils/serial/gaisler-uart.c-        .console_getc = gaisler_uart_getc
> > lib/utils/serial/gaisler-uart.c-};
> > --
> > lib/utils/serial/xlnx-uartlite.c-static struct sbi_console_device
> > xlnx_uartlite_console = {
> > lib/utils/serial/xlnx-uartlite.c-       .name = "xlnx-uartlite",
> > lib/utils/serial/xlnx-uartlite.c:       .console_putc = xlnx_uartlite_putc,
> > lib/utils/serial/xlnx-uartlite.c-       .console_getc = xlnx_uartlite_getc
> > lib/utils/serial/xlnx-uartlite.c-};
> > --
> > lib/utils/serial/cadence-uart.c-static struct sbi_console_device
> > cadence_console = {
> > lib/utils/serial/cadence-uart.c-        .name = "cadence_uart",
> > lib/utils/serial/cadence-uart.c:        .console_putc = cadence_uart_putc,
> > lib/utils/serial/cadence-uart.c-        .console_getc = cadence_uart_getc
> > lib/utils/serial/cadence-uart.c-};
> > --
> > lib/utils/sys/htif.c-static struct sbi_console_device htif_console = {
> > lib/utils/sys/htif.c-   .name = "htif",
> > lib/utils/sys/htif.c:   .console_putc = htif_putc,
> > lib/utils/sys/htif.c-   .console_getc = htif_getc
> > lib/utils/sys/htif.c-};
> >
> > Is it worth removing .console_putc by implementing .console_puts.?
>
> NACK, having console_puts in all serial drivers would mean
> duplicating generic code into all drivers.
Okay, then, I agree with the patch.

+static void semihosting_putc(char ch)
+{
+       semihosting_puts(&ch, 1);
+}

Acked-by: Guo Ren <guoren at kernel.org>

>
> Regards,
> Anup
>
> >
> > >  static int semihosting_getc(void)
> > >  {
> > >         char ch = 0;
> > > --
> > > 2.25.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
> >
> >
> >
> > --
> > Best Regards
> >  Guo Ren
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren


From yongxuan.wang at sifive.com  Tue Oct 24 03:11:41 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:41 +0000
Subject: [PATCH v2 1/5] lib: sbi: Improve the code of privilege mode and extensions detection
In-Reply-To: <20231024101145.32000-1-yongxuan.wang@sifive.com>
References: <20231024101145.32000-1-yongxuan.wang@sifive.com>
Message-ID: <20231024101145.32000-2-yongxuan.wang@sifive.com>

We can enhance the code by creating 2 unified interface with macro  for
privilege mode and extensions detection, which relies on supported
privilege modes and CSRs.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
 lib/sbi/sbi_hart.c | 88 ++++++++++++++++++++--------------------------
 1 file changed, 38 insertions(+), 50 deletions(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 29d6481..5c52b6c 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -802,6 +802,7 @@ static int hart_detect_features(struct sbi_scratch *scratch)
 	hfeatures->extensions = 0;
 	hfeatures->pmp_count = 0;
 	hfeatures->mhpm_mask = 0;
+	hfeatures->priv_version = SBI_HART_PRIV_VER_UNKNOWN;
 
 #define __check_hpm_csr(__csr, __mask) 					  \
 	oldval = csr_read_allowed(__csr, (ulong)&trap);			  \
@@ -894,67 +895,54 @@ __pmp_skip:
 #undef __check_csr_2
 #undef __check_csr
 
-	/* Detect if hart supports Priv v1.10 */
-	val = csr_read_allowed(CSR_MCOUNTEREN, (unsigned long)&trap);
-	if (!trap.cause)
-		hfeatures->priv_version = SBI_HART_PRIV_VER_1_10;
 
-	/* Detect if hart supports Priv v1.11 */
-	val = csr_read_allowed(CSR_MCOUNTINHIBIT, (unsigned long)&trap);
-	if (!trap.cause &&
-	    (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_10))
-		hfeatures->priv_version = SBI_HART_PRIV_VER_1_11;
+#define __check_priv(__csr, __base_priv, __priv)			\
+	val = csr_read_allowed(__csr, (ulong)&trap);			\
+	if (!trap.cause && (hfeatures->priv_version >= __base_priv)) {	\
+		hfeatures->priv_version = __priv;			\
+	}
 
+	/* Detect if hart supports Priv v1.10 */
+	__check_priv(CSR_MCOUNTEREN,
+		     SBI_HART_PRIV_VER_UNKNOWN, SBI_HART_PRIV_VER_1_10);
+	/* Detect if hart supports Priv v1.11 */
+	__check_priv(CSR_MCOUNTINHIBIT,
+		     SBI_HART_PRIV_VER_1_10, SBI_HART_PRIV_VER_1_11);
 	/* Detect if hart supports Priv v1.12 */
-	csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
-	if (!trap.cause &&
-	    (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_11))
-		hfeatures->priv_version = SBI_HART_PRIV_VER_1_12;
+	__check_priv(CSR_MENVCFG,
+		     SBI_HART_PRIV_VER_1_11, SBI_HART_PRIV_VER_1_12);
 
-	/* Counter overflow/filtering is not useful without mcounter/inhibit */
-	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_11) {
-		/* Detect if hart supports sscofpmf */
-		csr_read_allowed(CSR_SCOUNTOVF, (unsigned long)&trap);
-		if (!trap.cause)
-			__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_SSCOFPMF, true);
+#undef __check_priv_csr
+
+#define __check_ext_csr(__base_priv, __csr, __ext)			\
+	if (hfeatures->priv_version >= __base_priv) {			\
+		csr_read_allowed(__csr, (ulong)&trap);			\
+		if (!trap.cause)					\
+			__sbi_hart_update_extension(hfeatures,		\
+						    __ext, true);	\
 	}
 
+	/* Counter overflow/filtering is not useful without mcounter/inhibit */
+	/* Detect if hart supports sscofpmf */
+	__check_ext_csr(SBI_HART_PRIV_VER_1_11,
+		        CSR_SCOUNTOVF, SBI_HART_EXT_SSCOFPMF);
 	/* Detect if hart supports time CSR */
-	csr_read_allowed(CSR_TIME, (unsigned long)&trap);
-	if (!trap.cause)
-		__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_ZICNTR, true);
-
+	__check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
+			CSR_TIME, SBI_HART_EXT_ZICNTR);
 	/* Detect if hart has AIA local interrupt CSRs */
-	csr_read_allowed(CSR_MTOPI, (unsigned long)&trap);
-	if (!trap.cause)
-		__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_SMAIA, true);
-
+	__check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
+			CSR_MTOPI, SBI_HART_EXT_SMAIA);
 	/* Detect if hart supports stimecmp CSR(Sstc extension) */
-	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
-		csr_read_allowed(CSR_STIMECMP, (unsigned long)&trap);
-		if (!trap.cause)
-			__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_SSTC, true);
-	}
-
+	__check_ext_csr(SBI_HART_PRIV_VER_1_12,
+			CSR_STIMECMP, SBI_HART_EXT_SSTC);
 	/* Detect if hart supports mstateen CSRs */
-	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
-		val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
-		if (!trap.cause)
-			__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_SMSTATEEN, true);
-	}
-
+	__check_ext_csr(SBI_HART_PRIV_VER_1_12,
+			CSR_MSTATEEN0, SBI_HART_EXT_SMSTATEEN);
 	/* Detect if hart supports smcntrpmf */
-	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
-		csr_read_allowed(CSR_MCYCLECFG, (unsigned long)&trap);
-		if (!trap.cause)
-			__sbi_hart_update_extension(hfeatures,
-					SBI_HART_EXT_SMCNTRPMF, true);
-	}
+	__check_ext_csr(SBI_HART_PRIV_VER_1_12,
+			CSR_MCYCLECFG, SBI_HART_EXT_SMCNTRPMF);
+
+#undef __check_ext_csr
 
 	/* Let platform populate extensions */
 	rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
-- 
2.17.1



From yongxuan.wang at sifive.com  Tue Oct 24 03:11:40 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:40 +0000
Subject: [PATCH v2 0/5] Add Svadu extension support
Message-ID: <20231024101145.32000-1-yongxuan.wang@sifive.com>

This series enables Svadu extension support by configuring the menvcfg
CSR and, if available, displays the Svadu extension in the boot log.

Additionally, we've made some programming improvements in
lib/sbi/sbi_hart.c and lib/utils/fdt/fdt_helper.c.

---
v2:
- Rearrange the patches to do the code refactoring first before adding
  new features
- Suggested by Anup and Atish, detect extensions from DT instead of
  menvcfg CSR
- Enable access to some extensions through menvcfg CSR if they are
  present in the device tree.

Yong-Xuan Wang (5):
  lib: sbi: Improve the code of privilege mode and extensions detection
  lib: sbi: Refactor the code for enable extensions in menvfg CSR
  lib: sbi: Using one array to define the name of extensions
  lib: sbi: Detect extensions from the ISA string in DT
  lib: sbi: Add support for Svadu extension

 include/sbi/riscv_encoding.h |   6 +-
 include/sbi/sbi_hart.h       |  15 +++
 lib/sbi/sbi_hart.c           | 226 +++++++++++++----------------------
 lib/utils/fdt/fdt_helper.c   |   5 +-
 4 files changed, 104 insertions(+), 148 deletions(-)

-- 
2.17.1



From yongxuan.wang at sifive.com  Tue Oct 24 03:11:42 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:42 +0000
Subject: [PATCH v2 2/5] lib: sbi: Refactor the code for enable extensions in menvfg CSR
In-Reply-To: <20231024101145.32000-1-yongxuan.wang@sifive.com>
References: <20231024101145.32000-1-yongxuan.wang@sifive.com>
Message-ID: <20231024101145.32000-3-yongxuan.wang@sifive.com>

Use 1 variable to store the value of menvcfg.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
 include/sbi/riscv_encoding.h |  5 -----
 lib/sbi/sbi_hart.c           | 15 ++++++---------
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index a545242..92ee0a8 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -207,13 +207,8 @@
 
 #define MHPMEVENT_SSCOF_MASK		_ULL(0xFFFF000000000000)
 
-#if __riscv_xlen > 32
 #define ENVCFG_STCE			(_ULL(1) << 63)
 #define ENVCFG_PBMTE			(_ULL(1) << 62)
-#else
-#define ENVCFGH_STCE			(_UL(1) << 31)
-#define ENVCFGH_PBMTE			(_UL(1) << 30)
-#endif
 #define ENVCFG_CBZE			(_UL(1) << 7)
 #define ENVCFG_CBCFE			(_UL(1) << 6)
 #define ENVCFG_CBIE_SHIFT		4
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5c52b6c..1589111 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -108,6 +108,9 @@ static void mstatus_init(struct sbi_scratch *scratch)
 
 	if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) {
 		menvcfg_val = csr_read(CSR_MENVCFG);
+#if __riscv_xlen == 32
+		menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
+#endif
 
 		/*
 		 * Set menvcfg.CBZE == 1
@@ -139,9 +142,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		 * If Svpbmt extension is not available then menvcfg.PBMTE
 		 * will be read-only zero.
 		 */
-#if __riscv_xlen > 32
 		menvcfg_val |= ENVCFG_PBMTE;
-#endif
 
 		/*
 		 * The spec doesn't explicitly describe the reset value of menvcfg.
@@ -149,17 +150,13 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		 * hardware.
 		 */
 		if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC)) {
-#if __riscv_xlen == 32
-			unsigned long menvcfgh_val;
-			menvcfgh_val = csr_read(CSR_MENVCFGH);
-			menvcfgh_val |= ENVCFGH_STCE;
-			csr_write(CSR_MENVCFGH, menvcfgh_val);
-#else
 			menvcfg_val |= ENVCFG_STCE;
-#endif
 		}
 
 		csr_write(CSR_MENVCFG, menvcfg_val);
+#if __riscv_xlen == 32
+		csr_write(CSR_MENVCFGH, menvcfg_val >> 32);
+#endif
 	}
 
 	/* Disable all interrupts */
-- 
2.17.1



From yongxuan.wang at sifive.com  Tue Oct 24 03:11:43 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:43 +0000
Subject: [PATCH v2 3/5] lib: sbi: Using one array to define the name of extensions
In-Reply-To: <20231024101145.32000-1-yongxuan.wang@sifive.com>
References: <20231024101145.32000-1-yongxuan.wang@sifive.com>
Message-ID: <20231024101145.32000-4-yongxuan.wang@sifive.com>

Define an array sbi_hart_ext to map extension ID and name , and use it
for ISA parsing and printing out the supported extensions.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
---
 include/sbi/sbi_hart.h     |  7 ++++
 lib/sbi/sbi_hart.c         | 72 ++++++++++++--------------------------
 lib/utils/fdt/fdt_helper.c |  5 ++-
 3 files changed, 34 insertions(+), 50 deletions(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index e60f415..33bf327 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -47,6 +47,13 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_MAX,
 };
 
+struct sbi_hart_ext_data {
+	const unsigned int id;
+	const char *name;
+};
+
+extern const struct sbi_hart_ext_data sbi_hart_ext[];
+
 /*
  * Smepmp enforces access boundaries between M-mode and
  * S/U-mode. When it is enabled, the PMPs are programmed
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 1589111..add0155 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -652,42 +652,22 @@ bool sbi_hart_has_extension(struct sbi_scratch *scratch,
 		return false;
 }
 
-static inline char *sbi_hart_extension_id2string(int ext)
-{
-	char *estr = NULL;
-
-	switch (ext) {
-	case SBI_HART_EXT_SMAIA:
-		estr = "smaia";
-		break;
-	case SBI_HART_EXT_SMSTATEEN:
-		estr = "smstateen";
-		break;
-	case SBI_HART_EXT_SSCOFPMF:
-		estr = "sscofpmf";
-		break;
-	case SBI_HART_EXT_SSTC:
-		estr = "sstc";
-		break;
-	case SBI_HART_EXT_ZICNTR:
-		estr = "zicntr";
-		break;
-	case SBI_HART_EXT_ZIHPM:
-		estr = "zihpm";
-		break;
-	case SBI_HART_EXT_SMEPMP:
-		estr = "smepmp";
-		break;
-	case SBI_HART_EXT_SMCNTRPMF:
-		estr = "smcntrpmf";
-		break;
-	default:
-		break;
-	}
-
-	return estr;
+#define __SBI_HART_EXT_DATA(_name, _id) {	\
+	.name = #_name,				\
+	.id = _id,				\
 }
 
+const struct sbi_hart_ext_data sbi_hart_ext[] = {
+	__SBI_HART_EXT_DATA(smaia, SBI_HART_EXT_SMAIA),
+	__SBI_HART_EXT_DATA(smepmp, SBI_HART_EXT_SMEPMP),
+	__SBI_HART_EXT_DATA(smstateen, SBI_HART_EXT_SMSTATEEN),
+	__SBI_HART_EXT_DATA(sscofpmf, SBI_HART_EXT_SSCOFPMF),
+	__SBI_HART_EXT_DATA(sstc, SBI_HART_EXT_SSTC),
+	__SBI_HART_EXT_DATA(zicntr, SBI_HART_EXT_ZICNTR),
+	__SBI_HART_EXT_DATA(zihpm, SBI_HART_EXT_ZIHPM),
+	__SBI_HART_EXT_DATA(smcntrpmf, SBI_HART_EXT_SMCNTRPMF),
+};
+
 /**
  * Get the hart extensions in string format
  *
@@ -702,8 +682,8 @@ void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
 {
 	struct sbi_hart_features *hfeatures =
 			sbi_scratch_offset_ptr(scratch, hart_features_offset);
-	int offset = 0, ext = 0;
-	char *temp;
+	int offset = 0;
+	size_t i;
 
 	if (!extensions_str || nestr <= 0)
 		return;
@@ -712,20 +692,14 @@ void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
 	if (!hfeatures->extensions)
 		goto done;
 
-	do {
-		if (hfeatures->extensions & BIT(ext)) {
-			temp = sbi_hart_extension_id2string(ext);
-			if (temp) {
-				sbi_snprintf(extensions_str + offset,
-					     nestr - offset,
-					     "%s,", temp);
-				offset = offset + sbi_strlen(temp) + 1;
-			}
+	for (i = 0; i < SBI_HART_EXT_MAX; i++) {
+		if (hfeatures->extensions & BIT(sbi_hart_ext[i].id)) {
+			sbi_snprintf(extensions_str + offset,
+				     nestr - offset,
+				     "%s,", sbi_hart_ext[i].name);
+			offset = offset + sbi_strlen(sbi_hart_ext[i].name) + 1;
 		}
-
-		ext++;
-	} while (ext < SBI_HART_EXT_MAX);
-
+	}
 done:
 	if (offset)
 		extensions_str[offset - 1] = '\0';
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 9ae7f09..9cef68a 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -375,7 +375,10 @@ static int fdt_parse_isa_one_hart(const char *isa, unsigned long *extensions)
 				continue;			\
 			}
 
-		set_multi_letter_ext("smepmp", SBI_HART_EXT_SMEPMP);
+		for (j = 0; j < SBI_HART_EXT_MAX; j++) {
+			set_multi_letter_ext(sbi_hart_ext[j].name,
+					     sbi_hart_ext[j].id);
+		}
 #undef set_multi_letter_ext
 	}
 
-- 
2.17.1



From yongxuan.wang at sifive.com  Tue Oct 24 03:11:44 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:44 +0000
Subject: [PATCH v2 4/5] lib: sbi: Detect extensions from the ISA string in DT
In-Reply-To: <20231024101145.32000-1-yongxuan.wang@sifive.com>
References: <20231024101145.32000-1-yongxuan.wang@sifive.com>
Message-ID: <20231024101145.32000-5-yongxuan.wang@sifive.com>

Enable access to some extensions through menvcfg and show them in "Boot
HART ISA Extensions" if they are present in the device tree.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
---
 include/sbi/sbi_hart.h |  6 +++++
 lib/sbi/sbi_hart.c     | 51 +++++++++++++-----------------------------
 2 files changed, 22 insertions(+), 35 deletions(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 33bf327..0424da8 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -42,6 +42,12 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_ZIHPM,
 	/** Hart has Smcntrpmf extension */
 	SBI_HART_EXT_SMCNTRPMF,
+	/** Hart has Zicboz extension */
+	SBI_HART_EXT_ZICBOZ,
+	/** Hart has Zicbom extension */
+	SBI_HART_EXT_ZICBOM,
+	/** Hart has Svpbmt extension */
+	SBI_HART_EXT_SVPBMT,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index add0155..4fb5153 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -112,46 +112,24 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		menvcfg_val |= ((uint64_t)csr_read(CSR_MENVCFGH)) << 32;
 #endif
 
-		/*
-		 * Set menvcfg.CBZE == 1
-		 *
-		 * If Zicboz extension is not available then writes to
-		 * menvcfg.CBZE will be ignored because it is a WARL field.
-		 */
-		menvcfg_val |= ENVCFG_CBZE;
+#define __set_menvcfg_ext(__ext, __bit)					\
+		if (sbi_hart_has_extension(scratch, __ext)) {		\
+			menvcfg_val |= __bit;				\
+		}
 
 		/*
-		 * Set menvcfg.CBCFE == 1
-		 *
-		 * If Zicbom extension is not available then writes to
-		 * menvcfg.CBCFE will be ignored because it is a WARL field.
+		* Enable access to extensions if they are present in the
+		 * hardware or in the device tree.
 		 */
-		menvcfg_val |= ENVCFG_CBCFE;
 
-		/*
-		 * Set menvcfg.CBIE == 3
-		 *
-		 * If Zicbom extension is not available then writes to
-		 * menvcfg.CBIE will be ignored because it is a WARL field.
-		 */
-		menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
+		__set_menvcfg_ext(SBI_HART_EXT_ZICBOZ, ENVCFG_CBZE);
+		__set_menvcfg_ext(SBI_HART_EXT_ZICBOM, ENVCFG_CBCFE);
+		__set_menvcfg_ext(SBI_HART_EXT_ZICBOM,
+				  ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT);
+		__set_menvcfg_ext(SBI_HART_EXT_SVPBMT, ENVCFG_PBMTE);
+		__set_menvcfg_ext(SBI_HART_EXT_SSTC, ENVCFG_STCE);
 
-		/*
-		 * Set menvcfg.PBMTE == 1 for RV64 or RV128
-		 *
-		 * If Svpbmt extension is not available then menvcfg.PBMTE
-		 * will be read-only zero.
-		 */
-		menvcfg_val |= ENVCFG_PBMTE;
-
-		/*
-		 * The spec doesn't explicitly describe the reset value of menvcfg.
-		 * Enable access to stimecmp if sstc extension is present in the
-		 * hardware.
-		 */
-		if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSTC)) {
-			menvcfg_val |= ENVCFG_STCE;
-		}
+#undef __set_menvcfg_ext
 
 		csr_write(CSR_MENVCFG, menvcfg_val);
 #if __riscv_xlen == 32
@@ -666,6 +644,9 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
 	__SBI_HART_EXT_DATA(zicntr, SBI_HART_EXT_ZICNTR),
 	__SBI_HART_EXT_DATA(zihpm, SBI_HART_EXT_ZIHPM),
 	__SBI_HART_EXT_DATA(smcntrpmf, SBI_HART_EXT_SMCNTRPMF),
+	__SBI_HART_EXT_DATA(zicboz, SBI_HART_EXT_ZICBOZ),
+	__SBI_HART_EXT_DATA(zicbom, SBI_HART_EXT_ZICBOM),
+	__SBI_HART_EXT_DATA(svpbmt, SBI_HART_EXT_SVPBMT),
 };
 
 /**
-- 
2.17.1



From yongxuan.wang at sifive.com  Tue Oct 24 03:11:45 2023
From: yongxuan.wang at sifive.com (Yong-Xuan Wang)
Date: Tue, 24 Oct 2023 10:11:45 +0000
Subject: [PATCH v2 5/5] lib: sbi: Add support for Svadu extension
In-Reply-To: <20231024101145.32000-1-yongxuan.wang@sifive.com>
References: <20231024101145.32000-1-yongxuan.wang@sifive.com>
Message-ID: <20231024101145.32000-6-yongxuan.wang@sifive.com>

This patch detects the Svadu extension from DT and enables the ADUE bit
in the menvcfg CSR for lower privilege modes.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang at sifive.com>
---
 include/sbi/riscv_encoding.h | 1 +
 include/sbi/sbi_hart.h       | 2 ++
 lib/sbi/sbi_hart.c           | 2 ++
 3 files changed, 5 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 92ee0a8..8a81787 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -209,6 +209,7 @@
 
 #define ENVCFG_STCE			(_ULL(1) << 63)
 #define ENVCFG_PBMTE			(_ULL(1) << 62)
+#define ENVCFG_ADUE			(_ULL(1) << 61)
 #define ENVCFG_CBZE			(_UL(1) << 7)
 #define ENVCFG_CBCFE			(_UL(1) << 6)
 #define ENVCFG_CBIE_SHIFT		4
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 0424da8..83471c1 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -48,6 +48,8 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_ZICBOM,
 	/** Hart has Svpbmt extension */
 	SBI_HART_EXT_SVPBMT,
+	/** Hart has Svadu extension */
+	SBI_HART_EXT_SVADU,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 4fb5153..9874e77 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -128,6 +128,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
 				  ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT);
 		__set_menvcfg_ext(SBI_HART_EXT_SVPBMT, ENVCFG_PBMTE);
 		__set_menvcfg_ext(SBI_HART_EXT_SSTC, ENVCFG_STCE);
+		__set_menvcfg_ext(SBI_HART_EXT_SVADU, ENVCFG_ADUE);
 
 #undef __set_menvcfg_ext
 
@@ -647,6 +648,7 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
 	__SBI_HART_EXT_DATA(zicboz, SBI_HART_EXT_ZICBOZ),
 	__SBI_HART_EXT_DATA(zicbom, SBI_HART_EXT_ZICBOM),
 	__SBI_HART_EXT_DATA(svpbmt, SBI_HART_EXT_SVPBMT),
+	__SBI_HART_EXT_DATA(svadu, SBI_HART_EXT_SVADU),
 };
 
 /**
-- 
2.17.1



From wxjstz at 126.com  Tue Oct 24 21:30:57 2023
From: wxjstz at 126.com (Xiang W)
Date: Wed, 25 Oct 2023 12:30:57 +0800
Subject: [PATCH 2/2] lib: utils/serial: remove semihosting_putc
In-Reply-To: <20231025043104.748104-1-wxjstz@126.com>
References: <20231025043104.748104-1-wxjstz@126.com>
Message-ID: <20231025043104.748104-2-wxjstz@126.com>

For some debuggers that do not implement SYSWRITEC and SYSREADC
operations, we can use SYSWRITE and SYSREAD instead like the
implementation of semihosting_putc(). This makes
semihosting_putc/semihosting_puts similar. Since
console_putc/console_puts are now interchangeable, removing the
semihosting_putc.

Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/utils/serial/semihosting.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index ce65887..19ebaa0 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
 
 /* clang-format on */
 
-static void semihosting_putc(char ch)
-{
-	semihosting_trap(SYSWRITEC, &ch);
-}
-
 static unsigned long semihosting_puts(const char *str, unsigned long len)
 {
 	char ch;
@@ -199,7 +194,6 @@ static int semihosting_getc(void)
 
 static struct sbi_console_device semihosting_console = {
 	.name = "semihosting",
-	.console_putc = semihosting_putc,
 	.console_puts = semihosting_puts,
 	.console_getc = semihosting_getc
 };
-- 
2.42.0



From wxjstz at 126.com  Tue Oct 24 21:30:56 2023
From: wxjstz at 126.com (Xiang W)
Date: Wed, 25 Oct 2023 12:30:56 +0800
Subject: [PATCH 1/2] lib: sbi: Make console_puts/console_putc interchangeable
Message-ID: <20231025043104.748104-1-wxjstz@126.com>

console_puts/console_putc should replace each other, but the previous
sbi_putc can only use console_putc. This patch improves this problem.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_console.c | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index 2b3b0a3..ab09a5c 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -37,28 +37,22 @@ int sbi_getc(void)
 	return -1;
 }
 
-void sbi_putc(char ch)
-{
-	if (console_dev && console_dev->console_putc) {
-		if (ch == '\n')
-			console_dev->console_putc('\r');
-		console_dev->console_putc(ch);
-	}
-}
-
 static unsigned long nputs(const char *str, unsigned long len)
 {
-	unsigned long i, ret;
+	unsigned long i;
 
-	if (console_dev && console_dev->console_puts) {
-		ret = console_dev->console_puts(str, len);
-	} else {
-		for (i = 0; i < len; i++)
-			sbi_putc(str[i]);
-		ret = len;
+	if (console_dev) {
+		if (console_dev->console_puts)
+			return console_dev->console_puts(str, len);
+		else if (console_dev->console_putc) {
+			for (i = 0; i < len; i++) {
+				if (str[i] == '\n')
+					console_dev->console_putc('\r');
+				console_dev->console_putc(str[i]);
+			}
+		}
 	}
-
-	return ret;
+	return len;
 }
 
 static void nputs_all(const char *str, unsigned long len)
@@ -69,6 +63,11 @@ static void nputs_all(const char *str, unsigned long len)
 		p += nputs(&str[p], len - p);
 }
 
+void sbi_putc(char ch)
+{
+	nputs_all(&ch, 1);
+}
+
 void sbi_puts(const char *str)
 {
 	unsigned long len = sbi_strlen(str);
-- 
2.42.0



From guoren at kernel.org  Tue Oct 24 23:51:47 2023
From: guoren at kernel.org (Guo Ren)
Date: Wed, 25 Oct 2023 14:51:47 +0800
Subject: [PATCH 2/2] lib: utils/serial: remove semihosting_putc
In-Reply-To: <20231025043104.748104-2-wxjstz@126.com>
References: <20231025043104.748104-1-wxjstz@126.com> <20231025043104.748104-2-wxjstz@126.com>
Message-ID: <CAJF2gTRLBhjkSOOg=uz=XapN6uv6DKPpwLHeM928Go3xpwc91g@mail.gmail.com>

On Wed, Oct 25, 2023 at 12:31?PM Xiang W <wxjstz at 126.com> wrote:
>
> For some debuggers that do not implement SYSWRITEC and SYSREADC
> operations, we can use SYSWRITE and SYSREAD instead like the
> implementation of semihosting_putc(). This makes
> semihosting_putc/semihosting_puts similar. Since
> console_putc/console_puts are now interchangeable, removing the
> semihosting_putc.
>
> Signed-off-by: Chen Pei <cp0613 at linux.alibaba.com>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
>  lib/utils/serial/semihosting.c | 6 ------
>  1 file changed, 6 deletions(-)
>
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index ce65887..19ebaa0 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -160,11 +160,6 @@ static long semihosting_write(long fd, const void *memp, size_t len)
>
>  /* clang-format on */
>
> -static void semihosting_putc(char ch)
> -{
> -       semihosting_trap(SYSWRITEC, &ch);
> -}
> -
>  static unsigned long semihosting_puts(const char *str, unsigned long len)
>  {
>         char ch;
> @@ -199,7 +194,6 @@ static int semihosting_getc(void)
>
>  static struct sbi_console_device semihosting_console = {
>         .name = "semihosting",
> -       .console_putc = semihosting_putc,
Reviewed-by: Guo Ren <guoren at kerenl.org>

>         .console_puts = semihosting_puts,
>         .console_getc = semihosting_getc
>  };
> --
> 2.42.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren


From guoren at kernel.org  Tue Oct 24 23:53:48 2023
From: guoren at kernel.org (Guo Ren)
Date: Wed, 25 Oct 2023 14:53:48 +0800
Subject: [PATCH 1/2] lib: sbi: Make console_puts/console_putc interchangeable
In-Reply-To: <20231025043104.748104-1-wxjstz@126.com>
References: <20231025043104.748104-1-wxjstz@126.com>
Message-ID: <CAJF2gTSKWVQA=qi=G8Lcd5jMvsmT=T28gQp5rKfjLMJ5vaAu1A@mail.gmail.com>

On Wed, Oct 25, 2023 at 12:32?PM Xiang W <wxjstz at 126.com> wrote:
>
> console_puts/console_putc should replace each other, but the previous
> sbi_putc can only use console_putc. This patch improves this problem.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
>  lib/sbi/sbi_console.c | 35 +++++++++++++++++------------------
>  1 file changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> index 2b3b0a3..ab09a5c 100644
> --- a/lib/sbi/sbi_console.c
> +++ b/lib/sbi/sbi_console.c
> @@ -37,28 +37,22 @@ int sbi_getc(void)
>         return -1;
>  }
>
> -void sbi_putc(char ch)
> -{
> -       if (console_dev && console_dev->console_putc) {
> -               if (ch == '\n')
> -                       console_dev->console_putc('\r');
> -               console_dev->console_putc(ch);
> -       }
> -}
> -
>  static unsigned long nputs(const char *str, unsigned long len)
>  {
> -       unsigned long i, ret;
> +       unsigned long i;
>
> -       if (console_dev && console_dev->console_puts) {
> -               ret = console_dev->console_puts(str, len);
> -       } else {
> -               for (i = 0; i < len; i++)
> -                       sbi_putc(str[i]);
> -               ret = len;
> +       if (console_dev) {
> +               if (console_dev->console_puts)
> +                       return console_dev->console_puts(str, len);
> +               else if (console_dev->console_putc) {
> +                       for (i = 0; i < len; i++) {
> +                               if (str[i] == '\n')
> +                                       console_dev->console_putc('\r');
> +                               console_dev->console_putc(str[i]);
> +                       }
> +               }
>         }
> -
> -       return ret;
> +       return len;
The return becomes meaningless, right?

>  }
>
>  static void nputs_all(const char *str, unsigned long len)
> @@ -69,6 +63,11 @@ static void nputs_all(const char *str, unsigned long len)
>                 p += nputs(&str[p], len - p);
>  }
>
> +void sbi_putc(char ch)
> +{
> +       nputs_all(&ch, 1);
> +}
> +
>  void sbi_puts(const char *str)
>  {
>         unsigned long len = sbi_strlen(str);
> --
> 2.42.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren


From wxjstz at 126.com  Wed Oct 25 00:28:52 2023
From: wxjstz at 126.com (Xiang W)
Date: Wed, 25 Oct 2023 15:28:52 +0800
Subject: [PATCH 1/2] lib: sbi: Make console_puts/console_putc
 interchangeable
In-Reply-To: <CAJF2gTSKWVQA=qi=G8Lcd5jMvsmT=T28gQp5rKfjLMJ5vaAu1A@mail.gmail.com>
References: <20231025043104.748104-1-wxjstz@126.com>
	 <CAJF2gTSKWVQA=qi=G8Lcd5jMvsmT=T28gQp5rKfjLMJ5vaAu1A@mail.gmail.com>
Message-ID: <0924c043e1c989cd813c4cc985510be8554662fa.camel@126.com>

? 2023-10-25???? 14:53 +0800?Guo Ren???
> On Wed, Oct 25, 2023 at 12:32?PM Xiang W <wxjstz at 126.com> wrote:
> > 
> > console_puts/console_putc should replace each other, but the previous
> > sbi_putc can only use console_putc. This patch improves this problem.
> > 
> > Signed-off-by: Xiang W <wxjstz at 126.com>
> > ---
> > ?lib/sbi/sbi_console.c | 35 +++++++++++++++++------------------
> > ?1 file changed, 17 insertions(+), 18 deletions(-)
> > 
> > diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> > index 2b3b0a3..ab09a5c 100644
> > --- a/lib/sbi/sbi_console.c
> > +++ b/lib/sbi/sbi_console.c
> > @@ -37,28 +37,22 @@ int sbi_getc(void)
> > ??????? return -1;
> > ?}
> > 
> > -void sbi_putc(char ch)
> > -{
> > -?????? if (console_dev && console_dev->console_putc) {
> > -?????????????? if (ch == '\n')
> > -?????????????????????? console_dev->console_putc('\r');
> > -?????????????? console_dev->console_putc(ch);
> > -?????? }
> > -}
> > -
> > ?static unsigned long nputs(const char *str, unsigned long len)
> > ?{
> > -?????? unsigned long i, ret;
> > +?????? unsigned long i;
> > 
> > -?????? if (console_dev && console_dev->console_puts) {
> > -?????????????? ret = console_dev->console_puts(str, len);
> > -?????? } else {
> > -?????????????? for (i = 0; i < len; i++)
> > -?????????????????????? sbi_putc(str[i]);
> > -?????????????? ret = len;
> > +?????? if (console_dev) {
> > +?????????????? if (console_dev->console_puts)
> > +?????????????????????? return console_dev->console_puts(str, len);
> > +?????????????? else if (console_dev->console_putc) {
> > +?????????????????????? for (i = 0; i < len; i++) {
> > +?????????????????????????????? if (str[i] == '\n')
> > +?????????????????????????????????????? console_dev->console_putc('\r');
> > +?????????????????????????????? console_dev->console_putc(str[i]);
> > +?????????????????????? }
> > +?????????????? }
> > ??????? }
> > -
> > -?????? return ret;
> > +?????? return len;
> The return becomes meaningless, right?
Even if console_dev is NULL, it cannot return 0, otherwise it will cause nputs_all
to fall into an infinite loop.

Regards,
Xiang W
> 
> > ?}
> > 
> > ?static void nputs_all(const char *str, unsigned long len)
> > @@ -69,6 +63,11 @@ static void nputs_all(const char *str, unsigned long len)
> > ??????????????? p += nputs(&str[p], len - p);
> > ?}
> > 
> > +void sbi_putc(char ch)
> > +{
> > +?????? nputs_all(&ch, 1);
> > +}
> > +
> > ?void sbi_puts(const char *str)
> > ?{
> > ??????? unsigned long len = sbi_strlen(str);
> > --
> > 2.42.0
> > 
> > 
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
> 
> 
> 


From guoren at kernel.org  Wed Oct 25 00:51:34 2023
From: guoren at kernel.org (Guo Ren)
Date: Wed, 25 Oct 2023 15:51:34 +0800
Subject: [PATCH 1/2] lib: sbi: Make console_puts/console_putc interchangeable
In-Reply-To: <0924c043e1c989cd813c4cc985510be8554662fa.camel@126.com>
References: <20231025043104.748104-1-wxjstz@126.com> <CAJF2gTSKWVQA=qi=G8Lcd5jMvsmT=T28gQp5rKfjLMJ5vaAu1A@mail.gmail.com>
 <0924c043e1c989cd813c4cc985510be8554662fa.camel@126.com>
Message-ID: <CAJF2gTTjEGFPdUdWGnW1wozPK8s3kxmAWRmY3-ZOy+SYsSe7xA@mail.gmail.com>

On Wed, Oct 25, 2023 at 3:29?PM Xiang W <wxjstz at 126.com> wrote:
>
> ? 2023-10-25???? 14:53 +0800?Guo Ren???
> > On Wed, Oct 25, 2023 at 12:32?PM Xiang W <wxjstz at 126.com> wrote:
> > >
> > > console_puts/console_putc should replace each other, but the previous
> > > sbi_putc can only use console_putc. This patch improves this problem.
> > >
> > > Signed-off-by: Xiang W <wxjstz at 126.com>
> > > ---
> > >  lib/sbi/sbi_console.c | 35 +++++++++++++++++------------------
> > >  1 file changed, 17 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> > > index 2b3b0a3..ab09a5c 100644
> > > --- a/lib/sbi/sbi_console.c
> > > +++ b/lib/sbi/sbi_console.c
> > > @@ -37,28 +37,22 @@ int sbi_getc(void)
> > >         return -1;
> > >  }
> > >
> > > -void sbi_putc(char ch)
> > > -{
> > > -       if (console_dev && console_dev->console_putc) {
> > > -               if (ch == '\n')
> > > -                       console_dev->console_putc('\r');
> > > -               console_dev->console_putc(ch);
> > > -       }
> > > -}
> > > -
> > >  static unsigned long nputs(const char *str, unsigned long len)
> > >  {
> > > -       unsigned long i, ret;
> > > +       unsigned long i;
> > >
> > > -       if (console_dev && console_dev->console_puts) {
> > > -               ret = console_dev->console_puts(str, len);
> > > -       } else {
> > > -               for (i = 0; i < len; i++)
> > > -                       sbi_putc(str[i]);
> > > -               ret = len;
> > > +       if (console_dev) {
> > > +               if (console_dev->console_puts)
> > > +                       return console_dev->console_puts(str, len);
> > > +               else if (console_dev->console_putc) {
> > > +                       for (i = 0; i < len; i++) {
> > > +                               if (str[i] == '\n')
> > > +                                       console_dev->console_putc('\r');
> > > +                               console_dev->console_putc(str[i]);
> > > +                       }
> > > +               }
> > >         }
> > > -
> > > -       return ret;
> > > +       return len;
> > The return becomes meaningless, right?
> Even if console_dev is NULL, it cannot return 0, otherwise it will cause nputs_all
> to fall into an infinite loop.
If console_dev is NULL, we assume all strings were sent out. Okay, I got it, so:

Reviewed-by: Guo Ren <guoren at kernel.org>

>
> Regards,
> Xiang W
> >
> > >  }
> > >
> > >  static void nputs_all(const char *str, unsigned long len)
> > > @@ -69,6 +63,11 @@ static void nputs_all(const char *str, unsigned long len)
> > >                 p += nputs(&str[p], len - p);
> > >  }
> > >
> > > +void sbi_putc(char ch)
> > > +{
> > > +       nputs_all(&ch, 1);
> > > +}
> > > +
> > >  void sbi_puts(const char *str)
> > >  {
> > >         unsigned long len = sbi_strlen(str);
> > > --
> > > 2.42.0
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
> >
> >
> >
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Best Regards
 Guo Ren


From heinrich.schuchardt at canonical.com  Sat Oct 28 15:31:37 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Sun, 29 Oct 2023 00:31:37 +0200
Subject: [PATCH 1/1] include: sbi: macros for mseccfg.sseed and .useed
Message-ID: <20231028223137.95007-1-heinrich.schuchardt@canonical.com>

Define macros to access the sseed and the useed bits in the machine
security configuration register (mseccfg). These are defined in the
Zkr ISA extension [1] to control access to the seed CSR.

[1] RISC-V Cryptography Extensions Volume I
    Scalar & Entropy Source Instructions
    Version v1.0.1, 18'th Feb, 2022: Ratified
    https://drive.google.com/file/d/1Thd010Eh2DqnhDHpDd3SM7Ame7KENkPw/view

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 include/sbi/riscv_encoding.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index a545242..0996d64 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -678,6 +678,10 @@
 #define MSECCFG_MMWP			(_UL(1) << MSECCFG_MMWP_SHIFT)
 #define MSECCFG_RLB_SHIFT		(2)
 #define MSECCFG_RLB			(_UL(1) << MSECCFG_RLB_SHIFT)
+#define MSECCFG_USEED_SHIFT		(8)
+#define MSECCFG_USEED			(_UL(1) << MSECCFG_USEED_SHIFT)
+#define MSECCFG_SSEED_SHIFT		(9)
+#define MSECCFG_SSEED			(_UL(1) << MSECCFG_SSEED_SHIFT)
 
 /* Counter Overflow CSR */
 #define CSR_SCOUNTOVF			0xda0
-- 
2.40.1



From heinrich.schuchardt at canonical.com  Sat Oct 28 15:49:56 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Sun, 29 Oct 2023 00:49:56 +0200
Subject: [RFC 0/3] Enable access to seed CSR in S-mode
Message-ID: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>

The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.

Machine mode has always access to the CSR, supervisor, and user mode
only if the corresponding bits sseed and useed are set in mseccfg.

With this series S-mode access to the seed register is enabled if the
Zkr extension is present. U-mode access is disabled.

QEMU 8.1.2 seems to have a bug:

The mseccfg register can only be accessed when setting cpu flag x-epmp=on.
The Privileged Architecture does not foresee this.

Heinrich Schuchardt (3):
  include: sbi: macros for mseccfg.sseed and .useed
  lib: sbi: Add Zkr in hart extensions
  lib: sbi: enable seed access in S-mode

 include/sbi/riscv_encoding.h |  4 ++++
 include/sbi/sbi_hart.h       |  2 ++
 lib/sbi/sbi_hart.c           | 15 +++++++++++++++
 lib/utils/fdt/fdt_helper.c   |  1 +
 4 files changed, 22 insertions(+)

-- 
2.40.1



From heinrich.schuchardt at canonical.com  Sat Oct 28 15:49:57 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Sun, 29 Oct 2023 00:49:57 +0200
Subject: [PATCH 1/3] include: sbi: macros for mseccfg.sseed and .useed
In-Reply-To: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
Message-ID: <20231028224959.95465-2-heinrich.schuchardt@canonical.com>

Define macros to access the sseed and the useed bit in the machine
security configuration register (mseccfg).

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
Just resending this patch which should be merged independent of how
we set mseccfg.sseed in future.
---
 include/sbi/riscv_encoding.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index a545242..0996d64 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -678,6 +678,10 @@
 #define MSECCFG_MMWP			(_UL(1) << MSECCFG_MMWP_SHIFT)
 #define MSECCFG_RLB_SHIFT		(2)
 #define MSECCFG_RLB			(_UL(1) << MSECCFG_RLB_SHIFT)
+#define MSECCFG_USEED_SHIFT		(8)
+#define MSECCFG_USEED			(_UL(1) << MSECCFG_USEED_SHIFT)
+#define MSECCFG_SSEED_SHIFT		(9)
+#define MSECCFG_SSEED			(_UL(1) << MSECCFG_SSEED_SHIFT)
 
 /* Counter Overflow CSR */
 #define CSR_SCOUNTOVF			0xda0
-- 
2.40.1



From heinrich.schuchardt at canonical.com  Sat Oct 28 15:49:59 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Sun, 29 Oct 2023 00:49:59 +0200
Subject: [RFC 3/3] lib: sbi: enable seed access in S-mode
In-Reply-To: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
Message-ID: <20231028224959.95465-4-heinrich.schuchardt@canonical.com>

If ISA extension Zkr is available, set

    mseccfg.sseed=1
    mseccfg.useed=0

This enables access to the seed CSR in S-mode but not in U-mode.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/sbi/sbi_hart.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 569596f..5a3e8ee 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -530,6 +530,15 @@ int sbi_hart_unmap_saddr(void)
 	return pmp_disable(SBI_SMEPMP_RESV_ENTRY);
 }
 
+static void sbi_hart_zkr_configure(struct sbi_scratch *scratch)
+{
+	unsigned long mseccfg_val = csr_read(CSR_MSECCFG);
+
+	mseccfg_val |= MSECCFG_SSEED;
+	mseccfg_val &= ~MSECCFG_USEED;
+	csr_set(CSR_MSECCFG, mseccfg_val);
+}
+
 int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 {
 	int rc;
@@ -551,6 +560,9 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 		rc = sbi_hart_oldpmp_configure(scratch, pmp_count,
 						pmp_gran_log2, pmp_addr_max);
 
+	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZKR))
+		sbi_hart_zkr_configure(scratch);
+
 	/*
 	 * As per section 3.7.2 of privileged specification v1.12,
 	 * virtual address translations can be speculatively performed
-- 
2.40.1



From heinrich.schuchardt at canonical.com  Sat Oct 28 15:49:58 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Sun, 29 Oct 2023 00:49:58 +0200
Subject: [RFC 2/3] lib: sbi: Add Zkr in hart extensions
In-Reply-To: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
Message-ID: <20231028224959.95465-3-heinrich.schuchardt@canonical.com>

- Add Zkr as extension in sbi_hart_extensions enum
- Return "zkr" string for Zkr extension from sbi_hart_extension_id2string

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 include/sbi/sbi_hart.h     | 2 ++
 lib/sbi/sbi_hart.c         | 3 +++
 lib/utils/fdt/fdt_helper.c | 1 +
 3 files changed, 6 insertions(+)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index e60f415..fe1124a 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -40,6 +40,8 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_ZICNTR,
 	/** HART has Zihpm extension */
 	SBI_HART_EXT_ZIHPM,
+	/** HART has Zkr extension */
+	SBI_HART_EXT_ZKR,
 	/** Hart has Smcntrpmf extension */
 	SBI_HART_EXT_SMCNTRPMF,
 
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 29d6481..569596f 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -678,6 +678,9 @@ static inline char *sbi_hart_extension_id2string(int ext)
 	case SBI_HART_EXT_ZIHPM:
 		estr = "zihpm";
 		break;
+	case SBI_HART_EXT_ZKR:
+		estr = "zkr";
+		break;
 	case SBI_HART_EXT_SMEPMP:
 		estr = "smepmp";
 		break;
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 9ae7f09..35be7ba 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -376,6 +376,7 @@ static int fdt_parse_isa_one_hart(const char *isa, unsigned long *extensions)
 			}
 
 		set_multi_letter_ext("smepmp", SBI_HART_EXT_SMEPMP);
+		set_multi_letter_ext("zkr", SBI_HART_EXT_ZKR);
 #undef set_multi_letter_ext
 	}
 
-- 
2.40.1



From wxjstz at 126.com  Sun Oct 29 09:14:15 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 30 Oct 2023 00:14:15 +0800
Subject: [RFC 2/3] lib: sbi: Add Zkr in hart extensions
In-Reply-To: <20231028224959.95465-3-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
	 <20231028224959.95465-3-heinrich.schuchardt@canonical.com>
Message-ID: <5b98888723820a1dff2a6cc3f92d1a48b9411561.camel@126.com>

? 2023-10-29???? 00:49 +0200?Heinrich Schuchardt???
> - Add Zkr as extension in sbi_hart_extensions enum
> - Return "zkr" string for Zkr extension from sbi_hart_extension_id2string
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> ?include/sbi/sbi_hart.h???? | 2 ++
> ?lib/sbi/sbi_hart.c???????? | 3 +++
> ?lib/utils/fdt/fdt_helper.c | 1 +
> ?3 files changed, 6 insertions(+)
> 
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index e60f415..fe1124a 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -40,6 +40,8 @@ enum sbi_hart_extensions {
> ?	SBI_HART_EXT_ZICNTR,
> ?	/** HART has Zihpm extension */
> ?	SBI_HART_EXT_ZIHPM,
> +	/** HART has Zkr extension */
> +	SBI_HART_EXT_ZKR,
> ?	/** Hart has Smcntrpmf extension */
> ?	SBI_HART_EXT_SMCNTRPMF,
> ?
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 29d6481..569596f 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -678,6 +678,9 @@ static inline char *sbi_hart_extension_id2string(int ext)
> ?	case SBI_HART_EXT_ZIHPM:
> ?		estr = "zihpm";
> ?		break;
> +	case SBI_HART_EXT_ZKR:
> +		estr = "zkr";
> +		break;
> ?	case SBI_HART_EXT_SMEPMP:
> ?		estr = "smepmp";
> ?		break;
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 9ae7f09..35be7ba 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -376,6 +376,7 @@ static int fdt_parse_isa_one_hart(const char *isa, unsigned long *extensions)
> ?			}
> ?
> ?		set_multi_letter_ext("smepmp", SBI_HART_EXT_SMEPMP);
> +		set_multi_letter_ext("zkr", SBI_HART_EXT_ZKR);
Look good to me.

But! This patch will conflict with
https://lists.infradead.org/pipermail/opensbi/2023-October/005770.html

Regards,
Xiang W
> ?#undef set_multi_letter_ext
> ?	}
> ?
> -- 
> 2.40.1
> 
> 



From wxjstz at 126.com  Sun Oct 29 09:38:00 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 30 Oct 2023 00:38:00 +0800
Subject: [RFC 3/3] lib: sbi: enable seed access in S-mode
In-Reply-To: <20231028224959.95465-4-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
	 <20231028224959.95465-4-heinrich.schuchardt@canonical.com>
Message-ID: <b9d5f65a06781a77f0a6deb04b5539fd5b456d4d.camel@126.com>

? 2023-10-29???? 00:49 +0200?Heinrich Schuchardt???
> If ISA extension Zkr is available, set
> 
> ??? mseccfg.sseed=1
> ??? mseccfg.useed=0
> 
> This enables access to the seed CSR in S-mode but not in U-mode.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> ?lib/sbi/sbi_hart.c | 12 ++++++++++++
> ?1 file changed, 12 insertions(+)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 569596f..5a3e8ee 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -530,6 +530,15 @@ int sbi_hart_unmap_saddr(void)
> ?	return pmp_disable(SBI_SMEPMP_RESV_ENTRY);
> ?}
> ?
> +static void sbi_hart_zkr_configure(struct sbi_scratch *scratch)
> +{
> +	unsigned long mseccfg_val = csr_read(CSR_MSECCFG);
> +
> +	mseccfg_val |= MSECCFG_SSEED;
> +	mseccfg_val &= ~MSECCFG_USEED;
> +	csr_set(CSR_MSECCFG, mseccfg_val);
> +}
> +
> ?int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
> ?{
> ?	int rc;
> @@ -551,6 +560,9 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
> ?		rc = sbi_hart_oldpmp_configure(scratch, pmp_count,
> ?						pmp_gran_log2, pmp_addr_max);
> ?
> +	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZKR))
> +		sbi_hart_zkr_configure(scratch);
> +
What is the relationship between zkr and pmp? Maybe it's better to move 
into sbi_hart_reinit.

Regards,
Xiang W
> ?	/*
> ?	 * As per section 3.7.2 of privileged specification v1.12,
> ?	 * virtual address translations can be speculatively performed
> -- 
> 2.40.1
> 
> 



From wxjstz at 126.com  Sun Oct 29 09:42:02 2023
From: wxjstz at 126.com (Xiang W)
Date: Mon, 30 Oct 2023 00:42:02 +0800
Subject: [PATCH 1/3] include: sbi: macros for mseccfg.sseed and .useed
In-Reply-To: <20231028224959.95465-2-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
	 <20231028224959.95465-2-heinrich.schuchardt@canonical.com>
Message-ID: <77c58a70e31ee9a40e202f1958344481e7b94651.camel@126.com>

? 2023-10-29???? 00:49 +0200?Heinrich Schuchardt???
> Define macros to access the sseed and the useed bit in the machine
> security configuration register (mseccfg).
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> Just resending this patch which should be merged independent of how
> we set mseccfg.sseed in future.
> ---
> ?include/sbi/riscv_encoding.h | 4 ++++
> ?1 file changed, 4 insertions(+)
> 
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index a545242..0996d64 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -678,6 +678,10 @@
> ?#define MSECCFG_MMWP			(_UL(1) << MSECCFG_MMWP_SHIFT)
> ?#define MSECCFG_RLB_SHIFT		(2)
> ?#define MSECCFG_RLB			(_UL(1) << MSECCFG_RLB_SHIFT)
> +#define MSECCFG_USEED_SHIFT		(8)
> +#define MSECCFG_USEED			(_UL(1) << MSECCFG_USEED_SHIFT)
> +#define MSECCFG_SSEED_SHIFT		(9)
> +#define MSECCFG_SSEED			(_UL(1) << MSECCFG_SSEED_SHIFT)
> ?
> ?/* Counter Overflow CSR */
> ?#define CSR_SCOUNTOVF			0xda0
> -- 
> 2.40.1
> 
> 



From wxjstz at 126.com  Mon Oct 30 09:39:40 2023
From: wxjstz at 126.com (Xiang W)
Date: Tue, 31 Oct 2023 00:39:40 +0800
Subject: [PATCH] lib: sbi: change sbi_hart_features.extensions as an array
Message-ID: <20231030164046.25108-1-wxjstz@126.com>

In the future there may be a lot of ISA extensions, a 'long' may not
be able to accommodate, changed to an array for the future.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_hart.h      |  3 ++-
 lib/sbi/sbi_hart.c          | 32 ++++++++++++--------------------
 platform/generic/platform.c |  2 +-
 3 files changed, 15 insertions(+), 22 deletions(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index e60f415..3b73f63 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -11,6 +11,7 @@
 #define __SBI_HART_H__
 
 #include <sbi/sbi_types.h>
+#include <sbi/sbi_bitops.h>
 
 /** Possible privileged specification versions of a hart */
 enum sbi_hart_priv_versions {
@@ -65,7 +66,7 @@ enum sbi_hart_extensions {
 struct sbi_hart_features {
 	bool detected;
 	int priv_version;
-	unsigned long extensions;
+	unsigned long extensions[BITS_TO_LONGS(SBI_HART_EXT_MAX)];
 	unsigned int pmp_count;
 	unsigned int pmp_addr_bits;
 	unsigned long pmp_gran;
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 29d6481..f94eba5 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -614,9 +614,9 @@ static inline void __sbi_hart_update_extension(
 					bool enable)
 {
 	if (enable)
-		hfeatures->extensions |= BIT(ext);
+		__set_bit(ext, hfeatures->extensions);
 	else
-		hfeatures->extensions &= ~BIT(ext);
+		__clear_bit(ext, hfeatures->extensions);
 }
 
 /**
@@ -649,7 +649,7 @@ bool sbi_hart_has_extension(struct sbi_scratch *scratch,
 	struct sbi_hart_features *hfeatures =
 			sbi_scratch_offset_ptr(scratch, hart_features_offset);
 
-	if (hfeatures->extensions & BIT(ext))
+	if (__test_bit(ext, hfeatures->extensions))
 		return true;
 	else
 		return false;
@@ -712,24 +712,16 @@ void sbi_hart_get_extensions_str(struct sbi_scratch *scratch,
 		return;
 	sbi_memset(extensions_str, 0, nestr);
 
-	if (!hfeatures->extensions)
-		goto done;
-
-	do {
-		if (hfeatures->extensions & BIT(ext)) {
-			temp = sbi_hart_extension_id2string(ext);
-			if (temp) {
-				sbi_snprintf(extensions_str + offset,
-					     nestr - offset,
-					     "%s,", temp);
-				offset = offset + sbi_strlen(temp) + 1;
-			}
+	for_each_set_bit(ext, hfeatures->extensions, SBI_HART_EXT_MAX) {
+		temp = sbi_hart_extension_id2string(ext);
+		if (temp) {
+			sbi_snprintf(extensions_str + offset,
+				     nestr - offset,
+				     "%s,", temp);
+			offset = offset + sbi_strlen(temp) + 1;
 		}
+	}
 
-		ext++;
-	} while (ext < SBI_HART_EXT_MAX);
-
-done:
 	if (offset)
 		extensions_str[offset - 1] = '\0';
 	else
@@ -799,7 +791,7 @@ static int hart_detect_features(struct sbi_scratch *scratch)
 		return 0;
 
 	/* Clear hart features */
-	hfeatures->extensions = 0;
+	sbi_memset(hfeatures->extensions, 0, sizeof(hfeatures->extensions));
 	hfeatures->pmp_count = 0;
 	hfeatures->mhpm_mask = 0;
 
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..9182faa 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -215,7 +215,7 @@ static int generic_extensions_init(struct sbi_hart_features *hfeatures)
 
 	/* Parse the ISA string from FDT and enable the listed extensions */
 	rc = fdt_parse_isa_extensions(fdt_get_address(), current_hartid(),
-				      &hfeatures->extensions);
+				      hfeatures->extensions);
 
 	if (rc)
 		return rc;
-- 
2.42.0



From heinrich.schuchardt at canonical.com  Mon Oct 30 09:41:52 2023
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 30 Oct 2023 18:41:52 +0200
Subject: [RFC 3/3] lib: sbi: enable seed access in S-mode
In-Reply-To: <20231028224959.95465-4-heinrich.schuchardt@canonical.com>
References: <20231028224959.95465-1-heinrich.schuchardt@canonical.com>
 <20231028224959.95465-4-heinrich.schuchardt@canonical.com>
Message-ID: <7d9bfb00-1f61-433a-a558-bd8f4e77399b@canonical.com>

On 10/29/23 01:49, Heinrich Schuchardt wrote:
> If ISA extension Zkr is available, set
> 
>      mseccfg.sseed=1
>      mseccfg.useed=0
> 
> This enables access to the seed CSR in S-mode but not in U-mode.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Anup pointed me to a previous patch:

lib: sbi: Configure seed bits when MSECCFG is readable
https://patchwork.ozlabs.org/project/opensbi/patch/20230712083254.1585244-1-sameo at rivosinc.com/

Best regards

Heinrich


