[PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines

[Atish Patra]

On Tue, Nov 21, 2023 at 11:40 PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> This patch adds CSR for Andes PMU extension.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> ---
> Changes v1 -> v2:
>   - Rename andes_pmu() -> has_andes_pmu()
> Changes v2 -> v3:
>   - Include Anup's RB tag
> ---
>  platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index f570994..ce31617 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -12,6 +12,17 @@
>  #define CSR_MDCM_CFG           0xfc1
>  #define CSR_MMSC_CFG           0xfc2
>
> +/* Machine Trap Related Registers */
> +#define CSR_MSLIDELEG          0x7d5
> +
> +/* Counter Related Registers */
> +#define CSR_MCOUNTERWEN                0x7ce
> +#define CSR_MCOUNTERINTEN      0x7cf
> +#define CSR_MCOUNTERMASK_M     0x7d1
> +#define CSR_MCOUNTERMASK_S     0x7d2
> +#define CSR_MCOUNTERMASK_U     0x7d3
> +#define CSR_MCOUNTEROVF                0x7d4
> +
>  #define MICM_CFG_ISZ_OFFSET            6
>  #define MICM_CFG_ISZ_MASK              (0x7  << MICM_CFG_ISZ_OFFSET)
>
> @@ -26,4 +37,19 @@
>  #define MCACHE_CTL_CCTL_SUEN_OFFSET    8
>  #define MCACHE_CTL_CCTL_SUEN_MASK      (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
>
> +/* Performance monitor */
> +#define MMSC_CFG_PMNDS_MASK            (1 << 15)
> +#define MIP_PMOVI                      (1 << 18)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define has_andes_pmu()                                        \
> +({                                                     \
> +       (((csr_read(CSR_MMSC_CFG) &                     \
> +          MMSC_CFG_PMNDS_MASK)                         \
> +         && misa_extension('S')) ? true : false);      \
> +})
> +
> +#endif /* __ASSEMBLER__ */
> +
>  #endif /* _RISCV_ANDES45_H */
> --
> 2.34.1
>


Reviewed-by: Atish Patra <atishp at rivosinc.com>
-- 
Regards,
Atish