[PATCH v7] platform: generic: renesas: rzfive: Add SBI EXT to check for enabling IOCP errata

[Conor Dooley]

On Fri, Mar 17, 2023 at 02:03:57PM +0000, Lad Prabhakar wrote:
> I/O Coherence Port (IOCP) provides an AXI interface for connecting
> external non-caching masters, such as DMA controllers. The accesses
> from IOCP are coherent with D-Caches and L2 Cache.
> 
> IOCP is a specification option and is disabled on the Renesas RZ/Five
> SoC due to this reason IP blocks using DMA will fail.
> 
> As a workaround for SoCs with IOCP disabled CMO needs to be handled by
> software. Firstly OpenSBI configures the memory region as
> "Memory, Non-cacheable, Bufferable" and passes this region as a global
> shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
> allocations happen from this region and synchronization callbacks are
> implemented to synchronize when doing DMA transactions.
> 
> SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be
> applied to handle cache management.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>

> +static bool andes45_cache_controlable(void)

FWIW, controllable has 3 Ls

I'm not really au fait with this neck of the woods, but what you're
doing makes sense to me..
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Thanks,
Conor.

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