[PATCH v2 1/2] docs: pmu: fix Unmatched example typo

[Anup Patel]

On Fri, Sep 2, 2022 at 1:11 PM Nikita Shubin <nikita.shubin at maquefel.me> wrote:
>
> From: Nikita Shubin <n.shubin at yadro.com>
>
> bitmap for MHPMCOUNTERx should be 0x18 and not 0x0c, we check
> against SBI_PMU_FIXED_CTR_MASK which assumes than first 3 bits are
> dedicated to mcycle, mtime and minstret, u74 has 2 hardware counters.
>
> Reported-by: Zhang Xin <zhangxin.xa at gmail.com>
> Signed-off-by: Nikita Shubin <n.shubin at yadro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> v1->v2:
> - replaced email
> ---
>  docs/pmu_support.md | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 8751bb5..ca6ca25 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -93,8 +93,8 @@ pmu {
>   */
>  pmu {
>         compatible                      = "riscv,pmu";
> -       riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0xc>,
> -                                         <0x0 0x1 0xffffffff 0xfff800ff 0xc>,
> -                                         <0x0 0x2 0xffffffff 0xffffe0ff 0xc>;
> +       riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
> +                                         <0x0 0x1 0xffffffff 0xfff800ff 0x18>,
> +                                         <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
>  };
>  ```
> --
> 2.35.1
>