From geomatsi at gmail.com  Tue Nov  1 02:39:06 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Tue, 1 Nov 2022 12:39:06 +0300
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <CAEUhbmWDqCtb9ZifTTq2yPR=H_5a70msprvcWAyU3QKDLdMS2w@mail.gmail.com>
References: <20221031211859.910439-1-geomatsi@gmail.com>
 <CAEUhbmWDqCtb9ZifTTq2yPR=H_5a70msprvcWAyU3QKDLdMS2w@mail.gmail.com>
Message-ID: <Y2DpOqSS+5eJOtrJ@curiosity>

Hi Bin and all,

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> >
> > Software support for RISC-V hardware triggers consists of the
> > following major components:
> > - U-mode: gdb support for setting hw breakpoints/watchpoints
> > - S/VS-mode: hardware breakpoints framework in Linux kernel
> 
> Do you have WIP patches for gdb and Linux kernel?

Linux RFC patch has been posted for review to linux-riscv mailing list:
https://lore.kernel.org/linux-riscv/20221031213225.912258-1-geomatsi at gmail.com/T/#u

GDB support is a work in progress at the moment. Patches have not yet
been posted.

> > - M-mode: SBI firmware code to handle triggers
> >
> > SBI Debug Trigger extension proposal (draft v4) has been posted
> > by Anup Patel to lists.riscv.org tech-debug mailing list:
> >
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> 
> I believe this patch won't be merged until the SBI spec has been ratified?

I think so. Besides, RISC-V Debug Support specificaton v1.0.0 has not yet
been ratified as well. So both Debug Support spec and SBI Debug Trigger
extension need to be ratified before the support for hardware breakpoints
can be merged into Linux and OpenSBI.

> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> >
> > Initial implementation has the following limitations:
> > - only mcontrol6 trigger type is supported
> 
> I would suggest add type 2 trigger support too, since it's the one
> that SiFive FU540/740 supports.

Agree. RISC-V Debug spec v1.0.0 recommends to use type 6 trigger in
newer implementations. But if this type is not supported, we should
be able to fall back to type 2 triggers.

> > - no support for chained triggers
> > - trigger update supports only address change
> >
> > Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> > ---
> >  include/sbi/riscv_dbtr.h          |  78 ++++++
> >  include/sbi/riscv_encoding.h      |   1 +
> >  include/sbi/sbi_dbtr.h            |  79 ++++++
> >  include/sbi/sbi_ecall_interface.h |  10 +
> >  lib/sbi/Kconfig                   |   4 +
> >  lib/sbi/objects.mk                |   3 +
> >  lib/sbi/sbi_dbtr.c                | 404 ++++++++++++++++++++++++++++++
> >  lib/sbi/sbi_ecall_dbtr.c          |  68 +++++
> >  lib/sbi/sbi_init.c                |   9 +
> >  9 files changed, 656 insertions(+)
> >  create mode 100644 include/sbi/riscv_dbtr.h
> >  create mode 100644 include/sbi/sbi_dbtr.h
> >  create mode 100644 lib/sbi/sbi_dbtr.c
> >  create mode 100644 lib/sbi/sbi_ecall_dbtr.c
> >
> 
> Regards,
> Bin

Regards,
Sergey


From geomatsi at gmail.com  Tue Nov  1 03:20:29 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Tue, 1 Nov 2022 13:20:29 +0300
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <6aaa58fd3e049b77a3caee7c3a016412a8e54ee8.camel@126.com>
References: <20221031211859.910439-1-geomatsi@gmail.com>
 <6aaa58fd3e049b77a3caee7c3a016412a8e54ee8.camel@126.com>
Message-ID: <Y2Dy7Y4hsrb+LcPH@curiosity>


Hi Xiang W and all,

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> > 
> > Software support for RISC-V hardware triggers consists of the
> > following major components:
> > - U-mode: gdb support for setting hw breakpoints/watchpoints
> > - S/VS-mode: hardware breakpoints framework in Linux kernel
> > - M-mode: SBI firmware code to handle triggers
> > 
> > SBI Debug Trigger extension proposal (draft v4) has been posted
> > by Anup Patel to lists.riscv.org tech-debug mailing list:
> > 
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> > 
> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> > 
> > Initial implementation has the following limitations:
> > - only mcontrol6 trigger type is supported
> > - no support for chained triggers
> > - trigger update supports only address change

...

> > +int sbi_dbtr_num_trig(unsigned long data, unsigned long *out)
> > +{
> > +???????unsigned long type = ((union riscv_dbtr_tdata1)data).type;
> 
> chain need to be care. If chain=1, we need to find the number of
> consecutive pairs of trigger.

There can be more than two triggers in chained configuration.
So I would suggest to check the availability of suitable
consecutive triggers in sbi_dbtr_install_trig handler.

> > +???????u32 hartid = current_hartid();
> > +???????unsigned long total = 0;
> > +???????int i;
> > +
> > +
> > +???????if (data == 0) {
> > +???????????????sbi_dprintf("%s: hart%d: total triggers: %u\n",
> > +?????????????????????????? __func__, hartid, total_trigs);
> > +???????????????*out = total_trigs;
> > +???????????????return SBI_SUCCESS;
> > +???????}
> > +
> > +???????for (i = 0; i < total_trigs; i++) {
 
> If only RISCV_DBTR_TRIG_MCONTROL6 is supported, do we need to find other
> types of triggers?

The idea is to add support for more types, e.g. icount and mcontrol.

> > +???????/* Check requested triggers configuration */
> > +???????for (k = 0; k < trig_count; k++) {
> > +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> > +???????????????ctrl = (union riscv_dbtr_tdata1_mcontrol6)recv->tdata1;
> > +
> > +???????????????if (ctrl.type != RISCV_DBTR_TRIG_MCONTROL6) {
> 
> why not support RISCV_DBTR_TRIG_MCONTROL?

Well, new debug spec recommends to use mcontrol6. But, as it was pointed
out in other review comments, there exists hardware which supports
mcontrol but not mcontrol6. So we have to be able to fall-back to using
mcontrol when needed.

Regards,
Sergey


From geomatsi at gmail.com  Tue Nov  1 03:55:44 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Tue, 1 Nov 2022 13:55:44 +0300
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <E994763E-172E-4C90-AA97-0F8F899ADF55@jrtc27.com>
References: <20221031211859.910439-1-geomatsi@gmail.com>
 <E994763E-172E-4C90-AA97-0F8F899ADF55@jrtc27.com>
Message-ID: <Y2D7MMfuqDGC3e0X@curiosity>

Hi Jessica and all,

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> > 
> > Software support for RISC-V hardware triggers consists of the
> > following major components:
> > - U-mode: gdb support for setting hw breakpoints/watchpoints
> > - S/VS-mode: hardware breakpoints framework in Linux kernel
> > - M-mode: SBI firmware code to handle triggers
> > 
> > SBI Debug Trigger extension proposal (draft v4) has been posted
> > by Anup Patel to lists.riscv.org tech-debug mailing list:
> > 
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> > 
> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> > 
> > Initial implementation has the following limitations:
> > - only mcontrol6 trigger type is supported
> > - no support for chained triggers
> > - trigger update supports only address change

...

> > +union riscv_dbtr_tdata1 {
> > +	unsigned long value;
> > +	struct {
> > +#if __riscv_xlen == 64
> > +		unsigned long data:59;
> > +#elif __riscv_xlen == 32
> > +		unsigned long data:27;
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif
> > +		unsigned long dmode:1;
> > +		unsigned long type:4;
> > +	};
> > +};
> 
> Bitfield order depends on endianness (type is in the MSBs for
> little-endian but LSBs for big-endian).

Do we need to support non-standard BE cases as well ? If so, then
accessing fields in shared memory messages between OpenSBI and kernel
will have to be wrapped by cpu_to_le/le_to_cpu macros on both sides.

> > +/** SBI shared mem messages layout */
> > +struct sbi_dbtr_data_msg {
> > +	unsigned long tstate;
> > +	unsigned long tdata1;
> > +	unsigned long tdata2;
> > +	unsigned long tdata3;
> > +} __packed;
> 
> Why? This will give awful codegen.

Both packed structures define messages for data exchange via shared
memory between OpenSBI and kernel. We have to make sure that these
structures have the same layout on both sides.
 
Regards,
Sergey


From anup at brainfault.org  Tue Nov  1 04:01:33 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 1 Nov 2022 16:31:33 +0530
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <Y2D7MMfuqDGC3e0X@curiosity>
References: <20221031211859.910439-1-geomatsi@gmail.com> <E994763E-172E-4C90-AA97-0F8F899ADF55@jrtc27.com>
 <Y2D7MMfuqDGC3e0X@curiosity>
Message-ID: <CAAhSdy3SUVook-K4xMdh7R_dGRF0teo0BThYMreEPMJYHuBWMg@mail.gmail.com>

On Tue, Nov 1, 2022 at 4:25 PM Sergey Matyukevich <geomatsi at gmail.com> wrote:
>
> Hi Jessica and all,
>
> > > RISC-V Debug specification includes Sdtrig ISA extension.
> > > This extension describes Trigger Module. Triggers can cause
> > > a breakpoint exception, entry into Debug Mode, or a trace
> > > action without having to execute a special instruction. For
> > > native debugging triggers can be used to implement hardware
> > > breakpoints and watchpoints.
> > >
> > > Software support for RISC-V hardware triggers consists of the
> > > following major components:
> > > - U-mode: gdb support for setting hw breakpoints/watchpoints
> > > - S/VS-mode: hardware breakpoints framework in Linux kernel
> > > - M-mode: SBI firmware code to handle triggers
> > >
> > > SBI Debug Trigger extension proposal (draft v4) has been posted
> > > by Anup Patel to lists.riscv.org tech-debug mailing list:
> > >
> > > https://lists.riscv.org/g/tech-debug/topic/92375492
> > >
> > > This patch provides initial implementation of SBI Debug
> > > Trigger Extension in OpenSBI library based on the
> > > suggested extension proposal.
> > >
> > > Initial implementation has the following limitations:
> > > - only mcontrol6 trigger type is supported
> > > - no support for chained triggers
> > > - trigger update supports only address change
>
> ...
>
> > > +union riscv_dbtr_tdata1 {
> > > +   unsigned long value;
> > > +   struct {
> > > +#if __riscv_xlen == 64
> > > +           unsigned long data:59;
> > > +#elif __riscv_xlen == 32
> > > +           unsigned long data:27;
> > > +#else
> > > +#error "Unexpected __riscv_xlen"
> > > +#endif
> > > +           unsigned long dmode:1;
> > > +           unsigned long type:4;
> > > +   };
> > > +};
> >
> > Bitfield order depends on endianness (type is in the MSBs for
> > little-endian but LSBs for big-endian).
>
> Do we need to support non-standard BE cases as well ? If so, then
> accessing fields in shared memory messages between OpenSBI and kernel
> will have to be wrapped by cpu_to_le/le_to_cpu macros on both sides.

Yes, in the long term we might support BE in both Linux and OpenSBI
so better to avoid bitfield for data structures in shared memory.

>
> > > +/** SBI shared mem messages layout */
> > > +struct sbi_dbtr_data_msg {
> > > +   unsigned long tstate;
> > > +   unsigned long tdata1;
> > > +   unsigned long tdata2;
> > > +   unsigned long tdata3;
> > > +} __packed;
> >
> > Why? This will give awful codegen.
>
> Both packed structures define messages for data exchange via shared
> memory between OpenSBI and kernel. We have to make sure that these
> structures have the same layout on both sides.
>
> Regards,
> Sergey

Regards,
Anup


From jrtc27 at jrtc27.com  Tue Nov  1 08:32:21 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Tue, 1 Nov 2022 15:32:21 +0000
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <Y2D7MMfuqDGC3e0X@curiosity>
References: <20221031211859.910439-1-geomatsi@gmail.com>
 <E994763E-172E-4C90-AA97-0F8F899ADF55@jrtc27.com>
 <Y2D7MMfuqDGC3e0X@curiosity>
Message-ID: <8C149CB6-B872-4AF8-A953-1CEA64E15688@jrtc27.com>

On 1 Nov 2022, at 10:55, Sergey Matyukevich <geomatsi at gmail.com> wrote:
> 
> Hi Jessica and all,
> 
>>> RISC-V Debug specification includes Sdtrig ISA extension.
>>> This extension describes Trigger Module. Triggers can cause
>>> a breakpoint exception, entry into Debug Mode, or a trace
>>> action without having to execute a special instruction. For
>>> native debugging triggers can be used to implement hardware
>>> breakpoints and watchpoints.
>>> 
>>> Software support for RISC-V hardware triggers consists of the
>>> following major components:
>>> - U-mode: gdb support for setting hw breakpoints/watchpoints
>>> - S/VS-mode: hardware breakpoints framework in Linux kernel
>>> - M-mode: SBI firmware code to handle triggers
>>> 
>>> SBI Debug Trigger extension proposal (draft v4) has been posted
>>> by Anup Patel to lists.riscv.org tech-debug mailing list:
>>> 
>>> https://lists.riscv.org/g/tech-debug/topic/92375492
>>> 
>>> This patch provides initial implementation of SBI Debug
>>> Trigger Extension in OpenSBI library based on the
>>> suggested extension proposal.
>>> 
>>> Initial implementation has the following limitations:
>>> - only mcontrol6 trigger type is supported
>>> - no support for chained triggers
>>> - trigger update supports only address change
> 
> ...
> 
>>> +union riscv_dbtr_tdata1 {
>>> +	unsigned long value;
>>> +	struct {
>>> +#if __riscv_xlen == 64
>>> +		unsigned long data:59;
>>> +#elif __riscv_xlen == 32
>>> +		unsigned long data:27;
>>> +#else
>>> +#error "Unexpected __riscv_xlen"
>>> +#endif
>>> +		unsigned long dmode:1;
>>> +		unsigned long type:4;
>>> +	};
>>> +};
>> 
>> Bitfield order depends on endianness (type is in the MSBs for
>> little-endian but LSBs for big-endian).
> 
> Do we need to support non-standard BE cases as well ? If so, then
> accessing fields in shared memory messages between OpenSBI and kernel
> will have to be wrapped by cpu_to_le/le_to_cpu macros on both sides.
> 
>>> +/** SBI shared mem messages layout */
>>> +struct sbi_dbtr_data_msg {
>>> +	unsigned long tstate;
>>> +	unsigned long tdata1;
>>> +	unsigned long tdata2;
>>> +	unsigned long tdata3;
>>> +} __packed;
>> 
>> Why? This will give awful codegen.
> 
> Both packed structures define messages for data exchange via shared
> memory between OpenSBI and kernel. We have to make sure that these
> structures have the same layout on both sides.

You don?t need packed for that, just like you don?t need to pack every
struct passed to a kernel from userspace. We have a well-defined ABI
that guarantees there will not be any padding in that struct, and I
don?t know of any ABI in the world that would.

Jess



From geomatsi at gmail.com  Tue Nov  1 09:25:05 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Tue, 1 Nov 2022 19:25:05 +0300
Subject: [PATCH RFC v1 1/1] lib: sbi: add support for debug triggers
In-Reply-To: <CAAhSdy3SUVook-K4xMdh7R_dGRF0teo0BThYMreEPMJYHuBWMg@mail.gmail.com>
References: <20221031211859.910439-1-geomatsi@gmail.com>
 <E994763E-172E-4C90-AA97-0F8F899ADF55@jrtc27.com>
 <Y2D7MMfuqDGC3e0X@curiosity>
 <CAAhSdy3SUVook-K4xMdh7R_dGRF0teo0BThYMreEPMJYHuBWMg@mail.gmail.com>
Message-ID: <Y2FIYXGkrWtPIzQm@curiosity>

> > > > RISC-V Debug specification includes Sdtrig ISA extension.
> > > > This extension describes Trigger Module. Triggers can cause
> > > > a breakpoint exception, entry into Debug Mode, or a trace
> > > > action without having to execute a special instruction. For
> > > > native debugging triggers can be used to implement hardware
> > > > breakpoints and watchpoints.
> > > >
> > > > Software support for RISC-V hardware triggers consists of the
> > > > following major components:
> > > > - U-mode: gdb support for setting hw breakpoints/watchpoints
> > > > - S/VS-mode: hardware breakpoints framework in Linux kernel
> > > > - M-mode: SBI firmware code to handle triggers
> > > >
> > > > SBI Debug Trigger extension proposal (draft v4) has been posted
> > > > by Anup Patel to lists.riscv.org tech-debug mailing list:
> > > >
> > > > https://lists.riscv.org/g/tech-debug/topic/92375492
> > > >
> > > > This patch provides initial implementation of SBI Debug
> > > > Trigger Extension in OpenSBI library based on the
> > > > suggested extension proposal.
> > > >
> > > > Initial implementation has the following limitations:
> > > > - only mcontrol6 trigger type is supported
> > > > - no support for chained triggers
> > > > - trigger update supports only address change
> >
> > ...
> >
> > > > +union riscv_dbtr_tdata1 {
> > > > +   unsigned long value;
> > > > +   struct {
> > > > +#if __riscv_xlen == 64
> > > > +           unsigned long data:59;
> > > > +#elif __riscv_xlen == 32
> > > > +           unsigned long data:27;
> > > > +#else
> > > > +#error "Unexpected __riscv_xlen"
> > > > +#endif
> > > > +           unsigned long dmode:1;
> > > > +           unsigned long type:4;
> > > > +   };
> > > > +};
> > >
> > > Bitfield order depends on endianness (type is in the MSBs for
> > > little-endian but LSBs for big-endian).
> >
> > Do we need to support non-standard BE cases as well ? If so, then
> > accessing fields in shared memory messages between OpenSBI and kernel
> > will have to be wrapped by cpu_to_le/le_to_cpu macros on both sides.
> 
> Yes, in the long term we might support BE in both Linux and OpenSBI
> so better to avoid bitfield for data structures in shared memory.

Do we have to avoid using bitfields in this context ?
How about using a Linux approach with appropriate defines:

union riscv_dbtr_tdata1_mcontrol6 {
	unsigned long value;
	struct {
#if defined(__LITTLE_ENDIAN_BITFIELD)
		unsigned long load:1;
		unsigned long store:1;
		...
#elif defined (__BIG_ENDIAN_BITFIELD)
		...
		unsigned long store:1;
		unsigned long load:1;
#endif
	};


Regards,
Sergey


From prabhakar.csengg at gmail.com  Sun Nov  6 14:29:16 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Sun, 6 Nov 2022 22:29:16 +0000
Subject: [PATCH RFC 0/7] Add support for Renesas RZ/Five SoC
In-Reply-To: <20221028004042.135549-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221028004042.135549-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CA+V-a8tLeQ8Zj_r72mqhOCypz_CJTkf0c7-muAVUtVrE=6n7EQ@mail.gmail.com>

On Fri, Oct 28, 2022 at 1:40 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Hi All,
>
> This patch series adds initial support to RZ/Five SoC (which is equipped
> with AX45MP AndesCore). Platform supports DT based probing.
>
> Linux support is currently being upstreamed the latest patchset can be
> found at [0].(DT bindings can be seen here)
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220920184904.90495-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
>   and is used in a similar manner as compared Andes AE350 [1]
>   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
>
Gentle ping for review.

Cheers,
Prabhakar

> Below are the logs for U-Boot (2022.10) and OpenSBI:
> --------------------------------------------------
> U-Boot SPL 2022.10-00192-g0cf0a0919b-dirty (Oct 28 2022 - 01:09:54 +0100)
> Trying to boot from NOR
>
> OpenSBI v1.1-87-gc46891e
>    ____                    _____ ____ _____
>   / __ \                  / ____|  _ \_   _|
>  | |  | |_ __   ___ _ __ | (___ | |_) || |
>  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
>  | |__| | |_) |  __/ | | |____) | |_) || |_
>   \____/| .__/ \___|_| |_|_____/|____/_____|
>         | |
>         |_|
>
> Platform Name             : smarc-rzfZ/Five
> Platform Features         : medeleg
> Platform HART Count       : 1
> Platform IPI Device       : andes_plicsw
> Platform Timer Device     : andes_plmt @ 12000000Hz
> Platform Console Device   : renesas_scif
> Platform HSM Device       : ---
> Platform PMU Device       : ---
> Platform Reboot Device    : ---
> Platform Shutdown Device  : ---
> Firmware Base             : 0x44000000
> Firmware Size             : 152 KB
> Runtime SBI Version       : 1.0
>
> Domain0 Name              : root
> Domain0 Boot HART         : 0
> Domain0 HARTs             : 0*
> Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
> Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
> Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
> Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
> Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
> Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
> Domain0 Next Address      : 0x0000000050000000
> Domain0 Next Arg1         : 0x00000000500be568
> Domain0 Next Mode         : S-mode
> Domain0 SysReset          : yes
>
> Boot HART ID              : 0
> Boot HART Domain          : root
> Boot HART Priv Version    : v1.11
> Boot HART Base ISA        : rv64imafdcnx
> Boot HART ISA Extensions  : none
> Boot HART PMP Count       : 16
> Boot HART PMP Granularity : 8
> Boot HART PMP Address Bits: 36
> Boot HART MHPM Count      : 4
> Boot HART MIDELEG         : 0x0000000000000222
> Boot HART MEDELEG         : 0x000000000000b109
>
>
> U-Boot 2022.10-00192-g0cf0a0919b-dirty (Oct 28 2022 - 01:09:54 +0100)
>
> CPU:   rv64imafdc
> Model: smarc-rzf
> DRAM:  896 MiB
> SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
> MMC:   sd at 11c00000: 0, sd at 11c10000: 1
> Loading Environment from MMC... OK
> In:    serial at 1004b800
> Out:   serial at 1004b800
> Err:   serial at 1004b800
> Net:   eth0: ethernet at 11c30000
> Hit any key to stop autoboot:  0
> =>
> --------------------------------------------------
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (7):
>   lib: utils: serial: Add Renesas SCIF driver
>   lib: utils: serial: Add FDT driver for Renesas SCIF
>   platform: andes/ae350: Split header platform.h header file
>   lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
>   platform: Add Renesas RZ/Five initial support
>   scripts: Add Renesas RZ/Five to platform list in the binary archive
>     script
>   docs: platform: Add documentation for Renesas RZ/Five SoC
>
>  docs/platform/platform.md                  |   4 +
>  docs/platform/renesas-rzfive.md            | 139 ++++++++++++++++++
>  include/sbi_utils/fdt/fdt_helper.h         |   3 +
>  include/sbi_utils/serial/renesas-scif.h    |  11 ++
>  lib/utils/fdt/fdt_helper.c                 |  23 +++
>  lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
>  lib/utils/serial/Kconfig                   |   9 ++
>  lib/utils/serial/fdt_serial_renesas_scif.c |  31 ++++
>  lib/utils/serial/objects.mk                |   4 +
>  lib/utils/serial/renesas_scif.c            | 140 ++++++++++++++++++
>  platform/andes/ae350/common-platform.h     |  94 ++++++++++++
>  platform/andes/ae350/platform.h            |  82 +----------
>  platform/renesas/rzfive/Kconfig            |  32 ++++
>  platform/renesas/rzfive/configs/defconfig  |   0
>  platform/renesas/rzfive/objects.mk         |  18 +++
>  platform/renesas/rzfive/platform.c         | 161 +++++++++++++++++++++
>  platform/renesas/rzfive/platform.h         |  24 +++
>  scripts/create-binary-archive.sh           |   1 +
>  18 files changed, 698 insertions(+), 81 deletions(-)
>  create mode 100644 docs/platform/renesas-rzfive.md
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
>  create mode 100644 lib/utils/serial/renesas_scif.c
>  create mode 100644 platform/andes/ae350/common-platform.h
>  create mode 100644 platform/renesas/rzfive/Kconfig
>  create mode 100644 platform/renesas/rzfive/configs/defconfig
>  create mode 100644 platform/renesas/rzfive/objects.mk
>  create mode 100644 platform/renesas/rzfive/platform.c
>  create mode 100644 platform/renesas/rzfive/platform.h
>
> --
> 2.17.1
>


From bmeng.cn at gmail.com  Mon Nov  7 17:39:22 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 8 Nov 2022 09:39:22 +0800
Subject: [PATCH RFC 0/7] Add support for Renesas RZ/Five SoC
In-Reply-To: <CA+V-a8tLeQ8Zj_r72mqhOCypz_CJTkf0c7-muAVUtVrE=6n7EQ@mail.gmail.com>
References: <20221028004042.135549-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <CA+V-a8tLeQ8Zj_r72mqhOCypz_CJTkf0c7-muAVUtVrE=6n7EQ@mail.gmail.com>
Message-ID: <CAEUhbmUAT_Ho3EGfuFbXnXEOeqi+RuU3F0TgYX=oVmEPW3WvhQ@mail.gmail.com>

Hi,

On Mon, Nov 7, 2022 at 6:30 AM Lad, Prabhakar
<prabhakar.csengg at gmail.com> wrote:
>
> On Fri, Oct 28, 2022 at 1:40 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > Hi All,
> >
> > This patch series adds initial support to RZ/Five SoC (which is equipped
> > with AX45MP AndesCore). Platform supports DT based probing.
> >
> > Linux support is currently being upstreamed the latest patchset can be
> > found at [0].(DT bindings can be seen here)
> >
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220920184904.90495-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> >
> > - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> > - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
> >   and is used in a similar manner as compared Andes AE350 [1]
> >   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> > - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
> >
> Gentle ping for review.
>
> Cheers,
> Prabhakar
>
> > Below are the logs for U-Boot (2022.10) and OpenSBI:
> > --------------------------------------------------
> > U-Boot SPL 2022.10-00192-g0cf0a0919b-dirty (Oct 28 2022 - 01:09:54 +0100)
> > Trying to boot from NOR

Has U-Boot support been upstreamed?

> >
> > OpenSBI v1.1-87-gc46891e
> >    ____                    _____ ____ _____
> >   / __ \                  / ____|  _ \_   _|
> >  | |  | |_ __   ___ _ __ | (___ | |_) || |
> >  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
> >  | |__| | |_) |  __/ | | |____) | |_) || |_
> >   \____/| .__/ \___|_| |_|_____/|____/_____|
> >         | |
> >         |_|
> >
> > Platform Name             : smarc-rzfZ/Five
> > Platform Features         : medeleg
> > Platform HART Count       : 1
> > Platform IPI Device       : andes_plicsw
> > Platform Timer Device     : andes_plmt @ 12000000Hz
> > Platform Console Device   : renesas_scif
> > Platform HSM Device       : ---
> > Platform PMU Device       : ---
> > Platform Reboot Device    : ---
> > Platform Shutdown Device  : ---
> > Firmware Base             : 0x44000000
> > Firmware Size             : 152 KB
> > Runtime SBI Version       : 1.0
> >
> > Domain0 Name              : root
> > Domain0 Boot HART         : 0
> > Domain0 HARTs             : 0*
> > Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
> > Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
> > Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
> > Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
> > Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
> > Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
> > Domain0 Next Address      : 0x0000000050000000
> > Domain0 Next Arg1         : 0x00000000500be568
> > Domain0 Next Mode         : S-mode
> > Domain0 SysReset          : yes
> >
> > Boot HART ID              : 0
> > Boot HART Domain          : root
> > Boot HART Priv Version    : v1.11
> > Boot HART Base ISA        : rv64imafdcnx
> > Boot HART ISA Extensions  : none
> > Boot HART PMP Count       : 16
> > Boot HART PMP Granularity : 8
> > Boot HART PMP Address Bits: 36
> > Boot HART MHPM Count      : 4
> > Boot HART MIDELEG         : 0x0000000000000222
> > Boot HART MEDELEG         : 0x000000000000b109
> >
> >
> > U-Boot 2022.10-00192-g0cf0a0919b-dirty (Oct 28 2022 - 01:09:54 +0100)
> >
> > CPU:   rv64imafdc
> > Model: smarc-rzf
> > DRAM:  896 MiB
> > SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
> > MMC:   sd at 11c00000: 0, sd at 11c10000: 1
> > Loading Environment from MMC... OK
> > In:    serial at 1004b800
> > Out:   serial at 1004b800
> > Err:   serial at 1004b800
> > Net:   eth0: ethernet at 11c30000
> > Hit any key to stop autoboot:  0
> > =>
> > --------------------------------------------------
> >

Regards,
Bin


From apatel at ventanamicro.com  Mon Nov  7 19:25:09 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue,  8 Nov 2022 08:55:09 +0530
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using LLVM
Message-ID: <20221108032509.1382464-1-apatel@ventanamicro.com>

We fix the following semihosting compile error observed using LLVM:
lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
                ret = ch > -1 ? ch : -1;
                      ~~ ^ ~~

Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/utils/serial/semihosting.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 5012fa1..72bbbb3 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -155,7 +155,7 @@ static int semihosting_getc(void)
 
 	if (semihosting_infd < 0)  {
 		ch = semihosting_trap(SYSREADC, NULL);
-		ret = ch > -1 ? ch : -1;
+		ret = ((int)ch > -1) ? ch : -1;
 	} else
 		ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
 
-- 
2.34.1



From prabhakar.csengg at gmail.com  Tue Nov  8 00:42:44 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Tue, 8 Nov 2022 08:42:44 +0000
Subject: [PATCH RFC 0/7] Add support for Renesas RZ/Five SoC
In-Reply-To: <CAEUhbmUAT_Ho3EGfuFbXnXEOeqi+RuU3F0TgYX=oVmEPW3WvhQ@mail.gmail.com>
References: <20221028004042.135549-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CA+V-a8tLeQ8Zj_r72mqhOCypz_CJTkf0c7-muAVUtVrE=6n7EQ@mail.gmail.com> <CAEUhbmUAT_Ho3EGfuFbXnXEOeqi+RuU3F0TgYX=oVmEPW3WvhQ@mail.gmail.com>
Message-ID: <CA+V-a8v2yUniKsXrV_ZyBoDb=L=GQ-e-=uvVDUhjT+cJxrY0-A@mail.gmail.com>

Hi,

On Tue, Nov 8, 2022 at 1:39 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi,
>
> On Mon, Nov 7, 2022 at 6:30 AM Lad, Prabhakar
> <prabhakar.csengg at gmail.com> wrote:
> >
> > On Fri, Oct 28, 2022 at 1:40 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > Hi All,
> > >
> > > This patch series adds initial support to RZ/Five SoC (which is equipped
> > > with AX45MP AndesCore). Platform supports DT based probing.
> > >
> > > Linux support is currently being upstreamed the latest patchset can be
> > > found at [0].(DT bindings can be seen here)
> > >
> > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20220920184904.90495-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> > > - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
> > >   and is used in a similar manner as compared Andes AE350 [1]
> > >   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> > > - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
> > >
> > Gentle ping for review.
> >
> > Cheers,
> > Prabhakar
> >
> > > Below are the logs for U-Boot (2022.10) and OpenSBI:
> > > --------------------------------------------------
> > > U-Boot SPL 2022.10-00192-g0cf0a0919b-dirty (Oct 28 2022 - 01:09:54 +0100)
> > > Trying to boot from NOR
>
> Has U-Boot support been upstreamed?
>
It's in the pipeline (and should be done soon as you can see we are on
the latest u-boot release). I can share the repo link if you need.

Cheers,
Prabhakar


From schwab at suse.de  Tue Nov  8 01:02:05 2022
From: schwab at suse.de (Andreas Schwab)
Date: Tue, 08 Nov 2022 10:02:05 +0100
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using
 LLVM
In-Reply-To: <20221108032509.1382464-1-apatel@ventanamicro.com> (Anup Patel's
	message of "Tue, 8 Nov 2022 08:55:09 +0530")
References: <20221108032509.1382464-1-apatel@ventanamicro.com>
Message-ID: <mvmwn85ddki.fsf@suse.de>

On Nov 08 2022, Anup Patel wrote:

> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..72bbbb3 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -155,7 +155,7 @@ static int semihosting_getc(void)
>  
>  	if (semihosting_infd < 0)  {
>  		ch = semihosting_trap(SYSREADC, NULL);

This is using the wrong variable to record the return value of
semihosting_trap (which is of type long, not char).

> -		ret = ch > -1 ? ch : -1;
> +		ret = ((int)ch > -1) ? ch : -1;

I think this line can be removed, and the return value of
semihosting_trap can be returned directly.

-- 
Andreas Schwab, SUSE Labs, schwab at suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."


From wxjstz at 126.com  Tue Nov  8 01:36:59 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 08 Nov 2022 17:36:59 +0800
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using
 LLVM
In-Reply-To: <20221108032509.1382464-1-apatel@ventanamicro.com>
References: <20221108032509.1382464-1-apatel@ventanamicro.com>
Message-ID: <4e99c7f7cd261a7d6d582c0fbbcb1b9c8c31fb09.camel@126.com>

? 2022-11-08???? 08:55 +0530?Anup Patel???
> We fix the following semihosting compile error observed using LLVM:
> lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-
> Wtautological-constant-out-of-range-compare]
> ??????????????? ret = ch > -1 ? ch : -1;
> ????????????????????? ~~ ^ ~~
> 
> Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
> ?lib/utils/serial/semihosting.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..72bbbb3 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -155,7 +155,7 @@ static int semihosting_getc(void)
> ?
> ????????if (semihosting_infd < 0)? {
> ????????????????ch = semihosting_trap(SYSREADC, NULL);
> -???????????????ret = ch > -1 ? ch : -1;
> +???????????????ret = ((int)ch > -1) ? ch : -1;
> ????????} else
> ????????????????ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;

There is a bug here. This line should be changed to:
                ret = semihosting_read(semihosting_infd, &ch, 1) == 0 ? ch : -1;

The return value of semihosting_read is buffer_length - bytes_read. Not the length
of characters read. The following is the code comment from openocd about SYS_READ. 

		case SEMIHOSTING_SYS_READ:	/* 0x06 */
			/*
			 * Reads the contents of a file into a buffer. The file position
			 * is specified either:
			 * - Explicitly by a SYS_SEEK.
			 * - Implicitly one byte beyond the previous SYS_READ or
			 * SYS_WRITE request.
			 *
			 * The file position is at the start of the file when it is
			 * opened, and is lost when the file is closed. Perform the
			 * file operation as a single action whenever possible. For
			 * example, do not split a read of 16KB into four 4KB chunks
			 * unless there is no alternative.
			 *
			 * Entry
			 * On entry, the PARAMETER REGISTER contains a pointer to a
			 * three-field data block:
			 * - field 1 Contains a handle for a file previously opened
			 * with SYS_OPEN.
			 * - field 2 Points to a buffer.
			 * - field 3 Contains the number of bytes to read to the buffer
			 * from the file.
			 *
			 * Return
			 * On exit, the RETURN REGISTER contains the number of bytes not
			 * filled in the buffer (buffer_length - bytes_read) as follows:
			 * - If the RETURN REGISTER is 0, the entire buffer was
			 * successfully filled.
			 * - If the RETURN REGISTER is the same as field 3, no bytes
			 * were read (EOF can be assumed).
			 * - If the RETURN REGISTER contains a value smaller than
			 * field 3, the read succeeded but the buffer was only partly
			 * filled. For interactive devices, this is the most common
			 * return value.
			 */

> ?
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Tue Nov  8 01:46:55 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 08 Nov 2022 17:46:55 +0800
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using
 LLVM
In-Reply-To: <mvmwn85ddki.fsf@suse.de>
References: <20221108032509.1382464-1-apatel@ventanamicro.com>
	 <mvmwn85ddki.fsf@suse.de>
Message-ID: <19880fa58963e209de13ed962fc02e595ad294d3.camel@126.com>

? 2022-11-08???? 10:02 +0100?Andreas Schwab???
> On Nov 08 2022, Anup Patel wrote:
> 
> > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > index 5012fa1..72bbbb3 100644
> > --- a/lib/utils/serial/semihosting.c
> > +++ b/lib/utils/serial/semihosting.c
> > @@ -155,7 +155,7 @@ static int semihosting_getc(void)
> > ?
> > ????????if (semihosting_infd < 0)? {
> > ????????????????ch = semihosting_trap(SYSREADC, NULL);
> 
> This is using the wrong variable to record the return value of
> semihosting_trap (which is of type long, not char).
> 
> > -???????????????ret = ch > -1 ? ch : -1;
> > +???????????????ret = ((int)ch > -1) ? ch : -1;
> 
> I think this line can be removed, and the return value of
> semihosting_trap can be returned directly.

This line is used to handle error codes, semihosting_trap may
have multiple return values less than 0, but console_getc can
only return -1.

Suggest:
		ret = semihosting_trap(SYSREADC, NULL);
		ret = ret < 0 ? -1 : ret;

Regards,
Xiang W
> 
> -- 
> Andreas Schwab, SUSE Labs, schwab at suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE? 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
> 




From 1220749046 at qq.com  Tue Nov  8 02:10:21 2022
From: 1220749046 at qq.com (1220749046 at qq.com)
Date: Tue,  8 Nov 2022 18:10:21 +0800
Subject: [PATCH] firmware: payloads: Remove duplicate "ALIGN"
Message-ID: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>

From: zhangleizheng <zhangleizheng at eswincomputing.com>

". = ALIGN(0x1000)" is used redundantly in firmware/fw_base.ldS
and fw_base.ldS files.

Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
---
 firmware/fw_base.ldS           | 2 --
 firmware/payloads/test.elf.ldS | 2 --
 2 files changed, 4 deletions(-)

diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
index 220c043..382da25 100644
--- a/firmware/fw_base.ldS
+++ b/firmware/fw_base.ldS
@@ -24,8 +24,6 @@
 		PROVIDE(_text_end = .);
 	}
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* End of the code sections */
 
 	/* Beginning of the read-only data sections */
diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
index f3f3242..763103c 100644
--- a/firmware/payloads/test.elf.ldS
+++ b/firmware/payloads/test.elf.ldS
@@ -33,8 +33,6 @@ SECTIONS
 		PROVIDE(_text_end = .);
 	}
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* End of the code sections */
 
 	/* Beginning of the read-only data sections */
-- 
2.17.1



From ajones at ventanamicro.com  Tue Nov  8 03:36:43 2022
From: ajones at ventanamicro.com (Andrew Jones)
Date: Tue, 8 Nov 2022 12:36:43 +0100
Subject: [PATCH] firmware: payloads: Remove duplicate "ALIGN"
In-Reply-To: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
References: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
Message-ID: <20221108113643.njqgagnrabxqw66a@kamzik>

On Tue, Nov 08, 2022 at 06:10:21PM +0800, 1220749046 at qq.com wrote:
> From: zhangleizheng <zhangleizheng at eswincomputing.com>
> 
> ". = ALIGN(0x1000)" is used redundantly in firmware/fw_base.ldS
> and fw_base.ldS files.
> 
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
> ---
>  firmware/fw_base.ldS           | 2 --
>  firmware/payloads/test.elf.ldS | 2 --
>  2 files changed, 4 deletions(-)
> 
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 220c043..382da25 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -24,8 +24,6 @@
>  		PROVIDE(_text_end = .);
>  	}
>  
> -	. = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>  	/* End of the code sections */
>  
>  	/* Beginning of the read-only data sections */
> diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
> index f3f3242..763103c 100644
> --- a/firmware/payloads/test.elf.ldS
> +++ b/firmware/payloads/test.elf.ldS
> @@ -33,8 +33,6 @@ SECTIONS
>  		PROVIDE(_text_end = .);
>  	}
>  
> -	. = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>  	/* End of the code sections */
>  
>  	/* Beginning of the read-only data sections */
> -- 
> 2.17.1
>

Reviewed-by: Andrew Jones <ajones at ventanamicro.com>


From apatel at ventanamicro.com  Tue Nov  8 04:05:19 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 8 Nov 2022 17:35:19 +0530
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using LLVM
In-Reply-To: <mvmwn85ddki.fsf@suse.de>
References: <20221108032509.1382464-1-apatel@ventanamicro.com> <mvmwn85ddki.fsf@suse.de>
Message-ID: <CAK9=C2XN-pbY-McMSC-u3JrnhpBccGMSezhALbOL95B3w2D4Gw@mail.gmail.com>

On Tue, Nov 8, 2022 at 2:32 PM Andreas Schwab <schwab at suse.de> wrote:
>
> On Nov 08 2022, Anup Patel wrote:
>
> > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > index 5012fa1..72bbbb3 100644
> > --- a/lib/utils/serial/semihosting.c
> > +++ b/lib/utils/serial/semihosting.c
> > @@ -155,7 +155,7 @@ static int semihosting_getc(void)
> >
> >       if (semihosting_infd < 0)  {
> >               ch = semihosting_trap(SYSREADC, NULL);
>
> This is using the wrong variable to record the return value of
> semihosting_trap (which is of type long, not char).

I agree with you. We should use a different variable instead of ch.

>
> > -             ret = ch > -1 ? ch : -1;
> > +             ret = ((int)ch > -1) ? ch : -1;
>
> I think this line can be removed, and the return value of
> semihosting_trap can be returned directly.

This is a legacy call where we are supposed to return -1 for failure.
(Refer, https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#extension-console-getchar-eid-0x02)

Regards,
Anup


From apatel at ventanamicro.com  Tue Nov  8 04:06:29 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 8 Nov 2022 17:36:29 +0530
Subject: [PATCH] lib: utils/serial: Fix semihosting compile error using LLVM
In-Reply-To: <19880fa58963e209de13ed962fc02e595ad294d3.camel@126.com>
References: <20221108032509.1382464-1-apatel@ventanamicro.com>
 <mvmwn85ddki.fsf@suse.de> <19880fa58963e209de13ed962fc02e595ad294d3.camel@126.com>
Message-ID: <CAK9=C2Warq49PWJkhNA=nSJ5qvQHuM=yyi2Yvn6zNZAJY4-6Pg@mail.gmail.com>

On Tue, Nov 8, 2022 at 3:19 PM Xiang W <wxjstz at 126.com> wrote:
>
> ? 2022-11-08???? 10:02 +0100?Andreas Schwab???
> > On Nov 08 2022, Anup Patel wrote:
> >
> > > diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> > > index 5012fa1..72bbbb3 100644
> > > --- a/lib/utils/serial/semihosting.c
> > > +++ b/lib/utils/serial/semihosting.c
> > > @@ -155,7 +155,7 @@ static int semihosting_getc(void)
> > >
> > >         if (semihosting_infd < 0)  {
> > >                 ch = semihosting_trap(SYSREADC, NULL);
> >
> > This is using the wrong variable to record the return value of
> > semihosting_trap (which is of type long, not char).
> >
> > > -               ret = ch > -1 ? ch : -1;
> > > +               ret = ((int)ch > -1) ? ch : -1;
> >
> > I think this line can be removed, and the return value of
> > semihosting_trap can be returned directly.
>
> This line is used to handle error codes, semihosting_trap may
> have multiple return values less than 0, but console_getc can
> only return -1.
>
> Suggest:
>                 ret = semihosting_trap(SYSREADC, NULL);
>                 ret = ret < 0 ? -1 : ret;

Andreas suggested a similar thing as well so I will send v2 patch.

Regards,
Anup

>
> Regards,
> Xiang W
> >
> > --
> > Andreas Schwab, SUSE Labs, schwab at suse.de
> > GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> > "And now for something completely different."
> >
>
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From apatel at ventanamicro.com  Tue Nov  8 04:10:16 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue,  8 Nov 2022 17:40:16 +0530
Subject: [PATCH v2] lib: utils/serial: Fix semihosting compile error using LLVM
Message-ID: <20221108121016.1441356-1-apatel@ventanamicro.com>

We fix the following semihosting compile error observed using LLVM:
lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
                ret = ch > -1 ? ch : -1;
                      ~~ ^ ~~

Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/utils/serial/semihosting.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 5012fa1..86fa296 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -154,8 +154,8 @@ static int semihosting_getc(void)
 	int ret;
 
 	if (semihosting_infd < 0)  {
-		ch = semihosting_trap(SYSREADC, NULL);
-		ret = ch > -1 ? ch : -1;
+		ret = semihosting_trap(SYSREADC, NULL);
+		ret = ret < 0 ? -1 : ret;
 	} else
 		ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
 
-- 
2.34.1



From wxjstz at 126.com  Tue Nov  8 19:54:27 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed,  9 Nov 2022 11:54:27 +0800
Subject: [PATCH] lib: utils/serial: Fix semihosting_getc
Message-ID: <20221109035427.120086-1-wxjstz@126.com>

semihosting_read returns buffer_length - bytes_read, so a successful
read should return 0. This patch fixes this issue.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/utils/serial/semihosting.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Below is the code comment from openocd about SYS_READ

		case SEMIHOSTING_SYS_READ:	/* 0x06 */
			/*
			 * Reads the contents of a file into a buffer. The file position
			 * is specified either:
			 * - Explicitly by a SYS_SEEK.
			 * - Implicitly one byte beyond the previous SYS_READ or
			 * SYS_WRITE request.
			 *
			 * The file position is at the start of the file when it is
			 * opened, and is lost when the file is closed. Perform the
			 * file operation as a single action whenever possible. For
			 * example, do not split a read of 16KB into four 4KB chunks
			 * unless there is no alternative.
			 *
			 * Entry
			 * On entry, the PARAMETER REGISTER contains a pointer to a
			 * three-field data block:
			 * - field 1 Contains a handle for a file previously opened
			 * with SYS_OPEN.
			 * - field 2 Points to a buffer.
			 * - field 3 Contains the number of bytes to read to the buffer
			 * from the file.
			 *
			 * Return
			 * On exit, the RETURN REGISTER contains the number of bytes not
			 * filled in the buffer (buffer_length - bytes_read) as follows:
			 * - If the RETURN REGISTER is 0, the entire buffer was
			 * successfully filled.
			 * - If the RETURN REGISTER is the same as field 3, no bytes
			 * were read (EOF can be assumed).
			 * - If the RETURN REGISTER contains a value smaller than
			 * field 3, the read succeeded but the buffer was only partly
			 * filled. For interactive devices, this is the most common
			 * return value.
			 */

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 5012fa1..79eb583 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -157,7 +157,7 @@ static int semihosting_getc(void)
 		ch = semihosting_trap(SYSREADC, NULL);
 		ret = ch > -1 ? ch : -1;
 	} else
-		ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
+		ret = semihosting_read(semihosting_infd, &ch, 1) == 0 ? ch : -1;
 
 	return ret;
 }
-- 
2.30.2



From dramforever at live.com  Tue Nov  8 22:53:37 2022
From: dramforever at live.com (Vivian Wang)
Date: Wed,  9 Nov 2022 14:53:37 +0800
Subject: [PATCH] lib: sbi_ecall: Split up sbi_ecall_replace
Message-ID: <TYYP286MB14394A21B7C5D612DBC5F3ECC63E9@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>

Split up sbi_ecall_replace so that each extension is in its individual
file.

Also reorganize the corresponding section in lib/sbi/objects.mk so
that it is grouped by extension, now that the object file targets are
split up.

Signed-off-by: Vivian Wang <dramforever at live.com>
---
 lib/sbi/objects.mk                            |  22 +++-
 lib/sbi/sbi_ecall_ipi.c                       |  36 ++++++
 ...sbi_ecall_replace.c => sbi_ecall_rfence.c} | 122 +-----------------
 lib/sbi/sbi_ecall_srst.c                      |  75 +++++++++++
 lib/sbi/sbi_ecall_time.c                      |  40 ++++++
 5 files changed, 169 insertions(+), 126 deletions(-)
 create mode 100644 lib/sbi/sbi_ecall_ipi.c
 rename lib/sbi/{sbi_ecall_replace.c => sbi_ecall_rfence.c} (50%)
 create mode 100644 lib/sbi/sbi_ecall_srst.c
 create mode 100644 lib/sbi/sbi_ecall_time.c

diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 783c46d..c774ebb 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -17,20 +17,30 @@ libsbi-objs-y += sbi_ecall_exts.o
 
 # The order of below extensions is performance optimized
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_TIME) += ecall_time
+libsbi-objs-$(CONFIG_SBI_ECALL_TIME) += sbi_ecall_time.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_RFENCE) += ecall_rfence
+libsbi-objs-$(CONFIG_SBI_ECALL_RFENCE) += sbi_ecall_rfence.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_IPI) += ecall_ipi
+libsbi-objs-$(CONFIG_SBI_ECALL_IPI) += sbi_ecall_ipi.o
+
 carray-sbi_ecall_exts-y += ecall_base
+libsbi-objs-y += sbi_ecall_base.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
+libsbi-objs-$(CONFIG_SBI_ECALL_HSM) += sbi_ecall_hsm.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
+libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
-carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
+libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
 
-libsbi-objs-y += sbi_ecall_base.o
-libsbi-objs-$(CONFIG_SBI_ECALL_HSM) += sbi_ecall_hsm.o
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
 libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
-libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
-libsbi-objs-y += sbi_ecall_replace.o
+
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
 libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
 
 libsbi-objs-y += sbi_bitmap.o
diff --git a/lib/sbi/sbi_ecall_ipi.c b/lib/sbi/sbi_ecall_ipi.c
new file mode 100644
index 0000000..f4797e1
--- /dev/null
+++ b/lib/sbi/sbi_ecall_ipi.c
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel at wdc.com>
+ *   Atish Patra <atish.patra at wdc.com>
+ */
+
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_ipi.h>
+
+static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
+				 const struct sbi_trap_regs *regs,
+				 unsigned long *out_val,
+				 struct sbi_trap_info *out_trap)
+{
+	int ret = 0;
+
+	if (funcid == SBI_EXT_IPI_SEND_IPI)
+		ret = sbi_ipi_send_smode(regs->a0, regs->a1);
+	else
+		ret = SBI_ENOTSUPP;
+
+	return ret;
+}
+
+struct sbi_ecall_extension ecall_ipi = {
+	.extid_start = SBI_EXT_IPI,
+	.extid_end = SBI_EXT_IPI,
+	.handle = sbi_ecall_ipi_handler,
+};
diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_rfence.c
similarity index 50%
rename from lib/sbi/sbi_ecall_replace.c
rename to lib/sbi/sbi_ecall_rfence.c
index 0ea00d6..8f0e3d7 100644
--- a/lib/sbi/sbi_ecall_replace.c
+++ b/lib/sbi/sbi_ecall_rfence.c
@@ -9,44 +9,12 @@
  */
 
 #include <sbi/riscv_asm.h>
+#include <sbi/sbi_error.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
-#include <sbi/sbi_error.h>
-#include <sbi/sbi_hart.h>
-#include <sbi/sbi_ipi.h>
-#include <sbi/sbi_system.h>
-#include <sbi/sbi_timer.h>
-#include <sbi/sbi_tlb.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_tlb.h>
 
-#ifdef CONFIG_SBI_ECALL_TIME
-static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
-				  const struct sbi_trap_regs *regs,
-				  unsigned long *out_val,
-				  struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-
-	if (funcid == SBI_EXT_TIME_SET_TIMER) {
-#if __riscv_xlen == 32
-		sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
-#else
-		sbi_timer_event_start((u64)regs->a0);
-#endif
-	} else
-		ret = SBI_ENOTSUPP;
-
-	return ret;
-}
-
-struct sbi_ecall_extension ecall_time = {
-	.extid_start = SBI_EXT_TIME,
-	.extid_end = SBI_EXT_TIME,
-	.handle = sbi_ecall_time_handler,
-};
-#endif
-
-#ifdef CONFIG_SBI_ECALL_RFENCE
 static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
 				    const struct sbi_trap_regs *regs,
 				    unsigned long *out_val,
@@ -116,89 +84,3 @@ struct sbi_ecall_extension ecall_rfence = {
 	.extid_end = SBI_EXT_RFENCE,
 	.handle = sbi_ecall_rfence_handler,
 };
-#endif
-
-#ifdef CONFIG_SBI_ECALL_IPI
-static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
-				 const struct sbi_trap_regs *regs,
-				 unsigned long *out_val,
-				 struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-
-	if (funcid == SBI_EXT_IPI_SEND_IPI)
-		ret = sbi_ipi_send_smode(regs->a0, regs->a1);
-	else
-		ret = SBI_ENOTSUPP;
-
-	return ret;
-}
-
-struct sbi_ecall_extension ecall_ipi = {
-	.extid_start = SBI_EXT_IPI,
-	.extid_end = SBI_EXT_IPI,
-	.handle = sbi_ecall_ipi_handler,
-};
-#endif
-
-#ifdef CONFIG_SBI_ECALL_SRST
-static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
-				  const struct sbi_trap_regs *regs,
-				  unsigned long *out_val,
-				  struct sbi_trap_info *out_trap)
-{
-	if (funcid == SBI_EXT_SRST_RESET) {
-		if ((((u32)-1U) <= ((u64)regs->a0)) ||
-		    (((u32)-1U) <= ((u64)regs->a1)))
-			return SBI_EINVAL;
-
-		switch (regs->a0) {
-		case SBI_SRST_RESET_TYPE_SHUTDOWN:
-		case SBI_SRST_RESET_TYPE_COLD_REBOOT:
-		case SBI_SRST_RESET_TYPE_WARM_REBOOT:
-			break;
-		default:
-			return SBI_EINVAL;
-		}
-
-		switch (regs->a1) {
-		case SBI_SRST_RESET_REASON_NONE:
-		case SBI_SRST_RESET_REASON_SYSFAIL:
-			break;
-		default:
-			return SBI_EINVAL;
-		}
-
-		if (sbi_system_reset_supported(regs->a0, regs->a1))
-			sbi_system_reset(regs->a0, regs->a1);
-	}
-
-	return SBI_ENOTSUPP;
-}
-
-static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
-{
-	u32 type, count = 0;
-
-	/*
-	 * At least one standard reset types should be supported by
-	 * the platform for SBI SRST extension to be usable.
-	 */
-
-	for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
-		if (sbi_system_reset_supported(type,
-					SBI_SRST_RESET_REASON_NONE))
-			count++;
-	}
-
-	*out_val = (count) ? 1 : 0;
-	return 0;
-}
-
-struct sbi_ecall_extension ecall_srst = {
-	.extid_start = SBI_EXT_SRST,
-	.extid_end = SBI_EXT_SRST,
-	.handle = sbi_ecall_srst_handler,
-	.probe = sbi_ecall_srst_probe,
-};
-#endif
diff --git a/lib/sbi/sbi_ecall_srst.c b/lib/sbi/sbi_ecall_srst.c
new file mode 100644
index 0000000..93b012c
--- /dev/null
+++ b/lib/sbi/sbi_ecall_srst.c
@@ -0,0 +1,75 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel at wdc.com>
+ *   Atish Patra <atish.patra at wdc.com>
+ */
+
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_system.h>
+
+static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	if (funcid == SBI_EXT_SRST_RESET) {
+		if ((((u32)-1U) <= ((u64)regs->a0)) ||
+		    (((u32)-1U) <= ((u64)regs->a1)))
+			return SBI_EINVAL;
+
+		switch (regs->a0) {
+		case SBI_SRST_RESET_TYPE_SHUTDOWN:
+		case SBI_SRST_RESET_TYPE_COLD_REBOOT:
+		case SBI_SRST_RESET_TYPE_WARM_REBOOT:
+			break;
+		default:
+			return SBI_EINVAL;
+		}
+
+		switch (regs->a1) {
+		case SBI_SRST_RESET_REASON_NONE:
+		case SBI_SRST_RESET_REASON_SYSFAIL:
+			break;
+		default:
+			return SBI_EINVAL;
+		}
+
+		if (sbi_system_reset_supported(regs->a0, regs->a1))
+			sbi_system_reset(regs->a0, regs->a1);
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
+{
+	u32 type, count = 0;
+
+	/*
+	 * At least one standard reset types should be supported by
+	 * the platform for SBI SRST extension to be usable.
+	 */
+
+	for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
+		if (sbi_system_reset_supported(type,
+					SBI_SRST_RESET_REASON_NONE))
+			count++;
+	}
+
+	*out_val = (count) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_srst = {
+	.extid_start = SBI_EXT_SRST,
+	.extid_end = SBI_EXT_SRST,
+	.handle = sbi_ecall_srst_handler,
+	.probe = sbi_ecall_srst_probe,
+};
diff --git a/lib/sbi/sbi_ecall_time.c b/lib/sbi/sbi_ecall_time.c
new file mode 100644
index 0000000..668cb17
--- /dev/null
+++ b/lib/sbi/sbi_ecall_time.c
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel at wdc.com>
+ *   Atish Patra <atish.patra at wdc.com>
+ */
+
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_timer.h>
+
+static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	int ret = 0;
+
+	if (funcid == SBI_EXT_TIME_SET_TIMER) {
+#if __riscv_xlen == 32
+		sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
+#else
+		sbi_timer_event_start((u64)regs->a0);
+#endif
+	} else
+		ret = SBI_ENOTSUPP;
+
+	return ret;
+}
+
+struct sbi_ecall_extension ecall_time = {
+	.extid_start = SBI_EXT_TIME,
+	.extid_end = SBI_EXT_TIME,
+	.handle = sbi_ecall_time_handler,
+};
-- 
2.38.0



From wxjstz at 126.com  Wed Nov  9 07:07:58 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 09 Nov 2022 23:07:58 +0800
Subject: [PATCH v2] lib: utils/serial: Fix semihosting compile error
 using LLVM
In-Reply-To: <20221108121016.1441356-1-apatel@ventanamicro.com>
References: <20221108121016.1441356-1-apatel@ventanamicro.com>
Message-ID: <4dcdf2c57c174bd13f3214d3f5f9bc663d5c110b.camel@126.com>

? 2022-11-08???? 17:40 +0530?Anup Patel???
> We fix the following semihosting compile error observed using LLVM:
> lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-
> Wtautological-constant-out-of-range-compare]
> ??????????????? ret = ch > -1 ? ch : -1;
> ????????????????????? ~~ ^ ~~
> 
> Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/serial/semihosting.c | 4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..86fa296 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -154,8 +154,8 @@ static int semihosting_getc(void)
> ????????int ret;
> ?
> ????????if (semihosting_infd < 0)? {
> -???????????????ch = semihosting_trap(SYSREADC, NULL);
> -???????????????ret = ch > -1 ? ch : -1;
> +???????????????ret = semihosting_trap(SYSREADC, NULL);
> +???????????????ret = ret < 0 ? -1 : ret;
> ????????} else
> ????????????????ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
> ?
> -- 
> 2.34.1
> 
> 




From 1220749046 at qq.com  Wed Nov  9 18:11:07 2022
From: 1220749046 at qq.com (1220749046 at qq.com)
Date: Thu, 10 Nov 2022 10:11:07 +0800
Subject: [PATCH] lib: utils/serial: Fix compilation errors with LLVM
Message-ID: <tencent_B61B313CB7C38FFC16B03BA1CBEC14BAB906@qq.com>

From: zhangleizheng <zhangleizheng at eswincomputing.com>

Fix: "Getting compilation error on generic firmware #269"
     opensbi/lib/utils/serial/semihosting.c:158:12: error: result
     of comparison of constant -1 with expression of type 'char'
     is always true [-Werror,-Wtautological-constant-out-of-range-compare]
        ret = ch > -1 ? ch : -1;

Using clang16 as the compiler.

Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
---
 lib/utils/serial/semihosting.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 5012fa1..27dba6f 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -150,11 +150,11 @@ static void semihosting_putc(char ch)
 
 static int semihosting_getc(void)
 {
-	char ch = 0;
+	signed char ch = 0;
 	int ret;
 
 	if (semihosting_infd < 0)  {
-		ch = semihosting_trap(SYSREADC, NULL);
+		ch = (signed char)semihosting_trap(SYSREADC, NULL);
 		ret = ch > -1 ? ch : -1;
 	} else
 		ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
-- 
2.17.1



From wxjstz at 126.com  Wed Nov  9 19:11:19 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 10 Nov 2022 11:11:19 +0800
Subject: [PATCH] lib: utils/serial: Fix compilation errors with LLVM
In-Reply-To: <tencent_B61B313CB7C38FFC16B03BA1CBEC14BAB906@qq.com>
References: <tencent_B61B313CB7C38FFC16B03BA1CBEC14BAB906@qq.com>
Message-ID: <eb85f94ccafe6fbba48ad4e8b34f40d9cfb4a786.camel@126.com>

? 2022-11-10???? 10:11 +0800?1220749046 at qq.com???
> From: zhangleizheng <zhangleizheng at eswincomputing.com>
> 
> Fix: "Getting compilation error on generic firmware #269"
> ???? opensbi/lib/utils/serial/semihosting.c:158:12: error: result
> ???? of comparison of constant -1 with expression of type 'char'
> ???? is always true [-Werror,-Wtautological-constant-out-of-range-compare]
> ??????? ret = ch > -1 ? ch : -1;
> 
> Using clang16 as the compiler.
> 
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>

repeat with
https://lists.infradead.org/pipermail/opensbi/2022-November/003543.html
https://lists.infradead.org/pipermail/opensbi/2022-November/003552.html

Regards,
Xiang W

> ---
> ?lib/utils/serial/semihosting.c | 4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..27dba6f 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -150,11 +150,11 @@ static void semihosting_putc(char ch)
> ?
> ?static int semihosting_getc(void)
> ?{
> -???????char ch = 0;
> +???????signed char ch = 0;
> ????????int ret;
> ?
> ????????if (semihosting_infd < 0)? {
> -???????????????ch = semihosting_trap(SYSREADC, NULL);
> +???????????????ch = (signed char)semihosting_trap(SYSREADC, NULL);
> ????????????????ret = ch > -1 ? ch : -1;
> ????????} else
> ????????????????ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
> -- 
> 2.17.1
> 
> 




From wxjstz at 126.com  Wed Nov  9 20:38:35 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 10 Nov 2022 12:38:35 +0800
Subject: [PATCH] lib: utils/serial: Fix semihosting_getc
In-Reply-To: <20221109035427.120086-1-wxjstz@126.com>
References: <20221109035427.120086-1-wxjstz@126.com>
Message-ID: <9e634c3c557a1fde1016077da4b982cea11089c2.camel@126.com>

? 2022-11-09???? 11:54 +0800?Xiang W???
> semihosting_read returns buffer_length - bytes_read, so a successful
> read should return 0. This patch fixes this issue.
> 
> Signed-off-by: Xiang W <wxjstz at 126.com>
sorry? please revoke this patch.

I ignored repackaged semihosting_read, returned len - ret.

Regards,
Xiang W

> ---
> ?lib/utils/serial/semihosting.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Below is the code comment from openocd about SYS_READ
> 
> ????????????????case SEMIHOSTING_SYS_READ:??????/* 0x06 */
> ????????????????????????/*
> ???????????????????????? * Reads the contents of a file into a buffer. The file position
> ???????????????????????? * is specified either:
> ???????????????????????? * - Explicitly by a SYS_SEEK.
> ???????????????????????? * - Implicitly one byte beyond the previous SYS_READ or
> ???????????????????????? * SYS_WRITE request.
> ???????????????????????? *
> ???????????????????????? * The file position is at the start of the file when it is
> ???????????????????????? * opened, and is lost when the file is closed. Perform the
> ???????????????????????? * file operation as a single action whenever possible. For
> ???????????????????????? * example, do not split a read of 16KB into four 4KB chunks
> ???????????????????????? * unless there is no alternative.
> ???????????????????????? *
> ???????????????????????? * Entry
> ???????????????????????? * On entry, the PARAMETER REGISTER contains a pointer to a
> ???????????????????????? * three-field data block:
> ???????????????????????? * - field 1 Contains a handle for a file previously opened
> ???????????????????????? * with SYS_OPEN.
> ???????????????????????? * - field 2 Points to a buffer.
> ???????????????????????? * - field 3 Contains the number of bytes to read to the buffer
> ???????????????????????? * from the file.
> ???????????????????????? *
> ???????????????????????? * Return
> ???????????????????????? * On exit, the RETURN REGISTER contains the number of bytes not
> ???????????????????????? * filled in the buffer (buffer_length - bytes_read) as follows:
> ???????????????????????? * - If the RETURN REGISTER is 0, the entire buffer was
> ???????????????????????? * successfully filled.
> ???????????????????????? * - If the RETURN REGISTER is the same as field 3, no bytes
> ???????????????????????? * were read (EOF can be assumed).
> ???????????????????????? * - If the RETURN REGISTER contains a value smaller than
> ???????????????????????? * field 3, the read succeeded but the buffer was only partly
> ???????????????????????? * filled. For interactive devices, this is the most common
> ???????????????????????? * return value.
> ???????????????????????? */
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..79eb583 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -157,7 +157,7 @@ static int semihosting_getc(void)
> ????????????????ch = semihosting_trap(SYSREADC, NULL);
> ????????????????ret = ch > -1 ? ch : -1;
> ????????} else
> -???????????????ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
> +???????????????ret = semihosting_read(semihosting_infd, &ch, 1) == 0 ? ch : -1;
> ?
> ????????return ret;
> ?}
> -- 
> 2.30.2
> 
> 




From apatel at ventanamicro.com  Thu Nov 10 09:00:13 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 10 Nov 2022 22:30:13 +0530
Subject: [RFC PATCH 0/3] OpenSBI debug console support
Message-ID: <20221110170016.1477865-1-apatel@ventanamicro.com>

The latest draft-v4 proposal of SBI debug console can be found here:
https://lists.riscv.org/g/tech-unixplatformspec/message/1815

This series implements SBI debug console support in OpenSBI
as-per above draft proposal.

These patches can also be found in riscv_sbi_dbcn_v1 branch
at: https://github.com/avpatel/opensbi.git

Anup Patel (3):
  include: Add defines for SBI debug console extension
  lib: sbi: Add sbi_nputs() function
  lib: sbi: Implement SBI debug console extension

 include/sbi/sbi_console.h         |  2 ++
 include/sbi/sbi_ecall_interface.h |  4 ++++
 lib/sbi/Kconfig                   |  4 ++++
 lib/sbi/objects.mk                |  1 +
 lib/sbi/sbi_console.c             | 10 ++++++++++
 lib/sbi/sbi_ecall_replace.c       | 30 ++++++++++++++++++++++++++++++
 6 files changed, 51 insertions(+)

-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 10 09:00:14 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 10 Nov 2022 22:30:14 +0530
Subject: [RFC PATCH 1/3] include: Add defines for SBI debug console extension
In-Reply-To: <20221110170016.1477865-1-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
Message-ID: <20221110170016.1477865-2-apatel@ventanamicro.com>

We add SBI debug console extension related defines/enum to the
SBI ecall interface header.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_ecall_interface.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index a3f2bf4..1dd3874 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -29,6 +29,7 @@
 #define SBI_EXT_HSM				0x48534D
 #define SBI_EXT_SRST				0x53525354
 #define SBI_EXT_PMU				0x504D55
+#define SBI_EXT_DBCN				0x4442434E
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -230,6 +231,9 @@ enum sbi_pmu_ctr_type {
 /* Flags defined for counter stop function */
 #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_PUTS		0x0
+
 /* SBI base specification related macros */
 #define SBI_SPEC_VERSION_MAJOR_OFFSET		24
 #define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 10 09:00:15 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 10 Nov 2022 22:30:15 +0530
Subject: [RFC PATCH 2/3] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221110170016.1477865-1-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
Message-ID: <20221110170016.1477865-3-apatel@ventanamicro.com>

We add new sbi_nputs() which help us print a fixed number of characters
from a physical memory location.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_console.h |  2 ++
 lib/sbi/sbi_console.c     | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
index e15b55d..1bdeeb9 100644
--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -33,6 +33,8 @@ void sbi_putc(char ch);
 
 void sbi_puts(const char *str);
 
+void sbi_nputs(const char *str, unsigned long len);
+
 void sbi_gets(char *s, int maxwidth, char endchar);
 
 int __printf(2, 3) sbi_sprintf(char *out, const char *format, ...);
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index cfef2f8..a975708 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -51,6 +51,16 @@ void sbi_puts(const char *str)
 	spin_unlock(&console_out_lock);
 }
 
+void sbi_nputs(const char *str, unsigned long len)
+{
+	unsigned long i;
+
+	spin_lock(&console_out_lock);
+	for (i = 0; i < len; i++)
+		sbi_putc(str[i]);
+	spin_unlock(&console_out_lock);
+}
+
 void sbi_gets(char *s, int maxwidth, char endchar)
 {
 	int ch;
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 10 09:00:16 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 10 Nov 2022 22:30:16 +0530
Subject: [RFC PATCH 3/3] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221110170016.1477865-1-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
Message-ID: <20221110170016.1477865-4-apatel@ventanamicro.com>

We implement SBI debug console extension as one of the replacement
SBI extensions. This extension is only available when OpenSBI platform
provides a console device to generic library.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/sbi/Kconfig             |  4 ++++
 lib/sbi/objects.mk          |  1 +
 lib/sbi/sbi_ecall_replace.c | 30 ++++++++++++++++++++++++++++++
 3 files changed, 35 insertions(+)

diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index df74bba..ef6728b 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -26,6 +26,10 @@ config SBI_ECALL_PMU
 	bool "Performance Monitoring Unit extension"
 	default y
 
+config SBI_ECALL_DBCN
+	bool "Debug Console extension"
+	default y
+
 config SBI_ECALL_LEGACY
 	bool "SBI v0.1 legacy extensions"
 	default y
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index 783c46d..7ccad52 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -23,6 +23,7 @@ carray-sbi_ecall_exts-y += ecall_base
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
 
diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_replace.c
index 0ea00d6..a092e2f 100644
--- a/lib/sbi/sbi_ecall_replace.c
+++ b/lib/sbi/sbi_ecall_replace.c
@@ -9,6 +9,7 @@
  */
 
 #include <sbi/riscv_asm.h>
+#include <sbi/sbi_console.h>
 #include <sbi/sbi_ecall.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
@@ -202,3 +203,32 @@ struct sbi_ecall_extension ecall_srst = {
 	.probe = sbi_ecall_srst_probe,
 };
 #endif
+
+#ifdef CONFIG_SBI_ECALL_DBCN
+static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
+		/* TODO: sanity check on the physical address range */
+		sbi_nputs((const char *)regs->a1, regs->a0);
+		return 0;
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
+{
+	*out_val = (sbi_console_get_device()) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_dbcn = {
+	.extid_start = SBI_EXT_DBCN,
+	.extid_end = SBI_EXT_DBCN,
+	.handle = sbi_ecall_dbcn_handler,
+	.probe = sbi_ecall_dbcn_probe,
+};
+#endif
-- 
2.34.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:20:58 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:20:58 +0000
Subject: [PATCH v2 0/7] Add support for Renesas RZ/Five SoC
Message-ID: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Hi All,

This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
is equipped with AX45MP AndesCore). Platform supports DT based probing.

Linux support is currently being upstreamed the latest patchset can be
found at [0](currently in linux-next, DT bindings can be seen here)

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

- PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
- PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
  and is used in a similar manner as compared Andes AE350 [1]
  [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
- SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79

RFC->v2
* Fixed comments pointed by Xiang W
* Included RB tag from Yu Chien Peter Lin for patch #3

RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

Note, in below the log "Platform Name" -> "smarc-rzfZ/Five" in platform.c
we are parsing the DT and updating plat->name which is 64bytes only but in
the DT the string is quite big enough. Should we better of change the name
in sbi_platform to pointer instead?

Below are the logs for U-Boot (2022.10) and OpenSBI:
--------------------------------------------------

U-Boot SPL 2022.10-00192-gbc7f070181-dirty (Nov 11 2022 - 16:31:17 +0000)
Trying to boot from NOR

OpenSBI v1.1-87-g888468d
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : Rmarc-rzfZ/Five
Platform Features         : medeleg
Platform HART Count       : 1
Platform IPI Device       : andes_plicsw
Platform Timer Device     : andes_plmt @ 12000000Hz
Platform Console Device   : renesas_scif
Platform HSM Device       : ---
Platform PMU Device       : ---
Platform Reboot Device    : ---
Platform Shutdown Device  : ---
Firmware Base             : 0x44000000
Firmware Size             : 152 KB
Runtime SBI Version       : 1.0

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000050000000
Domain0 Next Arg1         : 0x00000000500be568
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART Priv Version    : v1.11
Boot HART Base ISA        : rv64imafdcnx
Boot HART ISA Extensions  : none
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 8
Boot HART PMP Address Bits: 36
Boot HART MHPM Count      : 4
Boot HART MIDELEG         : 0x0000000000000222
Boot HART MEDELEG         : 0x000000000000b109


U-Boot 2022.10-00192-gbc7f070181-dirty (Nov 11 2022 - 16:31:17 +0000)

CPU:   rv64imafdc
Model: smarc-rzf
DRAM:  896 MiB
SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
MMC:   sd at 11c00000: 0, sd at 11c10000: 1
Loading Environment from MMC... OK
In:    serial at 1004b800
Out:   serial at 1004b800
Err:   serial at 1004b800
Net:   eth0: ethernet at 11c30000
Hit any key to stop autoboot:  0
=> sbi
SBI 1.0
OpenSBI 1.1
Machine:
  Vendor ID 31e
  Architecture ID 8000000000008a45
  Implementation ID 500
Extensions:
  sbi_set_timer
  sbi_console_putchar
  sbi_console_getchar
  sbi_clear_ipi
  sbi_send_ipi
  sbi_remote_fence_i
  sbi_remote_sfence_vma
  sbi_remote_sfence_vma_asid
  sbi_shutdown
  SBI Base Functionality
  Timer Extension
  IPI Extension
  RFENCE Extension
  Hart State Management Extension
  Performance Monitoring Unit Extension
=>

Cheers,
Prabhakar

Lad Prabhakar (7):
  lib: utils: serial: Add Renesas SCIF driver
  lib: utils: serial: Add FDT driver for Renesas SCIF
  platform: andes/ae350: Split platform.h header file
  lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
  platform: Add Renesas RZ/Five initial support
  scripts: Add Renesas RZ/Five to platform list in the binary archive
    script
  docs: platform: Add documentation for Renesas RZ/Five SoC

 docs/platform/platform.md                  |   5 +
 docs/platform/renesas-rzfive.md            | 143 ++++++++++++++++++
 include/sbi_utils/fdt/fdt_helper.h         |   3 +
 include/sbi_utils/serial/renesas-scif.h    |  11 ++
 lib/utils/fdt/fdt_helper.c                 |  11 ++
 lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
 lib/utils/serial/Kconfig                   |   9 ++
 lib/utils/serial/fdt_serial_renesas_scif.c |  31 ++++
 lib/utils/serial/objects.mk                |   4 +
 lib/utils/serial/renesas_scif.c            | 139 ++++++++++++++++++
 platform/andes/ae350/common-platform.h     |  94 ++++++++++++
 platform/andes/ae350/platform.h            |  82 +----------
 platform/renesas/rzfive/Kconfig            |  32 ++++
 platform/renesas/rzfive/configs/defconfig  |   0
 platform/renesas/rzfive/objects.mk         |  18 +++
 platform/renesas/rzfive/platform.c         | 161 +++++++++++++++++++++
 platform/renesas/rzfive/platform.h         |  24 +++
 scripts/create-binary-archive.sh           |   1 +
 18 files changed, 690 insertions(+), 81 deletions(-)
 create mode 100644 docs/platform/renesas-rzfive.md
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
 create mode 100644 lib/utils/serial/renesas_scif.c
 create mode 100644 platform/andes/ae350/common-platform.h
 create mode 100644 platform/renesas/rzfive/Kconfig
 create mode 100644 platform/renesas/rzfive/configs/defconfig
 create mode 100644 platform/renesas/rzfive/objects.mk
 create mode 100644 platform/renesas/rzfive/platform.c
 create mode 100644 platform/renesas/rzfive/platform.h

-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:20:59 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:20:59 +0000
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
<takeki.hamada.ak at bp.renesas.com>

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* Fixed comments pointed by Xiang W
---
 include/sbi_utils/serial/renesas-scif.h |  11 ++
 lib/utils/serial/Kconfig                |   4 +
 lib/utils/serial/objects.mk             |   1 +
 lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
 4 files changed, 155 insertions(+)
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/renesas_scif.c

diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
new file mode 100644
index 0000000..0002a1a
--- /dev/null
+++ b/include/sbi_utils/serial/renesas-scif.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#ifndef __SERIAL_RENESAS_SCIF_H__
+#define __SERIAL_RENESAS_SCIF_H__
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif /* __SERIAL_RENESAS_SCIF_H__ */
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index da549a7..f6ed803 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -59,6 +59,10 @@ config SERIAL_GAISLER
 	bool "Gaisler UART support"
 	default n
 
+config SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF support"
+	default n
+
 config SERIAL_SHAKTI
 	bool "Shakti UART support"
 	default n
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 98f3f9a..6520424 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
 
 libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
+libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
 libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
new file mode 100644
index 0000000..0586e1a
--- /dev/null
+++ b/lib/utils/serial/renesas_scif.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_timer.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+/* clang-format off */
+
+#define SCIF_REG_SMR		0x0
+#define SCIF_REG_BRR		0x2
+#define SCIF_REG_SCR		0x4
+#define SCIF_REG_FTDR		0x6
+#define SCIF_REG_FSR		0x8
+#define SCIF_REG_FRDR		0xa
+#define SCIF_REG_FCR		0xc
+#define SCIF_REG_LSR		0x12
+#define SCIF_REG_SEMR		0x14
+
+#define SCIF_RFRST		0x2 /* Reset assert receive-FIFO (bit[1]) */
+#define SCIF_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2]) */
+
+#define SCIF_FCR_RST_ASSRT_TFRF	(SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
+#define SCIF_FCR_RST_NGATE_TFRF	0x0 /* Reset negate tx-FIFO & rx-FIFO*/
+
+#define SCIF_RE			0x10 /* Enable receive (bit[4])  */
+#define SCIF_TE			0x20 /* Enable transmit(bit[5])  */
+#define SCIF_SCR_RCV_TRN_EN	(SCIF_RE | SCIF_TE) /* Enable receive & transmit */
+#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
+
+#define SCIF_FSR_ER		0x80 /* Receive error flag */
+#define SCIF_FSR_TEND		0x40 /* Detect break flag */
+#define SCIF_FSR_TDFE		0x20 /* Detect break flag */
+#define SCIF_FSR_BRK		0x10 /* Detect break flag */
+#define SCIF_FSR_RDF		0x2  /* Receive FIFO data full flag */
+#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
+
+#define SCIF_FSR_RXD_CHK	(SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
+#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
+
+#define SCIF_LSR_ORER		0x1 /* Overrun error flag */
+
+#define SCIF_SPTR_SPB2DT	0x1 /* if SCR.TE setting, don't care */
+#define SCIF_SPTR_SPB2IO	0x2 /* if SCR.TE setting, don't care */
+
+#define SCIF_SEMR_BRME		0x20 /* bit-rate modulation enable */
+#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
+
+#define SCIF_SIZE(reg)		((reg == SCIF_REG_BRR) || \
+				 (reg == SCIF_REG_FTDR) || \
+				 (reg == SCIF_REG_FRDR) || \
+				 (reg == SCIF_REG_SEMR))
+
+#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
+
+/* clang-format on */
+
+static volatile char *scif_base;
+
+static u32 get_reg(u32 offset)
+{
+	if (SCIF_SIZE(offset))
+		return readb(scif_base + offset);
+
+	return readw(scif_base + offset);
+}
+
+static void set_reg(u32 offset, u32 val)
+{
+	if (SCIF_SIZE(offset))
+		return writeb(val, scif_base + offset);
+
+	return writew(val, scif_base + offset);
+}
+
+static void scif_wait(unsigned long baudrate)
+{
+	unsigned long utime;
+
+	utime = 1000000 / baudrate + 1;
+
+	sbi_timer_udelay(utime);
+}
+
+static void renesas_scif_putc(char ch)
+{
+	uint16_t reg;
+
+	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
+		;
+
+	set_reg(SCIF_REG_FTDR, ch);
+	reg = get_reg(SCIF_REG_FSR);
+	reg &= ~SCIF_FSR_TXD_CHK;
+	set_reg(SCIF_REG_FSR, reg);
+}
+
+static struct sbi_console_device renesas_scif_console = {
+	.name		= "renesas_scif",
+	.console_putc	= renesas_scif_putc,
+};
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
+{
+	volatile uint16_t data16;
+
+	scif_base = (volatile char *)base;
+
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS); /* Disable receive & transmit */
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_TFRF); /* Reset assert tx-FIFO & rx-FIFO */
+
+	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
+	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
+
+	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
+	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
+
+	set_reg(SCIF_REG_SCR, 0x0); /* Select internal clock, SC_CLK pin unused for output pin */
+
+	set_reg(SCIF_REG_SMR, 0x0); /* Set asynchronous, 8bit data, no-parity, 1 stop and Po/1 */
+
+	data16 = get_reg(SCIF_REG_SEMR);
+	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS)); /* Select to access BRR */
+	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
+
+	scif_wait(baudrate);
+
+	/* FTCR is left at initial value, because this interrupt isn't used. */
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_TFRF); /* Reset negate tx-FIFO, rx-FIFO. */
+
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN); /* Enable receive & transmit w/SC_CLK=no output */
+
+	sbi_console_set_device(&renesas_scif_console);
+
+	return 0;
+}
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:00 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:00 +0000
Subject: [PATCH v2 2/7] lib: utils: serial: Add FDT driver for Renesas SCIF
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial at 1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = <0 0x1004b800 0 0x400>;
                    interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
                                 <414 IRQ_TYPE_LEVEL_HIGH>,
                                 <415 IRQ_TYPE_LEVEL_HIGH>,
                                 <413 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
                    clock-names = "fck";
                    power-domains = <&cpg>;
                    resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and
  DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros.

DT binding [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80
---
 include/sbi_utils/fdt/fdt_helper.h         |  3 +++
 lib/utils/fdt/fdt_helper.c                 | 11 ++++++++
 lib/utils/serial/Kconfig                   |  5 ++++
 lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++
 lib/utils/serial/objects.mk                |  3 +++
 5 files changed, 53 insertions(+)
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c

diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
index c39f77a..09f3095 100644
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
 int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 				struct platform_uart_data *uart);
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart);
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);
 
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index d390436..8f2d619 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -23,6 +23,9 @@
 #define DEFAULT_UART_REG_IO_WIDTH	1
 #define DEFAULT_UART_REG_OFFSET		0
 
+#define DEFAULT_RENESAS_SCIF_FREQ		100000000
+#define DEFAULT_RENESAS_SCIF_BAUD		115200
+
 #define DEFAULT_SIFIVE_UART_FREQ		0
 #define DEFAULT_SIFIVE_UART_BAUD		115200
 #define DEFAULT_SIFIVE_UART_REG_SHIFT		0
@@ -370,6 +373,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 	return 0;
 }
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart)
+{
+	return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
+					  DEFAULT_RENESAS_SCIF_FREQ,
+					  DEFAULT_RENESAS_SCIF_BAUD);
+}
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart)
 {
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index f6ed803..e3589ca 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF
 	select SYS_HTIF
 	default n
 
+config FDT_SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF FDT driver"
+	select SERIAL_RENESAS_SCIF
+	default n
+
 config FDT_SERIAL_SHAKTI
 	bool "Shakti UART FDT driver"
 	select SERIAL_SHAKTI
diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c
new file mode 100644
index 0000000..c331ca1
--- /dev/null
+++ b/lib/utils/serial/fdt_serial_renesas_scif.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+static int serial_renesas_scif_init(void *fdt, int nodeoff,
+				    const struct fdt_match *match)
+{
+	struct platform_uart_data uart = { 0 };
+	int ret;
+
+	ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart);
+	if (ret)
+		return ret;
+
+	return renesas_scif_init(uart.addr, uart.freq, uart.baud);
+}
+
+static const struct fdt_match serial_renesas_scif_match[] = {
+	{ .compatible = "renesas,scif-r9a07g043" },
+	{ /* sentinel */ }
+};
+
+struct fdt_serial fdt_serial_renesas_scif = {
+	.match_table = serial_renesas_scif_match,
+	.init = serial_renesas_scif_init
+};
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 6520424..1e6bd2e 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o
 
+carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif
+libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o
+
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o
 
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:01 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:01 +0000
Subject: [PATCH v2 3/7] platform: andes/ae350: Split platform.h header file
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Split up the platform.h header file into
- platform.h #Contains platform specific macros
- common-platform.h #contains macros common across Andes platforms

This is in preparation for adding the Renesas RZ/Five SoC which is based
on Andes AX45MP core.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
RFC->v2
* Updated patch subject
* Included RB tag from Yu Chien Peter Lin
---
 platform/andes/ae350/common-platform.h | 94 ++++++++++++++++++++++++++
 platform/andes/ae350/platform.h        | 82 +---------------------
 2 files changed, 96 insertions(+), 80 deletions(-)
 create mode 100644 platform/andes/ae350/common-platform.h

diff --git a/platform/andes/ae350/common-platform.h b/platform/andes/ae350/common-platform.h
new file mode 100644
index 0000000..6334a2e
--- /dev/null
+++ b/platform/andes/ae350/common-platform.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Andes Technology Corporation
+ *
+ * Authors:
+ *   Zong Li <zong at andestech.com>
+ *   Nylon Chen <nylon7 at andestech.com>
+ */
+
+#ifndef _AE350_COMMON_PLATFORM_H_
+#define _AE350_COMMON_PLATFORM_H_
+
+/* Memory and Miscellaneous Registers */
+#define CSR_MILMB		0x7c0
+#define CSR_MDLMB		0x7c1
+#define CSR_MECC_CDOE		0x7c2
+#define CSR_MNVEC		0x7c3
+#define CSR_MPFTCTL		0x7c5
+#define CSR_MCACHECTL		0x7ca
+#define CSR_MCCTLBEGINADDR	0x7cb
+#define CSR_MCCTLCOMMAND	0x7cc
+#define CSR_MCCTLDATA		0x7cc
+#define CSR_SCCTLDATA		0x9cd
+#define CSR_UCCTLBEGINADDR	0x80c
+#define CSR_MMISCCTL		0x7d0
+
+/* nds v5 mmisc_ctl register*/
+#define V5_MMISC_CTL_VEC_PLIC_OFFSET		1
+#define V5_MMISC_CTL_RVCOMPM_OFFSET		2
+#define V5_MMISC_CTL_BRPE_OFFSET		3
+#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET		6
+#define V5_MMISC_CTL_NON_BLOCKING_OFFSET	8
+#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET	9
+#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET	10
+#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1	13
+#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2	14
+
+#define V5_MMISC_CTL_VEC_PLIC_EN	(1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
+#define V5_MMISC_CTL_RVCOMPM_EN		(1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
+#define V5_MMISC_CTL_BRPE_EN		(1UL << V5_MMISC_CTL_BRPE_OFFSET)
+#define V5_MMISC_CTL_MSA_OR_UNA_EN	(1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
+#define V5_MMISC_CTL_NON_BLOCKING_EN	(1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
+#define V5_MCACHE_CTL_L1I_PREFETCH_EN	(1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
+#define V5_MCACHE_CTL_L1D_PREFETCH_EN	(1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
+#define V5_MCACHE_CTL_DC_WAROUND_1_EN	(1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
+#define V5_MCACHE_CTL_DC_WAROUND_2_EN	(1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
+
+#define V5_MMISC_CTL_MASK	(V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN | \
+				 V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | \
+				 V5_MMISC_CTL_NON_BLOCKING_EN)
+
+/* nds mcache_ctl register */
+#define V5_MCACHE_CTL_IC_EN_OFFSET	0
+#define V5_MCACHE_CTL_DC_EN_OFFSET	1
+#define V5_MCACHE_CTL_IC_ECCEN_OFFSET	2
+#define V5_MCACHE_CTL_DC_ECCEN_OFFSET	4
+#define V5_MCACHE_CTL_IC_RWECC_OFFSET	6
+#define V5_MCACHE_CTL_DC_RWECC_OFFSET	7
+#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET	8
+
+/* nds cctl command */
+#define V5_UCCTL_L1D_WBINVAL_ALL	6
+#define V5_UCCTL_L1D_WB_ALL		7
+
+#define V5_MCACHE_CTL_IC_EN	(1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN	(1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_IC_RWECC	(1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
+#define V5_MCACHE_CTL_DC_RWECC	(1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
+#define V5_MCACHE_CTL_CCTL_SUEN	(1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
+
+#define V5_MCACHE_CTL_MASK	(V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN | \
+				 V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC | \
+				 V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN | \
+				 V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN | \
+				 V5_MCACHE_CTL_DC_WAROUND_2_EN)
+
+#define V5_L2C_CTL_OFFSET		0x8
+#define V5_L2C_CTL_ENABLE_OFFSET	0
+#define V5_L2C_CTL_IPFDPT_OFFSET	3
+#define V5_L2C_CTL_DPFDPT_OFFSET	5
+#define V5_L2C_CTL_TRAMOCTL_OFFSET	8
+#define V5_L2C_CTL_TRAMICTL_OFFSET	10
+#define V5_L2C_CTL_DRAMOCTL_OFFSET	11
+#define V5_L2C_CTL_DRAMICTL_OFFSET	13
+
+#define V5_L2C_CTL_ENABLE_MASK		(1UL << V5_L2C_CTL_ENABLE_OFFSET)
+#define V5_L2C_CTL_IPFDPT_MASK		(3UL << V5_L2C_CTL_IPFDPT_OFFSET)
+#define V5_L2C_CTL_DPFDPT_MASK		(3UL << V5_L2C_CTL_DPFDPT_OFFSET)
+#define V5_L2C_CTL_TRAMOCTL_MASK	(3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
+#define V5_L2C_CTL_TRAMICTL_MASK	(1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
+#define V5_L2C_CTL_DRAMOCTL_MASK	(3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
+#define V5_L2C_CTL_DRAMICTL_MASK	(1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
+
+#endif /* _AE350_COMMON_PLATFORM_H_ */
diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h
index 903bef0..45de792 100644
--- a/platform/andes/ae350/platform.h
+++ b/platform/andes/ae350/platform.h
@@ -11,21 +11,9 @@
 #ifndef _AE350_PLATFORM_H_
 #define _AE350_PLATFORM_H_
 
-#define AE350_L2C_ADDR			0xe0500000
+#include "common-platform.h"
 
-/*Memory and Miscellaneous Registers*/
-#define CSR_MILMB		0x7c0
-#define CSR_MDLMB		0x7c1
-#define CSR_MECC_CDOE		0x7c2
-#define CSR_MNVEC		0x7c3
-#define CSR_MPFTCTL		0x7c5
-#define CSR_MCACHECTL		0x7ca
-#define CSR_MCCTLBEGINADDR	0x7cb
-#define CSR_MCCTLCOMMAND	0x7cc
-#define CSR_MCCTLDATA		0x7cc
-#define CSR_SCCTLDATA		0x9cd
-#define CSR_UCCTLBEGINADDR	0x80c
-#define CSR_MMISCCTL		0x7d0
+#define AE350_L2C_ADDR			0xe0500000
 
 enum sbi_ext_andes_fid {
 	SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
@@ -40,70 +28,4 @@ enum sbi_ext_andes_fid {
 	SBI_EXT_ANDES_WRITE_AROUND,
 };
 
-/* nds v5 mmisc_ctl register*/
-#define V5_MMISC_CTL_VEC_PLIC_OFFSET            1
-#define V5_MMISC_CTL_RVCOMPM_OFFSET             2
-#define V5_MMISC_CTL_BRPE_OFFSET                3
-#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET          6
-#define V5_MMISC_CTL_NON_BLOCKING_OFFSET        8
-#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET       9
-#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET       10
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1       13
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2       14
-
-#define V5_MMISC_CTL_VEC_PLIC_EN        (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
-#define V5_MMISC_CTL_RVCOMPM_EN         (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
-#define V5_MMISC_CTL_BRPE_EN            (1UL << V5_MMISC_CTL_BRPE_OFFSET)
-#define V5_MMISC_CTL_MSA_OR_UNA_EN      (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
-#define V5_MMISC_CTL_NON_BLOCKING_EN    (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
-#define V5_MCACHE_CTL_L1I_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_L1D_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_DC_WAROUND_1_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
-#define V5_MCACHE_CTL_DC_WAROUND_2_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
-
-#define V5_MMISC_CTL_MASK  (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
-	| V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
-
-/* nds mcache_ctl register*/
-#define V5_MCACHE_CTL_IC_EN_OFFSET      0
-#define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_IC_ECCEN_OFFSET   2
-#define V5_MCACHE_CTL_DC_ECCEN_OFFSET   4
-#define V5_MCACHE_CTL_IC_RWECC_OFFSET   6
-#define V5_MCACHE_CTL_DC_RWECC_OFFSET   7
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET  8
-
-/*nds cctl command*/
-#define V5_UCCTL_L1D_WBINVAL_ALL 6
-#define V5_UCCTL_L1D_WB_ALL 7
-
-#define V5_MCACHE_CTL_IC_EN     (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN     (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_IC_RWECC  (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_DC_RWECC  (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-
-#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
-	| V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
-	| V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
-	| V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
-	| V5_MCACHE_CTL_DC_WAROUND_2_EN)
-
-#define V5_L2C_CTL_OFFSET           0x8
-#define V5_L2C_CTL_ENABLE_OFFSET    0
-#define V5_L2C_CTL_IPFDPT_OFFSET    3
-#define V5_L2C_CTL_DPFDPT_OFFSET    5
-#define V5_L2C_CTL_TRAMOCTL_OFFSET  8
-#define V5_L2C_CTL_TRAMICTL_OFFSET  10
-#define V5_L2C_CTL_DRAMOCTL_OFFSET  11
-#define V5_L2C_CTL_DRAMICTL_OFFSET  13
-
-#define V5_L2C_CTL_ENABLE_MASK      (1UL << V5_L2C_CTL_ENABLE_OFFSET)
-#define V5_L2C_CTL_IPFDPT_MASK      (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
-#define V5_L2C_CTL_DPFDPT_MASK      (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
-#define V5_L2C_CTL_TRAMOCTL_MASK    (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
-#define V5_L2C_CTL_TRAMICTL_MASK    (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
-#define V5_L2C_CTL_DRAMOCTL_MASK    (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
-#define V5_L2C_CTL_DRAMICTL_MASK    (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
-
 #endif /* _AE350_PLATFORM_H_ */
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:04 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:04 +0000
Subject: [PATCH v2 6/7] scripts: Add Renesas RZ/Five to platform list in the binary archive script
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-7-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

This patch adds Renesas RZ/Five (R9A07G043F) SoC to RV64 platform list in
the binary archive script.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* No change
---
 scripts/create-binary-archive.sh | 1 +
 1 file changed, 1 insertion(+)

diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index 261a45a..28a5b2f 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -104,6 +104,7 @@ build_opensbi() {
 		BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
 		BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
 		BUILD_PLATFORM_SUBDIR+=("andes/ae350")
+		BUILD_PLATFORM_SUBDIR+=("renesas/rzfive")
 		BUILD_PLATFORM_SUBDIR+=("generic")
 		;;
 	*)
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:03 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:03 +0000
Subject: [PATCH v2 5/7] platform: Add Renesas RZ/Five initial support
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* Updated commit description
---
 platform/renesas/rzfive/Kconfig           |  32 +++++
 platform/renesas/rzfive/configs/defconfig |   0
 platform/renesas/rzfive/objects.mk        |  18 +++
 platform/renesas/rzfive/platform.c        | 161 ++++++++++++++++++++++
 platform/renesas/rzfive/platform.h        |  24 ++++
 5 files changed, 235 insertions(+)
 create mode 100644 platform/renesas/rzfive/Kconfig
 create mode 100644 platform/renesas/rzfive/configs/defconfig
 create mode 100644 platform/renesas/rzfive/objects.mk
 create mode 100644 platform/renesas/rzfive/platform.c
 create mode 100644 platform/renesas/rzfive/platform.h

diff --git a/platform/renesas/rzfive/Kconfig b/platform/renesas/rzfive/Kconfig
new file mode 100644
index 0000000..c5e8a19
--- /dev/null
+++ b/platform/renesas/rzfive/Kconfig
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: BSD-2-Clause
+
+config PLATFORM_RENESAS_RZFIVE
+	bool
+	select FDT
+	select FDT_SERIAL
+	select FDT_SERIAL_RENESAS_SCIF
+	select FDT_TIMER
+	select FDT_TIMER_PLMT
+	select FDT_IRQCHIP
+	select FDT_IRQCHIP_PLIC
+	select FDT_IPI
+	select FDT_IPI_PLICSW
+	default y
+
+if PLATFORM_RENESAS_RZFIVE
+
+config PLATFORM_RENESAS_RZFIVE_NAME
+	string "Platform default name"
+	default "Renesas RZ/Five"
+
+config PLATFORM_RENESAS_RZFIVE_MAJOR_VER
+	int "Platform major version"
+	range 0 65535
+	default 0
+
+config PLATFORM_RENESAS_RZFIVE_MINOR_VER
+	int "Platform minor version"
+	range 0 65535
+	default 1
+
+endif
diff --git a/platform/renesas/rzfive/configs/defconfig b/platform/renesas/rzfive/configs/defconfig
new file mode 100644
index 0000000..e69de29
diff --git a/platform/renesas/rzfive/objects.mk b/platform/renesas/rzfive/objects.mk
new file mode 100644
index 0000000..302b3d6
--- /dev/null
+++ b/platform/renesas/rzfive/objects.mk
@@ -0,0 +1,18 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2022 Renesas Electronics Corp.
+#
+
+# Compiler flags
+platform-cppflags-y =
+platform-cflags-y =
+platform-asflags-y =
+platform-ldflags-y =
+
+# Objects to build
+platform-objs-y += ../../andes/ae350/cache.o platform.o
+
+# Blobs to build
+FW_TEXT_START=0x00000000
+FW_DYNAMIC=y
diff --git a/platform/renesas/rzfive/platform.c b/platform/renesas/rzfive/platform.c
new file mode 100644
index 0000000..cfc557c
--- /dev/null
+++ b/platform/renesas/rzfive/platform.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Based on platform/andes/ae350/platform.c
+ * Copyright (c) 2019 Andes Technology Corporation
+ */
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_ipi.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_trap.h>
+#include <sbi_utils/fdt/fdt_domain.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/timer/fdt_timer.h>
+
+#include "../../andes/ae350/cache.h"
+
+#include "platform.h"
+
+struct sbi_platform platform;
+unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
+			       unsigned long arg2, unsigned long arg3,
+			       unsigned long arg4)
+{
+	const char *model;
+	void *fdt = (void *)arg1;
+	u32 hartid, hart_count = 0;
+	int rc, root_offset, cpus_offset, cpu_offset, len;
+
+	root_offset = fdt_path_offset(fdt, "/");
+	if (root_offset < 0)
+		goto fail;
+
+	model = fdt_getprop(fdt, root_offset, "model", &len);
+	if (model)
+		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
+
+	cpus_offset = fdt_path_offset(fdt, "/cpus");
+	if (cpus_offset < 0)
+		goto fail;
+
+	fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
+		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
+		if (rc)
+			continue;
+
+		if (SBI_HARTMASK_MAX_BITS <= hartid)
+			continue;
+
+		hart_count++;
+	}
+
+	platform.hart_count = hart_count;
+
+	/* Return original FDT pointer */
+	return arg1;
+
+fail:
+	while (1)
+		wfi();
+}
+
+/* Platform final initialization. */
+static int rzfive_final_init(bool cold_boot)
+{
+	void *fdt;
+
+	if (!cold_boot)
+		return 0;
+
+	fdt = fdt_get_address();
+	fdt_fixups(fdt);
+	fdt_domain_fixup(fdt);
+
+	return 0;
+}
+
+/* Vendor-Specific SBI handler */
+static int rzfive_vendor_ext_provider(long extid, long funcid,
+				      const struct sbi_trap_regs *regs,
+				      unsigned long *out_value,
+				      struct sbi_trap_info *out_trap)
+{
+	int ret = 0;
+
+	switch (funcid) {
+	case SBI_EXT_RENESAS_RZFIVE_GET_MCACHE_CTL_STATUS:
+		*out_value = csr_read(CSR_MCACHECTL);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_GET_MMISC_CTL_STATUS:
+		*out_value = csr_read(CSR_MMISCCTL);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_SET_MCACHE_CTL:
+		ret = mcall_set_mcache_ctl(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_SET_MMISC_CTL:
+		ret = mcall_set_mmisc_ctl(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_ICACHE_OP:
+		ret = mcall_icache_op(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_DCACHE_OP:
+		ret = mcall_dcache_op(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_L1CACHE_I_PREFETCH:
+		ret = mcall_l1_cache_i_prefetch_op(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_L1CACHE_D_PREFETCH:
+		ret = mcall_l1_cache_d_prefetch_op(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_NON_BLOCKING_LOAD_STORE:
+		ret = mcall_non_blocking_load_store(regs->a0);
+		break;
+	case SBI_EXT_RENESAS_RZFIVE_WRITE_AROUND:
+		ret = mcall_write_around(regs->a0);
+		break;
+	default:
+		sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
+		asm volatile("ebreak");
+	}
+
+	return ret;
+}
+
+static int rzfive_domains_init(void)
+{
+	return fdt_domains_populate(fdt_get_address());
+}
+
+/* Platform descriptor. */
+static const struct sbi_platform_operations platform_ops = {
+	.final_init		= rzfive_final_init,
+	.domains_init		= rzfive_domains_init,
+	.console_init		= fdt_serial_init,
+	.irqchip_init		= fdt_irqchip_init,
+	.ipi_init		= fdt_ipi_init,
+	.timer_init		= fdt_timer_init,
+	.vendor_ext_provider	= rzfive_vendor_ext_provider
+};
+
+struct sbi_platform platform = {
+	.opensbi_version = OPENSBI_VERSION,
+	.platform_version =
+		SBI_PLATFORM_VERSION(CONFIG_PLATFORM_RENESAS_RZFIVE_MAJOR_VER,
+				     CONFIG_PLATFORM_RENESAS_RZFIVE_MINOR_VER),
+	.name = CONFIG_PLATFORM_RENESAS_RZFIVE_NAME,
+	.features = SBI_PLATFORM_DEFAULT_FEATURES,
+	.hart_count = SBI_HARTMASK_MAX_BITS,
+	.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
+	.platform_ops_addr = (unsigned long)&platform_ops
+};
diff --git a/platform/renesas/rzfive/platform.h b/platform/renesas/rzfive/platform.h
new file mode 100644
index 0000000..e46ca91
--- /dev/null
+++ b/platform/renesas/rzfive/platform.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#ifndef _RZFIVE_PLATFORM_H_
+#define _RZFIVE_PLATFORM_H_
+
+#include "../../andes/ae350/common-platform.h"
+
+enum sbi_ext_andes_fid {
+	SBI_EXT_RENESAS_RZFIVE_GET_MCACHE_CTL_STATUS = 0,
+	SBI_EXT_RENESAS_RZFIVE_GET_MMISC_CTL_STATUS,
+	SBI_EXT_RENESAS_RZFIVE_SET_MCACHE_CTL,
+	SBI_EXT_RENESAS_RZFIVE_SET_MMISC_CTL,
+	SBI_EXT_RENESAS_RZFIVE_ICACHE_OP,
+	SBI_EXT_RENESAS_RZFIVE_DCACHE_OP,
+	SBI_EXT_RENESAS_RZFIVE_L1CACHE_I_PREFETCH,
+	SBI_EXT_RENESAS_RZFIVE_L1CACHE_D_PREFETCH,
+	SBI_EXT_RENESAS_RZFIVE_NON_BLOCKING_LOAD_STORE,
+	SBI_EXT_RENESAS_RZFIVE_WRITE_AROUND,
+};
+
+#endif /* _RZFIVE_PLATFORM_H_ */
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:02 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:02 +0000
Subject: [PATCH v2 4/7] lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.

While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.

dts example (Single-core AX45MP):

    soc: soc {
          ....
          plic: interrupt-controller at 12c00000 {
              compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
              #interrupt-cells = <2>;
              #address-cells = <0>;
              riscv,ndev = <511>;
              interrupt-controller;
              reg = <0x0 0x12c00000 0 0x400000>;
              clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
              power-domains = <&cpg>;
              resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
              interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
          };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* No change

DT binding [0]
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..83d091a 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -163,7 +163,8 @@ static const struct fdt_match irqchip_plic_match[] = {
 	{ .compatible = "sifive,plic-1.0.0" },
 	{ .compatible = "thead,c900-plic",
 	  .data = thead_plic_plat_init },
-	{ },
+	{ .compatible = "andestech,nceplic100" },
+	{ /* sentinel */ }
 };
 
 struct fdt_irqchip fdt_irqchip_plic = {
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 11 10:21:05 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri, 11 Nov 2022 18:21:05 +0000
Subject: [PATCH v2 7/7] docs: platform: Add documentation for Renesas RZ/Five SoC
In-Reply-To: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221111182105.614094-8-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
RFC->v2
* Updated doc
---
 docs/platform/platform.md       |   5 ++
 docs/platform/renesas-rzfive.md | 143 ++++++++++++++++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 docs/platform/renesas-rzfive.md

diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index f291931..4504d87 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
 
+* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
+  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
+  be found in the file *[renesas-rzfive.md]*.
+
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *objects.mk*,
@@ -54,3 +58,4 @@ comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
+[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
new file mode 100644
index 0000000..94c7654
--- /dev/null
+++ b/docs/platform/renesas-rzfive.md
@@ -0,0 +1,143 @@
+Renesas RZ/Five SoC (R9A07G043F) Platform
+=========================================
+The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
+1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
+- Gigabit Ethernet 2ch
+- CAN interface (CAN-FD) 2ch
+- USB 2.0 interface 2ch
+- SD interface 2ch
+- AD converter 2ch
+making it ideal for applications such as entry-class social infrastructure
+gateway control and industrial gateway control.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=renesas/rzfive* parameter to the top level make command.
+
+Platform Options
+----------------
+
+The Renesas RZ/Five platform does not have any platform-specific options.
+
+Building Renesas RZ/Five Platform
+---------------------------------
+
+```
+make PLATFORM=renesas/rzfive
+```
+
+DTS Example: (RZ/Five AX45MP)
+-----------------------------
+
+```
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <12000000>;
+
+		cpu0: cpu at 0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ranges;
+
+		scif0: serial at 1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller at 11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller at 11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl at 11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plmt0: plmt0 at 110c0000 {
+			compatible = "andestech,plmt0", "riscv,plmt0";
+			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
+			interrupts-extended = <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller at 12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <511>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+
+		plicsw: interrupt-controller at 13000000 {
+			compatible = "andestech,plicsw";
+			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
+			interrupts-extended = <&cpu0_intc 3>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+		};
+	};
+```
-- 
2.17.1



From atishp at atishpatra.org  Sat Nov 12 00:48:43 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:48:43 -0800
Subject: [RFC PATCH 0/3] OpenSBI debug console support
In-Reply-To: <20221110170016.1477865-1-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
Message-ID: <CAOnJCULX39RtWh=r4jBvDeJBb7fBnZ0xq=GDsM8=p39hxdnTkg@mail.gmail.com>

On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> The latest draft-v4 proposal of SBI debug console can be found here:
> https://lists.riscv.org/g/tech-unixplatformspec/message/1815
>

Can you send it as a patch to the tec-prs mailing list in the adoc
format as well ?

> This series implements SBI debug console support in OpenSBI
> as-per above draft proposal.
>
> These patches can also be found in riscv_sbi_dbcn_v1 branch
> at: https://github.com/avpatel/opensbi.git
>
> Anup Patel (3):
>   include: Add defines for SBI debug console extension
>   lib: sbi: Add sbi_nputs() function
>   lib: sbi: Implement SBI debug console extension
>
>  include/sbi/sbi_console.h         |  2 ++
>  include/sbi/sbi_ecall_interface.h |  4 ++++
>  lib/sbi/Kconfig                   |  4 ++++
>  lib/sbi/objects.mk                |  1 +
>  lib/sbi/sbi_console.c             | 10 ++++++++++
>  lib/sbi/sbi_ecall_replace.c       | 30 ++++++++++++++++++++++++++++++
>  6 files changed, 51 insertions(+)
>
> --
> 2.34.1
>


-- 
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 00:49:14 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:49:14 -0800
Subject: [RFC PATCH 1/3] include: Add defines for SBI debug console extension
In-Reply-To: <20221110170016.1477865-2-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com> <20221110170016.1477865-2-apatel@ventanamicro.com>
Message-ID: <CAOnJCUJ6seDva3+4i=KgAvOyyMm8zco9y7ORjHN6XMpw2W=5WQ@mail.gmail.com>

On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add SBI debug console extension related defines/enum to the
> SBI ecall interface header.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_ecall_interface.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index a3f2bf4..1dd3874 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -29,6 +29,7 @@
>  #define SBI_EXT_HSM                            0x48534D
>  #define SBI_EXT_SRST                           0x53525354
>  #define SBI_EXT_PMU                            0x504D55
> +#define SBI_EXT_DBCN                           0x4442434E
>
>  /* SBI function IDs for BASE extension*/
>  #define SBI_EXT_BASE_GET_SPEC_VERSION          0x0
> @@ -230,6 +231,9 @@ enum sbi_pmu_ctr_type {
>  /* Flags defined for counter stop function */
>  #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
>
> +/* SBI function IDs for DBCN extension */
> +#define SBI_EXT_DBCN_CONSOLE_PUTS              0x0
> +
>  /* SBI base specification related macros */
>  #define SBI_SPEC_VERSION_MAJOR_OFFSET          24
>  #define SBI_SPEC_VERSION_MAJOR_MASK            0x7f
> --
> 2.34.1
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 00:49:46 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:49:46 -0800
Subject: [RFC PATCH 2/3] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221110170016.1477865-3-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com> <20221110170016.1477865-3-apatel@ventanamicro.com>
Message-ID: <CAOnJCUKu7EqzsoKxqdcO=MqkvRQXbcJKS3wJRO457Ce1QuXSfQ@mail.gmail.com>

On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add new sbi_nputs() which help us print a fixed number of characters
> from a physical memory location.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_console.h |  2 ++
>  lib/sbi/sbi_console.c     | 10 ++++++++++
>  2 files changed, 12 insertions(+)
>
> diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
> index e15b55d..1bdeeb9 100644
> --- a/include/sbi/sbi_console.h
> +++ b/include/sbi/sbi_console.h
> @@ -33,6 +33,8 @@ void sbi_putc(char ch);
>
>  void sbi_puts(const char *str);
>
> +void sbi_nputs(const char *str, unsigned long len);
> +
>  void sbi_gets(char *s, int maxwidth, char endchar);
>
>  int __printf(2, 3) sbi_sprintf(char *out, const char *format, ...);
> diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> index cfef2f8..a975708 100644
> --- a/lib/sbi/sbi_console.c
> +++ b/lib/sbi/sbi_console.c
> @@ -51,6 +51,16 @@ void sbi_puts(const char *str)
>         spin_unlock(&console_out_lock);
>  }
>
> +void sbi_nputs(const char *str, unsigned long len)
> +{
> +       unsigned long i;
> +
> +       spin_lock(&console_out_lock);
> +       for (i = 0; i < len; i++)
> +               sbi_putc(str[i]);
> +       spin_unlock(&console_out_lock);
> +}
> +
>  void sbi_gets(char *s, int maxwidth, char endchar)
>  {
>         int ch;
> --
> 2.34.1
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 00:54:12 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:54:12 -0800
Subject: [RFC PATCH 3/3] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221110170016.1477865-4-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com> <20221110170016.1477865-4-apatel@ventanamicro.com>
Message-ID: <CAOnJCU+zKsen8RFmsJn4e65GBgQKdrtNoQAZqU3vq3noqS4P0g@mail.gmail.com>

On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We implement SBI debug console extension as one of the replacement
> SBI extensions. This extension is only available when OpenSBI platform
> provides a console device to generic library.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/sbi/Kconfig             |  4 ++++
>  lib/sbi/objects.mk          |  1 +
>  lib/sbi/sbi_ecall_replace.c | 30 ++++++++++++++++++++++++++++++
>  3 files changed, 35 insertions(+)
>
> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> index df74bba..ef6728b 100644
> --- a/lib/sbi/Kconfig
> +++ b/lib/sbi/Kconfig
> @@ -26,6 +26,10 @@ config SBI_ECALL_PMU
>         bool "Performance Monitoring Unit extension"
>         default y
>
> +config SBI_ECALL_DBCN
> +       bool "Debug Console extension"
> +       default y
> +
>  config SBI_ECALL_LEGACY
>         bool "SBI v0.1 legacy extensions"
>         default y
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index 783c46d..7ccad52 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -23,6 +23,7 @@ carray-sbi_ecall_exts-y += ecall_base
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
>
> diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_replace.c
> index 0ea00d6..a092e2f 100644
> --- a/lib/sbi/sbi_ecall_replace.c
> +++ b/lib/sbi/sbi_ecall_replace.c
> @@ -9,6 +9,7 @@
>   */
>
>  #include <sbi/riscv_asm.h>
> +#include <sbi/sbi_console.h>
>  #include <sbi/sbi_ecall.h>
>  #include <sbi/sbi_ecall_interface.h>
>  #include <sbi/sbi_error.h>
> @@ -202,3 +203,32 @@ struct sbi_ecall_extension ecall_srst = {
>         .probe = sbi_ecall_srst_probe,
>  };
>  #endif
> +
> +#ifdef CONFIG_SBI_ECALL_DBCN
> +static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
> +                                 const struct sbi_trap_regs *regs,
> +                                 unsigned long *out_val,
> +                                 struct sbi_trap_info *out_trap)
> +{
> +       if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
> +               /* TODO: sanity check on the physical address range */

We need PMP validation to ensure that it is not one of the M-mode
reserved addresses.
What else needed to be done here ?

> +               sbi_nputs((const char *)regs->a1, regs->a0);
> +               return 0;
> +       }
> +
> +       return SBI_ENOTSUPP;
> +}
> +
> +static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
> +{
> +       *out_val = (sbi_console_get_device()) ? 1 : 0;
> +       return 0;
> +}
> +
> +struct sbi_ecall_extension ecall_dbcn = {
> +       .extid_start = SBI_EXT_DBCN,
> +       .extid_end = SBI_EXT_DBCN,
> +       .handle = sbi_ecall_dbcn_handler,
> +       .probe = sbi_ecall_dbcn_probe,
> +};
> +#endif
> --
> 2.34.1
>


--
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 00:55:31 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:55:31 -0800
Subject: [PATCH 1/2] lib: utils/fdt: Remove redundant code
In-Reply-To: <20221031112145.126615-2-wxjstz@126.com>
References: <20221031112145.126615-1-wxjstz@126.com> <20221031112145.126615-2-wxjstz@126.com>
Message-ID: <CAOnJCUJH_738YLvF27+ybLCHdztwL-71Y9msQUHSGz7dPfXpmg@mail.gmail.com>

On Mon, Oct 31, 2022 at 4:22 AM Xiang W <wxjstz at 126.com> wrote:
>
> uart->reg_offset and uart->reg_io_width are only used on uart8250 and
> not required on other platforms. Remove for sifive and gaisler.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
>  lib/utils/fdt/fdt_helper.c | 12 ------------
>  1 file changed, 12 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index d390436..cdd0b35 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -25,10 +25,6 @@
>
>  #define DEFAULT_SIFIVE_UART_FREQ               0
>  #define DEFAULT_SIFIVE_UART_BAUD               115200
> -#define DEFAULT_SIFIVE_UART_REG_SHIFT          0
> -#define DEFAULT_SIFIVE_UART_REG_IO_WIDTH       4
> -
> -#define DEFAULT_GAISLER_UART_REG_IO_WIDTH      4
>
>  #define DEFAULT_SHAKTI_UART_FREQ               50000000
>  #define DEFAULT_SHAKTI_UART_BAUD               115200
> @@ -363,10 +359,6 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>         if (rc)
>                 return rc;
>
> -       /* For Gaisler APBUART, the reg-shift and reg-io-width are fixed .*/
> -       uart->reg_shift    = DEFAULT_UART_REG_SHIFT;
> -       uart->reg_io_width = DEFAULT_GAISLER_UART_REG_IO_WIDTH;
> -
>         return 0;
>  }
>
> @@ -394,10 +386,6 @@ int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
>         if (rc)
>                 return rc;
>
> -       /* For SiFive UART, the reg-shift and reg-io-width are fixed .*/
> -       uart->reg_shift = DEFAULT_SIFIVE_UART_REG_SHIFT;
> -       uart->reg_io_width = DEFAULT_SIFIVE_UART_REG_IO_WIDTH;
> -
>         return 0;
>  }
>
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 00:57:52 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 00:57:52 -0800
Subject: [PATCH 2/2] lib: utils/fdt: Simplified code
In-Reply-To: <20221031112145.126615-3-wxjstz@126.com>
References: <20221031112145.126615-1-wxjstz@126.com> <20221031112145.126615-3-wxjstz@126.com>
Message-ID: <CAOnJCULovR8eiD8LEaa5QZF4Trb3SSrktffPGh6d72oTw+xUnA@mail.gmail.com>

On Mon, Oct 31, 2022 at 4:22 AM Xiang W <wxjstz at 126.com> wrote:
>
> Simplified fdt_parse_xxx_uart_node which direct call
> fdt_parse_uart_node_common.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
>  lib/utils/fdt/fdt_helper.c | 28 ++++------------------------
>  1 file changed, 4 insertions(+), 24 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index cdd0b35..72d8635 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -350,43 +350,27 @@ static int fdt_parse_uart_node_common(void *fdt, int nodeoffset,
>  int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>                                 struct platform_uart_data *uart)
>  {
> -       int rc;
>
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_UART_FREQ,
>                                         DEFAULT_UART_BAUD);
> -
> -       if (rc)
> -               return rc;
> -
> -       return 0;
>  }
>
>  int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
>
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_SHAKTI_UART_FREQ,
>                                         DEFAULT_SHAKTI_UART_BAUD);
> -
> -       return rc ? : 0;
>  }
>
>  int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
> -
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_SIFIVE_UART_FREQ,
>                                         DEFAULT_SIFIVE_UART_BAUD);
> -
> -       if (rc)
> -               return rc;
> -
> -       return 0;
>  }
>
>  int fdt_parse_uart_node(void *fdt, int nodeoffset,
> @@ -441,11 +425,7 @@ int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
>  int fdt_parse_xlnx_uartlite_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
> -
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart, 0, 0);
> -
> -       return rc ? : 0;
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart, 0, 0);
>  }
>
>  int fdt_parse_aplic_node(void *fdt, int nodeoff, struct aplic_data *aplic)
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From atishp at atishpatra.org  Sat Nov 12 01:03:52 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 12 Nov 2022 01:03:52 -0800
Subject: [PATCH] firmware: payloads: Remove duplicate "ALIGN"
In-Reply-To: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
References: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
Message-ID: <CAOnJCUKHVmGCZQpMdMprAWsPn6U5E4uABpSmbYq5Yo+26iNuyg@mail.gmail.com>

On Tue, Nov 8, 2022 at 2:11 AM <1220749046 at qq.com> wrote:
>
> From: zhangleizheng <zhangleizheng at eswincomputing.com>
>
> ". = ALIGN(0x1000)" is used redundantly in firmware/fw_base.ldS
> and fw_base.ldS files.
>
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
> ---
>  firmware/fw_base.ldS           | 2 --
>  firmware/payloads/test.elf.ldS | 2 --
>  2 files changed, 4 deletions(-)
>
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 220c043..382da25 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -24,8 +24,6 @@
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */
>
>         /* Beginning of the read-only data sections */
> diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
> index f3f3242..763103c 100644
> --- a/firmware/payloads/test.elf.ldS
> +++ b/firmware/payloads/test.elf.ldS
> @@ -33,8 +33,6 @@ SECTIONS
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */
>
>         /* Beginning of the read-only data sections */
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Good catch.

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From wxjstz at 126.com  Sat Nov 12 06:58:39 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 12 Nov 2022 22:58:39 +0800
Subject: [RFC PATCH 3/3] lib: sbi: Implement SBI debug console extension
In-Reply-To: <CAOnJCU+zKsen8RFmsJn4e65GBgQKdrtNoQAZqU3vq3noqS4P0g@mail.gmail.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
	 <20221110170016.1477865-4-apatel@ventanamicro.com>
	 <CAOnJCU+zKsen8RFmsJn4e65GBgQKdrtNoQAZqU3vq3noqS4P0g@mail.gmail.com>
Message-ID: <46cd84e0e4a2a62710b00f77fae307f5a7eb9922.camel@126.com>

? 2022-11-12???? 00:54 -0800?Atish Patra???
> On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
> > 
> > We implement SBI debug console extension as one of the replacement
> > SBI extensions. This extension is only available when OpenSBI platform
> > provides a console device to generic library.
> > 
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> > ?lib/sbi/Kconfig???????????? |? 4 ++++
> > ?lib/sbi/objects.mk????????? |? 1 +
> > ?lib/sbi/sbi_ecall_replace.c | 30 ++++++++++++++++++++++++++++++
> > ?3 files changed, 35 insertions(+)
> > 
> > diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> > index df74bba..ef6728b 100644
> > --- a/lib/sbi/Kconfig
> > +++ b/lib/sbi/Kconfig
> > @@ -26,6 +26,10 @@ config SBI_ECALL_PMU
> > ??????? bool "Performance Monitoring Unit extension"
> > ??????? default y
> > 
> > +config SBI_ECALL_DBCN
> > +?????? bool "Debug Console extension"
> > +?????? default y
> > +
> > ?config SBI_ECALL_LEGACY
> > ??????? bool "SBI v0.1 legacy extensions"
> > ??????? default y
> > diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> > index 783c46d..7ccad52 100644
> > --- a/lib/sbi/objects.mk
> > +++ b/lib/sbi/objects.mk
> > @@ -23,6 +23,7 @@ carray-sbi_ecall_exts-y += ecall_base
> > ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
> > ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
> > ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
> > +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
> > ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
> > ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
> > 
> > diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_replace.c
> > index 0ea00d6..a092e2f 100644
> > --- a/lib/sbi/sbi_ecall_replace.c
> > +++ b/lib/sbi/sbi_ecall_replace.c
> > @@ -9,6 +9,7 @@
> > ? */
> > 
> > ?#include <sbi/riscv_asm.h>
> > +#include <sbi/sbi_console.h>
> > ?#include <sbi/sbi_ecall.h>
> > ?#include <sbi/sbi_ecall_interface.h>
> > ?#include <sbi/sbi_error.h>
> > @@ -202,3 +203,32 @@ struct sbi_ecall_extension ecall_srst = {
> > ??????? .probe = sbi_ecall_srst_probe,
> > ?};
> > ?#endif
> > +
> > +#ifdef CONFIG_SBI_ECALL_DBCN
> > +static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
> > +???????????????????????????????? const struct sbi_trap_regs *regs,
> > +???????????????????????????????? unsigned long *out_val,
> > +???????????????????????????????? struct sbi_trap_info *out_trap)
> > +{
> > +?????? if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
> > +?????????????? /* TODO: sanity check on the physical address range */
> 
> We need PMP validation to ensure that it is not one of the M-mode
> reserved addresses.
> What else needed to be done here ?

We also need to confirm that this memory is not mmio.

We can imitate sbi_domain_check_addr to create sbi_domain_check_range for
range checking.

Regards,
Xiang W

> 
> > +?????????????? sbi_nputs((const char *)regs->a1, regs->a0);
> > +?????????????? return 0;
> > +?????? }
> > +
> > +?????? return SBI_ENOTSUPP;
> > +}
> > +
> > +static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
> > +{
> > +?????? *out_val = (sbi_console_get_device()) ? 1 : 0;
> > +?????? return 0;
> > +}
> > +
> > +struct sbi_ecall_extension ecall_dbcn = {
> > +?????? .extid_start = SBI_EXT_DBCN,
> > +?????? .extid_end = SBI_EXT_DBCN,
> > +?????? .handle = sbi_ecall_dbcn_handler,
> > +?????? .probe = sbi_ecall_dbcn_probe,
> > +};
> > +#endif
> > --
> > 2.34.1
> > 
> 
> 
> --
> Regards,
> Atish
> 




From apatel at ventanamicro.com  Sat Nov 12 08:32:42 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Sat, 12 Nov 2022 22:02:42 +0530
Subject: [RFC PATCH 3/3] lib: sbi: Implement SBI debug console extension
In-Reply-To: <CAOnJCU+zKsen8RFmsJn4e65GBgQKdrtNoQAZqU3vq3noqS4P0g@mail.gmail.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
 <20221110170016.1477865-4-apatel@ventanamicro.com> <CAOnJCU+zKsen8RFmsJn4e65GBgQKdrtNoQAZqU3vq3noqS4P0g@mail.gmail.com>
Message-ID: <CAK9=C2XNt6dBJJTrfqsPwK8-zyG2tDL6dYyjsb7moCFRbDfA8Q@mail.gmail.com>

On Sat, Nov 12, 2022 at 2:24 PM Atish Patra <atishp at atishpatra.org> wrote:
>
> On Thu, Nov 10, 2022 at 9:01 AM Anup Patel <apatel at ventanamicro.com> wrote:
> >
> > We implement SBI debug console extension as one of the replacement
> > SBI extensions. This extension is only available when OpenSBI platform
> > provides a console device to generic library.
> >
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> >  lib/sbi/Kconfig             |  4 ++++
> >  lib/sbi/objects.mk          |  1 +
> >  lib/sbi/sbi_ecall_replace.c | 30 ++++++++++++++++++++++++++++++
> >  3 files changed, 35 insertions(+)
> >
> > diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> > index df74bba..ef6728b 100644
> > --- a/lib/sbi/Kconfig
> > +++ b/lib/sbi/Kconfig
> > @@ -26,6 +26,10 @@ config SBI_ECALL_PMU
> >         bool "Performance Monitoring Unit extension"
> >         default y
> >
> > +config SBI_ECALL_DBCN
> > +       bool "Debug Console extension"
> > +       default y
> > +
> >  config SBI_ECALL_LEGACY
> >         bool "SBI v0.1 legacy extensions"
> >         default y
> > diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> > index 783c46d..7ccad52 100644
> > --- a/lib/sbi/objects.mk
> > +++ b/lib/sbi/objects.mk
> > @@ -23,6 +23,7 @@ carray-sbi_ecall_exts-y += ecall_base
> >  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
> >  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
> >  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
> > +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
> >  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
> >  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
> >
> > diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_replace.c
> > index 0ea00d6..a092e2f 100644
> > --- a/lib/sbi/sbi_ecall_replace.c
> > +++ b/lib/sbi/sbi_ecall_replace.c
> > @@ -9,6 +9,7 @@
> >   */
> >
> >  #include <sbi/riscv_asm.h>
> > +#include <sbi/sbi_console.h>
> >  #include <sbi/sbi_ecall.h>
> >  #include <sbi/sbi_ecall_interface.h>
> >  #include <sbi/sbi_error.h>
> > @@ -202,3 +203,32 @@ struct sbi_ecall_extension ecall_srst = {
> >         .probe = sbi_ecall_srst_probe,
> >  };
> >  #endif
> > +
> > +#ifdef CONFIG_SBI_ECALL_DBCN
> > +static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
> > +                                 const struct sbi_trap_regs *regs,
> > +                                 unsigned long *out_val,
> > +                                 struct sbi_trap_info *out_trap)
> > +{
> > +       if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
> > +               /* TODO: sanity check on the physical address range */
>
> We need PMP validation to ensure that it is not one of the M-mode
> reserved addresses.
> What else needed to be done here ?

Yes, I need to add required checks here.

Regards,
Anup

>
> > +               sbi_nputs((const char *)regs->a1, regs->a0);
> > +               return 0;
> > +       }
> > +
> > +       return SBI_ENOTSUPP;
> > +}
> > +
> > +static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
> > +{
> > +       *out_val = (sbi_console_get_device()) ? 1 : 0;
> > +       return 0;
> > +}
> > +
> > +struct sbi_ecall_extension ecall_dbcn = {
> > +       .extid_start = SBI_EXT_DBCN,
> > +       .extid_end = SBI_EXT_DBCN,
> > +       .handle = sbi_ecall_dbcn_handler,
> > +       .probe = sbi_ecall_dbcn_probe,
> > +};
> > +#endif
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish


From bmeng.cn at gmail.com  Mon Nov 14 05:52:16 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Mon, 14 Nov 2022 21:52:16 +0800
Subject: [RFC PATCH 1/3] include: Add defines for SBI debug console extension
In-Reply-To: <20221110170016.1477865-2-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com> <20221110170016.1477865-2-apatel@ventanamicro.com>
Message-ID: <CAEUhbmUhpNbn6cc5sQdnm8u9YcBV3vEie3-CARfJ9aNkfTP5wg@mail.gmail.com>

On Fri, Nov 11, 2022 at 1:02 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add SBI debug console extension related defines/enum to the
> SBI ecall interface header.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_ecall_interface.h | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Mon Nov 14 05:52:22 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Mon, 14 Nov 2022 21:52:22 +0800
Subject: [RFC PATCH 2/3] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221110170016.1477865-3-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com> <20221110170016.1477865-3-apatel@ventanamicro.com>
Message-ID: <CAEUhbmX=BBOs=MzA37uvbzGdu=+DFueQ8ZCW=jS3DHvT4K9oog@mail.gmail.com>

On Fri, Nov 11, 2022 at 1:03 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add new sbi_nputs() which help us print a fixed number of characters
> from a physical memory location.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_console.h |  2 ++
>  lib/sbi/sbi_console.c     | 10 ++++++++++
>  2 files changed, 12 insertions(+)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Mon Nov 14 08:06:14 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 15 Nov 2022 00:06:14 +0800
Subject: [PATCH] firmware: payloads: Remove duplicate "ALIGN"
In-Reply-To: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
References: <tencent_A5A2CFBAF1C09F3968C9EB028F1242CCD60A@qq.com>
Message-ID: <CAEUhbmX3fnzc5WL=Z+M4oYvGVCgYPxSOogMyKQU2Msn4sE9_4A@mail.gmail.com>

On Tue, Nov 8, 2022 at 6:12 PM <1220749046 at qq.com> wrote:
>
> From: zhangleizheng <zhangleizheng at eswincomputing.com>

nits: please use <First Name> <Last Name> format as the git user.name

>
> ". = ALIGN(0x1000)" is used redundantly in firmware/fw_base.ldS
> and fw_base.ldS files.

and firmware/payloads/test.elf.ldS files

>
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
> ---
>  firmware/fw_base.ldS           | 2 --
>  firmware/payloads/test.elf.ldS | 2 --
>  2 files changed, 4 deletions(-)
>
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 220c043..382da25 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -24,8 +24,6 @@
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */

nits: I would put ". = ALIGN(0x1000)" here in between the comments

and fix other ". = ALIGN(0x1000)" locations in this file too.

>
>         /* Beginning of the read-only data sections */
> diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
> index f3f3242..763103c 100644
> --- a/firmware/payloads/test.elf.ldS
> +++ b/firmware/payloads/test.elf.ldS
> @@ -33,8 +33,6 @@ SECTIONS
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */
>
>         /* Beginning of the read-only data sections */
> --

Regards,
Bin


From bmeng.cn at gmail.com  Mon Nov 14 08:09:44 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 15 Nov 2022 00:09:44 +0800
Subject: [PATCH v2] lib: utils/serial: Fix semihosting compile error using LLVM
In-Reply-To: <20221108121016.1441356-1-apatel@ventanamicro.com>
References: <20221108121016.1441356-1-apatel@ventanamicro.com>
Message-ID: <CAEUhbmXFRd4MgX6t7M5wnSiEQ-e8P8qJ2uTAti7mrwhVWQZBww@mail.gmail.com>

On Tue, Nov 8, 2022 at 8:12 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We fix the following semihosting compile error observed using LLVM:
> lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
>                 ret = ch > -1 ? ch : -1;
>                       ~~ ^ ~~
>
> Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/utils/serial/semihosting.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From anup at brainfault.org  Mon Nov 14 08:47:02 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 14 Nov 2022 22:17:02 +0530
Subject: [PATCH 1/2] lib: utils/fdt: Remove redundant code
In-Reply-To: <20221031112145.126615-2-wxjstz@126.com>
References: <20221031112145.126615-1-wxjstz@126.com> <20221031112145.126615-2-wxjstz@126.com>
Message-ID: <CAAhSdy1RCF7bOs=8XbjdnxoRao7dNU7pPckXAP93jja52am8aA@mail.gmail.com>

On Mon, Oct 31, 2022 at 4:52 PM Xiang W <wxjstz at 126.com> wrote:
>
> uart->reg_offset and uart->reg_io_width are only used on uart8250 and
> not required on other platforms. Remove for sifive and gaisler.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/fdt/fdt_helper.c | 12 ------------
>  1 file changed, 12 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index d390436..cdd0b35 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -25,10 +25,6 @@
>
>  #define DEFAULT_SIFIVE_UART_FREQ               0
>  #define DEFAULT_SIFIVE_UART_BAUD               115200
> -#define DEFAULT_SIFIVE_UART_REG_SHIFT          0
> -#define DEFAULT_SIFIVE_UART_REG_IO_WIDTH       4
> -
> -#define DEFAULT_GAISLER_UART_REG_IO_WIDTH      4
>
>  #define DEFAULT_SHAKTI_UART_FREQ               50000000
>  #define DEFAULT_SHAKTI_UART_BAUD               115200
> @@ -363,10 +359,6 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>         if (rc)
>                 return rc;
>
> -       /* For Gaisler APBUART, the reg-shift and reg-io-width are fixed .*/
> -       uart->reg_shift    = DEFAULT_UART_REG_SHIFT;
> -       uart->reg_io_width = DEFAULT_GAISLER_UART_REG_IO_WIDTH;
> -
>         return 0;
>  }
>
> @@ -394,10 +386,6 @@ int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
>         if (rc)
>                 return rc;
>
> -       /* For SiFive UART, the reg-shift and reg-io-width are fixed .*/
> -       uart->reg_shift = DEFAULT_SIFIVE_UART_REG_SHIFT;
> -       uart->reg_io_width = DEFAULT_SIFIVE_UART_REG_IO_WIDTH;
> -
>         return 0;
>  }
>
> --
> 2.30.2
>


From anup at brainfault.org  Mon Nov 14 08:47:36 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 14 Nov 2022 22:17:36 +0530
Subject: [PATCH 2/2] lib: utils/fdt: Simplified code
In-Reply-To: <20221031112145.126615-3-wxjstz@126.com>
References: <20221031112145.126615-1-wxjstz@126.com> <20221031112145.126615-3-wxjstz@126.com>
Message-ID: <CAAhSdy1PSAHbit7-qWZLYs5omvpTb3QsXEDdS1rgWQs50ZteXA@mail.gmail.com>

On Mon, Oct 31, 2022 at 4:52 PM Xiang W <wxjstz at 126.com> wrote:
>
> Simplified fdt_parse_xxx_uart_node which direct call
> fdt_parse_uart_node_common.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/fdt/fdt_helper.c | 28 ++++------------------------
>  1 file changed, 4 insertions(+), 24 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index cdd0b35..72d8635 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -350,43 +350,27 @@ static int fdt_parse_uart_node_common(void *fdt, int nodeoffset,
>  int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>                                 struct platform_uart_data *uart)
>  {
> -       int rc;
>
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_UART_FREQ,
>                                         DEFAULT_UART_BAUD);
> -
> -       if (rc)
> -               return rc;
> -
> -       return 0;
>  }
>
>  int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
>
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_SHAKTI_UART_FREQ,
>                                         DEFAULT_SHAKTI_UART_BAUD);
> -
> -       return rc ? : 0;
>  }
>
>  int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
> -
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
>                                         DEFAULT_SIFIVE_UART_FREQ,
>                                         DEFAULT_SIFIVE_UART_BAUD);
> -
> -       if (rc)
> -               return rc;
> -
> -       return 0;
>  }
>
>  int fdt_parse_uart_node(void *fdt, int nodeoffset,
> @@ -441,11 +425,7 @@ int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
>  int fdt_parse_xlnx_uartlite_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> -       int rc;
> -
> -       rc = fdt_parse_uart_node_common(fdt, nodeoffset, uart, 0, 0);
> -
> -       return rc ? : 0;
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart, 0, 0);
>  }
>
>  int fdt_parse_aplic_node(void *fdt, int nodeoff, struct aplic_data *aplic)
> --
> 2.30.2
>


From anup at brainfault.org  Mon Nov 14 08:58:41 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 14 Nov 2022 22:28:41 +0530
Subject: [PATCH] docs: fix some typos
In-Reply-To: <20221025005741.2441-1-zhangdongdong@eswincomputing.com>
References: <20221025005741.2441-1-zhangdongdong@eswincomputing.com>
Message-ID: <CAAhSdy2YqXtW-zcgEHAdiHxZuCuaEDKQJrMhYc-tkcogBgYavQ@mail.gmail.com>

On Tue, Oct 25, 2022 at 6:28 AM <zhangdongdong at eswincomputing.com> wrote:
>
> From: zhangdongdong <zhangdongdong at eswincomputing.com>
>
> Corrected the typos of some documents in the 'docs' folder.
>
> Signed-off-by:  zhangdongdong <zhangdongdong at eswincomputing.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/contributing.md          | 2 +-
>  docs/firmware/fw_dynamic.md   | 2 +-
>  docs/platform/fpga-ariane.md  | 2 +-
>  docs/platform/sifive_fu540.md | 2 +-
>  docs/platform/thead-c9xx.md   | 2 +-
>  5 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/docs/contributing.md b/docs/contributing.md
> index 9c2b3ba..78d909e 100644
> --- a/docs/contributing.md
> +++ b/docs/contributing.md
> @@ -29,7 +29,7 @@ and "top:".
>  5. Maintainers should use "Rebase and Merge" when using GitHub to merge pull
>  requests to avoid creating unnecessary merge commits.
>  6. Maintainers should avoid creating branches directly in the main
> -riscv/opensbi repository. Instead prefer using a fork of the riscv/opensbi main
> +riscv/opensbi repository. Instead, prefer using a fork of the riscv/opensbi main
>  repository and branches within that fork to create pull requests.
>  7. A maintainer cannot merge his own pull requests in the riscv/opensbi main
>  repository.
> diff --git a/docs/firmware/fw_dynamic.md b/docs/firmware/fw_dynamic.md
> index e251488..9fc8cfa 100644
> --- a/docs/firmware/fw_dynamic.md
> +++ b/docs/firmware/fw_dynamic.md
> @@ -31,6 +31,6 @@ directory.
>  *FW_DYNAMIC* Firmware Configuration Options
>  -------------------------------------------
>
> -The *FW_DYNAMIC* firmware does not requires any platform specific configuration
> +The *FW_DYNAMIC* firmware does not require any platform specific configuration
>  parameters because all required information is passed by previous booting stage
>  at runtime via *struct fw_dynamic_info*.
> diff --git a/docs/platform/fpga-ariane.md b/docs/platform/fpga-ariane.md
> index f95001f..9b1e156 100644
> --- a/docs/platform/fpga-ariane.md
> +++ b/docs/platform/fpga-ariane.md
> @@ -7,7 +7,7 @@ Linux.
>
>  The FPGA SoC currently contains the following peripherals:
>  - DDR3 memory controller
> -- SPI controller to conncet to an SDCard
> +- SPI controller to connect to an SDCard
>  - Ethernet controller
>  - JTAG port (see debugging section below)
>  - Bootrom containing zero stage bootloader and device tree.
> diff --git a/docs/platform/sifive_fu540.md b/docs/platform/sifive_fu540.md
> index 5cbca21..3dc1d28 100644
> --- a/docs/platform/sifive_fu540.md
> +++ b/docs/platform/sifive_fu540.md
> @@ -150,7 +150,7 @@ If you want to test OpenSBI with QEMU 'sifive_u' machine, please follow the
>  same instructions above, with the exception of not passing FW_FDT_PATH.
>
>  This is because QEMU generates a device tree blob on the fly based on the
> -command line parameters and it's compatible with the one used in the upstream
> +command line parameters, and it's compatible with the one used in the upstream
>  Linux kernel.
>
>  When U-Boot v2021.07 (or higher) is used as the payload, as the SiFive FU540
> diff --git a/docs/platform/thead-c9xx.md b/docs/platform/thead-c9xx.md
> index ced784d..8bb9e91 100644
> --- a/docs/platform/thead-c9xx.md
> +++ b/docs/platform/thead-c9xx.md
> @@ -13,7 +13,7 @@ Platform Options
>  ----------------
>
>  The *T-HEAD C9xx* does not have any platform-specific compile options
> -because it use generic platform.
> +because it uses generic platform.
>
>  ```
>  CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic /usr/bin/make
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From wxjstz at 126.com  Mon Nov 14 16:51:25 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 15 Nov 2022 08:51:25 +0800
Subject: [RFC PATCH 1/3] include: Add defines for SBI debug console
 extension
In-Reply-To: <20221110170016.1477865-2-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
	 <20221110170016.1477865-2-apatel@ventanamicro.com>
Message-ID: <af5057abae02725d058d0e0e5155ebdcc23be438.camel@126.com>

? 2022-11-10???? 22:30 +0530?Anup Patel???
> We add SBI debug console extension related defines/enum to the
> SBI ecall interface header.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?include/sbi/sbi_ecall_interface.h | 4 ++++
> ?1 file changed, 4 insertions(+)
> 
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index a3f2bf4..1dd3874 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -29,6 +29,7 @@
> ?#define SBI_EXT_HSM????????????????????????????0x48534D
> ?#define SBI_EXT_SRST???????????????????????????0x53525354
> ?#define SBI_EXT_PMU????????????????????????????0x504D55
> +#define SBI_EXT_DBCN???????????????????????????0x4442434E
> ?
> ?/* SBI function IDs for BASE extension*/
> ?#define SBI_EXT_BASE_GET_SPEC_VERSION??????????0x0
> @@ -230,6 +231,9 @@ enum sbi_pmu_ctr_type {
> ?/* Flags defined for counter stop function */
> ?#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
> ?
> +/* SBI function IDs for DBCN extension */
> +#define SBI_EXT_DBCN_CONSOLE_PUTS??????????????0x0
> +
> ?/* SBI base specification related macros */
> ?#define SBI_SPEC_VERSION_MAJOR_OFFSET??????????24
> ?#define SBI_SPEC_VERSION_MAJOR_MASK????????????0x7f
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Mon Nov 14 16:52:18 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 15 Nov 2022 08:52:18 +0800
Subject: [RFC PATCH 2/3] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221110170016.1477865-3-apatel@ventanamicro.com>
References: <20221110170016.1477865-1-apatel@ventanamicro.com>
	 <20221110170016.1477865-3-apatel@ventanamicro.com>
Message-ID: <bb3420fa5a4b94a605c1da272dcf8f85d1be7a14.camel@126.com>

? 2022-11-10???? 22:30 +0530?Anup Patel???
> We add new sbi_nputs() which help us print a fixed number of characters
> from a physical memory location.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me.

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?include/sbi/sbi_console.h |? 2 ++
> ?lib/sbi/sbi_console.c???? | 10 ++++++++++
> ?2 files changed, 12 insertions(+)
> 
> diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
> index e15b55d..1bdeeb9 100644
> --- a/include/sbi/sbi_console.h
> +++ b/include/sbi/sbi_console.h
> @@ -33,6 +33,8 @@ void sbi_putc(char ch);
> ?
> ?void sbi_puts(const char *str);
> ?
> +void sbi_nputs(const char *str, unsigned long len);
> +
> ?void sbi_gets(char *s, int maxwidth, char endchar);
> ?
> ?int __printf(2, 3) sbi_sprintf(char *out, const char *format, ...);
> diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> index cfef2f8..a975708 100644
> --- a/lib/sbi/sbi_console.c
> +++ b/lib/sbi/sbi_console.c
> @@ -51,6 +51,16 @@ void sbi_puts(const char *str)
> ????????spin_unlock(&console_out_lock);
> ?}
> ?
> +void sbi_nputs(const char *str, unsigned long len)
> +{
> +???????unsigned long i;
> +
> +???????spin_lock(&console_out_lock);
> +???????for (i = 0; i < len; i++)
> +???????????????sbi_putc(str[i]);
> +???????spin_unlock(&console_out_lock);
> +}
> +
> ?void sbi_gets(char *s, int maxwidth, char endchar)
> ?{
> ????????int ch;
> -- 
> 2.34.1
> 
> 




From bmeng.cn at gmail.com  Mon Nov 14 23:30:18 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 15 Nov 2022 15:30:18 +0800
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>

On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add Renesas SCIF driver.
>
> Based on a patch in the BSP by Takeki Hamada
> <takeki.hamada.ak at bp.renesas.com>

If there is a public URL for the BSP you mentioned, better put that in
the commit here for future reference.

>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> RFC->v2
> * Fixed comments pointed by Xiang W
> ---
>  include/sbi_utils/serial/renesas-scif.h |  11 ++
>  lib/utils/serial/Kconfig                |   4 +
>  lib/utils/serial/objects.mk             |   1 +
>  lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
>  4 files changed, 155 insertions(+)
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/renesas_scif.c
>
> diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> new file mode 100644
> index 0000000..0002a1a
> --- /dev/null
> +++ b/include/sbi_utils/serial/renesas-scif.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#ifndef __SERIAL_RENESAS_SCIF_H__
> +#define __SERIAL_RENESAS_SCIF_H__
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> +
> +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> index da549a7..f6ed803 100644
> --- a/lib/utils/serial/Kconfig
> +++ b/lib/utils/serial/Kconfig
> @@ -59,6 +59,10 @@ config SERIAL_GAISLER
>         bool "Gaisler UART support"
>         default n
>
> +config SERIAL_RENESAS_SCIF
> +       bool "Renesas SCIF support"
> +       default n
> +
>  config SERIAL_SHAKTI
>         bool "Shakti UART support"
>         default n
> diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> index 98f3f9a..6520424 100644
> --- a/lib/utils/serial/objects.mk
> +++ b/lib/utils/serial/objects.mk
> @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
>
>  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> new file mode 100644
> index 0000000..0586e1a
> --- /dev/null
> +++ b/lib/utils/serial/renesas_scif.c
> @@ -0,0 +1,139 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_timer.h>
> +#include <sbi_utils/serial/renesas-scif.h>
> +
> +/* clang-format off */
> +
> +#define SCIF_REG_SMR           0x0
> +#define SCIF_REG_BRR           0x2
> +#define SCIF_REG_SCR           0x4
> +#define SCIF_REG_FTDR          0x6
> +#define SCIF_REG_FSR           0x8
> +#define SCIF_REG_FRDR          0xa

This register is not used by the driver. Drop it.

> +#define SCIF_REG_FCR           0xc
> +#define SCIF_REG_LSR           0x12
> +#define SCIF_REG_SEMR          0x14
> +
> +#define SCIF_RFRST             0x2 /* Reset assert receive-FIFO (bit[1]) */
> +#define SCIF_TFRST             0x4 /* Reset assert transmit-FIFO(bit[2]) */

The above 2 macros should probably be named as SCIF_FCR_* as they only
apply to the FCR register.

> +
> +#define SCIF_FCR_RST_ASSRT_TFRF        (SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */

The macro name should probably be named to have RF come before TF,
like SCIF_FCR_RST_ASSRT_RFTF, to keep in consistency with the rest,
and the codes.

#define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_RFRST | SCIF_TFRST) /*
Reset assert rx-FIFO & tx-FIFO */

> +#define SCIF_FCR_RST_NGATE_TFRF        0x0 /* Reset negate tx-FIFO & rx-FIFO*/

ditto

need a space before */

> +
> +#define SCIF_RE                        0x10 /* Enable receive (bit[4])  */
> +#define SCIF_TE                        0x20 /* Enable transmit(bit[5])  */

The above 2 macros should probably be named as SCIF_SCR_* as they only
apply to the SCR register.

nits: only need one space fore */

> +#define SCIF_SCR_RCV_TRN_EN    (SCIF_RE | SCIF_TE) /* Enable receive & transmit */
> +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> +
> +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> +#define SCIF_FSR_TEND          0x40 /* Detect break flag */
> +#define SCIF_FSR_TDFE          0x20 /* Detect break flag */

The comments of the above 2 bit fields are wrong

> +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> +#define SCIF_FSR_RDF           0x2  /* Receive FIFO data full flag */

This bit field seems not to be used anywhere. Drop it?

> +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> +
> +#define SCIF_FSR_RXD_CHK       (SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
> +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> +
> +#define SCIF_LSR_ORER          0x1 /* Overrun error flag */

This macro is not used anywhere. Drop it.

> +
> +#define SCIF_SPTR_SPB2DT       0x1 /* if SCR.TE setting, don't care */
> +#define SCIF_SPTR_SPB2IO       0x2 /* if SCR.TE setting, don't care */

The above 2 macros are not used anywhere. Drop them.

> +
> +#define SCIF_SEMR_BRME         0x20 /* bit-rate modulation enable */

This macro is not used anywhere. Drop it.

> +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> +
> +#define SCIF_SIZE(reg)         ((reg == SCIF_REG_BRR) || \
> +                                (reg == SCIF_REG_FTDR) || \
> +                                (reg == SCIF_REG_FRDR) || \

I don't see the driver programs SCIF_REG_FRDR register. We can just
remove it to save some cycles.

> +                                (reg == SCIF_REG_SEMR))

The name of this macro is not meaningful. It looks like it's the size
of a register at the first glance but it's actually returning logical
true or false.
Better rename it to something like SCIF_REG_8BIT(reg).

> +
> +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> +
> +/* clang-format on */
> +
> +static volatile char *scif_base;
> +
> +static u32 get_reg(u32 offset)
> +{
> +       if (SCIF_SIZE(offset))
> +               return readb(scif_base + offset);
> +
> +       return readw(scif_base + offset);
> +}
> +
> +static void set_reg(u32 offset, u32 val)
> +{
> +       if (SCIF_SIZE(offset))
> +               return writeb(val, scif_base + offset);
> +
> +       return writew(val, scif_base + offset);
> +}
> +
> +static void scif_wait(unsigned long baudrate)
> +{
> +       unsigned long utime;
> +
> +       utime = 1000000 / baudrate + 1;

What is this?

> +
> +       sbi_timer_udelay(utime);
> +}
> +
> +static void renesas_scif_putc(char ch)
> +{
> +       uint16_t reg;
> +
> +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> +               ;
> +
> +       set_reg(SCIF_REG_FTDR, ch);
> +       reg = get_reg(SCIF_REG_FSR);
> +       reg &= ~SCIF_FSR_TXD_CHK;
> +       set_reg(SCIF_REG_FSR, reg);

The FSR Tx status bits clear should happen before writing a new char
to the Tx fifo, no?

> +}
> +
> +static struct sbi_console_device renesas_scif_console = {
> +       .name           = "renesas_scif",
> +       .console_putc   = renesas_scif_putc,
> +};
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
> +{
> +       volatile uint16_t data16;
> +
> +       scif_base = (volatile char *)base;
> +
> +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS); /* Disable receive & transmit */
> +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_TFRF); /* Reset assert tx-FIFO & rx-FIFO */
> +
> +       data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> +       set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> +
> +       data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> +       set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> +
> +       set_reg(SCIF_REG_SCR, 0x0); /* Select internal clock, SC_CLK pin unused for output pin */
> +
> +       set_reg(SCIF_REG_SMR, 0x0); /* Set asynchronous, 8bit data, no-parity, 1 stop and Po/1 */
> +
> +       data16 = get_reg(SCIF_REG_SEMR);
> +       set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS)); /* Select to access BRR */
> +       set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> +
> +       scif_wait(baudrate);

What is this?

> +
> +       /* FTCR is left at initial value, because this interrupt isn't used. */

What is FTCR? There is no such register in your defines.

> +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_TFRF); /* Reset negate tx-FIFO, rx-FIFO. */
> +
> +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN); /* Enable receive & transmit w/SC_CLK=no output */
> +
> +       sbi_console_set_device(&renesas_scif_console);
> +
> +       return 0;
> +}

Regards,
Bin


From anup at brainfault.org  Tue Nov 15 03:16:20 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 15 Nov 2022 16:46:20 +0530
Subject: [PATCH v2] lib: utils/serial: Fix semihosting compile error using LLVM
In-Reply-To: <20221108121016.1441356-1-apatel@ventanamicro.com>
References: <20221108121016.1441356-1-apatel@ventanamicro.com>
Message-ID: <CAAhSdy0GrckC+SG7k2h-mz0=WjGh79HEhswGiac-0eoLWxvP8w@mail.gmail.com>

On Tue, Nov 8, 2022 at 5:40 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We fix the following semihosting compile error observed using LLVM:
> lib/utils/serial/semihosting.c:158:12: error: result of comparison of constant -1 with expression of type 'char' is always true [-Werror,-Wtautological-constant-out-of-range-compare]
>                 ret = ch > -1 ? ch : -1;
>                       ~~ ^ ~~
>
> Fixes: 7f09fba86e43 ("lib: utils/serial: add semihosting support")
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Regards,
Anup

> ---
>  lib/utils/serial/semihosting.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 5012fa1..86fa296 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -154,8 +154,8 @@ static int semihosting_getc(void)
>         int ret;
>
>         if (semihosting_infd < 0)  {
> -               ch = semihosting_trap(SYSREADC, NULL);
> -               ret = ch > -1 ? ch : -1;
> +               ret = semihosting_trap(SYSREADC, NULL);
> +               ret = ret < 0 ? -1 : ret;
>         } else
>                 ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
>
> --
> 2.34.1
>


From anup at brainfault.org  Tue Nov 15 03:22:02 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 15 Nov 2022 16:52:02 +0530
Subject: [PATCH] lib: sbi_ecall: Split up sbi_ecall_replace
In-Reply-To: <TYYP286MB14394A21B7C5D612DBC5F3ECC63E9@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
References: <TYYP286MB14394A21B7C5D612DBC5F3ECC63E9@TYYP286MB1439.JPNP286.PROD.OUTLOOK.COM>
Message-ID: <CAAhSdy2LZnDx5gZxSANfOUO9NyqbrUgJN_K7bctkiy10bpNBHg@mail.gmail.com>

On Wed, Nov 9, 2022 at 12:24 PM Vivian Wang <dramforever at live.com> wrote:
>
> Split up sbi_ecall_replace so that each extension is in its individual
> file.
>
> Also reorganize the corresponding section in lib/sbi/objects.mk so
> that it is grouped by extension, now that the object file targets are
> split up.
>
> Signed-off-by: Vivian Wang <dramforever at live.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/objects.mk                            |  22 +++-
>  lib/sbi/sbi_ecall_ipi.c                       |  36 ++++++
>  ...sbi_ecall_replace.c => sbi_ecall_rfence.c} | 122 +-----------------
>  lib/sbi/sbi_ecall_srst.c                      |  75 +++++++++++
>  lib/sbi/sbi_ecall_time.c                      |  40 ++++++
>  5 files changed, 169 insertions(+), 126 deletions(-)
>  create mode 100644 lib/sbi/sbi_ecall_ipi.c
>  rename lib/sbi/{sbi_ecall_replace.c => sbi_ecall_rfence.c} (50%)
>  create mode 100644 lib/sbi/sbi_ecall_srst.c
>  create mode 100644 lib/sbi/sbi_ecall_time.c
>
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index 783c46d..c774ebb 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -17,20 +17,30 @@ libsbi-objs-y += sbi_ecall_exts.o
>
>  # The order of below extensions is performance optimized
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_TIME) += ecall_time
> +libsbi-objs-$(CONFIG_SBI_ECALL_TIME) += sbi_ecall_time.o
> +
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_RFENCE) += ecall_rfence
> +libsbi-objs-$(CONFIG_SBI_ECALL_RFENCE) += sbi_ecall_rfence.o
> +
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_IPI) += ecall_ipi
> +libsbi-objs-$(CONFIG_SBI_ECALL_IPI) += sbi_ecall_ipi.o
> +
>  carray-sbi_ecall_exts-y += ecall_base
> +libsbi-objs-y += sbi_ecall_base.o
> +
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_HSM) += ecall_hsm
> +libsbi-objs-$(CONFIG_SBI_ECALL_HSM) += sbi_ecall_hsm.o
> +
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_SRST) += ecall_srst
> +libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
> +
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
> -carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
> -carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
> +libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
>
> -libsbi-objs-y += sbi_ecall_base.o
> -libsbi-objs-$(CONFIG_SBI_ECALL_HSM) += sbi_ecall_hsm.o
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
>  libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
> -libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
> -libsbi-objs-y += sbi_ecall_replace.o
> +
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
>  libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
>
>  libsbi-objs-y += sbi_bitmap.o
> diff --git a/lib/sbi/sbi_ecall_ipi.c b/lib/sbi/sbi_ecall_ipi.c
> new file mode 100644
> index 0000000..f4797e1
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_ipi.c
> @@ -0,0 +1,36 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + *   Anup Patel <anup.patel at wdc.com>
> + *   Atish Patra <atish.patra at wdc.com>
> + */
> +
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_ipi.h>
> +
> +static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
> +                                const struct sbi_trap_regs *regs,
> +                                unsigned long *out_val,
> +                                struct sbi_trap_info *out_trap)
> +{
> +       int ret = 0;
> +
> +       if (funcid == SBI_EXT_IPI_SEND_IPI)
> +               ret = sbi_ipi_send_smode(regs->a0, regs->a1);
> +       else
> +               ret = SBI_ENOTSUPP;
> +
> +       return ret;
> +}
> +
> +struct sbi_ecall_extension ecall_ipi = {
> +       .extid_start = SBI_EXT_IPI,
> +       .extid_end = SBI_EXT_IPI,
> +       .handle = sbi_ecall_ipi_handler,
> +};
> diff --git a/lib/sbi/sbi_ecall_replace.c b/lib/sbi/sbi_ecall_rfence.c
> similarity index 50%
> rename from lib/sbi/sbi_ecall_replace.c
> rename to lib/sbi/sbi_ecall_rfence.c
> index 0ea00d6..8f0e3d7 100644
> --- a/lib/sbi/sbi_ecall_replace.c
> +++ b/lib/sbi/sbi_ecall_rfence.c
> @@ -9,44 +9,12 @@
>   */
>
>  #include <sbi/riscv_asm.h>
> +#include <sbi/sbi_error.h>
>  #include <sbi/sbi_ecall.h>
>  #include <sbi/sbi_ecall_interface.h>
> -#include <sbi/sbi_error.h>
> -#include <sbi/sbi_hart.h>
> -#include <sbi/sbi_ipi.h>
> -#include <sbi/sbi_system.h>
> -#include <sbi/sbi_timer.h>
> -#include <sbi/sbi_tlb.h>
>  #include <sbi/sbi_trap.h>
> +#include <sbi/sbi_tlb.h>
>
> -#ifdef CONFIG_SBI_ECALL_TIME
> -static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
> -                                 const struct sbi_trap_regs *regs,
> -                                 unsigned long *out_val,
> -                                 struct sbi_trap_info *out_trap)
> -{
> -       int ret = 0;
> -
> -       if (funcid == SBI_EXT_TIME_SET_TIMER) {
> -#if __riscv_xlen == 32
> -               sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
> -#else
> -               sbi_timer_event_start((u64)regs->a0);
> -#endif
> -       } else
> -               ret = SBI_ENOTSUPP;
> -
> -       return ret;
> -}
> -
> -struct sbi_ecall_extension ecall_time = {
> -       .extid_start = SBI_EXT_TIME,
> -       .extid_end = SBI_EXT_TIME,
> -       .handle = sbi_ecall_time_handler,
> -};
> -#endif
> -
> -#ifdef CONFIG_SBI_ECALL_RFENCE
>  static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
>                                     const struct sbi_trap_regs *regs,
>                                     unsigned long *out_val,
> @@ -116,89 +84,3 @@ struct sbi_ecall_extension ecall_rfence = {
>         .extid_end = SBI_EXT_RFENCE,
>         .handle = sbi_ecall_rfence_handler,
>  };
> -#endif
> -
> -#ifdef CONFIG_SBI_ECALL_IPI
> -static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
> -                                const struct sbi_trap_regs *regs,
> -                                unsigned long *out_val,
> -                                struct sbi_trap_info *out_trap)
> -{
> -       int ret = 0;
> -
> -       if (funcid == SBI_EXT_IPI_SEND_IPI)
> -               ret = sbi_ipi_send_smode(regs->a0, regs->a1);
> -       else
> -               ret = SBI_ENOTSUPP;
> -
> -       return ret;
> -}
> -
> -struct sbi_ecall_extension ecall_ipi = {
> -       .extid_start = SBI_EXT_IPI,
> -       .extid_end = SBI_EXT_IPI,
> -       .handle = sbi_ecall_ipi_handler,
> -};
> -#endif
> -
> -#ifdef CONFIG_SBI_ECALL_SRST
> -static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
> -                                 const struct sbi_trap_regs *regs,
> -                                 unsigned long *out_val,
> -                                 struct sbi_trap_info *out_trap)
> -{
> -       if (funcid == SBI_EXT_SRST_RESET) {
> -               if ((((u32)-1U) <= ((u64)regs->a0)) ||
> -                   (((u32)-1U) <= ((u64)regs->a1)))
> -                       return SBI_EINVAL;
> -
> -               switch (regs->a0) {
> -               case SBI_SRST_RESET_TYPE_SHUTDOWN:
> -               case SBI_SRST_RESET_TYPE_COLD_REBOOT:
> -               case SBI_SRST_RESET_TYPE_WARM_REBOOT:
> -                       break;
> -               default:
> -                       return SBI_EINVAL;
> -               }
> -
> -               switch (regs->a1) {
> -               case SBI_SRST_RESET_REASON_NONE:
> -               case SBI_SRST_RESET_REASON_SYSFAIL:
> -                       break;
> -               default:
> -                       return SBI_EINVAL;
> -               }
> -
> -               if (sbi_system_reset_supported(regs->a0, regs->a1))
> -                       sbi_system_reset(regs->a0, regs->a1);
> -       }
> -
> -       return SBI_ENOTSUPP;
> -}
> -
> -static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
> -{
> -       u32 type, count = 0;
> -
> -       /*
> -        * At least one standard reset types should be supported by
> -        * the platform for SBI SRST extension to be usable.
> -        */
> -
> -       for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
> -               if (sbi_system_reset_supported(type,
> -                                       SBI_SRST_RESET_REASON_NONE))
> -                       count++;
> -       }
> -
> -       *out_val = (count) ? 1 : 0;
> -       return 0;
> -}
> -
> -struct sbi_ecall_extension ecall_srst = {
> -       .extid_start = SBI_EXT_SRST,
> -       .extid_end = SBI_EXT_SRST,
> -       .handle = sbi_ecall_srst_handler,
> -       .probe = sbi_ecall_srst_probe,
> -};
> -#endif
> diff --git a/lib/sbi/sbi_ecall_srst.c b/lib/sbi/sbi_ecall_srst.c
> new file mode 100644
> index 0000000..93b012c
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_srst.c
> @@ -0,0 +1,75 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + *   Anup Patel <anup.patel at wdc.com>
> + *   Atish Patra <atish.patra at wdc.com>
> + */
> +
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_system.h>
> +
> +static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
> +                                 const struct sbi_trap_regs *regs,
> +                                 unsigned long *out_val,
> +                                 struct sbi_trap_info *out_trap)
> +{
> +       if (funcid == SBI_EXT_SRST_RESET) {
> +               if ((((u32)-1U) <= ((u64)regs->a0)) ||
> +                   (((u32)-1U) <= ((u64)regs->a1)))
> +                       return SBI_EINVAL;
> +
> +               switch (regs->a0) {
> +               case SBI_SRST_RESET_TYPE_SHUTDOWN:
> +               case SBI_SRST_RESET_TYPE_COLD_REBOOT:
> +               case SBI_SRST_RESET_TYPE_WARM_REBOOT:
> +                       break;
> +               default:
> +                       return SBI_EINVAL;
> +               }
> +
> +               switch (regs->a1) {
> +               case SBI_SRST_RESET_REASON_NONE:
> +               case SBI_SRST_RESET_REASON_SYSFAIL:
> +                       break;
> +               default:
> +                       return SBI_EINVAL;
> +               }
> +
> +               if (sbi_system_reset_supported(regs->a0, regs->a1))
> +                       sbi_system_reset(regs->a0, regs->a1);
> +       }
> +
> +       return SBI_ENOTSUPP;
> +}
> +
> +static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
> +{
> +       u32 type, count = 0;
> +
> +       /*
> +        * At least one standard reset types should be supported by
> +        * the platform for SBI SRST extension to be usable.
> +        */
> +
> +       for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
> +               if (sbi_system_reset_supported(type,
> +                                       SBI_SRST_RESET_REASON_NONE))
> +                       count++;
> +       }
> +
> +       *out_val = (count) ? 1 : 0;
> +       return 0;
> +}
> +
> +struct sbi_ecall_extension ecall_srst = {
> +       .extid_start = SBI_EXT_SRST,
> +       .extid_end = SBI_EXT_SRST,
> +       .handle = sbi_ecall_srst_handler,
> +       .probe = sbi_ecall_srst_probe,
> +};
> diff --git a/lib/sbi/sbi_ecall_time.c b/lib/sbi/sbi_ecall_time.c
> new file mode 100644
> index 0000000..668cb17
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_time.c
> @@ -0,0 +1,40 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + *   Anup Patel <anup.patel at wdc.com>
> + *   Atish Patra <atish.patra at wdc.com>
> + */
> +
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_timer.h>
> +
> +static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
> +                                 const struct sbi_trap_regs *regs,
> +                                 unsigned long *out_val,
> +                                 struct sbi_trap_info *out_trap)
> +{
> +       int ret = 0;
> +
> +       if (funcid == SBI_EXT_TIME_SET_TIMER) {
> +#if __riscv_xlen == 32
> +               sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
> +#else
> +               sbi_timer_event_start((u64)regs->a0);
> +#endif
> +       } else
> +               ret = SBI_ENOTSUPP;
> +
> +       return ret;
> +}
> +
> +struct sbi_ecall_extension ecall_time = {
> +       .extid_start = SBI_EXT_TIME,
> +       .extid_end = SBI_EXT_TIME,
> +       .handle = sbi_ecall_time_handler,
> +};
> --
> 2.38.0
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Tue Nov 15 03:30:39 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 15 Nov 2022 17:00:39 +0530
Subject: [PATCH v2 4/7] lib: utils/irqchip: Add compatible string for
 Andestech NCEPLIC100
In-Reply-To: <20221111182105.614094-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221111182105.614094-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy36WvvWuwr-s4Qt+VgWvwxDhmHRdB0CH0UCq_j4yo6AxA@mail.gmail.com>

On Fri, Nov 11, 2022 at 11:51 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
> which is equipped with AX45MP AndesCore.
>
> While at it drop the comma after the sentinel as it does not make sense to
> have a comma after a sentinel, as any new elements must be added before the
> sentinel.
>
> dts example (Single-core AX45MP):
>
>     soc: soc {
>           ....
>           plic: interrupt-controller at 12c00000 {
>               compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
>               #interrupt-cells = <2>;
>               #address-cells = <0>;
>               riscv,ndev = <511>;
>               interrupt-controller;
>               reg = <0x0 0x12c00000 0 0x400000>;
>               clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
>               power-domains = <&cpg>;
>               resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>               interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
>           };
>           ....
>     };
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> RFC->v2
> * No change
>
> DT binding [0]
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
> ---
>  lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..83d091a 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -163,7 +163,8 @@ static const struct fdt_match irqchip_plic_match[] = {
>         { .compatible = "sifive,plic-1.0.0" },
>         { .compatible = "thead,c900-plic",
>           .data = thead_plic_plat_init },
> -       { },
> +       { .compatible = "andestech,nceplic100" },
> +       { /* sentinel */ }
>  };
>
>  struct fdt_irqchip fdt_irqchip_plic = {
> --
> 2.17.1
>


From anup at brainfault.org  Tue Nov 15 03:44:40 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 15 Nov 2022 17:14:40 +0530
Subject: [PATCH v2 5/7] platform: Add Renesas RZ/Five initial support
In-Reply-To: <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy3eJ4YJrFZA0zN_4aMFMM=W_MBJmi_7-ngMSw7y85XCWg@mail.gmail.com>

On Fri, Nov 11, 2022 at 11:51 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> This commit provides basic support for the Renesas RZ/Five
> (R9A07G043F) SoC.
>
> The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> - Gigabit Ethernet 2ch
> - CAN interface (CAN-FD) 2ch
> - USB 2.0 interface 2ch
> - SD interface 2ch
> - AD converter 2ch
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> RFC->v2
> * Updated commit description
> ---
>  platform/renesas/rzfive/Kconfig           |  32 +++++
>  platform/renesas/rzfive/configs/defconfig |   0
>  platform/renesas/rzfive/objects.mk        |  18 +++
>  platform/renesas/rzfive/platform.c        | 161 ++++++++++++++++++++++
>  platform/renesas/rzfive/platform.h        |  24 ++++
>  5 files changed, 235 insertions(+)
>  create mode 100644 platform/renesas/rzfive/Kconfig
>  create mode 100644 platform/renesas/rzfive/configs/defconfig
>  create mode 100644 platform/renesas/rzfive/objects.mk
>  create mode 100644 platform/renesas/rzfive/platform.c
>  create mode 100644 platform/renesas/rzfive/platform.h
>
> diff --git a/platform/renesas/rzfive/Kconfig b/platform/renesas/rzfive/Kconfig
> new file mode 100644
> index 0000000..c5e8a19
> --- /dev/null
> +++ b/platform/renesas/rzfive/Kconfig
> @@ -0,0 +1,32 @@
> +# SPDX-License-Identifier: BSD-2-Clause
> +
> +config PLATFORM_RENESAS_RZFIVE
> +       bool
> +       select FDT
> +       select FDT_SERIAL
> +       select FDT_SERIAL_RENESAS_SCIF
> +       select FDT_TIMER
> +       select FDT_TIMER_PLMT
> +       select FDT_IRQCHIP
> +       select FDT_IRQCHIP_PLIC
> +       select FDT_IPI
> +       select FDT_IPI_PLICSW
> +       default y
> +
> +if PLATFORM_RENESAS_RZFIVE
> +
> +config PLATFORM_RENESAS_RZFIVE_NAME
> +       string "Platform default name"
> +       default "Renesas RZ/Five"
> +
> +config PLATFORM_RENESAS_RZFIVE_MAJOR_VER
> +       int "Platform major version"
> +       range 0 65535
> +       default 0
> +
> +config PLATFORM_RENESAS_RZFIVE_MINOR_VER
> +       int "Platform minor version"
> +       range 0 65535
> +       default 1
> +
> +endif
> diff --git a/platform/renesas/rzfive/configs/defconfig b/platform/renesas/rzfive/configs/defconfig
> new file mode 100644
> index 0000000..e69de29
> diff --git a/platform/renesas/rzfive/objects.mk b/platform/renesas/rzfive/objects.mk
> new file mode 100644
> index 0000000..302b3d6
> --- /dev/null
> +++ b/platform/renesas/rzfive/objects.mk
> @@ -0,0 +1,18 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2022 Renesas Electronics Corp.
> +#
> +
> +# Compiler flags
> +platform-cppflags-y =
> +platform-cflags-y =
> +platform-asflags-y =
> +platform-ldflags-y =
> +
> +# Objects to build
> +platform-objs-y += ../../andes/ae350/cache.o platform.o

The fact that you have to compile ae350/cache.c as part of this platform
shows we need to improve code re-use.

Further, the platform.c added by this patch is very similar to platform.c
of andes/ae350. Both platform.c files are subset of what is already there
in generic/platform.c.

I suggest you do the following:
1) Move andes/ae350 as a platform override under generic/platform/andes/ae350
2) Add rzfive as platform override under generic/platform/renesas/rzfive
3) The common Andes cache operations will be a library under
    generic/platform/andes/ae350 which can be selected by renesas/rzfive
4) The common Andes header can be under generic/include/andes/ae350
5) Enable drivers required by andes/ae350 and renesas/rzfive platform
    overrides in generic/configs/defconfig

Regards,
Anup


> +
> +# Blobs to build
> +FW_TEXT_START=0x00000000
> +FW_DYNAMIC=y
> diff --git a/platform/renesas/rzfive/platform.c b/platform/renesas/rzfive/platform.c
> new file mode 100644
> index 0000000..cfc557c
> --- /dev/null
> +++ b/platform/renesas/rzfive/platform.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + * Based on platform/andes/ae350/platform.c
> + * Copyright (c) 2019 Andes Technology Corporation
> + */
> +
> +#include <libfdt.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_const.h>
> +#include <sbi/sbi_hartmask.h>
> +#include <sbi/sbi_ipi.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi_utils/fdt/fdt_domain.h>
> +#include <sbi_utils/fdt/fdt_fixup.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/ipi/fdt_ipi.h>
> +#include <sbi_utils/irqchip/fdt_irqchip.h>
> +#include <sbi_utils/serial/fdt_serial.h>
> +#include <sbi_utils/timer/fdt_timer.h>
> +
> +#include "../../andes/ae350/cache.h"
> +
> +#include "platform.h"
> +
> +struct sbi_platform platform;
> +unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
> +                              unsigned long arg2, unsigned long arg3,
> +                              unsigned long arg4)
> +{
> +       const char *model;
> +       void *fdt = (void *)arg1;
> +       u32 hartid, hart_count = 0;
> +       int rc, root_offset, cpus_offset, cpu_offset, len;
> +
> +       root_offset = fdt_path_offset(fdt, "/");
> +       if (root_offset < 0)
> +               goto fail;
> +
> +       model = fdt_getprop(fdt, root_offset, "model", &len);
> +       if (model)
> +               sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
> +
> +       cpus_offset = fdt_path_offset(fdt, "/cpus");
> +       if (cpus_offset < 0)
> +               goto fail;
> +
> +       fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
> +               rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> +               if (rc)
> +                       continue;
> +
> +               if (SBI_HARTMASK_MAX_BITS <= hartid)
> +                       continue;
> +
> +               hart_count++;
> +       }
> +
> +       platform.hart_count = hart_count;
> +
> +       /* Return original FDT pointer */
> +       return arg1;
> +
> +fail:
> +       while (1)
> +               wfi();
> +}
> +
> +/* Platform final initialization. */
> +static int rzfive_final_init(bool cold_boot)
> +{
> +       void *fdt;
> +
> +       if (!cold_boot)
> +               return 0;
> +
> +       fdt = fdt_get_address();
> +       fdt_fixups(fdt);
> +       fdt_domain_fixup(fdt);
> +
> +       return 0;
> +}
> +
> +/* Vendor-Specific SBI handler */
> +static int rzfive_vendor_ext_provider(long extid, long funcid,
> +                                     const struct sbi_trap_regs *regs,
> +                                     unsigned long *out_value,
> +                                     struct sbi_trap_info *out_trap)
> +{
> +       int ret = 0;
> +
> +       switch (funcid) {
> +       case SBI_EXT_RENESAS_RZFIVE_GET_MCACHE_CTL_STATUS:
> +               *out_value = csr_read(CSR_MCACHECTL);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_GET_MMISC_CTL_STATUS:
> +               *out_value = csr_read(CSR_MMISCCTL);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_SET_MCACHE_CTL:
> +               ret = mcall_set_mcache_ctl(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_SET_MMISC_CTL:
> +               ret = mcall_set_mmisc_ctl(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_ICACHE_OP:
> +               ret = mcall_icache_op(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_DCACHE_OP:
> +               ret = mcall_dcache_op(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_L1CACHE_I_PREFETCH:
> +               ret = mcall_l1_cache_i_prefetch_op(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_L1CACHE_D_PREFETCH:
> +               ret = mcall_l1_cache_d_prefetch_op(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_NON_BLOCKING_LOAD_STORE:
> +               ret = mcall_non_blocking_load_store(regs->a0);
> +               break;
> +       case SBI_EXT_RENESAS_RZFIVE_WRITE_AROUND:
> +               ret = mcall_write_around(regs->a0);
> +               break;
> +       default:
> +               sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
> +               asm volatile("ebreak");
> +       }
> +
> +       return ret;
> +}
> +
> +static int rzfive_domains_init(void)
> +{
> +       return fdt_domains_populate(fdt_get_address());
> +}
> +
> +/* Platform descriptor. */
> +static const struct sbi_platform_operations platform_ops = {
> +       .final_init             = rzfive_final_init,
> +       .domains_init           = rzfive_domains_init,
> +       .console_init           = fdt_serial_init,
> +       .irqchip_init           = fdt_irqchip_init,
> +       .ipi_init               = fdt_ipi_init,
> +       .timer_init             = fdt_timer_init,
> +       .vendor_ext_provider    = rzfive_vendor_ext_provider
> +};
> +
> +struct sbi_platform platform = {
> +       .opensbi_version = OPENSBI_VERSION,
> +       .platform_version =
> +               SBI_PLATFORM_VERSION(CONFIG_PLATFORM_RENESAS_RZFIVE_MAJOR_VER,
> +                                    CONFIG_PLATFORM_RENESAS_RZFIVE_MINOR_VER),
> +       .name = CONFIG_PLATFORM_RENESAS_RZFIVE_NAME,
> +       .features = SBI_PLATFORM_DEFAULT_FEATURES,
> +       .hart_count = SBI_HARTMASK_MAX_BITS,
> +       .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
> +       .platform_ops_addr = (unsigned long)&platform_ops
> +};
> diff --git a/platform/renesas/rzfive/platform.h b/platform/renesas/rzfive/platform.h
> new file mode 100644
> index 0000000..e46ca91
> --- /dev/null
> +++ b/platform/renesas/rzfive/platform.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#ifndef _RZFIVE_PLATFORM_H_
> +#define _RZFIVE_PLATFORM_H_
> +
> +#include "../../andes/ae350/common-platform.h"
> +
> +enum sbi_ext_andes_fid {
> +       SBI_EXT_RENESAS_RZFIVE_GET_MCACHE_CTL_STATUS = 0,
> +       SBI_EXT_RENESAS_RZFIVE_GET_MMISC_CTL_STATUS,
> +       SBI_EXT_RENESAS_RZFIVE_SET_MCACHE_CTL,
> +       SBI_EXT_RENESAS_RZFIVE_SET_MMISC_CTL,
> +       SBI_EXT_RENESAS_RZFIVE_ICACHE_OP,
> +       SBI_EXT_RENESAS_RZFIVE_DCACHE_OP,
> +       SBI_EXT_RENESAS_RZFIVE_L1CACHE_I_PREFETCH,
> +       SBI_EXT_RENESAS_RZFIVE_L1CACHE_D_PREFETCH,
> +       SBI_EXT_RENESAS_RZFIVE_NON_BLOCKING_LOAD_STORE,
> +       SBI_EXT_RENESAS_RZFIVE_WRITE_AROUND,
> +};
> +
> +#endif /* _RZFIVE_PLATFORM_H_ */
> --
> 2.17.1
>


From bmeng.cn at gmail.com  Tue Nov 15 06:06:48 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 15 Nov 2022 22:06:48 +0800
Subject: [PATCH v2 4/7] lib: utils/irqchip: Add compatible string for
 Andestech NCEPLIC100
In-Reply-To: <20221111182105.614094-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221111182105.614094-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAEUhbmVGK_QK2opxx0a3mOUi2VHqQ-OWqzp-C1BmJws51oBv3g@mail.gmail.com>

On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
> which is equipped with AX45MP AndesCore.
>
> While at it drop the comma after the sentinel as it does not make sense to
> have a comma after a sentinel, as any new elements must be added before the
> sentinel.
>
> dts example (Single-core AX45MP):
>
>     soc: soc {
>           ....
>           plic: interrupt-controller at 12c00000 {
>               compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
>               #interrupt-cells = <2>;
>               #address-cells = <0>;
>               riscv,ndev = <511>;
>               interrupt-controller;
>               reg = <0x0 0x12c00000 0 0x400000>;
>               clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
>               power-domains = <&cpg>;
>               resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>               interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
>           };
>           ....
>     };
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> RFC->v2
> * No change
>
> DT binding [0]
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
> ---
>  lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From prabhakar.csengg at gmail.com  Tue Nov 15 09:33:54 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Tue, 15 Nov 2022 17:33:54 +0000
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>
Message-ID: <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com>

Hi Bin,

Thank you for the review.

On Tue, Nov 15, 2022 at 7:30 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > Add Renesas SCIF driver.
> >
> > Based on a patch in the BSP by Takeki Hamada
> > <takeki.hamada.ak at bp.renesas.com>
>
> If there is a public URL for the BSP you mentioned, better put that in
> the commit here for future reference.
>
you mean link for the BSP/File/Commit. Ive followed the same approach
that we follow on Linux.

> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > RFC->v2
> > * Fixed comments pointed by Xiang W
> > ---
> >  include/sbi_utils/serial/renesas-scif.h |  11 ++
> >  lib/utils/serial/Kconfig                |   4 +
> >  lib/utils/serial/objects.mk             |   1 +
> >  lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
> >  4 files changed, 155 insertions(+)
> >  create mode 100644 include/sbi_utils/serial/renesas-scif.h
> >  create mode 100644 lib/utils/serial/renesas_scif.c
> >
> > diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> > new file mode 100644
> > index 0000000..0002a1a
> > --- /dev/null
> > +++ b/include/sbi_utils/serial/renesas-scif.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: BSD-2-Clause */
> > +/*
> > + * Copyright (C) 2022 Renesas Electronics Corporation
> > + */
> > +
> > +#ifndef __SERIAL_RENESAS_SCIF_H__
> > +#define __SERIAL_RENESAS_SCIF_H__
> > +
> > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> > +
> > +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> > diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> > index da549a7..f6ed803 100644
> > --- a/lib/utils/serial/Kconfig
> > +++ b/lib/utils/serial/Kconfig
> > @@ -59,6 +59,10 @@ config SERIAL_GAISLER
> >         bool "Gaisler UART support"
> >         default n
> >
> > +config SERIAL_RENESAS_SCIF
> > +       bool "Renesas SCIF support"
> > +       default n
> > +
> >  config SERIAL_SHAKTI
> >         bool "Shakti UART support"
> >         default n
> > diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> > index 98f3f9a..6520424 100644
> > --- a/lib/utils/serial/objects.mk
> > +++ b/lib/utils/serial/objects.mk
> > @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
> >
> >  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
> >  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> > +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
> >  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
> >  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
> >  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> > diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> > new file mode 100644
> > index 0000000..0586e1a
> > --- /dev/null
> > +++ b/lib/utils/serial/renesas_scif.c
> > @@ -0,0 +1,139 @@
> > +// SPDX-License-Identifier: BSD-2-Clause
> > +/*
> > + * Copyright (C) 2022 Renesas Electronics Corporation
> > + */
> > +
> > +#include <sbi/riscv_io.h>
> > +#include <sbi/sbi_console.h>
> > +#include <sbi/sbi_timer.h>
> > +#include <sbi_utils/serial/renesas-scif.h>
> > +
> > +/* clang-format off */
> > +
> > +#define SCIF_REG_SMR           0x0
> > +#define SCIF_REG_BRR           0x2
> > +#define SCIF_REG_SCR           0x4
> > +#define SCIF_REG_FTDR          0x6
> > +#define SCIF_REG_FSR           0x8
> > +#define SCIF_REG_FRDR          0xa
>
> This register is not used by the driver. Drop it.
>
OK, I will drop it.

> > +#define SCIF_REG_FCR           0xc
> > +#define SCIF_REG_LSR           0x12
> > +#define SCIF_REG_SEMR          0x14
> > +
> > +#define SCIF_RFRST             0x2 /* Reset assert receive-FIFO (bit[1]) */
> > +#define SCIF_TFRST             0x4 /* Reset assert transmit-FIFO(bit[2]) */
>
> The above 2 macros should probably be named as SCIF_FCR_* as they only
> apply to the FCR register.
>
Agreed.

> > +
> > +#define SCIF_FCR_RST_ASSRT_TFRF        (SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
>
> The macro name should probably be named to have RF come before TF,
> like SCIF_FCR_RST_ASSRT_RFTF, to keep in consistency with the rest,
> and the codes.
>
Agreed.

> #define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_RFRST | SCIF_TFRST) /*
> Reset assert rx-FIFO & tx-FIFO */
>
> > +#define SCIF_FCR_RST_NGATE_TFRF        0x0 /* Reset negate tx-FIFO & rx-FIFO*/
>
> ditto
>
> need a space before */
>
OK, I will fix it.

> > +
> > +#define SCIF_RE                        0x10 /* Enable receive (bit[4])  */
> > +#define SCIF_TE                        0x20 /* Enable transmit(bit[5])  */
>
> The above 2 macros should probably be named as SCIF_SCR_* as they only
> apply to the SCR register.
>
Agreed.

> nits: only need one space fore */
>
> > +#define SCIF_SCR_RCV_TRN_EN    (SCIF_RE | SCIF_TE) /* Enable receive & transmit */
> > +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> > +
> > +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> > +#define SCIF_FSR_TEND          0x40 /* Detect break flag */
> > +#define SCIF_FSR_TDFE          0x20 /* Detect break flag */
>
> The comments of the above 2 bit fields are wrong
>
Ouch will fix that.

> > +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> > +#define SCIF_FSR_RDF           0x2  /* Receive FIFO data full flag */
>
> This bit field seems not to be used anywhere. Drop it?
>
Sure, I will drop it.

> > +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> > +
> > +#define SCIF_FSR_RXD_CHK       (SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
> > +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> > +
> > +#define SCIF_LSR_ORER          0x1 /* Overrun error flag */
>
> This macro is not used anywhere. Drop it.
>
ditto.

> > +
> > +#define SCIF_SPTR_SPB2DT       0x1 /* if SCR.TE setting, don't care */
> > +#define SCIF_SPTR_SPB2IO       0x2 /* if SCR.TE setting, don't care */
>
> The above 2 macros are not used anywhere. Drop them.
>
ditto.

> > +
> > +#define SCIF_SEMR_BRME         0x20 /* bit-rate modulation enable */
>
> This macro is not used anywhere. Drop it.
>
ditto.

> > +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> > +
> > +#define SCIF_SIZE(reg)         ((reg == SCIF_REG_BRR) || \
> > +                                (reg == SCIF_REG_FTDR) || \
> > +                                (reg == SCIF_REG_FRDR) || \
>
> I don't see the driver programs SCIF_REG_FRDR register. We can just
> remove it to save some cycles.
>
> > +                                (reg == SCIF_REG_SEMR))
>
> The name of this macro is not meaningful. It looks like it's the size
> of a register at the first glance but it's actually returning logical
> true or false.
> Better rename it to something like SCIF_REG_8BIT(reg).
>
Good point, I'll rename it.

> > +
> > +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> > +
> > +/* clang-format on */
> > +
> > +static volatile char *scif_base;
> > +
> > +static u32 get_reg(u32 offset)
> > +{
> > +       if (SCIF_SIZE(offset))
> > +               return readb(scif_base + offset);
> > +
> > +       return readw(scif_base + offset);
> > +}
> > +
> > +static void set_reg(u32 offset, u32 val)
> > +{
> > +       if (SCIF_SIZE(offset))
> > +               return writeb(val, scif_base + offset);
> > +
> > +       return writew(val, scif_base + offset);
> > +}
> > +
> > +static void scif_wait(unsigned long baudrate)
> > +{
> > +       unsigned long utime;
> > +
> > +       utime = 1000000 / baudrate + 1;
>
> What is this?
>
It's the delay required when using the external clock. But as we arent
using it on RZ/Five SMARC we can get rid of it for now.

> > +
> > +       sbi_timer_udelay(utime);
> > +}
> > +
> > +static void renesas_scif_putc(char ch)
> > +{
> > +       uint16_t reg;
> > +
> > +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> > +               ;
> > +
> > +       set_reg(SCIF_REG_FTDR, ch);
> > +       reg = get_reg(SCIF_REG_FSR);
> > +       reg &= ~SCIF_FSR_TXD_CHK;
> > +       set_reg(SCIF_REG_FSR, reg);
>
> The FSR Tx status bits clear should happen before writing a new char
> to the Tx fifo, no?
>
No, this has to be cleared only after char write.

> > +}
> > +
> > +static struct sbi_console_device renesas_scif_console = {
> > +       .name           = "renesas_scif",
> > +       .console_putc   = renesas_scif_putc,
> > +};
> > +
> > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
> > +{
> > +       volatile uint16_t data16;
> > +
> > +       scif_base = (volatile char *)base;
> > +
> > +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS); /* Disable receive & transmit */
> > +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_TFRF); /* Reset assert tx-FIFO & rx-FIFO */
> > +
> > +       data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> > +       set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> > +
> > +       data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> > +       set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> > +
> > +       set_reg(SCIF_REG_SCR, 0x0); /* Select internal clock, SC_CLK pin unused for output pin */
> > +
> > +       set_reg(SCIF_REG_SMR, 0x0); /* Set asynchronous, 8bit data, no-parity, 1 stop and Po/1 */
> > +
> > +       data16 = get_reg(SCIF_REG_SEMR);
> > +       set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS)); /* Select to access BRR */
> > +       set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> > +
> > +       scif_wait(baudrate);
>
> What is this?
>
As mentioned above I'll get rid of it.

> > +
> > +       /* FTCR is left at initial value, because this interrupt isn't used. */
>
> What is FTCR? There is no such register in your defines.
>
It's the "FIFO Trigger Control Register". I'll drop the comment.

Cheers,
Prabhakar


From zhangleizheng at eswincomputing.com  Tue Nov 15 23:27:16 2022
From: zhangleizheng at eswincomputing.com (zhangleizheng at eswincomputing.com)
Date: Wed, 16 Nov 2022 15:27:16 +0800
Subject: [PATCH] platform: andes/ae350: Avoid repeated inclusion of header files
Message-ID: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>

From: zhangleizheng <zhangleizheng at eswincomputing.com>

Avoid cache.h reuse when compiling.

Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
---
 platform/andes/ae350/cache.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
index e1c1826..8e00a1d 100644
--- a/platform/andes/ae350/cache.h
+++ b/platform/andes/ae350/cache.h
@@ -7,6 +7,9 @@
  *   Nylon Chen <nylon7 at andestech.com>
  */
 
+#ifndef _AE350_CACHE_H_
+#define _AE350_CACHE_H_
+
 uintptr_t mcall_set_mcache_ctl(unsigned long input);
 uintptr_t mcall_set_mmisc_ctl(unsigned long input);
 uintptr_t mcall_icache_op(unsigned int enable);
@@ -15,3 +18,5 @@ uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
 uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
 uintptr_t mcall_non_blocking_load_store(unsigned long enable);
 uintptr_t mcall_write_around(unsigned long enable);
+
+#endif /* _AE350_CACHE_H_ */
-- 
2.17.1



From bmeng.cn at gmail.com  Wed Nov 16 00:47:36 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 16 Nov 2022 16:47:36 +0800
Subject: [PATCH] platform: andes/ae350: Avoid repeated inclusion of header files
In-Reply-To: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>
References: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAEUhbmVz1JTN_yWArB4qzj2g_rSEnoxfBLSYhA1KWjUNiWK2=Q@mail.gmail.com>

On Wed, Nov 16, 2022 at 3:29 PM <zhangleizheng at eswincomputing.com> wrote:
>
> From: zhangleizheng <zhangleizheng at eswincomputing.com>
>
> Avoid cache.h reuse when compiling.
>
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>

nits: use "First Name" "Last Name" as the git.user.name

> ---
>  platform/andes/ae350/cache.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
> index e1c1826..8e00a1d 100644
> --- a/platform/andes/ae350/cache.h
> +++ b/platform/andes/ae350/cache.h
> @@ -7,6 +7,9 @@
>   *   Nylon Chen <nylon7 at andestech.com>
>   */
>
> +#ifndef _AE350_CACHE_H_
> +#define _AE350_CACHE_H_
> +
>  uintptr_t mcall_set_mcache_ctl(unsigned long input);
>  uintptr_t mcall_set_mmisc_ctl(unsigned long input);
>  uintptr_t mcall_icache_op(unsigned int enable);
> @@ -15,3 +18,5 @@ uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
>  uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
>  uintptr_t mcall_non_blocking_load_store(unsigned long enable);
>  uintptr_t mcall_write_around(unsigned long enable);
> +
> +#endif /* _AE350_CACHE_H_ */
> --

Otherwise,
Reviewed-by: Bin Meng <bmeng at tinylab.org>


From eric.lin at sifive.com  Wed Nov 16 02:18:26 2022
From: eric.lin at sifive.com (Eric Lin)
Date: Wed, 16 Nov 2022 18:18:26 +0800
Subject: [PATCH] lib: sbi: Bypass CY and IR bit setting in mcountinhibit
Message-ID: <20221116101826.10465-1-eric.lin@sifive.com>

CYCLE and INSTRET counters are part of uABI and they were
re-enable for userspace in Linux riscv pmu driver.

To make these counters increase normally in userspace, we bypass
CY and IR bit checking when setting mcountinhibit register.

LINK:https://lore.kernel.org/all/20220928131807.30386-1-palmer at rivosinc.com/
Signed-off-by: Eric Lin <eric.lin at sifive.com>
---
 lib/sbi/sbi_pmu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 91d9ccc..28107e5 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -318,7 +318,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
 	if (cidx >= num_hw_ctrs || cidx == 1)
 		return SBI_EINVAL;
 
-	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
+	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
 		goto skip_inhibit_update;
 
 	/*
@@ -413,7 +413,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 	unsigned long mctr_inhbt;
 
-	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
+	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
 		return 0;
 
 	mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
-- 
2.36.1



From jrtc27 at jrtc27.com  Wed Nov 16 06:56:32 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Wed, 16 Nov 2022 14:56:32 +0000
Subject: [PATCH] lib: sbi: Bypass CY and IR bit setting in mcountinhibit
In-Reply-To: <20221116101826.10465-1-eric.lin@sifive.com>
References: <20221116101826.10465-1-eric.lin@sifive.com>
Message-ID: <E95DA6B1-DCB9-45D9-BB30-8EC53F2D1596@jrtc27.com>

On 16 Nov 2022, at 10:18, Eric Lin <eric.lin at sifive.com> wrote:
> 
> CYCLE and INSTRET counters are part of uABI and they were
> re-enable for userspace in Linux riscv pmu driver.
> 
> To make these counters increase normally in userspace, we bypass
> CY and IR bit checking when setting mcountinhibit register.
> 
> LINK:https://lore.kernel.org/all/20220928131807.30386-1-palmer at rivosinc.com/
> Signed-off-by: Eric Lin <eric.lin at sifive.com>

If Linux is making SBI calls it doesn?t want then it should stop making
those calls. S-mode requesting CY and IR inhibit bits be set is totally
legitimate in some circumstances, it?s not up to firmware to enforce a
specific S-mode OS policy.

Jess

> ---
> lib/sbi/sbi_pmu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index 91d9ccc..28107e5 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -318,7 +318,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
> 	if (cidx >= num_hw_ctrs || cidx == 1)
> 		return SBI_EINVAL;
> 
> -	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> +	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> 		goto skip_inhibit_update;
> 
> 	/*
> @@ -413,7 +413,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
> 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> 	unsigned long mctr_inhbt;
> 
> -	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> +	if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> 		return 0;
> 
> 	mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
> -- 
> 2.36.1
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



From prabhakar.csengg at gmail.com  Wed Nov 16 07:53:56 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Wed, 16 Nov 2022 15:53:56 +0000
Subject: [PATCH v2 5/7] platform: Add Renesas RZ/Five initial support
In-Reply-To: <CAAhSdy3eJ4YJrFZA0zN_4aMFMM=W_MBJmi_7-ngMSw7y85XCWg@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com> <CAAhSdy3eJ4YJrFZA0zN_4aMFMM=W_MBJmi_7-ngMSw7y85XCWg@mail.gmail.com>
Message-ID: <CA+V-a8voWQyHaT5K4HQM5s_+a=6ObQCYrnBQGsjgNWFJ8wuPfQ@mail.gmail.com>

Hi Anup,

Thank you for the review.

On Tue, Nov 15, 2022 at 11:44 AM Anup Patel <anup at brainfault.org> wrote:
>
> On Fri, Nov 11, 2022 at 11:51 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > This commit provides basic support for the Renesas RZ/Five
> > (R9A07G043F) SoC.
> >
> > The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
> > 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > - Gigabit Ethernet 2ch
> > - CAN interface (CAN-FD) 2ch
> > - USB 2.0 interface 2ch
> > - SD interface 2ch
> > - AD converter 2ch
> >
> > Useful links:
> > -------------
> > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> > [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > RFC->v2
> > * Updated commit description
> > ---
> >  platform/renesas/rzfive/Kconfig           |  32 +++++
> >  platform/renesas/rzfive/configs/defconfig |   0
> >  platform/renesas/rzfive/objects.mk        |  18 +++
> >  platform/renesas/rzfive/platform.c        | 161 ++++++++++++++++++++++
> >  platform/renesas/rzfive/platform.h        |  24 ++++
> >  5 files changed, 235 insertions(+)
> >  create mode 100644 platform/renesas/rzfive/Kconfig
> >  create mode 100644 platform/renesas/rzfive/configs/defconfig
> >  create mode 100644 platform/renesas/rzfive/objects.mk
> >  create mode 100644 platform/renesas/rzfive/platform.c
> >  create mode 100644 platform/renesas/rzfive/platform.h
> >
> > diff --git a/platform/renesas/rzfive/Kconfig b/platform/renesas/rzfive/Kconfig
> > new file mode 100644
> > index 0000000..c5e8a19
> > --- /dev/null
> > +++ b/platform/renesas/rzfive/Kconfig
> > @@ -0,0 +1,32 @@
> > +# SPDX-License-Identifier: BSD-2-Clause
> > +
> > +config PLATFORM_RENESAS_RZFIVE
> > +       bool
> > +       select FDT
> > +       select FDT_SERIAL
> > +       select FDT_SERIAL_RENESAS_SCIF
> > +       select FDT_TIMER
> > +       select FDT_TIMER_PLMT
> > +       select FDT_IRQCHIP
> > +       select FDT_IRQCHIP_PLIC
> > +       select FDT_IPI
> > +       select FDT_IPI_PLICSW
> > +       default y
> > +
> > +if PLATFORM_RENESAS_RZFIVE
> > +
> > +config PLATFORM_RENESAS_RZFIVE_NAME
> > +       string "Platform default name"
> > +       default "Renesas RZ/Five"
> > +
> > +config PLATFORM_RENESAS_RZFIVE_MAJOR_VER
> > +       int "Platform major version"
> > +       range 0 65535
> > +       default 0
> > +
> > +config PLATFORM_RENESAS_RZFIVE_MINOR_VER
> > +       int "Platform minor version"
> > +       range 0 65535
> > +       default 1
> > +
> > +endif
> > diff --git a/platform/renesas/rzfive/configs/defconfig b/platform/renesas/rzfive/configs/defconfig
> > new file mode 100644
> > index 0000000..e69de29
> > diff --git a/platform/renesas/rzfive/objects.mk b/platform/renesas/rzfive/objects.mk
> > new file mode 100644
> > index 0000000..302b3d6
> > --- /dev/null
> > +++ b/platform/renesas/rzfive/objects.mk
> > @@ -0,0 +1,18 @@
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause
> > +#
> > +# Copyright (C) 2022 Renesas Electronics Corp.
> > +#
> > +
> > +# Compiler flags
> > +platform-cppflags-y =
> > +platform-cflags-y =
> > +platform-asflags-y =
> > +platform-ldflags-y =
> > +
> > +# Objects to build
> > +platform-objs-y += ../../andes/ae350/cache.o platform.o
>
> The fact that you have to compile ae350/cache.c as part of this platform
> shows we need to improve code re-use.
>
> Further, the platform.c added by this patch is very similar to platform.c
> of andes/ae350. Both platform.c files are subset of what is already there
> in generic/platform.c.
>
> I suggest you do the following:
> 1) Move andes/ae350 as a platform override under generic/platform/andes/ae350
> 2) Add rzfive as platform override under generic/platform/renesas/rzfive
> 3) The common Andes cache operations will be a library under
>     generic/platform/andes/ae350 which can be selected by renesas/rzfive
> 4) The common Andes header can be under generic/include/andes/ae350
> 5) Enable drivers required by andes/ae350 and renesas/rzfive platform
>     overrides in generic/configs/defconfig
>
- The reason for not using generic is because the FW_TEXT_START is different.
-  I came across the thread where because the generic FW uses FW_PIC
it doesn matter about the FW_TEXT_START, is this correct?
-  Moving forward I built rz/five as part of generic override successfully
- But when I try and build the u-boot with fw_dynamic.bin I get the
below errors:
  - Image 'main-section' is missing external blobs and is
non-functional: opensbi
  - Image 'main-section' has faked external blobs and is
non-functional: fw_dynamic.bin
- Ignoring the warning and still flashing the image I dont get any
output from opensbi.

Am I missing something here?

Cheers,
Prabhakar


From zhangleizheng at eswincomputing.com  Wed Nov 16 23:17:05 2022
From: zhangleizheng at eswincomputing.com (zhangleizheng at eswincomputing.com)
Date: Thu, 17 Nov 2022 15:17:05 +0800
Subject: [PATCH] platform: generic/allwinner: Optimize header file location
Message-ID: <20221117071705.350-1-zhangleizheng@eswincomputing.com>

From: Leizheng Zhang <zhangleizheng at eswincomputing.com>

Optimize sbi/sbi_console.h file location

Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
---
 platform/generic/allwinner/sun20i-d1.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 6a502e5..d2a0f53 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -7,6 +7,7 @@
 #include <platform_override.h>
 #include <thead_c9xx.h>
 #include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
 #include <sbi/sbi_bitops.h>
 #include <sbi/sbi_ecall_interface.h>
 #include <sbi/sbi_error.h>
@@ -201,8 +202,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
 	return 0;
 }
 
-#include <sbi/sbi_console.h>
-
 static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
 {
 	unsigned long mip_val;
-- 
2.17.1



From bmeng.cn at gmail.com  Wed Nov 16 23:28:30 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Thu, 17 Nov 2022 15:28:30 +0800
Subject: [PATCH] platform: generic/allwinner: Optimize header file location
In-Reply-To: <20221117071705.350-1-zhangleizheng@eswincomputing.com>
References: <20221117071705.350-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAEUhbmW50AzOP9kEYbmT3mrVkP18Pqpg09KNL9qS3W=aUthwHA@mail.gmail.com>

On Thu, Nov 17, 2022 at 3:18 PM <zhangleizheng at eswincomputing.com> wrote:
>
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
>
> Optimize sbi/sbi_console.h file location
>
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> ---
>  platform/generic/allwinner/sun20i-d1.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 6a502e5..d2a0f53 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -7,6 +7,7 @@
>  #include <platform_override.h>
>  #include <thead_c9xx.h>
>  #include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>

nits: alphabetically this should be inserted after sbi_bitops.h

>  #include <sbi/sbi_bitops.h>
>  #include <sbi/sbi_ecall_interface.h>
>  #include <sbi/sbi_error.h>
> @@ -201,8 +202,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
>         return 0;
>  }
>
> -#include <sbi/sbi_console.h>
> -
>  static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
>  {
>         unsigned long mip_val;
> --

Otherwise,
Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Nov 16 23:52:18 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Thu, 17 Nov 2022 15:52:18 +0800
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com> <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com>
Message-ID: <CAEUhbmVAtQ+MScY4V6UpjZD+nURCvC7T-2fLC1diz_5GVURsZQ@mail.gmail.com>

Hi Prabhakar,

On Wed, Nov 16, 2022 at 1:34 AM Lad, Prabhakar
<prabhakar.csengg at gmail.com> wrote:
>
> Hi Bin,
>
> Thank you for the review.
>
> On Tue, Nov 15, 2022 at 7:30 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > Add Renesas SCIF driver.
> > >
> > > Based on a patch in the BSP by Takeki Hamada
> > > <takeki.hamada.ak at bp.renesas.com>
> >
> > If there is a public URL for the BSP you mentioned, better put that in
> > the commit here for future reference.
> >
> you mean link for the BSP/File/Commit. Ive followed the same approach
> that we follow on Linux.

Do you have any link for the BSP files, ie: on Renesas website?

>
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > ---
> > > RFC->v2
> > > * Fixed comments pointed by Xiang W
> > > ---
> > >  include/sbi_utils/serial/renesas-scif.h |  11 ++
> > >  lib/utils/serial/Kconfig                |   4 +
> > >  lib/utils/serial/objects.mk             |   1 +
> > >  lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
> > >  4 files changed, 155 insertions(+)
> > >  create mode 100644 include/sbi_utils/serial/renesas-scif.h
> > >  create mode 100644 lib/utils/serial/renesas_scif.c
> > >
> > > diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> > > new file mode 100644
> > > index 0000000..0002a1a
> > > --- /dev/null
> > > +++ b/include/sbi_utils/serial/renesas-scif.h
> > > @@ -0,0 +1,11 @@
> > > +/* SPDX-License-Identifier: BSD-2-Clause */
> > > +/*
> > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > + */
> > > +
> > > +#ifndef __SERIAL_RENESAS_SCIF_H__
> > > +#define __SERIAL_RENESAS_SCIF_H__
> > > +
> > > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> > > +
> > > +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> > > diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> > > index da549a7..f6ed803 100644
> > > --- a/lib/utils/serial/Kconfig
> > > +++ b/lib/utils/serial/Kconfig
> > > @@ -59,6 +59,10 @@ config SERIAL_GAISLER
> > >         bool "Gaisler UART support"
> > >         default n
> > >
> > > +config SERIAL_RENESAS_SCIF
> > > +       bool "Renesas SCIF support"
> > > +       default n
> > > +
> > >  config SERIAL_SHAKTI
> > >         bool "Shakti UART support"
> > >         default n
> > > diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> > > index 98f3f9a..6520424 100644
> > > --- a/lib/utils/serial/objects.mk
> > > +++ b/lib/utils/serial/objects.mk
> > > @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
> > >
> > >  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
> > >  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> > > +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
> > >  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
> > >  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
> > >  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> > > diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> > > new file mode 100644
> > > index 0000000..0586e1a
> > > --- /dev/null
> > > +++ b/lib/utils/serial/renesas_scif.c
> > > @@ -0,0 +1,139 @@
> > > +// SPDX-License-Identifier: BSD-2-Clause
> > > +/*
> > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > + */
> > > +
> > > +#include <sbi/riscv_io.h>
> > > +#include <sbi/sbi_console.h>
> > > +#include <sbi/sbi_timer.h>
> > > +#include <sbi_utils/serial/renesas-scif.h>
> > > +
> > > +/* clang-format off */
> > > +
> > > +#define SCIF_REG_SMR           0x0
> > > +#define SCIF_REG_BRR           0x2
> > > +#define SCIF_REG_SCR           0x4
> > > +#define SCIF_REG_FTDR          0x6
> > > +#define SCIF_REG_FSR           0x8
> > > +#define SCIF_REG_FRDR          0xa
> >
> > This register is not used by the driver. Drop it.
> >
> OK, I will drop it.
>
> > > +#define SCIF_REG_FCR           0xc
> > > +#define SCIF_REG_LSR           0x12
> > > +#define SCIF_REG_SEMR          0x14
> > > +
> > > +#define SCIF_RFRST             0x2 /* Reset assert receive-FIFO (bit[1]) */
> > > +#define SCIF_TFRST             0x4 /* Reset assert transmit-FIFO(bit[2]) */
> >
> > The above 2 macros should probably be named as SCIF_FCR_* as they only
> > apply to the FCR register.
> >
> Agreed.
>
> > > +
> > > +#define SCIF_FCR_RST_ASSRT_TFRF        (SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
> >
> > The macro name should probably be named to have RF come before TF,
> > like SCIF_FCR_RST_ASSRT_RFTF, to keep in consistency with the rest,
> > and the codes.
> >
> Agreed.
>
> > #define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_RFRST | SCIF_TFRST) /*
> > Reset assert rx-FIFO & tx-FIFO */
> >
> > > +#define SCIF_FCR_RST_NGATE_TFRF        0x0 /* Reset negate tx-FIFO & rx-FIFO*/
> >
> > ditto
> >
> > need a space before */
> >
> OK, I will fix it.
>
> > > +
> > > +#define SCIF_RE                        0x10 /* Enable receive (bit[4])  */
> > > +#define SCIF_TE                        0x20 /* Enable transmit(bit[5])  */
> >
> > The above 2 macros should probably be named as SCIF_SCR_* as they only
> > apply to the SCR register.
> >
> Agreed.
>
> > nits: only need one space fore */
> >
> > > +#define SCIF_SCR_RCV_TRN_EN    (SCIF_RE | SCIF_TE) /* Enable receive & transmit */
> > > +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> > > +
> > > +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> > > +#define SCIF_FSR_TEND          0x40 /* Detect break flag */
> > > +#define SCIF_FSR_TDFE          0x20 /* Detect break flag */
> >
> > The comments of the above 2 bit fields are wrong
> >
> Ouch will fix that.
>
> > > +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> > > +#define SCIF_FSR_RDF           0x2  /* Receive FIFO data full flag */
> >
> > This bit field seems not to be used anywhere. Drop it?
> >
> Sure, I will drop it.
>
> > > +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> > > +
> > > +#define SCIF_FSR_RXD_CHK       (SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
> > > +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> > > +
> > > +#define SCIF_LSR_ORER          0x1 /* Overrun error flag */
> >
> > This macro is not used anywhere. Drop it.
> >
> ditto.
>
> > > +
> > > +#define SCIF_SPTR_SPB2DT       0x1 /* if SCR.TE setting, don't care */
> > > +#define SCIF_SPTR_SPB2IO       0x2 /* if SCR.TE setting, don't care */
> >
> > The above 2 macros are not used anywhere. Drop them.
> >
> ditto.
>
> > > +
> > > +#define SCIF_SEMR_BRME         0x20 /* bit-rate modulation enable */
> >
> > This macro is not used anywhere. Drop it.
> >
> ditto.
>
> > > +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> > > +
> > > +#define SCIF_SIZE(reg)         ((reg == SCIF_REG_BRR) || \
> > > +                                (reg == SCIF_REG_FTDR) || \
> > > +                                (reg == SCIF_REG_FRDR) || \
> >
> > I don't see the driver programs SCIF_REG_FRDR register. We can just
> > remove it to save some cycles.
> >
> > > +                                (reg == SCIF_REG_SEMR))
> >
> > The name of this macro is not meaningful. It looks like it's the size
> > of a register at the first glance but it's actually returning logical
> > true or false.
> > Better rename it to something like SCIF_REG_8BIT(reg).
> >
> Good point, I'll rename it.
>
> > > +
> > > +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> > > +
> > > +/* clang-format on */
> > > +
> > > +static volatile char *scif_base;
> > > +
> > > +static u32 get_reg(u32 offset)
> > > +{
> > > +       if (SCIF_SIZE(offset))
> > > +               return readb(scif_base + offset);
> > > +
> > > +       return readw(scif_base + offset);
> > > +}
> > > +
> > > +static void set_reg(u32 offset, u32 val)
> > > +{
> > > +       if (SCIF_SIZE(offset))
> > > +               return writeb(val, scif_base + offset);
> > > +
> > > +       return writew(val, scif_base + offset);
> > > +}
> > > +
> > > +static void scif_wait(unsigned long baudrate)
> > > +{
> > > +       unsigned long utime;
> > > +
> > > +       utime = 1000000 / baudrate + 1;
> >
> > What is this?
> >
> It's the delay required when using the external clock. But as we arent
> using it on RZ/Five SMARC we can get rid of it for now.

Could we make such logic be based on DTS settings, instead of hardcoding?

This driver should be able to support both internal and external clocks, right?

>
> > > +
> > > +       sbi_timer_udelay(utime);
> > > +}
> > > +
> > > +static void renesas_scif_putc(char ch)
> > > +{
> > > +       uint16_t reg;
> > > +
> > > +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> > > +               ;
> > > +
> > > +       set_reg(SCIF_REG_FTDR, ch);
> > > +       reg = get_reg(SCIF_REG_FSR);
> > > +       reg &= ~SCIF_FSR_TXD_CHK;
> > > +       set_reg(SCIF_REG_FSR, reg);
> >
> > The FSR Tx status bits clear should happen before writing a new char
> > to the Tx fifo, no?
> >
> No, this has to be cleared only after char write.

Based on my read of the user manual, after the while () check, we can
clear the status bits. After you write a new char to the FIFO, the
status bits might be triggered by the new char write, instead of the
previous one. Hence clearing status bits after writing char will cause
the status bits check next time fail.

>
> > > +}
> > > +
> > > +static struct sbi_console_device renesas_scif_console = {
> > > +       .name           = "renesas_scif",
> > > +       .console_putc   = renesas_scif_putc,
> > > +};
> > > +
> > > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
> > > +{
> > > +       volatile uint16_t data16;
> > > +
> > > +       scif_base = (volatile char *)base;
> > > +
> > > +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS); /* Disable receive & transmit */
> > > +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_TFRF); /* Reset assert tx-FIFO & rx-FIFO */
> > > +
> > > +       data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> > > +       set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> > > +
> > > +       data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> > > +       set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> > > +
> > > +       set_reg(SCIF_REG_SCR, 0x0); /* Select internal clock, SC_CLK pin unused for output pin */
> > > +
> > > +       set_reg(SCIF_REG_SMR, 0x0); /* Set asynchronous, 8bit data, no-parity, 1 stop and Po/1 */
> > > +
> > > +       data16 = get_reg(SCIF_REG_SEMR);
> > > +       set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS)); /* Select to access BRR */
> > > +       set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> > > +
> > > +       scif_wait(baudrate);
> >
> > What is this?
> >
> As mentioned above I'll get rid of it.
>
> > > +
> > > +       /* FTCR is left at initial value, because this interrupt isn't used. */
> >
> > What is FTCR? There is no such register in your defines.
> >
> It's the "FIFO Trigger Control Register". I'll drop the comment.
>

Regards,
Bin


From samuel at sholland.org  Thu Nov 17 07:04:32 2022
From: samuel at sholland.org (Samuel Holland)
Date: Thu, 17 Nov 2022 09:04:32 -0600
Subject: [PATCH] platform: generic/allwinner: Optimize header file
 location
In-Reply-To: <20221117071705.350-1-zhangleizheng@eswincomputing.com>
References: <20221117071705.350-1-zhangleizheng@eswincomputing.com>
Message-ID: <3cbf7efd-0132-d3d2-60b3-a0e2cb6dabdd@sholland.org>

On 11/17/22 01:17, zhangleizheng at eswincomputing.com wrote:
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> 
> Optimize sbi/sbi_console.h file location
> 
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> ---
>  platform/generic/allwinner/sun20i-d1.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 6a502e5..d2a0f53 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -7,6 +7,7 @@
>  #include <platform_override.h>
>  #include <thead_c9xx.h>
>  #include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>

This header is not actually used anywhere in the file, so you can just
remove it.

Regards,
Samuel

>  #include <sbi/sbi_bitops.h>
>  #include <sbi/sbi_ecall_interface.h>
>  #include <sbi/sbi_error.h>
> @@ -201,8 +202,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
>  	return 0;
>  }
>  
> -#include <sbi/sbi_console.h>
> -
>  static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
>  {
>  	unsigned long mip_val;



From atishp at atishpatra.org  Thu Nov 17 15:00:19 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Thu, 17 Nov 2022 15:00:19 -0800
Subject: [PATCH] lib: sbi: Bypass CY and IR bit setting in mcountinhibit
In-Reply-To: <E95DA6B1-DCB9-45D9-BB30-8EC53F2D1596@jrtc27.com>
References: <20221116101826.10465-1-eric.lin@sifive.com> <E95DA6B1-DCB9-45D9-BB30-8EC53F2D1596@jrtc27.com>
Message-ID: <CAOnJCUKi8NSqNgDyKaT9u7w-bPFeMbCM=K6DYTzW+e+3srYfnA@mail.gmail.com>

On Wed, Nov 16, 2022 at 6:57 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>
> On 16 Nov 2022, at 10:18, Eric Lin <eric.lin at sifive.com> wrote:
> >
> > CYCLE and INSTRET counters are part of uABI and they were
> > re-enable for userspace in Linux riscv pmu driver.
> >
> > To make these counters increase normally in userspace, we bypass
> > CY and IR bit checking when setting mcountinhibit register.
> >
> > LINK:https://lore.kernel.org/all/20220928131807.30386-1-palmer at rivosinc.com/
> > Signed-off-by: Eric Lin <eric.lin at sifive.com>
>
> If Linux is making SBI calls it doesn?t want then it should stop making
> those calls. S-mode requesting CY and IR inhibit bits be set is totally
> legitimate in some circumstances, it?s not up to firmware to enforce a
> specific S-mode OS policy.
>

Yes. Start/sop is required when the user is doing perf stat or record
for these counters.

To increase the CYCLE and INSTRET,
pmu_sbi_starting_cpu( in drivers/perf/riscv_pmu_sbi.c)
should be modified to stop only the programmable counters. Not all.

> Jess
>
> > ---
> > lib/sbi/sbi_pmu.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> > index 91d9ccc..28107e5 100644
> > --- a/lib/sbi/sbi_pmu.c
> > +++ b/lib/sbi/sbi_pmu.c
> > @@ -318,7 +318,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
> >       if (cidx >= num_hw_ctrs || cidx == 1)
> >               return SBI_EINVAL;
> >
> > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> >               goto skip_inhibit_update;
> >
> >       /*
> > @@ -413,7 +413,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
> >       struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> >       unsigned long mctr_inhbt;
> >
> > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> >               return 0;
> >
> >       mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
> > --
> > 2.36.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Regards,
Atish


From zhangleizheng at eswincomputing.com  Thu Nov 17 21:20:29 2022
From: zhangleizheng at eswincomputing.com (zhangleizheng at eswincomputing.com)
Date: Fri, 18 Nov 2022 13:20:29 +0800
Subject: [PATCH v2] platform: generic/allwinner: Remove unused header files
Message-ID: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>

From: Leizheng Zhang <zhangleizheng at eswincomputing.com>

Remove "#include <sbi/sbi_console.h>"

Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
---
 platform/generic/allwinner/sun20i-d1.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 6a502e5..707313b 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -201,8 +201,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
 	return 0;
 }
 
-#include <sbi/sbi_console.h>
-
 static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
 {
 	unsigned long mip_val;
-- 
2.17.1



From prabhakar.csengg at gmail.com  Fri Nov 18 05:07:55 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Fri, 18 Nov 2022 13:07:55 +0000
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <CAEUhbmVAtQ+MScY4V6UpjZD+nURCvC7T-2fLC1diz_5GVURsZQ@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>
 <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com> <CAEUhbmVAtQ+MScY4V6UpjZD+nURCvC7T-2fLC1diz_5GVURsZQ@mail.gmail.com>
Message-ID: <CA+V-a8sJFTQE4xErgjKhZ_7-U9xMqApei1sR6r5GgtzPKK4Mkw@mail.gmail.com>

Hi Bin,

On Thu, Nov 17, 2022 at 7:52 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Prabhakar,
>
> On Wed, Nov 16, 2022 at 1:34 AM Lad, Prabhakar
> <prabhakar.csengg at gmail.com> wrote:
> >
> > Hi Bin,
> >
> > Thank you for the review.
> >
> > On Tue, Nov 15, 2022 at 7:30 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> > >
> > > On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > >
> > > > Add Renesas SCIF driver.
> > > >
> > > > Based on a patch in the BSP by Takeki Hamada
> > > > <takeki.hamada.ak at bp.renesas.com>
> > >
> > > If there is a public URL for the BSP you mentioned, better put that in
> > > the commit here for future reference.
> > >
> > you mean link for the BSP/File/Commit. Ive followed the same approach
> > that we follow on Linux.
>
> Do you have any link for the BSP files, ie: on Renesas website?
>
We have a meta layer link [1] on the website but we got github links
to the files/commit-id too if this is needed.

https://www.renesas.com/us/en/software-tool/rzfive-board-support-package-v10-update1-510-cip#overview

> >
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > ---
> > > > RFC->v2
> > > > * Fixed comments pointed by Xiang W
> > > > ---
> > > >  include/sbi_utils/serial/renesas-scif.h |  11 ++
> > > >  lib/utils/serial/Kconfig                |   4 +
> > > >  lib/utils/serial/objects.mk             |   1 +
> > > >  lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
> > > >  4 files changed, 155 insertions(+)
> > > >  create mode 100644 include/sbi_utils/serial/renesas-scif.h
> > > >  create mode 100644 lib/utils/serial/renesas_scif.c
> > > >
> > > > diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> > > > new file mode 100644
> > > > index 0000000..0002a1a
> > > > --- /dev/null
> > > > +++ b/include/sbi_utils/serial/renesas-scif.h
> > > > @@ -0,0 +1,11 @@
> > > > +/* SPDX-License-Identifier: BSD-2-Clause */
> > > > +/*
> > > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > > + */
> > > > +
> > > > +#ifndef __SERIAL_RENESAS_SCIF_H__
> > > > +#define __SERIAL_RENESAS_SCIF_H__
> > > > +
> > > > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> > > > +
> > > > +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> > > > diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> > > > index da549a7..f6ed803 100644
> > > > --- a/lib/utils/serial/Kconfig
> > > > +++ b/lib/utils/serial/Kconfig
> > > > @@ -59,6 +59,10 @@ config SERIAL_GAISLER
> > > >         bool "Gaisler UART support"
> > > >         default n
> > > >
> > > > +config SERIAL_RENESAS_SCIF
> > > > +       bool "Renesas SCIF support"
> > > > +       default n
> > > > +
> > > >  config SERIAL_SHAKTI
> > > >         bool "Shakti UART support"
> > > >         default n
> > > > diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> > > > index 98f3f9a..6520424 100644
> > > > --- a/lib/utils/serial/objects.mk
> > > > +++ b/lib/utils/serial/objects.mk
> > > > @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
> > > >
> > > >  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
> > > >  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> > > > +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
> > > >  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
> > > >  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
> > > >  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> > > > diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> > > > new file mode 100644
> > > > index 0000000..0586e1a
> > > > --- /dev/null
> > > > +++ b/lib/utils/serial/renesas_scif.c
> > > > @@ -0,0 +1,139 @@
> > > > +// SPDX-License-Identifier: BSD-2-Clause
> > > > +/*
> > > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > > + */
> > > > +
> > > > +#include <sbi/riscv_io.h>
> > > > +#include <sbi/sbi_console.h>
> > > > +#include <sbi/sbi_timer.h>
> > > > +#include <sbi_utils/serial/renesas-scif.h>
> > > > +
> > > > +/* clang-format off */
> > > > +
> > > > +#define SCIF_REG_SMR           0x0
> > > > +#define SCIF_REG_BRR           0x2
> > > > +#define SCIF_REG_SCR           0x4
> > > > +#define SCIF_REG_FTDR          0x6
> > > > +#define SCIF_REG_FSR           0x8
> > > > +#define SCIF_REG_FRDR          0xa
> > >
> > > This register is not used by the driver. Drop it.
> > >
> > OK, I will drop it.
> >
> > > > +#define SCIF_REG_FCR           0xc
> > > > +#define SCIF_REG_LSR           0x12
> > > > +#define SCIF_REG_SEMR          0x14
> > > > +
> > > > +#define SCIF_RFRST             0x2 /* Reset assert receive-FIFO (bit[1]) */
> > > > +#define SCIF_TFRST             0x4 /* Reset assert transmit-FIFO(bit[2]) */
> > >
> > > The above 2 macros should probably be named as SCIF_FCR_* as they only
> > > apply to the FCR register.
> > >
> > Agreed.
> >
> > > > +
> > > > +#define SCIF_FCR_RST_ASSRT_TFRF        (SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
> > >
> > > The macro name should probably be named to have RF come before TF,
> > > like SCIF_FCR_RST_ASSRT_RFTF, to keep in consistency with the rest,
> > > and the codes.
> > >
> > Agreed.
> >
> > > #define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_RFRST | SCIF_TFRST) /*
> > > Reset assert rx-FIFO & tx-FIFO */
> > >
> > > > +#define SCIF_FCR_RST_NGATE_TFRF        0x0 /* Reset negate tx-FIFO & rx-FIFO*/
> > >
> > > ditto
> > >
> > > need a space before */
> > >
> > OK, I will fix it.
> >
> > > > +
> > > > +#define SCIF_RE                        0x10 /* Enable receive (bit[4])  */
> > > > +#define SCIF_TE                        0x20 /* Enable transmit(bit[5])  */
> > >
> > > The above 2 macros should probably be named as SCIF_SCR_* as they only
> > > apply to the SCR register.
> > >
> > Agreed.
> >
> > > nits: only need one space fore */
> > >
> > > > +#define SCIF_SCR_RCV_TRN_EN    (SCIF_RE | SCIF_TE) /* Enable receive & transmit */
> > > > +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> > > > +
> > > > +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> > > > +#define SCIF_FSR_TEND          0x40 /* Detect break flag */
> > > > +#define SCIF_FSR_TDFE          0x20 /* Detect break flag */
> > >
> > > The comments of the above 2 bit fields are wrong
> > >
> > Ouch will fix that.
> >
> > > > +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> > > > +#define SCIF_FSR_RDF           0x2  /* Receive FIFO data full flag */
> > >
> > > This bit field seems not to be used anywhere. Drop it?
> > >
> > Sure, I will drop it.
> >
> > > > +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> > > > +
> > > > +#define SCIF_FSR_RXD_CHK       (SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
> > > > +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> > > > +
> > > > +#define SCIF_LSR_ORER          0x1 /* Overrun error flag */
> > >
> > > This macro is not used anywhere. Drop it.
> > >
> > ditto.
> >
> > > > +
> > > > +#define SCIF_SPTR_SPB2DT       0x1 /* if SCR.TE setting, don't care */
> > > > +#define SCIF_SPTR_SPB2IO       0x2 /* if SCR.TE setting, don't care */
> > >
> > > The above 2 macros are not used anywhere. Drop them.
> > >
> > ditto.
> >
> > > > +
> > > > +#define SCIF_SEMR_BRME         0x20 /* bit-rate modulation enable */
> > >
> > > This macro is not used anywhere. Drop it.
> > >
> > ditto.
> >
> > > > +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> > > > +
> > > > +#define SCIF_SIZE(reg)         ((reg == SCIF_REG_BRR) || \
> > > > +                                (reg == SCIF_REG_FTDR) || \
> > > > +                                (reg == SCIF_REG_FRDR) || \
> > >
> > > I don't see the driver programs SCIF_REG_FRDR register. We can just
> > > remove it to save some cycles.
> > >
> > > > +                                (reg == SCIF_REG_SEMR))
> > >
> > > The name of this macro is not meaningful. It looks like it's the size
> > > of a register at the first glance but it's actually returning logical
> > > true or false.
> > > Better rename it to something like SCIF_REG_8BIT(reg).
> > >
> > Good point, I'll rename it.
> >
> > > > +
> > > > +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> > > > +
> > > > +/* clang-format on */
> > > > +
> > > > +static volatile char *scif_base;
> > > > +
> > > > +static u32 get_reg(u32 offset)
> > > > +{
> > > > +       if (SCIF_SIZE(offset))
> > > > +               return readb(scif_base + offset);
> > > > +
> > > > +       return readw(scif_base + offset);
> > > > +}
> > > > +
> > > > +static void set_reg(u32 offset, u32 val)
> > > > +{
> > > > +       if (SCIF_SIZE(offset))
> > > > +               return writeb(val, scif_base + offset);
> > > > +
> > > > +       return writew(val, scif_base + offset);
> > > > +}
> > > > +
> > > > +static void scif_wait(unsigned long baudrate)
> > > > +{
> > > > +       unsigned long utime;
> > > > +
> > > > +       utime = 1000000 / baudrate + 1;
> > >
> > > What is this?
> > >
> > It's the delay required when using the external clock. But as we arent
> > using it on RZ/Five SMARC we can get rid of it for now.
>
> Could we make such logic be based on DTS settings, instead of hardcoding?
>
> This driver should be able to support both internal and external clocks, right?
>
Agreed it can be checked by DTS. For now I will drop this until I have
the HW to test this with EXT clock.

> >
> > > > +
> > > > +       sbi_timer_udelay(utime);
> > > > +}
> > > > +
> > > > +static void renesas_scif_putc(char ch)
> > > > +{
> > > > +       uint16_t reg;
> > > > +
> > > > +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> > > > +               ;
> > > > +
> > > > +       set_reg(SCIF_REG_FTDR, ch);
> > > > +       reg = get_reg(SCIF_REG_FSR);
> > > > +       reg &= ~SCIF_FSR_TXD_CHK;
> > > > +       set_reg(SCIF_REG_FSR, reg);
> > >
> > > The FSR Tx status bits clear should happen before writing a new char
> > > to the Tx fifo, no?
> > >
> > No, this has to be cleared only after char write.
>
> Based on my read of the user manual, after the while () check, we can
> clear the status bits. After you write a new char to the FIFO, the
> status bits might be triggered by the new char write, instead of the
> previous one. Hence clearing status bits after writing char will cause
> the status bits check next time fail.
>
>From the HW manual..
[Clearing conditions]
? TDFE is cleared to 0 when 0 is written in the TDFE bit after reading TDFE = 1.
? When transmit data is written to the FTDR register
^^ hence its cleared after the write here.

In Linux and u-boot too we follow the same approach with the existing
SCI/F driver.

Cheers,
Prabhakar


From bmeng.cn at gmail.com  Fri Nov 18 18:02:36 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 19 Nov 2022 10:02:36 +0800
Subject: [PATCH v2] platform: generic/allwinner: Remove unused header files
In-Reply-To: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
References: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAEUhbmU6JASkBWZoOs5HZLNy125YBQvdod9cJuFyTLi+LmtpXQ@mail.gmail.com>

On Fri, Nov 18, 2022 at 1:22 PM <zhangleizheng at eswincomputing.com> wrote:
>
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
>
> Remove "#include <sbi/sbi_console.h>"
>
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> ---
>  platform/generic/allwinner/sun20i-d1.c | 2 --
>  1 file changed, 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From wxjstz at 126.com  Sat Nov 19 00:27:58 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 19 Nov 2022 16:27:58 +0800
Subject: [PATCH v2] platform: generic/allwinner: Remove unused header
 files
In-Reply-To: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
References: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
Message-ID: <03bbab92b95b4341c47bf0fbb7e9d68458fa15c0.camel@126.com>

? 2022-11-18???? 13:20 +0800?zhangleizheng at eswincomputing.com???
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> 
> Remove "#include <sbi/sbi_console.h>"
> 
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?platform/generic/allwinner/sun20i-d1.c | 2 --
> ?1 file changed, 2 deletions(-)
> 
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 6a502e5..707313b 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -201,8 +201,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
> ????????return 0;
> ?}
> ?
> -#include <sbi/sbi_console.h>
> -
> ?static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
> ?{
> ????????unsigned long mip_val;
> -- 
> 2.17.1
> 
> 




From wxjstz at 126.com  Sat Nov 19 00:55:07 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 19 Nov 2022 16:55:07 +0800
Subject: [PATCH] platform: generic/allwinner: Remove ghostly type cast
Message-ID: <20221119085507.156418-1-wxjstz@126.com>

Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init
to be u32 for a while and u64 for a while.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 platform/generic/allwinner/sun20i-d1.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 6a502e5..18fcf56 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -146,14 +146,14 @@ static void sun20i_d1_riscv_cfg_restore(void)
 
 static void sun20i_d1_riscv_cfg_init(void)
 {
-	unsigned long entry = sbi_hartid_to_scratch(0)->warmboot_addr;
+	u64 entry = sbi_hartid_to_scratch(0)->warmboot_addr;
 
 	/* Enable MMIO access. */
 	writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
 
 	/* Program the reset entry address. */
-	writel_relaxed((u32)entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
-	writel_relaxed((u64)entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
+	writel_relaxed(entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
+	writel_relaxed(entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
 }
 
 static int sun20i_d1_hart_suspend(u32 suspend_type)
-- 
2.30.2



From bmeng.cn at gmail.com  Sun Nov 20 03:59:33 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sun, 20 Nov 2022 19:59:33 +0800
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <CA+V-a8sJFTQE4xErgjKhZ_7-U9xMqApei1sR6r5GgtzPKK4Mkw@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>
 <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com>
 <CAEUhbmVAtQ+MScY4V6UpjZD+nURCvC7T-2fLC1diz_5GVURsZQ@mail.gmail.com> <CA+V-a8sJFTQE4xErgjKhZ_7-U9xMqApei1sR6r5GgtzPKK4Mkw@mail.gmail.com>
Message-ID: <CAEUhbmV=vg4iap1h9h1Q0Ejvad4e2ZwVETjLqOarc-ajZYjTag@mail.gmail.com>

Hi Prabhakar,

On Fri, Nov 18, 2022 at 9:08 PM Lad, Prabhakar
<prabhakar.csengg at gmail.com> wrote:
>
> Hi Bin,
>
> On Thu, Nov 17, 2022 at 7:52 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, Nov 16, 2022 at 1:34 AM Lad, Prabhakar
> > <prabhakar.csengg at gmail.com> wrote:
> > >
> > > Hi Bin,
> > >
> > > Thank you for the review.
> > >
> > > On Tue, Nov 15, 2022 at 7:30 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> > > >
> > > > On Sat, Nov 12, 2022 at 2:22 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > >
> > > > > Add Renesas SCIF driver.
> > > > >
> > > > > Based on a patch in the BSP by Takeki Hamada
> > > > > <takeki.hamada.ak at bp.renesas.com>
> > > >
> > > > If there is a public URL for the BSP you mentioned, better put that in
> > > > the commit here for future reference.
> > > >
> > > you mean link for the BSP/File/Commit. Ive followed the same approach
> > > that we follow on Linux.
> >
> > Do you have any link for the BSP files, ie: on Renesas website?
> >
> We have a meta layer link [1] on the website but we got github links
> to the files/commit-id too if this is needed.
>
> https://www.renesas.com/us/en/software-tool/rzfive-board-support-package-v10-update1-510-cip#overview
>
> > >
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > > ---
> > > > > RFC->v2
> > > > > * Fixed comments pointed by Xiang W
> > > > > ---
> > > > >  include/sbi_utils/serial/renesas-scif.h |  11 ++
> > > > >  lib/utils/serial/Kconfig                |   4 +
> > > > >  lib/utils/serial/objects.mk             |   1 +
> > > > >  lib/utils/serial/renesas_scif.c         | 139 ++++++++++++++++++++++++
> > > > >  4 files changed, 155 insertions(+)
> > > > >  create mode 100644 include/sbi_utils/serial/renesas-scif.h
> > > > >  create mode 100644 lib/utils/serial/renesas_scif.c
> > > > >
> > > > > diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> > > > > new file mode 100644
> > > > > index 0000000..0002a1a
> > > > > --- /dev/null
> > > > > +++ b/include/sbi_utils/serial/renesas-scif.h
> > > > > @@ -0,0 +1,11 @@
> > > > > +/* SPDX-License-Identifier: BSD-2-Clause */
> > > > > +/*
> > > > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > > > + */
> > > > > +
> > > > > +#ifndef __SERIAL_RENESAS_SCIF_H__
> > > > > +#define __SERIAL_RENESAS_SCIF_H__
> > > > > +
> > > > > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> > > > > +
> > > > > +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> > > > > diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> > > > > index da549a7..f6ed803 100644
> > > > > --- a/lib/utils/serial/Kconfig
> > > > > +++ b/lib/utils/serial/Kconfig
> > > > > @@ -59,6 +59,10 @@ config SERIAL_GAISLER
> > > > >         bool "Gaisler UART support"
> > > > >         default n
> > > > >
> > > > > +config SERIAL_RENESAS_SCIF
> > > > > +       bool "Renesas SCIF support"
> > > > > +       default n
> > > > > +
> > > > >  config SERIAL_SHAKTI
> > > > >         bool "Shakti UART support"
> > > > >         default n
> > > > > diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> > > > > index 98f3f9a..6520424 100644
> > > > > --- a/lib/utils/serial/objects.mk
> > > > > +++ b/lib/utils/serial/objects.mk
> > > > > @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
> > > > >
> > > > >  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
> > > > >  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> > > > > +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
> > > > >  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
> > > > >  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
> > > > >  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> > > > > diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> > > > > new file mode 100644
> > > > > index 0000000..0586e1a
> > > > > --- /dev/null
> > > > > +++ b/lib/utils/serial/renesas_scif.c
> > > > > @@ -0,0 +1,139 @@
> > > > > +// SPDX-License-Identifier: BSD-2-Clause
> > > > > +/*
> > > > > + * Copyright (C) 2022 Renesas Electronics Corporation
> > > > > + */
> > > > > +
> > > > > +#include <sbi/riscv_io.h>
> > > > > +#include <sbi/sbi_console.h>
> > > > > +#include <sbi/sbi_timer.h>
> > > > > +#include <sbi_utils/serial/renesas-scif.h>
> > > > > +
> > > > > +/* clang-format off */
> > > > > +
> > > > > +#define SCIF_REG_SMR           0x0
> > > > > +#define SCIF_REG_BRR           0x2
> > > > > +#define SCIF_REG_SCR           0x4
> > > > > +#define SCIF_REG_FTDR          0x6
> > > > > +#define SCIF_REG_FSR           0x8
> > > > > +#define SCIF_REG_FRDR          0xa
> > > >
> > > > This register is not used by the driver. Drop it.
> > > >
> > > OK, I will drop it.
> > >
> > > > > +#define SCIF_REG_FCR           0xc
> > > > > +#define SCIF_REG_LSR           0x12
> > > > > +#define SCIF_REG_SEMR          0x14
> > > > > +
> > > > > +#define SCIF_RFRST             0x2 /* Reset assert receive-FIFO (bit[1]) */
> > > > > +#define SCIF_TFRST             0x4 /* Reset assert transmit-FIFO(bit[2]) */
> > > >
> > > > The above 2 macros should probably be named as SCIF_FCR_* as they only
> > > > apply to the FCR register.
> > > >
> > > Agreed.
> > >
> > > > > +
> > > > > +#define SCIF_FCR_RST_ASSRT_TFRF        (SCIF_RFRST | SCIF_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
> > > >
> > > > The macro name should probably be named to have RF come before TF,
> > > > like SCIF_FCR_RST_ASSRT_RFTF, to keep in consistency with the rest,
> > > > and the codes.
> > > >
> > > Agreed.
> > >
> > > > #define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_RFRST | SCIF_TFRST) /*
> > > > Reset assert rx-FIFO & tx-FIFO */
> > > >
> > > > > +#define SCIF_FCR_RST_NGATE_TFRF        0x0 /* Reset negate tx-FIFO & rx-FIFO*/
> > > >
> > > > ditto
> > > >
> > > > need a space before */
> > > >
> > > OK, I will fix it.
> > >
> > > > > +
> > > > > +#define SCIF_RE                        0x10 /* Enable receive (bit[4])  */
> > > > > +#define SCIF_TE                        0x20 /* Enable transmit(bit[5])  */
> > > >
> > > > The above 2 macros should probably be named as SCIF_SCR_* as they only
> > > > apply to the SCR register.
> > > >
> > > Agreed.
> > >
> > > > nits: only need one space fore */
> > > >
> > > > > +#define SCIF_SCR_RCV_TRN_EN    (SCIF_RE | SCIF_TE) /* Enable receive & transmit */
> > > > > +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> > > > > +
> > > > > +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> > > > > +#define SCIF_FSR_TEND          0x40 /* Detect break flag */
> > > > > +#define SCIF_FSR_TDFE          0x20 /* Detect break flag */
> > > >
> > > > The comments of the above 2 bit fields are wrong
> > > >
> > > Ouch will fix that.
> > >
> > > > > +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> > > > > +#define SCIF_FSR_RDF           0x2  /* Receive FIFO data full flag */
> > > >
> > > > This bit field seems not to be used anywhere. Drop it?
> > > >
> > > Sure, I will drop it.
> > >
> > > > > +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> > > > > +
> > > > > +#define SCIF_FSR_RXD_CHK       (SCIF_FSR_ER | SCIF_FSR_BRK | SCIF_FSR_DR)
> > > > > +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> > > > > +
> > > > > +#define SCIF_LSR_ORER          0x1 /* Overrun error flag */
> > > >
> > > > This macro is not used anywhere. Drop it.
> > > >
> > > ditto.
> > >
> > > > > +
> > > > > +#define SCIF_SPTR_SPB2DT       0x1 /* if SCR.TE setting, don't care */
> > > > > +#define SCIF_SPTR_SPB2IO       0x2 /* if SCR.TE setting, don't care */
> > > >
> > > > The above 2 macros are not used anywhere. Drop them.
> > > >
> > > ditto.
> > >
> > > > > +
> > > > > +#define SCIF_SEMR_BRME         0x20 /* bit-rate modulation enable */
> > > >
> > > > This macro is not used anywhere. Drop it.
> > > >
> > > ditto.
> > >
> > > > > +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> > > > > +
> > > > > +#define SCIF_SIZE(reg)         ((reg == SCIF_REG_BRR) || \
> > > > > +                                (reg == SCIF_REG_FTDR) || \
> > > > > +                                (reg == SCIF_REG_FRDR) || \
> > > >
> > > > I don't see the driver programs SCIF_REG_FRDR register. We can just
> > > > remove it to save some cycles.
> > > >
> > > > > +                                (reg == SCIF_REG_SEMR))
> > > >
> > > > The name of this macro is not meaningful. It looks like it's the size
> > > > of a register at the first glance but it's actually returning logical
> > > > true or false.
> > > > Better rename it to something like SCIF_REG_8BIT(reg).
> > > >
> > > Good point, I'll rename it.
> > >
> > > > > +
> > > > > +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> > > > > +
> > > > > +/* clang-format on */
> > > > > +
> > > > > +static volatile char *scif_base;
> > > > > +
> > > > > +static u32 get_reg(u32 offset)
> > > > > +{
> > > > > +       if (SCIF_SIZE(offset))
> > > > > +               return readb(scif_base + offset);
> > > > > +
> > > > > +       return readw(scif_base + offset);
> > > > > +}
> > > > > +
> > > > > +static void set_reg(u32 offset, u32 val)
> > > > > +{
> > > > > +       if (SCIF_SIZE(offset))
> > > > > +               return writeb(val, scif_base + offset);
> > > > > +
> > > > > +       return writew(val, scif_base + offset);
> > > > > +}
> > > > > +
> > > > > +static void scif_wait(unsigned long baudrate)
> > > > > +{
> > > > > +       unsigned long utime;
> > > > > +
> > > > > +       utime = 1000000 / baudrate + 1;
> > > >
> > > > What is this?
> > > >
> > > It's the delay required when using the external clock. But as we arent
> > > using it on RZ/Five SMARC we can get rid of it for now.
> >
> > Could we make such logic be based on DTS settings, instead of hardcoding?
> >
> > This driver should be able to support both internal and external clocks, right?
> >
> Agreed it can be checked by DTS. For now I will drop this until I have
> the HW to test this with EXT clock.
>
> > >
> > > > > +
> > > > > +       sbi_timer_udelay(utime);
> > > > > +}
> > > > > +
> > > > > +static void renesas_scif_putc(char ch)
> > > > > +{
> > > > > +       uint16_t reg;
> > > > > +
> > > > > +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> > > > > +               ;
> > > > > +
> > > > > +       set_reg(SCIF_REG_FTDR, ch);
> > > > > +       reg = get_reg(SCIF_REG_FSR);
> > > > > +       reg &= ~SCIF_FSR_TXD_CHK;
> > > > > +       set_reg(SCIF_REG_FSR, reg);
> > > >
> > > > The FSR Tx status bits clear should happen before writing a new char
> > > > to the Tx fifo, no?
> > > >
> > > No, this has to be cleared only after char write.
> >
> > Based on my read of the user manual, after the while () check, we can
> > clear the status bits. After you write a new char to the FIFO, the
> > status bits might be triggered by the new char write, instead of the
> > previous one. Hence clearing status bits after writing char will cause
> > the status bits check next time fail.
> >
> From the HW manual..
> [Clearing conditions]
> ? TDFE is cleared to 0 when 0 is written in the TDFE bit after reading TDFE = 1.
> ? When transmit data is written to the FTDR register
> ^^ hence its cleared after the write here.

These 2 conditions are OR, not AND, right?

So when the while loop breaks, it satisfies the first condition, and
we can clear the TDFE bit by writing zero to FSR.

But if you write the tx data to the FTDR register, after you do

set_reg(SCIF_REG_FTDR, ch);

There is a possibility that the TDFE bit is generated before before you do

reg = get_reg(SCIF_REG_FSR);
reg &= ~SCIF_FSR_TXD_CHK;
set_reg(SCIF_REG_FSR, reg);

then the TDFE bit gets cleared unexpectedly.

Next time when you want to write another char to the serial port the
while loop will never break.

>
> In Linux and u-boot too we follow the same approach with the existing
> SCI/F driver.

Regards,
Bin


From zhangleizheng at eswincomputing.com  Mon Nov 21 00:26:22 2022
From: zhangleizheng at eswincomputing.com (zhangleizheng at eswincomputing.com)
Date: Mon, 21 Nov 2022 16:26:22 +0800
Subject: [PATCH v2] firmware: payloads: Optimize usage of "ALIGN"
Message-ID: <20221121082622.1495-1-zhangleizheng@eswincomputing.com>

From: Leizheng Zhang <zhangleizheng at eswincomputing.com>

Delete the redundant "ALIGN" and adjust the position of "ALIGN"

Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
---
 firmware/fw_base.ldS           | 10 ++++------
 firmware/payloads/test.elf.ldS | 12 +++++-------
 2 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
index 220c043..5ea549f 100644
--- a/firmware/fw_base.ldS
+++ b/firmware/fw_base.ldS
@@ -24,13 +24,11 @@
 		PROVIDE(_text_end = .);
 	}
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* End of the code sections */
 
-	/* Beginning of the read-only data sections */
+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+	/* Beginning of the read-only data sections */
 
 	.rodata :
 	{
@@ -42,10 +40,10 @@
 
 	/* End of the read-only data sections */
 
-	/* Beginning of the read-write data sections */
-
 	. = ALIGN(0x1000); /* Ensure next section is page aligned */
 
+	/* Beginning of the read-write data sections */
+
 	.data :
 	{
 		PROVIDE(_data_start = .);
diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
index f3f3242..8d18a9c 100644
--- a/firmware/payloads/test.elf.ldS
+++ b/firmware/payloads/test.elf.ldS
@@ -33,13 +33,11 @@ SECTIONS
 		PROVIDE(_text_end = .);
 	}
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
-
 	/* End of the code sections */
 
-	/* Beginning of the read-only data sections */
+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
 
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+	/* Beginning of the read-only data sections */
 
 	.rodata :
 	{
@@ -51,10 +49,10 @@ SECTIONS
 
 	/* End of the read-only data sections */
 
-	/* Beginning of the read-write data sections */
-
-	. = ALIGN(0x1000); /* Ensure next section is page aligned */
+	. = ALIGN(0x1000); /* Ensure next section is page aligned */
 
+	/* Beginning of the read-write data sections */
+	
 	.data :
 	{
 		PROVIDE(_data_start = .);
-- 
2.17.1



From bmeng.cn at gmail.com  Mon Nov 21 01:29:12 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Mon, 21 Nov 2022 17:29:12 +0800
Subject: [PATCH v2] firmware: payloads: Optimize usage of "ALIGN"
In-Reply-To: <20221121082622.1495-1-zhangleizheng@eswincomputing.com>
References: <20221121082622.1495-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAEUhbmUs-7uyaXQGVh62B1F_F7bnKTw=sc5u-h6vVyOOCP4Jkw@mail.gmail.com>

On Mon, Nov 21, 2022 at 4:29 PM <zhangleizheng at eswincomputing.com> wrote:
>
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
>
> Delete the redundant "ALIGN" and adjust the position of "ALIGN"
>
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>
> ---
>  firmware/fw_base.ldS           | 10 ++++------
>  firmware/payloads/test.elf.ldS | 12 +++++-------
>  2 files changed, 9 insertions(+), 13 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From kalle.wachsmuth at gmail.com  Mon Nov 21 07:59:05 2022
From: kalle.wachsmuth at gmail.com (KaDiWa)
Date: Mon, 21 Nov 2022 16:59:05 +0100
Subject: [PATCH] Makefile: replace `echo` with `printf` for compatibility
Message-ID: <20221121155905.48577-1-kalle.wachsmuth@gmail.com>

I don't know why but `echo -n` didn't work for me. macOS supports the `-n` option but it doesn't work in the makefile. What it does instead is it literally writes `-n` to the file and then also
leaves a newline at the end.

I'm using GNU Make 4.4 (`gmake` from Homebrew).

Signed-off-by: KaDiWa <kalle.wachsmuth at gmail.com>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 8db6eab..98e42fc 100644
--- a/Makefile
+++ b/Makefile
@@ -224,7 +224,7 @@ $(KCONFIG_CONFIG): $(platform_src_dir)/configs/$(PLATFORM_DEFCONFIG) $(platform_
 
 $(KCONFIG_AUTOCMD): $(KCONFIG_CONFIG)
 	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
-	$(CMD_PREFIX)echo -n "$(KCONFIG_CONFIG): " > $(KCONFIG_AUTOCMD)
+	$(CMD_PREFIX)printf "%s: " $(KCONFIG_CONFIG) > $(KCONFIG_AUTOCMD)
 	$(CMD_PREFIX)cat $(KCONFIG_AUTOLIST) | tr '\n' ' ' >> $(KCONFIG_AUTOCMD)
 
 include $(KCONFIG_CONFIG)
-- 
2.37.1 (Apple Git-137.1)



From ajones at ventanamicro.com  Mon Nov 21 21:17:16 2022
From: ajones at ventanamicro.com (Andrew Jones)
Date: Tue, 22 Nov 2022 06:17:16 +0100
Subject: [PATCH] Makefile: replace `echo` with `printf` for compatibility
In-Reply-To: <20221121155905.48577-1-kalle.wachsmuth@gmail.com>
References: <20221121155905.48577-1-kalle.wachsmuth@gmail.com>
Message-ID: <20221122051716.akv4prhx3otgqazd@kamzik>

On Mon, Nov 21, 2022 at 04:59:05PM +0100, KaDiWa wrote:
> I don't know why but `echo -n` didn't work for me. macOS supports the `-n` option but it doesn't work in the makefile. What it does instead is it literally writes `-n` to the file and then also
> leaves a newline at the end.
> 
> I'm using GNU Make 4.4 (`gmake` from Homebrew).
> 
> Signed-off-by: KaDiWa <kalle.wachsmuth at gmail.com>
> ---
>  Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Makefile b/Makefile
> index 8db6eab..98e42fc 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -224,7 +224,7 @@ $(KCONFIG_CONFIG): $(platform_src_dir)/configs/$(PLATFORM_DEFCONFIG) $(platform_
>  
>  $(KCONFIG_AUTOCMD): $(KCONFIG_CONFIG)
>  	$(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
> -	$(CMD_PREFIX)echo -n "$(KCONFIG_CONFIG): " > $(KCONFIG_AUTOCMD)
> +	$(CMD_PREFIX)printf "%s: " $(KCONFIG_CONFIG) > $(KCONFIG_AUTOCMD)
>  	$(CMD_PREFIX)cat $(KCONFIG_AUTOLIST) | tr '\n' ' ' >> $(KCONFIG_AUTOCMD)
>  
>  include $(KCONFIG_CONFIG)
> -- 
> 2.37.1 (Apple Git-137.1)
> 
>

Reviewed-by: Andrew Jones <ajones at ventanamicro.com>


From anup at brainfault.org  Mon Nov 21 21:55:28 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 22 Nov 2022 11:25:28 +0530
Subject: [PATCH v2] firmware: payloads: Optimize usage of "ALIGN"
In-Reply-To: <20221121082622.1495-1-zhangleizheng@eswincomputing.com>
References: <20221121082622.1495-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAAhSdy12v2Xy+42O+3m7dZdS4AdTOwReCzWaG48eMxZJk398Dg@mail.gmail.com>

On Mon, Nov 21, 2022 at 1:58 PM <zhangleizheng at eswincomputing.com> wrote:
>
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
>
> Delete the redundant "ALIGN" and adjust the position of "ALIGN"
>
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>

Please carry the Reviewed-by tags which you obtained on your
previous patch revision.

For now, I had to manually pull Reviewed-by tags from the previous
patch.

Applied this patch to the riscv/opensbi repo.

Regards,
Anup
> ---
>  firmware/fw_base.ldS           | 10 ++++------
>  firmware/payloads/test.elf.ldS | 12 +++++-------
>  2 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS
> index 220c043..5ea549f 100644
> --- a/firmware/fw_base.ldS
> +++ b/firmware/fw_base.ldS
> @@ -24,13 +24,11 @@
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */
>
> -       /* Beginning of the read-only data sections */
> +       . = ALIGN(0x1000); /* Ensure next section is page aligned */
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> +       /* Beginning of the read-only data sections */
>
>         .rodata :
>         {
> @@ -42,10 +40,10 @@
>
>         /* End of the read-only data sections */
>
> -       /* Beginning of the read-write data sections */
> -
>         . = ALIGN(0x1000); /* Ensure next section is page aligned */
>
> +       /* Beginning of the read-write data sections */
> +
>         .data :
>         {
>                 PROVIDE(_data_start = .);
> diff --git a/firmware/payloads/test.elf.ldS b/firmware/payloads/test.elf.ldS
> index f3f3242..8d18a9c 100644
> --- a/firmware/payloads/test.elf.ldS
> +++ b/firmware/payloads/test.elf.ldS
> @@ -33,13 +33,11 @@ SECTIONS
>                 PROVIDE(_text_end = .);
>         }
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> -
>         /* End of the code sections */
>
> -       /* Beginning of the read-only data sections */
> +       . = ALIGN(0x1000); /* Ensure next section is page aligned */
>
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> +       /* Beginning of the read-only data sections */
>
>         .rodata :
>         {
> @@ -51,10 +49,10 @@ SECTIONS
>
>         /* End of the read-only data sections */
>
> -       /* Beginning of the read-write data sections */
> -
> -       . = ALIGN(0x1000); /* Ensure next section is page aligned */
> +       . = ALIGN(0x1000); /* Ensure next section is page aligned */
>
> +       /* Beginning of the read-write data sections */
> +
>         .data :
>         {
>                 PROVIDE(_data_start = .);
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Nov 21 22:31:13 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 22 Nov 2022 12:01:13 +0530
Subject: [PATCH v2] platform: generic/allwinner: Remove unused header files
In-Reply-To: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
References: <20221118052029.1275-1-zhangleizheng@eswincomputing.com>
Message-ID: <CAAhSdy0dVEt2pjsQPE0cuE5_WCBXVn9aq3Udm6MX-=nvdjGfZw@mail.gmail.com>

On Fri, Nov 18, 2022 at 10:51 AM <zhangleizheng at eswincomputing.com> wrote:
>
> From: Leizheng Zhang <zhangleizheng at eswincomputing.com>
>
> Remove "#include <sbi/sbi_console.h>"
>
> Signed-off-by: Leizheng Zhang <zhangleizheng at eswincomputing.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  platform/generic/allwinner/sun20i-d1.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 6a502e5..707313b 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -201,8 +201,6 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
>         return 0;
>  }
>
> -#include <sbi/sbi_console.h>
> -
>  static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
>  {
>         unsigned long mip_val;
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From qinhaijun at eswincomputing.com  Mon Nov 21 23:13:20 2022
From: qinhaijun at eswincomputing.com (qinhaijun at eswincomputing.com)
Date: Tue, 22 Nov 2022 15:13:20 +0800
Subject: [PATCH 0/1] add check for function parameter
Message-ID: <20221122071321.4274-1-qinhaijun@eswincomputing.com>

From: haijun qin <qinhaijun at eswincomputing.com>

sbi_ecall_base_handler is the interface for external calls, Object-oriented 
will be complex. So add pointer check to avoid calling errors.

haijun qin (1):
  lib: sbi_ecall_base: add check for function parameter pointers

 lib/sbi/sbi_ecall_base.c | 3 +++
 1 file changed, 3 insertions(+)


base-commit: 22f38ee6c658a660083aa45c4ec6c72f66a17260
-- 
2.17.1



From qinhaijun at eswincomputing.com  Mon Nov 21 23:13:21 2022
From: qinhaijun at eswincomputing.com (qinhaijun at eswincomputing.com)
Date: Tue, 22 Nov 2022 15:13:21 +0800
Subject: [PATCH 1/1] lib: sbi_ecall_base: add check for function parameter pointers
In-Reply-To: <20221122071321.4274-1-qinhaijun@eswincomputing.com>
References: <20221122071321.4274-1-qinhaijun@eswincomputing.com>
Message-ID: <20221122071321.4274-2-qinhaijun@eswincomputing.com>

From: haijun qin <qinhaijun at eswincomputing.com>

When a null pointer is passed in by mistake, the program will
enter the trap, so the check for the pointer is added.

Signed-off-by: haijun qin <qinhaijun at eswincomputing.com>
---
 lib/sbi/sbi_ecall_base.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/sbi/sbi_ecall_base.c b/lib/sbi/sbi_ecall_base.c
index 786d2ac..3d4a367 100644
--- a/lib/sbi/sbi_ecall_base.c
+++ b/lib/sbi/sbi_ecall_base.c
@@ -39,6 +39,9 @@ static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
 {
 	int ret = 0;
 
+	if(out_val == NULL)
+		return SBI_EINVALID_ADDR;
+
 	switch (funcid) {
 	case SBI_EXT_BASE_GET_SPEC_VERSION:
 		*out_val = (SBI_ECALL_VERSION_MAJOR <<
-- 
2.17.1



From wxjstz at 126.com  Tue Nov 22 00:17:21 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 22 Nov 2022 16:17:21 +0800
Subject: [PATCH 1/1] lib: sbi_ecall_base: add check for function
 parameter pointers
In-Reply-To: <20221122071321.4274-2-qinhaijun@eswincomputing.com>
References: <20221122071321.4274-1-qinhaijun@eswincomputing.com>
	 <20221122071321.4274-2-qinhaijun@eswincomputing.com>
Message-ID: <b5cfcd9458ff53b8ee0fb5042003476b9c859338.camel@126.com>

? 2022-11-22???? 15:13 +0800?qinhaijun at eswincomputing.com???
> From: haijun qin <qinhaijun at eswincomputing.com>
> 
> When a null pointer is passed in by mistake, the program will
> enter the trap, so the check for the pointer is added.
> 
> Signed-off-by: haijun qin <qinhaijun at eswincomputing.com>

sbi_ecall_extension->handle is only called at
https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_ecall.c#L110, 
where out_val is not empty.

If you want to detect parameters, you also need to detect regs and out_trap. and
add code like this in each extension implementation.

Regards,
Xiang W
> ---
> ?lib/sbi/sbi_ecall_base.c | 3 +++
> ?1 file changed, 3 insertions(+)
> 
> diff --git a/lib/sbi/sbi_ecall_base.c b/lib/sbi/sbi_ecall_base.c
> index 786d2ac..3d4a367 100644
> --- a/lib/sbi/sbi_ecall_base.c
> +++ b/lib/sbi/sbi_ecall_base.c
> @@ -39,6 +39,9 @@ static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
> ?{
> ????????int ret = 0;
> ?
> +???????if(out_val == NULL)
> +???????????????return SBI_EINVALID_ADDR;
> +
> ????????switch (funcid) {
> ????????case SBI_EXT_BASE_GET_SPEC_VERSION:
> ????????????????*out_val = (SBI_ECALL_VERSION_MAJOR <<
> -- 
> 2.17.1
> 
> 




From aldaya at gmail.com  Tue Nov 22 02:28:25 2022
From: aldaya at gmail.com (Alejandro Cabrera Aldaya)
Date: Tue, 22 Nov 2022 12:28:25 +0200
Subject: [PATCH] Makefile: bugfix for handling platform paths
Message-ID: <20221122102825.88440-1-aldaya@gmail.com>

If the path where this repo is located contains the platform name on it,
the original Makefile replaced its occurrences from the path making it an invalid path.
This commit prevents this behavior replacing only the last part of the path as intended.

Signed-off-by: Alejandro Cabrera Aldaya <aldaya at gmail.com>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 8db6eab..32d4c48 100644
--- a/Makefile
+++ b/Makefile
@@ -47,7 +47,7 @@ ifdef PLATFORM_DIR
     platform_parent_dir=$(platform_dir_path)
   else
     PLATFORM=$(shell basename $(platform_dir_path))
-    platform_parent_dir=$(subst $(PLATFORM),,$(platform_dir_path))
+    platform_parent_dir=$(shell dirname $(shell realpath $(platform_dir_path)))    
   endif
 else
  platform_parent_dir=$(src_dir)/platform
-- 
2.34.1



From wxjstz at 126.com  Tue Nov 22 05:42:38 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 22 Nov 2022 21:42:38 +0800
Subject: [PATCH] Makefile: bugfix for handling platform paths
In-Reply-To: <20221122102825.88440-1-aldaya@gmail.com>
References: <20221122102825.88440-1-aldaya@gmail.com>
Message-ID: <904be39c57862760477bc0663527c55ab6db6ad2.camel@126.com>

? 2022-11-22???? 12:28 +0200?Alejandro Cabrera Aldaya???
> If the path where this repo is located contains the platform name on it,
> the original Makefile replaced its occurrences from the path making it an invalid path.
> This commit prevents this behavior replacing only the last part of the path as intended.
> 
> Signed-off-by: Alejandro Cabrera Aldaya <aldaya at gmail.com>
> ---
> ?Makefile | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Makefile b/Makefile
> index 8db6eab..32d4c48 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -47,7 +47,7 @@ ifdef PLATFORM_DIR
> ???? platform_parent_dir=$(platform_dir_path)
> ?? else
> ???? PLATFORM=$(shell basename $(platform_dir_path))
> -??? platform_parent_dir=$(subst $(PLATFORM),,$(platform_dir_path))
> +??? platform_parent_dir=$(shell dirname $(shell realpath $(platform_dir_path)))??? 
> 

Looks good, could simplify it a bit.
	platform_parent_dir=$(shell realpath ${platform_dir_path}/..)

Reviewed-by: Xiang W <wxjstz at 126.com>

> ?? endif
> ?else
> ? platform_parent_dir=$(src_dir)/platform
> -- 
> 2.34.1
> 
> 




From ajones at ventanamicro.com  Tue Nov 22 09:29:36 2022
From: ajones at ventanamicro.com (Andrew Jones)
Date: Tue, 22 Nov 2022 18:29:36 +0100
Subject: [PATCH] Makefile: bugfix for handling platform paths
In-Reply-To: <904be39c57862760477bc0663527c55ab6db6ad2.camel@126.com>
References: <20221122102825.88440-1-aldaya@gmail.com>
 <904be39c57862760477bc0663527c55ab6db6ad2.camel@126.com>
Message-ID: <20221122172936.5ihepb3rgu7kw3jw@kamzik>

On Tue, Nov 22, 2022 at 09:42:38PM +0800, Xiang W wrote:
> ? 2022-11-22???? 12:28 +0200?Alejandro Cabrera Aldaya???
> > If the path where this repo is located contains the platform name on it,
> > the original Makefile replaced its occurrences from the path making it an invalid path.
> > This commit prevents this behavior replacing only the last part of the path as intended.
> > 
> > Signed-off-by: Alejandro Cabrera Aldaya <aldaya at gmail.com>
> > ---
> > ?Makefile | 2 +-
> > ?1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/Makefile b/Makefile
> > index 8db6eab..32d4c48 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -47,7 +47,7 @@ ifdef PLATFORM_DIR
> > ???? platform_parent_dir=$(platform_dir_path)
> > ?? else
> > ???? PLATFORM=$(shell basename $(platform_dir_path))
> > -??? platform_parent_dir=$(subst $(PLATFORM),,$(platform_dir_path))
> > +??? platform_parent_dir=$(shell dirname $(shell realpath $(platform_dir_path)))??? 
> > 
> 
> Looks good, could simplify it a bit.
> 	platform_parent_dir=$(shell realpath ${platform_dir_path}/..)

I like this simplified version better.

Reviewed-by: Andrew Jones <ajones at ventanamicro.com>

Thanks,
drew

> 
> Reviewed-by: Xiang W <wxjstz at 126.com>
> 
> > ?? endif
> > ?else
> > ? platform_parent_dir=$(src_dir)/platform
> > -- 
> > 2.34.1
> > 
> > 
> 
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From qinhaijun at eswincomputing.com  Tue Nov 22 17:24:24 2022
From: qinhaijun at eswincomputing.com (=?UTF-8?B?56em5rW35L+K?=)
Date: Wed, 23 Nov 2022 09:24:24 +0800 (GMT+08:00)
Subject: [PATCH 1/1] lib: sbi_ecall_base: add check for function
 parameter pointers
In-Reply-To: <b5cfcd9458ff53b8ee0fb5042003476b9c859338.camel@126.com>
References: <20221122071321.4274-1-qinhaijun@eswincomputing.com>
 <20221122071321.4274-2-qinhaijun@eswincomputing.com>
 <b5cfcd9458ff53b8ee0fb5042003476b9c859338.camel@126.com>
Message-ID: <5110d4cc.a19e.184a2160ba6.Coremail.qinhaijun@eswincomputing.com>

Hi Xiang W

Thanks for your review, then keep it as it is.

> ? 2022-11-22???? 15:13 +0800?qinhaijun at eswincomputing.com???
> > From: haijun qin <qinhaijun at eswincomputing.com>
> > 
> > When a null pointer is passed in by mistake, the program will
> > enter the trap, so the check for the pointer is added.
> > 
> > Signed-off-by: haijun qin <qinhaijun at eswincomputing.com>
> 
> sbi_ecall_extension->handle is only called at
> https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_ecall.c#L110, 
> where out_val is not empty.
> 
> If you want to detect parameters, you also need to detect regs and out_trap. and
> add code like this in each extension implementation.
> 
> Regards,
> Xiang W
> > ---
> > ?lib/sbi/sbi_ecall_base.c | 3 +++
> > ?1 file changed, 3 insertions(+)
> > 
> > diff --git a/lib/sbi/sbi_ecall_base.c b/lib/sbi/sbi_ecall_base.c
> > index 786d2ac..3d4a367 100644
> > --- a/lib/sbi/sbi_ecall_base.c
> > +++ b/lib/sbi/sbi_ecall_base.c
> > @@ -39,6 +39,9 @@ static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
> > ?{
> > ????????int ret = 0;
> > ?
> > +???????if(out_val == NULL)
> > +???????????????return SBI_EINVALID_ADDR;
> > +
> > ????????switch (funcid) {
> > ????????case SBI_EXT_BASE_GET_SPEC_VERSION:
> > ????????????????*out_val = (SBI_ECALL_VERSION_MAJOR <<
> > -- 
> > 2.17.1
> > 
> > 
> 
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

From marouene.boubakri at nxp.com  Wed Nov 23 00:35:17 2022
From: marouene.boubakri at nxp.com (Marouene Boubakri)
Date: Wed, 23 Nov 2022 08:35:17 +0000
Subject: [Issue] OpenSBI domains
Message-ID: <AS1PR04MB945575D72C9B1E2DAC0EF5EFFC0C9@AS1PR04MB9455.eurprd04.prod.outlook.com>

Hi,

This is not a patch sorry, but due to non-reactiveness  to issues open on Github, maybe this will go faster.
I'm trying to experiment with OpenSBI domains I'm not sure if this working as expected. (Random errors,  below)

Could you kindly provide a FULL DTS  showcasing the feature to align with that ? the one used here https://github.com/riscv-software-src/opensbi/blob/master/docs/domain_support.md

A generic DTS for virt Qemu machine will be much better.

Error 1:
sbi_trap_error: hart0: trap handler failed (error -2)
sbi_trap_error: hart0: mcause=0x0000000000000005 mtval=0x0000000000000004
sbi_trap_error: hart0: mepc=0x00000000800122a2 mstatus=0x8000000a00007800
sbi_trap_error: hart0: ra=0x0000000080003cd8 sp=0x000000008003aea0
sbi_trap_error: hart0: gp=0x0000000000000000 tp=0x000000008003b000
sbi_trap_error: hart0: s0=0x000000008003af10 s1=0x0000000000000000
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0xffffffffffffffff
sbi_trap_error: hart0: a2=0x0000000080019db0 a3=0x000000008003aeb8
sbi_trap_error: hart0: a4=0x0000000000000000 a5=0x000000008003b000
sbi_trap_error: hart0: a6=0x0000000000000000 a7=0x0000000000000050
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000000000000
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x000000008001d000
sbi_trap_error: hart0: s6=0x0000000000000000 s7=0x0000000000000005
sbi_trap_error: hart0: s8=0x0000000000002000 s9=0x0000000080029ab0
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000000
sbi_trap_error: hart0: t0=0x0000000080007b8c t1=0x0000000000000414
sbi_trap_error: hart0: t2=0x0000000000001000 t3=0x00000000000000a0
sbi_trap_error: hart0: t4=0x000000000000003f t5=0x0000000000000004
sbi_trap_error: hart0: t6=0x0000000000000000

Error 2:

sbi_domain_finalize: failed to start boot HART 0 for trusted-domain (error -3)
init_coldboot: domain finalize failed (error -3)

Error 3:
Nothing just happens.

Thank you
Maro



From apatel at ventanamicro.com  Wed Nov 23 02:57:23 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:23 +0530
Subject: [PATCH v2 0/6] OpenSBI debug console support
Message-ID: <20221123105729.194640-1-apatel@ventanamicro.com>

The latest draft-v4 proposal of SBI debug console can be found here:
https://lists.riscv.org/g/tech-unixplatformspec/message/1815

This series implements SBI debug console support in OpenSBI
as-per above draft proposal.

These patches can also be found in riscv_sbi_dbcn_v2 branch
at: https://github.com/avpatel/opensbi.git

Changes since v1:
 - New PATCH3 to implement sbi_domain_check_addr_range() function
 - Added checks in PATCH4 for location and size of string to print
 - New PATCH5 to add console_puts() callback in the console device
 - New PATCH6 to implement console_puts() for semihosting

Anup Patel (6):
  include: Add defines for SBI debug console extension
  lib: sbi: Add sbi_nputs() function
  lib: sbi: Add sbi_domain_check_addr_range() function
  lib: sbi: Implement SBI debug console extension
  lib: sbi: Add console_puts() callback in the console device
  lib: utils/serial: Implement console_puts() for semihosting

 include/sbi/sbi_console.h         |  5 +++
 include/sbi/sbi_domain.h          | 15 ++++++++
 include/sbi/sbi_ecall_interface.h |  4 ++
 lib/sbi/Kconfig                   |  4 ++
 lib/sbi/objects.mk                |  3 ++
 lib/sbi/sbi_console.c             | 25 +++++++++++--
 lib/sbi/sbi_domain.c              | 47 +++++++++++++++++++++++
 lib/sbi/sbi_ecall_dbcn.c          | 62 +++++++++++++++++++++++++++++++
 lib/utils/serial/semihosting.c    | 33 ++++++++++++++++
 9 files changed, 195 insertions(+), 3 deletions(-)
 create mode 100644 lib/sbi/sbi_ecall_dbcn.c

-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:24 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:24 +0530
Subject: [PATCH v2 1/6] include: Add defines for SBI debug console extension
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-2-apatel@ventanamicro.com>

We add SBI debug console extension related defines/enum to the
SBI ecall interface header.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Atish Patra <atishp at rivosinc.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_ecall_interface.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index a3f2bf4..1dd3874 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -29,6 +29,7 @@
 #define SBI_EXT_HSM				0x48534D
 #define SBI_EXT_SRST				0x53525354
 #define SBI_EXT_PMU				0x504D55
+#define SBI_EXT_DBCN				0x4442434E
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -230,6 +231,9 @@ enum sbi_pmu_ctr_type {
 /* Flags defined for counter stop function */
 #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_PUTS		0x0
+
 /* SBI base specification related macros */
 #define SBI_SPEC_VERSION_MAJOR_OFFSET		24
 #define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:25 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:25 +0530
Subject: [PATCH v2 2/6] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-3-apatel@ventanamicro.com>

We add new sbi_nputs() which help us print a fixed number of characters
from a physical memory location.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Atish Patra <atishp at rivosinc.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_console.h |  2 ++
 lib/sbi/sbi_console.c     | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
index e15b55d..1bdeeb9 100644
--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -33,6 +33,8 @@ void sbi_putc(char ch);
 
 void sbi_puts(const char *str);
 
+void sbi_nputs(const char *str, unsigned long len);
+
 void sbi_gets(char *s, int maxwidth, char endchar);
 
 int __printf(2, 3) sbi_sprintf(char *out, const char *format, ...);
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index cfef2f8..a975708 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -51,6 +51,16 @@ void sbi_puts(const char *str)
 	spin_unlock(&console_out_lock);
 }
 
+void sbi_nputs(const char *str, unsigned long len)
+{
+	unsigned long i;
+
+	spin_lock(&console_out_lock);
+	for (i = 0; i < len; i++)
+		sbi_putc(str[i]);
+	spin_unlock(&console_out_lock);
+}
+
 void sbi_gets(char *s, int maxwidth, char endchar)
 {
 	int ch;
-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:26 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:26 +0530
Subject: [PATCH v2 3/6] lib: sbi: Add sbi_domain_check_addr_range() function
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-4-apatel@ventanamicro.com>

We add sbi_domain_check_addr_range() helper function to check
whether a given address range is accessible under a particular
domain.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_domain.h | 15 +++++++++++++
 lib/sbi/sbi_domain.c     | 47 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..4afcc37 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags);
 
+/**
+ * Check whether we can access specified address range for given mode and
+ * memory region flags under a domain
+ * @param dom pointer to domain
+ * @param addr the start of the address range to be checked
+ * @param size the size of the address range to be checked
+ * @param mode the privilege mode of access
+ * @param access_flags bitmask of domain access types (enum sbi_domain_access)
+ * @return TRUE if access allowed otherwise FALSE
+ */
+bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
+				 unsigned long addr, unsigned long size,
+				 unsigned long mode,
+				 unsigned long access_flags);
+
 /** Dump domain details on the console */
 void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
 
diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index f24a8e5..6d19d2c 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -195,6 +195,24 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
 	return FALSE;
 }
 
+static const struct sbi_domain_memregion *find_region(
+						const struct sbi_domain *dom,
+						unsigned long addr)
+{
+	unsigned long rstart, rend;
+	struct sbi_domain_memregion *reg;
+
+	sbi_domain_for_each_memregion(dom, reg) {
+		rstart = reg->base;
+		rend = (reg->order < __riscv_xlen) ?
+			rstart + ((1UL << reg->order) - 1) : -1UL;
+		if (rstart <= addr && addr <= rend)
+			return reg;
+	}
+
+	return NULL;
+}
+
 static int sanitize_domain(const struct sbi_platform *plat,
 			   struct sbi_domain *dom)
 {
@@ -303,6 +321,35 @@ static int sanitize_domain(const struct sbi_platform *plat,
 	return 0;
 }
 
+bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
+				 unsigned long addr, unsigned long size,
+				 unsigned long mode,
+				 unsigned long access_flags)
+{
+	unsigned long pos = 0;
+	const struct sbi_domain_memregion *reg;
+
+	if (!dom)
+		return FALSE;
+
+	while (pos < size) {
+		reg = find_region(dom, addr + pos);
+		if (!reg)
+			return FALSE;
+
+		if (!sbi_domain_check_addr(dom, addr + pos,
+					   mode, access_flags))
+			return FALSE;
+
+		if (reg->order < __riscv_xlen)
+			pos += 1UL << reg->order;
+		else
+			break;
+	}
+
+	return TRUE;
+}
+
 void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
 {
 	u32 i, k;
-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:27 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:27 +0530
Subject: [PATCH v2 4/6] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-5-apatel@ventanamicro.com>

We implement SBI debug console extension as one of the replacement
SBI extensions. This extension is only available when OpenSBI platform
provides a console device to generic library.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/sbi/Kconfig          |  4 +++
 lib/sbi/objects.mk       |  3 ++
 lib/sbi/sbi_ecall_dbcn.c | 62 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 lib/sbi/sbi_ecall_dbcn.c

diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index df74bba..ef6728b 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -26,6 +26,10 @@ config SBI_ECALL_PMU
 	bool "Performance Monitoring Unit extension"
 	default y
 
+config SBI_ECALL_DBCN
+	bool "Debug Console extension"
+	default y
+
 config SBI_ECALL_LEGACY
 	bool "SBI v0.1 legacy extensions"
 	default y
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index c774ebb..319f38d 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -37,6 +37,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
 libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
 
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
+libsbi-objs-$(CONFIG_SBI_ECALL_DBCN) += sbi_ecall_dbcn.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
 libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
 
diff --git a/lib/sbi/sbi_ecall_dbcn.c b/lib/sbi/sbi_ecall_dbcn.c
new file mode 100644
index 0000000..19ac021
--- /dev/null
+++ b/lib/sbi/sbi_ecall_dbcn.c
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ *   Anup Patel <apatel at ventanamicro.com>
+ */
+
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/riscv_asm.h>
+
+static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	ulong smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
+			MSTATUS_MPP_SHIFT;
+
+	if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
+		/*
+		 * On RV32, the M-mode can only access the first 4GB of
+		 * the physical address space because M-mode does not have
+		 * MMU to access full 34-bit physical address space.
+		 *
+		 * Based on above, we simply fail if the upper 32bits of
+		 * the physical address (i.e. a2 register) is non-zero on
+		 * RV32.
+		 */
+#if __riscv_xlen == 32
+		if (regs->a2)
+			return SBI_ERR_FAILED;
+#endif
+		if (!sbi_domain_check_addr_range(sbi_domain_thishart_ptr(),
+					regs->a1, regs->a0, smode,
+					SBI_DOMAIN_READ|SBI_DOMAIN_WRITE))
+			return SBI_EINVALID_ADDR;
+		sbi_nputs((const char *)regs->a1, regs->a0);
+		return 0;
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
+{
+	*out_val = (sbi_console_get_device()) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_dbcn = {
+	.extid_start = SBI_EXT_DBCN,
+	.extid_end = SBI_EXT_DBCN,
+	.handle = sbi_ecall_dbcn_handler,
+	.probe = sbi_ecall_dbcn_probe,
+};
-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:28 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:28 +0530
Subject: [PATCH v2 5/6] lib: sbi: Add console_puts() callback in the console device
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-6-apatel@ventanamicro.com>

We add console_puts() callback in the console device which allows
console drivers (such as semihosting) to implement a specialized
way to output character string.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_console.h |  3 +++
 lib/sbi/sbi_console.c     | 19 ++++++++++++++-----
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
index 1bdeeb9..7e757a7 100644
--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -19,6 +19,9 @@ struct sbi_console_device {
 	/** Write a character to the console output */
 	void (*console_putc)(char ch);
 
+	/** Write a character string to the console output */
+	void (*console_puts)(const char *str, unsigned long len);
+
 	/** Read a character from the console input */
 	int (*console_getc)(void);
 };
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index a975708..3c98f4e 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -12,6 +12,7 @@
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
 
 static const struct sbi_console_device *console_dev = NULL;
 static spinlock_t console_out_lock	       = SPIN_LOCK_INITIALIZER;
@@ -44,9 +45,13 @@ void sbi_putc(char ch)
 void sbi_puts(const char *str)
 {
 	spin_lock(&console_out_lock);
-	while (*str) {
-		sbi_putc(*str);
-		str++;
+	if (console_dev && console_dev->console_puts) {
+		console_dev->console_puts(str, sbi_strlen(str));
+	} else {
+		while (*str) {
+			sbi_putc(*str);
+			str++;
+		}
 	}
 	spin_unlock(&console_out_lock);
 }
@@ -56,8 +61,12 @@ void sbi_nputs(const char *str, unsigned long len)
 	unsigned long i;
 
 	spin_lock(&console_out_lock);
-	for (i = 0; i < len; i++)
-		sbi_putc(str[i]);
+	if (console_dev && console_dev->console_puts) {
+		console_dev->console_puts(str, len);
+	} else {
+		for (i = 0; i < len; i++)
+			sbi_putc(str[i]);
+	}
 	spin_unlock(&console_out_lock);
 }
 
-- 
2.34.1



From apatel at ventanamicro.com  Wed Nov 23 02:57:29 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 16:27:29 +0530
Subject: [PATCH v2 6/6] lib: utils/serial: Implement console_puts() for semihosting
In-Reply-To: <20221123105729.194640-1-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
Message-ID: <20221123105729.194640-7-apatel@ventanamicro.com>

We implement console_puts() for semihosting serial driver to speed-up
semihosting based prints.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/utils/serial/semihosting.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 86fa296..773b75e 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -15,6 +15,7 @@
 
 #define SYSOPEN     0x01
 #define SYSWRITEC   0x03
+#define SYSWRITE    0x05
 #define SYSREAD     0x06
 #define SYSREADC    0x07
 #define SYSERRNO	0x13
@@ -93,6 +94,7 @@ static int semihosting_errno(void)
 }
 
 static int semihosting_infd = SBI_ENODEV;
+static int semihosting_outfd = SBI_ENODEV;
 
 static long semihosting_open(const char *fname, enum semihosting_open_mode mode)
 {
@@ -141,6 +143,21 @@ static long semihosting_read(long fd, void *memp, size_t len)
 	return len - ret;
 }
 
+static long semihosting_write(long fd, const void *memp, size_t len)
+{
+	long ret;
+	struct semihosting_rdwr_s write;
+
+	write.fd = fd;
+	write.memp = (void *)memp;
+	write.len = len;
+
+	ret = semihosting_trap(SYSWRITE, &write);
+	if (ret < 0)
+		return semihosting_errno();
+	return len - ret;
+}
+
 /* clang-format on */
 
 static void semihosting_putc(char ch)
@@ -148,6 +165,20 @@ static void semihosting_putc(char ch)
 	semihosting_trap(SYSWRITEC, &ch);
 }
 
+static void semihosting_puts(const char *str, unsigned long len)
+{
+	char ch;
+	unsigned long i;
+
+	if (semihosting_outfd < 0) {
+		for (i = 0; i < len; i++) {
+			ch = str[i];
+			semihosting_trap(SYSWRITEC, &ch);
+		}
+	} else
+		semihosting_write(semihosting_outfd, str, len);
+}
+
 static int semihosting_getc(void)
 {
 	char ch = 0;
@@ -165,12 +196,14 @@ static int semihosting_getc(void)
 static struct sbi_console_device semihosting_console = {
 	.name = "semihosting",
 	.console_putc = semihosting_putc,
+	.console_puts = semihosting_puts,
 	.console_getc = semihosting_getc
 };
 
 int semihosting_init(void)
 {
 	semihosting_infd = semihosting_open(":tt", MODE_READ);
+	semihosting_outfd = semihosting_open(":tt", MODE_WRITE);
 
 	sbi_console_set_device(&semihosting_console);
 
-- 
2.34.1



From wxjstz at 126.com  Wed Nov 23 05:58:23 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 23 Nov 2022 21:58:23 +0800
Subject: [PATCH v2 3/6] lib: sbi: Add sbi_domain_check_addr_range()
 function
In-Reply-To: <20221123105729.194640-4-apatel@ventanamicro.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
	 <20221123105729.194640-4-apatel@ventanamicro.com>
Message-ID: <f3059c8742ff12b8818586a8ce8788cd94037618.camel@126.com>

? 2022-11-23???? 16:27 +0530?Anup Patel???
> We add sbi_domain_check_addr_range() helper function to check
> whether a given address range is accessible under a particular
> domain.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
> ?include/sbi/sbi_domain.h | 15 +++++++++++++
> ?lib/sbi/sbi_domain.c???? | 47 ++++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 62 insertions(+)
> 
> diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> index 5553d21..4afcc37 100644
> --- a/include/sbi/sbi_domain.h
> +++ b/include/sbi/sbi_domain.h
> @@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> ?????????????????????????? unsigned long addr, unsigned long mode,
> ?????????????????????????? unsigned long access_flags);
> ?
> +/**
> + * Check whether we can access specified address range for given mode and
> + * memory region flags under a domain
> + * @param dom pointer to domain
> + * @param addr the start of the address range to be checked
> + * @param size the size of the address range to be checked
> + * @param mode the privilege mode of access
> + * @param access_flags bitmask of domain access types (enum sbi_domain_access)
> + * @return TRUE if access allowed otherwise FALSE
> + */
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +??????????????????????????????? unsigned long addr, unsigned long size,
> +??????????????????????????????? unsigned long mode,
> +??????????????????????????????? unsigned long access_flags);
> +
> ?/** Dump domain details on the console */
> ?void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
> ?
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index f24a8e5..6d19d2c 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -195,6 +195,24 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
> ????????return FALSE;
> ?}
> ?
> +static const struct sbi_domain_memregion *find_region(
> +???????????????????????????????????????????????const struct sbi_domain *dom,
> +???????????????????????????????????????????????unsigned long addr)
> +{
> +???????unsigned long rstart, rend;
> +???????struct sbi_domain_memregion *reg;
> +
> +???????sbi_domain_for_each_memregion(dom, reg) {
> +???????????????rstart = reg->base;
> +???????????????rend = (reg->order < __riscv_xlen) ?
> +???????????????????????rstart + ((1UL << reg->order) - 1) : -1UL;
> +???????????????if (rstart <= addr && addr <= rend)
> +???????????????????????return reg;
> +???????}
> +
> +???????return NULL;
> +}
> +
> ?static int sanitize_domain(const struct sbi_platform *plat,
> ?????????????????????????? struct sbi_domain *dom)
> ?{
> @@ -303,6 +321,35 @@ static int sanitize_domain(const struct sbi_platform *plat,
> ????????return 0;
> ?}
> ?
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +??????????????????????????????? unsigned long addr, unsigned long size,
> +??????????????????????????????? unsigned long mode,
> +??????????????????????????????? unsigned long access_flags)
> +{
> +???????unsigned long pos = 0;
> +???????const struct sbi_domain_memregion *reg;
> +
> +???????if (!dom)
> +???????????????return FALSE;
> +
> +???????while (pos < size) {
> +???????????????reg = find_region(dom, addr + pos);
> +???????????????if (!reg)
> +???????????????????????return FALSE;
> +
> +???????????????if (!sbi_domain_check_addr(dom, addr + pos,
> +????????????????????????????????????????? mode, access_flags))
> +???????????????????????return FALSE;
> +
> +???????????????if (reg->order < __riscv_xlen)
> +???????????????????????pos += 1UL << reg->order;
addr+pos not always point to the beginning of the region, so the size of the
region cannot be added directly.

suggestion:
	pos = reg->base + (1 << reg->order) - addr

Regards,
Xiang W
> +???????????????else
> +???????????????????????break;
> +???????}
> +
> +???????return TRUE;
> +}
> +
> ?void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
> ?{
> ????????u32 i, k;
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Wed Nov 23 05:36:01 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 23 Nov 2022 21:36:01 +0800
Subject: [Issue] OpenSBI domains
In-Reply-To: <AS1PR04MB945575D72C9B1E2DAC0EF5EFFC0C9@AS1PR04MB9455.eurprd04.prod.outlook.com>
References: <AS1PR04MB945575D72C9B1E2DAC0EF5EFFC0C9@AS1PR04MB9455.eurprd04.prod.outlook.com>
Message-ID: <e82005264d1e1d88acbe541e7abdabb7631c69d4.camel@126.com>

? 2022-11-23???? 08:35 +0000?Marouene Boubakri???
> Hi,
> 
> This is not a patch sorry, but due to non-reactiveness? to issues open on Github, maybe this will go faster.
> I'm trying to experiment with OpenSBI domains I'm not sure if this working as expected. (Random errors,? below)
> 
> Could you kindly provide a FULL DTS? showcasing the feature to align with that ? the one used here 
> https://github.com/riscv-software-src/opensbi/blob/master/docs/domain_support.md
> 
> A generic DTS for virt Qemu machine will be much better.
> 
> Error 1:
> sbi_trap_error: hart0: trap handler failed (error -2)
> sbi_trap_error: hart0: mcause=0x0000000000000005 mtval=0x0000000000000004
> sbi_trap_error: hart0: mepc=0x00000000800122a2 mstatus=0x8000000a00007800
> sbi_trap_error: hart0: ra=0x0000000080003cd8 sp=0x000000008003aea0
> sbi_trap_error: hart0: gp=0x0000000000000000 tp=0x000000008003b000
> sbi_trap_error: hart0: s0=0x000000008003af10 s1=0x0000000000000000
> sbi_trap_error: hart0: a0=0x0000000000000000 a1=0xffffffffffffffff
> sbi_trap_error: hart0: a2=0x0000000080019db0 a3=0x000000008003aeb8
> sbi_trap_error: hart0: a4=0x0000000000000000 a5=0x000000008003b000
> sbi_trap_error: hart0: a6=0x0000000000000000 a7=0x0000000000000050
> sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000000000000
> sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x000000008001d000
> sbi_trap_error: hart0: s6=0x0000000000000000 s7=0x0000000000000005
> sbi_trap_error: hart0: s8=0x0000000000002000 s9=0x0000000080029ab0
> sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000000
> sbi_trap_error: hart0: t0=0x0000000080007b8c t1=0x0000000000000414
> sbi_trap_error: hart0: t2=0x0000000000001000 t3=0x00000000000000a0
> sbi_trap_error: hart0: t4=0x000000000000003f t5=0x0000000000000004
> sbi_trap_error: hart0: t6=0x0000000000000000
> 
> Error 2:
> 
> sbi_domain_finalize: failed to start boot HART 0 for trusted-domain (error -3)
> init_coldboot: domain finalize failed (error -3)
> 
> Error 3:
> Nothing just happens.
> 
> Thank you
> Maro
> 
You'd better provide some details of your test so that we can reproduce it easily.

Regards,
Xiang W
> 




From apatel at ventanamicro.com  Wed Nov 23 07:44:02 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Wed, 23 Nov 2022 21:14:02 +0530
Subject: [PATCH v2 3/6] lib: sbi: Add sbi_domain_check_addr_range() function
In-Reply-To: <f3059c8742ff12b8818586a8ce8788cd94037618.camel@126.com>
References: <20221123105729.194640-1-apatel@ventanamicro.com>
 <20221123105729.194640-4-apatel@ventanamicro.com> <f3059c8742ff12b8818586a8ce8788cd94037618.camel@126.com>
Message-ID: <CAK9=C2XO1jXV4ZT3FwEH2OiH-dDaaXobNNsU5z=JA1a==Z7TfQ@mail.gmail.com>

On Wed, Nov 23, 2022 at 7:30 PM Xiang W <wxjstz at 126.com> wrote:
>
> ? 2022-11-23???? 16:27 +0530?Anup Patel???
> > We add sbi_domain_check_addr_range() helper function to check
> > whether a given address range is accessible under a particular
> > domain.
> >
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> >  include/sbi/sbi_domain.h | 15 +++++++++++++
> >  lib/sbi/sbi_domain.c     | 47 ++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> >
> > diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> > index 5553d21..4afcc37 100644
> > --- a/include/sbi/sbi_domain.h
> > +++ b/include/sbi/sbi_domain.h
> > @@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> >                            unsigned long addr, unsigned long mode,
> >                            unsigned long access_flags);
> >
> > +/**
> > + * Check whether we can access specified address range for given mode and
> > + * memory region flags under a domain
> > + * @param dom pointer to domain
> > + * @param addr the start of the address range to be checked
> > + * @param size the size of the address range to be checked
> > + * @param mode the privilege mode of access
> > + * @param access_flags bitmask of domain access types (enum sbi_domain_access)
> > + * @return TRUE if access allowed otherwise FALSE
> > + */
> > +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> > +                                unsigned long addr, unsigned long size,
> > +                                unsigned long mode,
> > +                                unsigned long access_flags);
> > +
> >  /** Dump domain details on the console */
> >  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
> >
> > diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> > index f24a8e5..6d19d2c 100644
> > --- a/lib/sbi/sbi_domain.c
> > +++ b/lib/sbi/sbi_domain.c
> > @@ -195,6 +195,24 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
> >         return FALSE;
> >  }
> >
> > +static const struct sbi_domain_memregion *find_region(
> > +                                               const struct sbi_domain *dom,
> > +                                               unsigned long addr)
> > +{
> > +       unsigned long rstart, rend;
> > +       struct sbi_domain_memregion *reg;
> > +
> > +       sbi_domain_for_each_memregion(dom, reg) {
> > +               rstart = reg->base;
> > +               rend = (reg->order < __riscv_xlen) ?
> > +                       rstart + ((1UL << reg->order) - 1) : -1UL;
> > +               if (rstart <= addr && addr <= rend)
> > +                       return reg;
> > +       }
> > +
> > +       return NULL;
> > +}
> > +
> >  static int sanitize_domain(const struct sbi_platform *plat,
> >                            struct sbi_domain *dom)
> >  {
> > @@ -303,6 +321,35 @@ static int sanitize_domain(const struct sbi_platform *plat,
> >         return 0;
> >  }
> >
> > +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> > +                                unsigned long addr, unsigned long size,
> > +                                unsigned long mode,
> > +                                unsigned long access_flags)
> > +{
> > +       unsigned long pos = 0;
> > +       const struct sbi_domain_memregion *reg;
> > +
> > +       if (!dom)
> > +               return FALSE;
> > +
> > +       while (pos < size) {
> > +               reg = find_region(dom, addr + pos);
> > +               if (!reg)
> > +                       return FALSE;
> > +
> > +               if (!sbi_domain_check_addr(dom, addr + pos,
> > +                                          mode, access_flags))
> > +                       return FALSE;
> > +
> > +               if (reg->order < __riscv_xlen)
> > +                       pos += 1UL << reg->order;
> addr+pos not always point to the beginning of the region, so the size of the
> region cannot be added directly.
>
> suggestion:
>         pos = reg->base + (1 << reg->order) - addr

This loop seems to be broken for overlapping regions.

What you are suggesting will also not work for overlapping regions.

Let me rethink.

Regards,
Anup

>
> Regards,
> Xiang W
> > +               else
> > +                       break;
> > +       }
> > +
> > +       return TRUE;
> > +}
> > +
> >  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
> >  {
> >         u32 i, k;
> > --
> > 2.34.1
> >
> >
>
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From wxjstz at 126.com  Wed Nov 23 19:04:38 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:04:38 +0800
Subject: [PATCH 0/3] Some optimizations and bug fixes about sbi_domain
Message-ID: <20221124030441.214213-1-wxjstz@126.com>


Xiang W (3):
  lib: sbi: Simplified mmio match checking
  lib: sbi: add in_region
  lib: sbi: fix is_region_valid

 lib/sbi/sbi_domain.c | 63 ++++++++++++++++++++------------------------
 1 file changed, 29 insertions(+), 34 deletions(-)

-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:04:39 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:04:39 +0800
Subject: [PATCH 1/3] lib: sbi: Simplified mmio match checking
In-Reply-To: <20221124030441.214213-1-wxjstz@126.com>
References: <20221124030441.214213-1-wxjstz@126.com>
Message-ID: <20221124030441.214213-2-wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index f24a8e5..fec9074 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -105,7 +105,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags)
 {
-	bool mmio = FALSE;
+	bool rmmio, mmio = FALSE;
 	struct sbi_domain_memregion *reg;
 	unsigned long rstart, rend, rflags, rwx = 0;
 
@@ -130,8 +130,8 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		rend = (reg->order < __riscv_xlen) ?
 			rstart + ((1UL << reg->order) - 1) : -1UL;
 		if (rstart <= addr && addr <= rend) {
-			if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
-			    (!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
+			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
+			if (mmio != rmmio)
 				return FALSE;
 			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
 		}
-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:04:41 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:04:41 +0800
Subject: [PATCH 3/3] lib: sbi: fix is_region_valid
In-Reply-To: <20221124030441.214213-1-wxjstz@126.com>
References: <20221124030441.214213-1-wxjstz@126.com>
Message-ID: <20221124030441.214213-4-wxjstz@126.com>

When order is equal to __riscv_xlen, the shift operation will not
perform any operation, which will cause
reg->base & (BIT(reg->order) - 1) to always be 0, and the condition
has not been established. This patch fixes this bug

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index eba60f6..1acf76c 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -142,6 +142,9 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 	if (reg->order < 3 || __riscv_xlen < reg->order)
 		return FALSE;
 
+	if (reg->order == __riscv_xlen && reg->base != 0)
+		return FALSE;
+
 	if (reg->base & (BIT(reg->order) - 1))
 		return FALSE;
 
-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:04:40 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:04:40 +0800
Subject: [PATCH 2/3] lib: sbi: add in_region
In-Reply-To: <20221124030441.214213-1-wxjstz@126.com>
References: <20221124030441.214213-1-wxjstz@126.com>
Message-ID: <20221124030441.214213-3-wxjstz@126.com>

It is a common operation to judge whether an address is in a
certain region, and add an inline function. and simplify
sbi_domain_memregion_init and is_region_subset.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 54 +++++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 31 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index fec9074..eba60f6 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -36,6 +36,14 @@ struct sbi_domain root = {
 	.system_reset_allowed = TRUE,
 };
 
+static inline bool in_region(unsigned long addr, const struct sbi_domain_memregion *reg)
+{
+	unsigned long s, e;
+	s= reg->base;
+	e = reg->order < __riscv_xlen ? reg->base + (BIT(reg->order) - 1) : -1;
+	return (s <= addr) && (addr <= e);
+}
+
 bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
 {
 	if (dom)
@@ -77,27 +85,18 @@ void sbi_domain_memregion_init(unsigned long addr,
 				unsigned long flags,
 				struct sbi_domain_memregion *reg)
 {
-	unsigned long base = 0, order;
+	unsigned long order;
+
+	if (reg == NULL)
+		return;
 
 	for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
-		if (order < __riscv_xlen) {
-			base = addr & ~((1UL << order) - 1UL);
-			if ((base <= addr) &&
-			    (addr < (base + (1UL << order))) &&
-			    (base <= (addr + size - 1UL)) &&
-			    ((addr + size - 1UL) < (base + (1UL << order))))
-				break;
-		} else {
-			base = 0;
+		reg->base = order < __riscv_xlen ? addr & ~((1UL << order) - 1UL) : 0;
+		reg->order = order;
+		if (in_region(addr,reg) && in_region(addr + size - 1, reg)) {
+			reg->flags = flags;
 			break;
 		}
-
-	}
-
-	if (reg) {
-		reg->base = base;
-		reg->order = order;
-		reg->flags = flags;
 	}
 }
 
@@ -126,10 +125,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
 			continue;
 
-		rstart = reg->base;
-		rend = (reg->order < __riscv_xlen) ?
-			rstart + ((1UL << reg->order) - 1) : -1UL;
-		if (rstart <= addr && addr <= rend) {
+		if (in_region(addr, reg)) {
 			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
 			if (mmio != rmmio)
 				return FALSE;
@@ -156,15 +152,11 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 static bool is_region_subset(const struct sbi_domain_memregion *regA,
 			     const struct sbi_domain_memregion *regB)
 {
-	ulong regA_start = regA->base;
-	ulong regA_end = regA->base + (BIT(regA->order) - 1);
-	ulong regB_start = regB->base;
-	ulong regB_end = regB->base + (BIT(regB->order) - 1);
-
-	if ((regB_start <= regA_start) &&
-	    (regA_start < regB_end) &&
-	    (regB_start < regA_end) &&
-	    (regA_end <= regB_end))
+	unsigned long start, end;
+	start = regA->base;
+	end = regA->order < __riscv_xlen ? regA->base + (BIT(regA->order) - 1) : -1;
+
+	if (in_region(start, regB) && in_region(end, regB))
 		return TRUE;
 
 	return FALSE;
@@ -423,7 +415,7 @@ int sbi_domain_register(struct sbi_domain *dom,
 	}
 
 	/* Assign index to domain */
-	dom->index = domain_count++;
+	dom->index = domaireg_mergedn_count++;
 	domidx_to_domain_table[dom->index] = dom;
 
 	/* Clear assigned HARTs of domain */
-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:11:41 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:11:41 +0800
Subject: [PATCH 2/3] lib: sbi: add in_region
In-Reply-To: <20221124030441.214213-3-wxjstz@126.com>
References: <20221124030441.214213-1-wxjstz@126.com>
	 <20221124030441.214213-3-wxjstz@126.com>
Message-ID: <eabdd340bc62a245399151ca788c38a49c32d6ba.camel@126.com>

? 2022-11-24???? 11:04 +0800?Xiang W???
> It is a common operation to judge whether an address is in a
> certain region, and add an inline function. and simplify
> sbi_domain_memregion_init and is_region_subset.
> 
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/sbi/sbi_domain.c | 54 +++++++++++++++++++-------------------------
> ?1 file changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index fec9074..eba60f6 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -36,6 +36,14 @@ struct sbi_domain root = {
> ????????.system_reset_allowed = TRUE,
> ?};
> ?
> +static inline bool in_region(unsigned long addr, const struct sbi_domain_memregion *reg)
> +{
> +???????unsigned long s, e;
> +???????s= reg->base;
> +???????e = reg->order < __riscv_xlen ? reg->base + (BIT(reg->order) - 1) : -1;
> +???????return (s <= addr) && (addr <= e);
> +}
> +
> ?bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
> ?{
> ????????if (dom)
> @@ -77,27 +85,18 @@ void sbi_domain_memregion_init(unsigned long addr,
> ????????????????????????????????unsigned long flags,
> ????????????????????????????????struct sbi_domain_memregion *reg)
> ?{
> -???????unsigned long base = 0, order;
> +???????unsigned long order;
> +
> +???????if (reg == NULL)
> +???????????????return;
> ?
> ????????for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
> -???????????????if (order < __riscv_xlen) {
> -???????????????????????base = addr & ~((1UL << order) - 1UL);
> -???????????????????????if ((base <= addr) &&
> -?????????????????????????? (addr < (base + (1UL << order))) &&
> -?????????????????????????? (base <= (addr + size - 1UL)) &&
> -?????????????????????????? ((addr + size - 1UL) < (base + (1UL << order))))
> -???????????????????????????????break;
> -???????????????} else {
> -???????????????????????base = 0;
> +???????????????reg->base = order < __riscv_xlen ? addr & ~((1UL << order) - 1UL) : 0;
> +???????????????reg->order = order;
> +???????????????if (in_region(addr,reg) && in_region(addr + size - 1, reg)) {
> +???????????????????????reg->flags = flags;
> ????????????????????????break;
> ????????????????}
> -
> -???????}
> -
> -???????if (reg) {
> -???????????????reg->base = base;
> -???????????????reg->order = order;
> -???????????????reg->flags = flags;
> ????????}
> ?}
> ?
> @@ -126,10 +125,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> ????????????????if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
> ????????????????????????continue;
> ?
> -???????????????rstart = reg->base;
> -???????????????rend = (reg->order < __riscv_xlen) ?
> -???????????????????????rstart + ((1UL << reg->order) - 1) : -1UL;
> -???????????????if (rstart <= addr && addr <= rend) {
> +???????????????if (in_region(addr, reg)) {
> ????????????????????????rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
> ????????????????????????if (mmio != rmmio)
> ????????????????????????????????return FALSE;
> @@ -156,15 +152,11 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
> ?static bool is_region_subset(const struct sbi_domain_memregion *regA,
> ???????????????????????????? const struct sbi_domain_memregion *regB)
> ?{
> -???????ulong regA_start = regA->base;
> -???????ulong regA_end = regA->base + (BIT(regA->order) - 1);
> -???????ulong regB_start = regB->base;
> -???????ulong regB_end = regB->base + (BIT(regB->order) - 1);
> -
> -???????if ((regB_start <= regA_start) &&
> -?????????? (regA_start < regB_end) &&
> -?????????? (regB_start < regA_end) &&
> -?????????? (regA_end <= regB_end))
> +???????unsigned long start, end;
> +???????start = regA->base;
> +???????end = regA->order < __riscv_xlen ? regA->base + (BIT(regA->order) - 1) : -1;
> +
> +???????if (in_region(start, regB) && in_region(end, regB))
> ????????????????return TRUE;
> ?
> ????????return FALSE;
> @@ -423,7 +415,7 @@ int sbi_domain_register(struct sbi_domain *dom,
> ????????}
> ?
> ????????/* Assign index to domain */
> -???????dom->index = domain_count++;
> +???????dom->index = domaireg_mergedn_count++;
sorry! mistakesedit! new patch will send

Regards,
Xiang W

> ????????domidx_to_domain_table[dom->index] = dom;
> ?
> ????????/* Clear assigned HARTs of domain */




From wxjstz at 126.com  Wed Nov 23 19:16:02 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:16:02 +0800
Subject: [PATCH v2 0/3] Some optimizations and bug fixes about sbi_domain
Message-ID: <20221124031605.216192-1-wxjstz@126.com>

Changes since v1:
fix [PATCH 2/3] mistakes edit

Xiang W (3):
  lib: sbi: Simplified mmio match checking
  lib: sbi: add in_region
  lib: sbi: fix is_region_valid

 lib/sbi/sbi_domain.c | 61 ++++++++++++++++++++------------------------
 1 file changed, 28 insertions(+), 33 deletions(-)

-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:16:05 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:16:05 +0800
Subject: [PATCH v2 3/3] lib: sbi: fix is_region_valid
In-Reply-To: <20221124031605.216192-1-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com>
Message-ID: <20221124031605.216192-4-wxjstz@126.com>

When order is equal to __riscv_xlen, the shift operation will not
perform any operation, which will cause
reg->base & (BIT(reg->order) - 1) to always be 0, and the condition
has not been established. This patch fixes this bug

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3365e74..65fae89 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -142,6 +142,9 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 	if (reg->order < 3 || __riscv_xlen < reg->order)
 		return FALSE;
 
+	if (reg->order == __riscv_xlen && reg->base != 0)
+		return FALSE;
+
 	if (reg->base & (BIT(reg->order) - 1))
 		return FALSE;
 
-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:16:03 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:16:03 +0800
Subject: [PATCH v2 1/3] lib: sbi: Simplified mmio match checking
In-Reply-To: <20221124031605.216192-1-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com>
Message-ID: <20221124031605.216192-2-wxjstz@126.com>

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index f24a8e5..fec9074 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -105,7 +105,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags)
 {
-	bool mmio = FALSE;
+	bool rmmio, mmio = FALSE;
 	struct sbi_domain_memregion *reg;
 	unsigned long rstart, rend, rflags, rwx = 0;
 
@@ -130,8 +130,8 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		rend = (reg->order < __riscv_xlen) ?
 			rstart + ((1UL << reg->order) - 1) : -1UL;
 		if (rstart <= addr && addr <= rend) {
-			if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
-			    (!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
+			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
+			if (mmio != rmmio)
 				return FALSE;
 			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
 		}
-- 
2.30.2



From wxjstz at 126.com  Wed Nov 23 19:16:04 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 24 Nov 2022 11:16:04 +0800
Subject: [PATCH v2 2/3] lib: sbi: add in_region
In-Reply-To: <20221124031605.216192-1-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com>
Message-ID: <20221124031605.216192-3-wxjstz@126.com>

It is a common operation to judge whether an address is in a
certain region, and add an inline function. and simplify
sbi_domain_memregion_init and is_region_subset.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_domain.c | 52 +++++++++++++++++++-------------------------
 1 file changed, 22 insertions(+), 30 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index fec9074..3365e74 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -36,6 +36,14 @@ struct sbi_domain root = {
 	.system_reset_allowed = TRUE,
 };
 
+static inline bool in_region(unsigned long addr, const struct sbi_domain_memregion *reg)
+{
+	unsigned long s, e;
+	s= reg->base;
+	e = reg->order < __riscv_xlen ? reg->base + (BIT(reg->order) - 1) : -1;
+	return (s <= addr) && (addr <= e);
+}
+
 bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
 {
 	if (dom)
@@ -77,27 +85,18 @@ void sbi_domain_memregion_init(unsigned long addr,
 				unsigned long flags,
 				struct sbi_domain_memregion *reg)
 {
-	unsigned long base = 0, order;
+	unsigned long order;
+
+	if (reg == NULL)
+		return;
 
 	for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
-		if (order < __riscv_xlen) {
-			base = addr & ~((1UL << order) - 1UL);
-			if ((base <= addr) &&
-			    (addr < (base + (1UL << order))) &&
-			    (base <= (addr + size - 1UL)) &&
-			    ((addr + size - 1UL) < (base + (1UL << order))))
-				break;
-		} else {
-			base = 0;
+		reg->base = order < __riscv_xlen ? addr & ~((1UL << order) - 1UL) : 0;
+		reg->order = order;
+		if (in_region(addr,reg) && in_region(addr + size - 1, reg)) {
+			reg->flags = flags;
 			break;
 		}
-
-	}
-
-	if (reg) {
-		reg->base = base;
-		reg->order = order;
-		reg->flags = flags;
 	}
 }
 
@@ -126,10 +125,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
 			continue;
 
-		rstart = reg->base;
-		rend = (reg->order < __riscv_xlen) ?
-			rstart + ((1UL << reg->order) - 1) : -1UL;
-		if (rstart <= addr && addr <= rend) {
+		if (in_region(addr, reg)) {
 			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
 			if (mmio != rmmio)
 				return FALSE;
@@ -156,15 +152,11 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 static bool is_region_subset(const struct sbi_domain_memregion *regA,
 			     const struct sbi_domain_memregion *regB)
 {
-	ulong regA_start = regA->base;
-	ulong regA_end = regA->base + (BIT(regA->order) - 1);
-	ulong regB_start = regB->base;
-	ulong regB_end = regB->base + (BIT(regB->order) - 1);
-
-	if ((regB_start <= regA_start) &&
-	    (regA_start < regB_end) &&
-	    (regB_start < regA_end) &&
-	    (regA_end <= regB_end))
+	unsigned long start, end;
+	start = regA->base;
+	end = regA->order < __riscv_xlen ? regA->base + (BIT(regA->order) - 1) : -1;
+
+	if (in_region(start, regB) && in_region(end, regB))
 		return TRUE;
 
 	return FALSE;
-- 
2.30.2



From apatel at ventanamicro.com  Thu Nov 24 05:29:00 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:00 +0530
Subject: [PATCH v3 0/6] OpenSBI debug console support
Message-ID: <20221124132906.257732-1-apatel@ventanamicro.com>

The latest draft-v4 proposal of SBI debug console can be found here:
https://lists.riscv.org/g/tech-unixplatformspec/message/1815

This series implements SBI debug console support in OpenSBI
as-per above draft proposal.

These patches can also be found in riscv_sbi_dbcn_v3 branch
at: https://github.com/avpatel/opensbi.git

Changes since v2:
 - Reworked sbi_domain_check_addr_range() in PATCH3 to make it work
   for overlapping regions.

Changes since v1:
 - New PATCH3 to implement sbi_domain_check_addr_range() function
 - Added checks in PATCH4 for location and size of string to print
 - New PATCH5 to add console_puts() callback in the console device
 - New PATCH6 to implement console_puts() for semihosting
 
Anup Patel (6):
  include: Add defines for SBI debug console extension
  lib: sbi: Add sbi_nputs() function
  lib: sbi: Add sbi_domain_check_addr_range() function
  lib: sbi: Implement SBI debug console extension
  lib: sbi: Add console_puts() callback in the console device
  lib: utils/serial: Implement console_puts() for semihosting

 include/sbi/sbi_console.h         |  5 +++
 include/sbi/sbi_domain.h          | 15 +++++++
 include/sbi/sbi_ecall_interface.h |  4 ++
 lib/sbi/Kconfig                   |  4 ++
 lib/sbi/objects.mk                |  3 ++
 lib/sbi/sbi_console.c             | 25 +++++++++--
 lib/sbi/sbi_domain.c              | 69 +++++++++++++++++++++++++++++++
 lib/sbi/sbi_ecall_dbcn.c          | 62 +++++++++++++++++++++++++++
 lib/utils/serial/semihosting.c    | 33 +++++++++++++++
 9 files changed, 217 insertions(+), 3 deletions(-)
 create mode 100644 lib/sbi/sbi_ecall_dbcn.c

-- 
2.34.1


From apatel at ventanamicro.com  Thu Nov 24 05:29:01 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:01 +0530
Subject: [PATCH v3 1/6] include: Add defines for SBI debug console extension
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-2-apatel@ventanamicro.com>

We add SBI debug console extension related defines/enum to the
SBI ecall interface header.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Atish Patra <atishp at rivosinc.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_ecall_interface.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index a3f2bf4..1dd3874 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -29,6 +29,7 @@
 #define SBI_EXT_HSM				0x48534D
 #define SBI_EXT_SRST				0x53525354
 #define SBI_EXT_PMU				0x504D55
+#define SBI_EXT_DBCN				0x4442434E
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -230,6 +231,9 @@ enum sbi_pmu_ctr_type {
 /* Flags defined for counter stop function */
 #define SBI_PMU_STOP_FLAG_RESET (1 << 0)
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_PUTS		0x0
+
 /* SBI base specification related macros */
 #define SBI_SPEC_VERSION_MAJOR_OFFSET		24
 #define SBI_SPEC_VERSION_MAJOR_MASK		0x7f
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 24 05:29:02 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:02 +0530
Subject: [PATCH v3 2/6] lib: sbi: Add sbi_nputs() function
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-3-apatel@ventanamicro.com>

We add new sbi_nputs() which help us print a fixed number of characters
from a physical memory location.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Atish Patra <atishp at rivosinc.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_console.h |  2 ++
 lib/sbi/sbi_console.c     | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
index e15b55d..1bdeeb9 100644
--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -33,6 +33,8 @@ void sbi_putc(char ch);
 
 void sbi_puts(const char *str);
 
+void sbi_nputs(const char *str, unsigned long len);
+
 void sbi_gets(char *s, int maxwidth, char endchar);
 
 int __printf(2, 3) sbi_sprintf(char *out, const char *format, ...);
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index cfef2f8..a975708 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -51,6 +51,16 @@ void sbi_puts(const char *str)
 	spin_unlock(&console_out_lock);
 }
 
+void sbi_nputs(const char *str, unsigned long len)
+{
+	unsigned long i;
+
+	spin_lock(&console_out_lock);
+	for (i = 0; i < len; i++)
+		sbi_putc(str[i]);
+	spin_unlock(&console_out_lock);
+}
+
 void sbi_gets(char *s, int maxwidth, char endchar)
 {
 	int ch;
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 24 05:29:03 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:03 +0530
Subject: [PATCH v3 3/6] lib: sbi: Add sbi_domain_check_addr_range() function
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-4-apatel@ventanamicro.com>

We add sbi_domain_check_addr_range() helper function to check
whether a given address range is accessible under a particular
domain.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_domain.h | 15 +++++++++
 lib/sbi/sbi_domain.c     | 69 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..4afcc37 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags);
 
+/**
+ * Check whether we can access specified address range for given mode and
+ * memory region flags under a domain
+ * @param dom pointer to domain
+ * @param addr the start of the address range to be checked
+ * @param size the size of the address range to be checked
+ * @param mode the privilege mode of access
+ * @param access_flags bitmask of domain access types (enum sbi_domain_access)
+ * @return TRUE if access allowed otherwise FALSE
+ */
+bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
+				 unsigned long addr, unsigned long size,
+				 unsigned long mode,
+				 unsigned long access_flags);
+
 /** Dump domain details on the console */
 void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
 
diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index f24a8e5..11a547c 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -195,6 +195,44 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
 	return FALSE;
 }
 
+static const struct sbi_domain_memregion *find_region(
+						const struct sbi_domain *dom,
+						unsigned long addr)
+{
+	unsigned long rstart, rend;
+	struct sbi_domain_memregion *reg;
+
+	sbi_domain_for_each_memregion(dom, reg) {
+		rstart = reg->base;
+		rend = (reg->order < __riscv_xlen) ?
+			rstart + ((1UL << reg->order) - 1) : -1UL;
+		if (rstart <= addr && addr <= rend)
+			return reg;
+	}
+
+	return NULL;
+}
+
+static const struct sbi_domain_memregion *find_next_subset_region(
+				const struct sbi_domain *dom,
+				const struct sbi_domain_memregion *reg,
+				unsigned long addr)
+{
+	struct sbi_domain_memregion *sreg, *ret = NULL;
+
+	sbi_domain_for_each_memregion(dom, sreg) {
+		if (sreg == reg || (sreg->base <= addr) ||
+		    !is_region_subset(sreg, reg))
+			continue;
+
+		if (!ret || (sreg->base < ret->base) ||
+		    ((sreg->base == ret->base) && (sreg->order < ret->order)))
+			ret = sreg;
+	}
+
+	return ret;
+}
+
 static int sanitize_domain(const struct sbi_platform *plat,
 			   struct sbi_domain *dom)
 {
@@ -303,6 +341,37 @@ static int sanitize_domain(const struct sbi_platform *plat,
 	return 0;
 }
 
+bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
+				 unsigned long addr, unsigned long size,
+				 unsigned long mode,
+				 unsigned long access_flags)
+{
+	unsigned long max = addr + size;
+	const struct sbi_domain_memregion *reg, *sreg;
+
+	if (!dom)
+		return FALSE;
+
+	while (addr < max) {
+		reg = find_region(dom, addr);
+		if (!reg)
+			return FALSE;
+
+		if (!sbi_domain_check_addr(dom, addr, mode, access_flags))
+			return FALSE;
+
+		sreg = find_next_subset_region(dom, reg, addr);
+		if (sreg)
+			addr = sreg->base;
+		else if (reg->order < __riscv_xlen)
+			addr = reg->base + (1UL << reg->order);
+		else
+			break;
+	}
+
+	return TRUE;
+}
+
 void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
 {
 	u32 i, k;
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 24 05:29:04 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:04 +0530
Subject: [PATCH v3 4/6] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-5-apatel@ventanamicro.com>

We implement SBI debug console extension as one of the replacement
SBI extensions. This extension is only available when OpenSBI platform
provides a console device to generic library.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/sbi/Kconfig          |  4 +++
 lib/sbi/objects.mk       |  3 ++
 lib/sbi/sbi_ecall_dbcn.c | 62 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 lib/sbi/sbi_ecall_dbcn.c

diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index df74bba..ef6728b 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -26,6 +26,10 @@ config SBI_ECALL_PMU
 	bool "Performance Monitoring Unit extension"
 	default y
 
+config SBI_ECALL_DBCN
+	bool "Debug Console extension"
+	default y
+
 config SBI_ECALL_LEGACY
 	bool "SBI v0.1 legacy extensions"
 	default y
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index c774ebb..319f38d 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -37,6 +37,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
 libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
 
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
+libsbi-objs-$(CONFIG_SBI_ECALL_DBCN) += sbi_ecall_dbcn.o
+
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
 libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
 
diff --git a/lib/sbi/sbi_ecall_dbcn.c b/lib/sbi/sbi_ecall_dbcn.c
new file mode 100644
index 0000000..19ac021
--- /dev/null
+++ b/lib/sbi/sbi_ecall_dbcn.c
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ *   Anup Patel <apatel at ventanamicro.com>
+ */
+
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/riscv_asm.h>
+
+static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	ulong smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
+			MSTATUS_MPP_SHIFT;
+
+	if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
+		/*
+		 * On RV32, the M-mode can only access the first 4GB of
+		 * the physical address space because M-mode does not have
+		 * MMU to access full 34-bit physical address space.
+		 *
+		 * Based on above, we simply fail if the upper 32bits of
+		 * the physical address (i.e. a2 register) is non-zero on
+		 * RV32.
+		 */
+#if __riscv_xlen == 32
+		if (regs->a2)
+			return SBI_ERR_FAILED;
+#endif
+		if (!sbi_domain_check_addr_range(sbi_domain_thishart_ptr(),
+					regs->a1, regs->a0, smode,
+					SBI_DOMAIN_READ|SBI_DOMAIN_WRITE))
+			return SBI_EINVALID_ADDR;
+		sbi_nputs((const char *)regs->a1, regs->a0);
+		return 0;
+	}
+
+	return SBI_ENOTSUPP;
+}
+
+static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
+{
+	*out_val = (sbi_console_get_device()) ? 1 : 0;
+	return 0;
+}
+
+struct sbi_ecall_extension ecall_dbcn = {
+	.extid_start = SBI_EXT_DBCN,
+	.extid_end = SBI_EXT_DBCN,
+	.handle = sbi_ecall_dbcn_handler,
+	.probe = sbi_ecall_dbcn_probe,
+};
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 24 05:29:05 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:05 +0530
Subject: [PATCH v3 5/6] lib: sbi: Add console_puts() callback in the console device
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-6-apatel@ventanamicro.com>

We add console_puts() callback in the console device which allows
console drivers (such as semihosting) to implement a specialized
way to output character string.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_console.h |  3 +++
 lib/sbi/sbi_console.c     | 19 ++++++++++++++-----
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
index 1bdeeb9..7e757a7 100644
--- a/include/sbi/sbi_console.h
+++ b/include/sbi/sbi_console.h
@@ -19,6 +19,9 @@ struct sbi_console_device {
 	/** Write a character to the console output */
 	void (*console_putc)(char ch);
 
+	/** Write a character string to the console output */
+	void (*console_puts)(const char *str, unsigned long len);
+
 	/** Read a character from the console input */
 	int (*console_getc)(void);
 };
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index a975708..3c98f4e 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -12,6 +12,7 @@
 #include <sbi/sbi_hart.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_scratch.h>
+#include <sbi/sbi_string.h>
 
 static const struct sbi_console_device *console_dev = NULL;
 static spinlock_t console_out_lock	       = SPIN_LOCK_INITIALIZER;
@@ -44,9 +45,13 @@ void sbi_putc(char ch)
 void sbi_puts(const char *str)
 {
 	spin_lock(&console_out_lock);
-	while (*str) {
-		sbi_putc(*str);
-		str++;
+	if (console_dev && console_dev->console_puts) {
+		console_dev->console_puts(str, sbi_strlen(str));
+	} else {
+		while (*str) {
+			sbi_putc(*str);
+			str++;
+		}
 	}
 	spin_unlock(&console_out_lock);
 }
@@ -56,8 +61,12 @@ void sbi_nputs(const char *str, unsigned long len)
 	unsigned long i;
 
 	spin_lock(&console_out_lock);
-	for (i = 0; i < len; i++)
-		sbi_putc(str[i]);
+	if (console_dev && console_dev->console_puts) {
+		console_dev->console_puts(str, len);
+	} else {
+		for (i = 0; i < len; i++)
+			sbi_putc(str[i]);
+	}
 	spin_unlock(&console_out_lock);
 }
 
-- 
2.34.1



From apatel at ventanamicro.com  Thu Nov 24 05:29:06 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Thu, 24 Nov 2022 18:59:06 +0530
Subject: [PATCH v3 6/6] lib: utils/serial: Implement console_puts() for semihosting
In-Reply-To: <20221124132906.257732-1-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
Message-ID: <20221124132906.257732-7-apatel@ventanamicro.com>

We implement console_puts() for semihosting serial driver to speed-up
semihosting based prints.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/utils/serial/semihosting.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 86fa296..773b75e 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -15,6 +15,7 @@
 
 #define SYSOPEN     0x01
 #define SYSWRITEC   0x03
+#define SYSWRITE    0x05
 #define SYSREAD     0x06
 #define SYSREADC    0x07
 #define SYSERRNO	0x13
@@ -93,6 +94,7 @@ static int semihosting_errno(void)
 }
 
 static int semihosting_infd = SBI_ENODEV;
+static int semihosting_outfd = SBI_ENODEV;
 
 static long semihosting_open(const char *fname, enum semihosting_open_mode mode)
 {
@@ -141,6 +143,21 @@ static long semihosting_read(long fd, void *memp, size_t len)
 	return len - ret;
 }
 
+static long semihosting_write(long fd, const void *memp, size_t len)
+{
+	long ret;
+	struct semihosting_rdwr_s write;
+
+	write.fd = fd;
+	write.memp = (void *)memp;
+	write.len = len;
+
+	ret = semihosting_trap(SYSWRITE, &write);
+	if (ret < 0)
+		return semihosting_errno();
+	return len - ret;
+}
+
 /* clang-format on */
 
 static void semihosting_putc(char ch)
@@ -148,6 +165,20 @@ static void semihosting_putc(char ch)
 	semihosting_trap(SYSWRITEC, &ch);
 }
 
+static void semihosting_puts(const char *str, unsigned long len)
+{
+	char ch;
+	unsigned long i;
+
+	if (semihosting_outfd < 0) {
+		for (i = 0; i < len; i++) {
+			ch = str[i];
+			semihosting_trap(SYSWRITEC, &ch);
+		}
+	} else
+		semihosting_write(semihosting_outfd, str, len);
+}
+
 static int semihosting_getc(void)
 {
 	char ch = 0;
@@ -165,12 +196,14 @@ static int semihosting_getc(void)
 static struct sbi_console_device semihosting_console = {
 	.name = "semihosting",
 	.console_putc = semihosting_putc,
+	.console_puts = semihosting_puts,
 	.console_getc = semihosting_getc
 };
 
 int semihosting_init(void)
 {
 	semihosting_infd = semihosting_open(":tt", MODE_READ);
+	semihosting_outfd = semihosting_open(":tt", MODE_WRITE);
 
 	sbi_console_set_device(&semihosting_console);
 
-- 
2.34.1



From wxjstz at 126.com  Thu Nov 24 18:01:04 2022
From: wxjstz at 126.com (Xiang W)
Date: Fri, 25 Nov 2022 10:01:04 +0800
Subject: [PATCH v3 3/6] lib: sbi: Add sbi_domain_check_addr_range()
 function
In-Reply-To: <20221124132906.257732-4-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
	 <20221124132906.257732-4-apatel@ventanamicro.com>
Message-ID: <c0682a86617cd97f7fe460b1085427344d174f3d.camel@126.com>

? 2022-11-24???? 18:59 +0530?Anup Patel???
> We add sbi_domain_check_addr_range() helper function to check
> whether a given address range is accessible under a particular
> domain.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?include/sbi/sbi_domain.h | 15 +++++++++
> ?lib/sbi/sbi_domain.c???? | 69 ++++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 84 insertions(+)
> 
> diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> index 5553d21..4afcc37 100644
> --- a/include/sbi/sbi_domain.h
> +++ b/include/sbi/sbi_domain.h
> @@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> ?????????????????????????? unsigned long addr, unsigned long mode,
> ?????????????????????????? unsigned long access_flags);
> ?
> +/**
> + * Check whether we can access specified address range for given mode and
> + * memory region flags under a domain
> + * @param dom pointer to domain
> + * @param addr the start of the address range to be checked
> + * @param size the size of the address range to be checked
> + * @param mode the privilege mode of access
> + * @param access_flags bitmask of domain access types (enum sbi_domain_access)
> + * @return TRUE if access allowed otherwise FALSE
> + */
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +??????????????????????????????? unsigned long addr, unsigned long size,
> +??????????????????????????????? unsigned long mode,
> +??????????????????????????????? unsigned long access_flags);
> +
> ?/** Dump domain details on the console */
> ?void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
> ?
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index f24a8e5..11a547c 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -195,6 +195,44 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
> ????????return FALSE;
> ?}
> ?
> +static const struct sbi_domain_memregion *find_region(
> +???????????????????????????????????????????????const struct sbi_domain *dom,
> +???????????????????????????????????????????????unsigned long addr)
> +{
> +???????unsigned long rstart, rend;
> +???????struct sbi_domain_memregion *reg;
> +
> +???????sbi_domain_for_each_memregion(dom, reg) {
> +???????????????rstart = reg->base;
> +???????????????rend = (reg->order < __riscv_xlen) ?
> +???????????????????????rstart + ((1UL << reg->order) - 1) : -1UL;
> +???????????????if (rstart <= addr && addr <= rend)
> +???????????????????????return reg;
> +???????}
> +
> +???????return NULL;
> +}
> +
> +static const struct sbi_domain_memregion *find_next_subset_region(
> +???????????????????????????????const struct sbi_domain *dom,
> +???????????????????????????????const struct sbi_domain_memregion *reg,
> +???????????????????????????????unsigned long addr)
> +{
> +???????struct sbi_domain_memregion *sreg, *ret = NULL;
> +
> +???????sbi_domain_for_each_memregion(dom, sreg) {
> +???????????????if (sreg == reg || (sreg->base <= addr) ||
> +?????????????????? !is_region_subset(sreg, reg))
> +???????????????????????continue;
> +
> +???????????????if (!ret || (sreg->base < ret->base) ||
> +?????????????????? ((sreg->base == ret->base) && (sreg->order < ret->order)))
> +???????????????????????ret = sreg;
> +???????}
> +
> +???????return ret;
> +}
> +
> ?static int sanitize_domain(const struct sbi_platform *plat,
> ?????????????????????????? struct sbi_domain *dom)
> ?{
> @@ -303,6 +341,37 @@ static int sanitize_domain(const struct sbi_platform *plat,
> ????????return 0;
> ?}
> ?
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +??????????????????????????????? unsigned long addr, unsigned long size,
> +??????????????????????????????? unsigned long mode,
> +??????????????????????????????? unsigned long access_flags)
> +{
> +???????unsigned long max = addr + size;
> +???????const struct sbi_domain_memregion *reg, *sreg;
> +
> +???????if (!dom)
> +???????????????return FALSE;
> +
> +???????while (addr < max) {
> +???????????????reg = find_region(dom, addr);
> +???????????????if (!reg)
> +???????????????????????return FALSE;
> +
> +???????????????if (!sbi_domain_check_addr(dom, addr, mode, access_flags))
> +???????????????????????return FALSE;
> +
> +???????????????sreg = find_next_subset_region(dom, reg, addr);
> +???????????????if (sreg)
> +???????????????????????addr = sreg->base;
> +???????????????else if (reg->order < __riscv_xlen)
> +???????????????????????addr = reg->base + (1UL << reg->order);
> +???????????????else
> +???????????????????????break;
> +???????}
> +
> +???????return TRUE;
> +}
> +
> ?void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
> ?{
> ????????u32 i, k;
> -- 
> 2.34.1
> 
> 




From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:22 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:22 +0100
Subject: [PATCH 0/5] lib: fixes for fdt functions
Message-ID: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>

* Use correct type for variables used in error checks
* Avoid duplicates checks
* Don't assign values that are never used.

Heinrich Schuchardt (5):
  lib: simplify fdt_parse_plmt_node()
  lib: simplify fdt_parse_plicsw_node()
  lib: fix fdt_parse_plmt_node()
  lib: fix fdt_parse_plicsw_node()
  lib: simplify fdt_translate_address()

 lib/utils/fdt/fdt_helper.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

-- 
2.37.2



From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:24 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:24 +0100
Subject: [PATCH 2/5] lib: simplify fdt_parse_plicsw_node()
In-Reply-To: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221125140827.47018-3-heinrich.schuchardt@canonical.com>

We should not check !plicsw_base || !size twice.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index dbd7484..57c0248 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -868,7 +868,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !plicsw_base || !size)
+	if (rc < 0)
 		return SBI_ENODEV;
 	*plicsw_base = reg_addr;
 	*size = reg_size;
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:25 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:25 +0100
Subject: [PATCH 3/5] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221125140827.47018-4-heinrich.schuchardt@canonical.com>

cpu_offset, cpu_intc_offset must int to discover failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 57c0248..ea969e5 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -805,7 +805,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 {
 	const fdt32_t *val;
 	int rc, i, count;
-	uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
+	uint64_t reg_addr, reg_size;
 	u32 phandle, hwirq, hartid, hcount;
 
 	if (nodeoffset < 0 || !fdt || !plmt_base ||
@@ -826,6 +826,8 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 
 	hcount = 0;
 	for (i = 0; i < (count / 2); i++) {
+		int cpu_offset, cpu_intc_offset;
+
 		phandle = fdt32_to_cpu(val[2 * i]);
 		hwirq = fdt32_to_cpu(val[2 * i + 1]);
 
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:26 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:26 +0100
Subject: [PATCH 4/5] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221125140827.47018-5-heinrich.schuchardt@canonical.com>

cpu_offset and cpu_intc_offset must be int to detect failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index ea969e5..da96282 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -861,7 +861,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 {
 	const fdt32_t *val;
 	int rc, i, count;
-	uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
+	uint64_t reg_addr, reg_size;
 	u32 phandle, hwirq, hartid, hcount;
 
 	if (nodeoffset < 0 || !fdt || !plicsw_base ||
@@ -882,6 +882,8 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 
 	hcount = 0;
 	for (i = 0; i < (count / 2); i++) {
+		int cpu_offset, cpu_intc_offset;
+
 		phandle = fdt32_to_cpu(val[2 * i]);
 		hwirq = fdt32_to_cpu(val[2 * i + 1]);
 
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:23 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:23 +0100
Subject: [PATCH 1/5] lib: simplify fdt_parse_plmt_node()
In-Reply-To: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221125140827.47018-2-heinrich.schuchardt@canonical.com>

We should not check !plmt_base || !plmt_size twice.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 89b8bba..dbd7484 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -814,7 +814,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !plmt_base || !plmt_size)
+	if (rc < 0)
 		return SBI_ENODEV;
 	*plmt_base = reg_addr;
 	*plmt_size = reg_size;
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Fri Nov 25 06:08:27 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Fri, 25 Nov 2022 15:08:27 +0100
Subject: [PATCH 5/5] lib: simplify fdt_translate_address()
In-Reply-To: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221125140827.47018-6-heinrich.schuchardt@canonical.com>

Don't assign a value to offset which is never used.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index da96282..b8d0eea 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -124,7 +124,7 @@ static int fdt_translate_address(void *fdt, uint64_t reg, int parent,
 	int i, rlen;
 	int cell_addr, cell_size;
 	const fdt32_t *ranges;
-	uint64_t offset = 0, caddr = 0, paddr = 0, rsize = 0;
+	uint64_t offset, caddr = 0, paddr = 0, rsize = 0;
 
 	cell_addr = fdt_address_cells(fdt, parent);
 	if (cell_addr < 1)
-- 
2.37.2



From research_trasio at irq.a4lg.com  Sat Nov 26 00:52:19 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sat, 26 Nov 2022 08:52:19 +0000
Subject: [PATCH 0/3] Query Compiler Features for Better Disassembling
Message-ID: <cover.1669452733.git.research_trasio@irq.a4lg.com>

Hello,

This patchset makes the resulting ELF files (e.g. fw_dynamic.elf)
disassembled correctly (as possible) on the latest toolchain, when compiled
and assembled with the latest GNU toolchain (especially on Binutils master
[going to be 2.40?] but some changes are also effective on 2.39).

In this letter, I will call master commit of GNU Binutils as 2.40.



[BEFORE THE PATCHSET: GNU Binutils 2.39 and 2.40]

Note that some annotations are added.

000000008000a0d0 <__sbi_hfence_gvma_gpa>:
    8000a0d0:   62050073            .word   0x62050073
                                    ^^^^^^^^^^^^^^^^^^
                                    Printed as data
    8000a0d4:   8082                ret
    8000a0d6:   0001                nop

# (quote from csr_read_num)
    800047b6:   3c002573            csrr    a0,0x3c0
                                               ^^^^^
                                               Raw CSR number (pmpaddr16)
    800047ba:   8082                ret



[PATCH 1/3]
** partially effective on GNU Binutils 2.39 and 2.40 **

It optionally replaces ".word" (which emits a 32-bit "data" word) in
lib/sbi/sbi_hfence.S with ".insn" with raw value (which emits an
"instruction" word) when supported by the assembler.

Before this commit and on GNU Binutils, an ELF mapping symbol "$d" (from
here, data follows) is inserted before ".word".  Even if the hfence.*
instruction itself is recognized, ".word"s are recognized as data, not
instructions (due to the existence of mapping symbol).
e
Instead, ".insn" emits (possibly variable length) instruction word and
inserts "$x" (from here, instruction follows) mapping symbol where
necessary.  Note that, not all assemblers support ".insn" with raw
instruction value.  This commit checks ".insn" with raw value support.

After that, objdump of __sbi_hfence_gvma_gpa will look like this
(for PATCH 2-3/3, GNU Binutils 2.39 output will be the same):

000000008000a0d0 <__sbi_hfence_gvma_gpa>:
    8000a0d0:   62050073            .4byte  0x62050073
                                    ^^^^^^^^^^^^^^^^^^
                                    Printed as an instruction
                                    (but not recognized as hfence.gvma yet)
    8000a0d4:   8082                ret
    8000a0d6:   0001                nop



[PATCH 2/3]
** effective on GNU Binutils 2.40 **

".option arch,+h" assembler directive enables 'H' extension support in the
section (may be the file scope depending on the Binutils version).

It will be reflected to the ELF mapping symbols "$x[arch]" (where [arch]
is an ISA string) on GNU Binutils 2.40 and 'H' extension can be partially
enabled (only on lib/sbi/sbi_hfence.o).

At first, I intended this to be fully effective on GNU Binutils 2.39 (where
section-level architecture change will be reflected to file scope and 'H'
extension dependency is merged into final ELF files).
However, due to a bug in the linker (to be specific, riscv_merge_std_ext
function in BFD), it did not happen on 2.39.

After that, objdump of __sbi_hfence_gvma_gpa in GNU Binutils 2.40 will be:

000000008000a0d0 <__sbi_hfence_gvma_gpa>:
    8000a0d0:   62050073            hfence.gvma     a0
                                    ^^^^^^^^^^^^^^^^^^
                                    Printed as a hfence.gvma instruction
    8000a0d4:   8082                ret
    8000a0d6:   0001                nop



[PATCH 3/3]
** effective on GNU Binutils 2.39 or later **

OpenSBI uses some privileged architecture version 1.12 CSRs and this commit
reflects this version to the final ELF file.  As a result, 1.12 CSRs are
correctly named (instead of raw numbers).

After that, objdump of csr_read_num will look like this
(both on GNU Binutils 2.39 and 2.40):

# (quote from csr_read_num)
    800047b6:   3c002573            csrr    a0,pmpaddr16
                                               ^^^^^^^^^
                                               CSR name new in v1.12
    800047ba:   8082                ret



Thanks,
Tsukasa




Tsukasa OI (3):
  lib: sbi: Optionally use ".insn" instead of ".word"
  lib: sbi: Optionally use ".option arch,+h"
  Makefile: Optionally specify latest privileged specification

 Makefile             | 26 ++++++++++++++++++++++++++
 lib/sbi/sbi_hfence.S | 20 ++++++++++++--------
 2 files changed, 38 insertions(+), 8 deletions(-)


base-commit: 1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 00:52:20 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sat, 26 Nov 2022 08:52:20 +0000
Subject: [PATCH 1/3] lib: sbi: Optionally use ".insn" instead of ".word"
In-Reply-To: <cover.1669452733.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com>
Message-ID: <d0ab3f9e2b778ce834a81ec56c3cfd9d0fe255d2.1669452733.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

".word" is used to emit a data word (32-bits) and recent GNU assembler
adds mapping symbol "$d" before ".word" to make sure that this is a data
word.  However, in lib/sbi/sbi_hfence.S, we use this to emit hfence.*
instructions (for assemblers that do not support hfence.*).  The mapping
symbol "$d" prevents these instructions being disassembled as code.

Instead, ".insn" is available to emit raw instructions but not all
assemblers with ".insn" support raw values.

This commit tests support of ".insn" with raw value in the Makefile
(AS_SUPPORT_INSN_RAW_DIRECTIVE) and optionally replaces ".word" with ".insn"
when ".insn" with raw value is supported.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 Makefile             |  8 ++++++++
 lib/sbi/sbi_hfence.S | 16 ++++++++--------
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 8db6eabe9fda..e942dfdc00bc 100644
--- a/Makefile
+++ b/Makefile
@@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the ".insn" directive on the assembler (with raw value) is supported
+AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
+
 # Build Info:
 # OPENSBI_BUILD_TIME_STAMP -- the compilation time stamp
 # OPENSBI_BUILD_COMPILER_VERSION -- the compiler version info
@@ -323,6 +326,11 @@ ifeq ($(BUILD_INFO),y)
 GENFLAGS	+=	-DOPENSBI_BUILD_TIME_STAMP="\"$(OPENSBI_BUILD_TIME_STAMP)\""
 GENFLAGS	+=	-DOPENSBI_BUILD_COMPILER_VERSION="\"$(OPENSBI_BUILD_COMPILER_VERSION)\""
 endif
+ifeq ($(AS_SUPPORT_INSN_RAW_DIRECTIVE),y)
+GENFLAGS    +=  -DRAW_INSN=".insn"
+else
+GENFLAGS    +=  -DRAW_INSN=".word"
+endif
 ifdef PLATFORM
 GENFLAGS	+=	-include $(KCONFIG_AUTOHEADER)
 endif
diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
index e11e6505383d..40882e036932 100644
--- a/lib/sbi/sbi_hfence.S
+++ b/lib/sbi/sbi_hfence.S
@@ -32,7 +32,7 @@ __sbi_hfence_gvma_vmid_gpa:
 	 * HFENCE.GVMA a0, a1
 	 * 0110001 01011 01010 000 00000 1110011
 	 */
-	.word 0x62b50073
+	RAW_INSN 0x62b50073
 	ret
 
 	.align 3
@@ -44,7 +44,7 @@ __sbi_hfence_gvma_vmid:
 	 * HFENCE.GVMA zero, a0
 	 * 0110001 01010 00000 000 00000 1110011
 	 */
-	.word 0x62a00073
+	RAW_INSN 0x62a00073
 	ret
 
 	.align 3
@@ -56,7 +56,7 @@ __sbi_hfence_gvma_gpa:
 	 * HFENCE.GVMA a0
 	 * 0110001 00000 01010 000 00000 1110011
 	 */
-	.word 0x62050073
+	RAW_INSN 0x62050073
 	ret
 
 	.align 3
@@ -68,7 +68,7 @@ __sbi_hfence_gvma_all:
 	 * HFENCE.GVMA
 	 * 0110001 00000 00000 000 00000 1110011
 	 */
-	.word 0x62000073
+	RAW_INSN 0x62000073
 	ret
 
 	/*
@@ -95,7 +95,7 @@ __sbi_hfence_vvma_asid_va:
 	 * HFENCE.VVMA a0, a1
 	 * 0010001 01011 01010 000 00000 1110011
 	 */
-	.word 0x22b50073
+	RAW_INSN 0x22b50073
 	ret
 
 	.align 3
@@ -107,7 +107,7 @@ __sbi_hfence_vvma_asid:
 	 * HFENCE.VVMA zero, a0
 	 * 0010001 01010 00000 000 00000 1110011
 	 */
-	.word 0x22a00073
+	RAW_INSN 0x22a00073
 	ret
 
 	.align 3
@@ -119,7 +119,7 @@ __sbi_hfence_vvma_va:
 	 * HFENCE.VVMA zero, a0
 	 * 0010001 00000 01010 000 00000 1110011
 	 */
-	.word 0x22050073
+	RAW_INSN 0x22050073
 	ret
 
 	.align 3
@@ -131,5 +131,5 @@ __sbi_hfence_vvma_all:
 	 * HFENCE.VVMA
 	 * 0010001 00000 00000 000 00000 1110011
 	 */
-	.word 0x22000073
+	RAW_INSN 0x22000073
 	ret
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 00:52:21 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sat, 26 Nov 2022 08:52:21 +0000
Subject: [PATCH 2/3] lib: sbi: Optionally use ".option arch,+h"
In-Reply-To: <cover.1669452733.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com>
Message-ID: <f8a205b8a6cd5591bc4a4c018b7ce02c167c1faf.1669452733.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

On the debugger / disassembler, disassembling hfence.* as hfence.* requires
indication of the 'H'-extension use.

".option arch,+[EXT_NAME]" is one of the such ways and this commit
optionally inserts this assembler directive when supported.

It enables disassembling on the software which supports "$x[arch]" (mapping
symbols with ISA string) - latest GNU Binutils (will be released as 2.40).
Note that this commit alone won't make disassembler behavior correct on
GNU Binutils 2.39 because of a linker issue.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 Makefile             | 6 ++++++
 lib/sbi/sbi_hfence.S | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/Makefile b/Makefile
index e942dfdc00bc..e77648ff33c3 100644
--- a/Makefile
+++ b/Makefile
@@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the assembler support the H extension with .option arch,+h
+AS_SUPPORT_H_EXT_BY_OPTION_ARCH := $(shell echo ".option arch,+h" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
+
 # Check whether the ".insn" directive on the assembler (with raw value) is supported
 AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
 
@@ -331,6 +334,9 @@ GENFLAGS    +=  -DRAW_INSN=".insn"
 else
 GENFLAGS    +=  -DRAW_INSN=".word"
 endif
+ifeq ($(AS_SUPPORT_H_EXT_BY_OPTION_ARCH),y)
+GENFLAGS    +=  -DOPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
+endif
 ifdef PLATFORM
 GENFLAGS	+=	-include $(KCONFIG_AUTOHEADER)
 endif
diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
index 40882e036932..146a41959a67 100644
--- a/lib/sbi/sbi_hfence.S
+++ b/lib/sbi/sbi_hfence.S
@@ -8,6 +8,10 @@
  *   Atish Patra <anup.patel at wdc.com>
  */
 
+#ifdef OPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
+	.option arch,+h
+#endif
+
 	/*
 	 * HFENCE.GVMA rs1, rs2
 	 * HFENCE.GVMA zero, rs2
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 00:52:22 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sat, 26 Nov 2022 08:52:22 +0000
Subject: [PATCH 3/3] Makefile: Optionally specify latest privileged specification
In-Reply-To: <cover.1669452733.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com>
Message-ID: <45c05cbaf0655b762afd780a96a736a09f33ab4f.1669452733.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

Although that OpenSBI can be compiled with compiler with the privileged
architecture version 1.11, it partially uses CSRs from the latest
privileged specification, version 1.12.

To enable fully-featured disassembling (through ELF attributes), this commit
queries whether the assembler supports -mpriv-spec=1.12 and adds
"-Wa,-mpriv-spec=1.12" to CFLAGS and ASFLAGS when supported.
---
 Makefile | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Makefile b/Makefile
index e77648ff33c3..47e20ffa0661 100644
--- a/Makefile
+++ b/Makefile
@@ -164,6 +164,9 @@ else
 USE_LD_FLAG	=	-fuse-ld=bfd
 endif
 
+# Setup privileged architecture
+OPENSBI_PRIV_SPEC = 1.12
+
 # Check whether the linker supports creating PIEs
 OPENSBI_LD_PIE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) $(USE_LD_FLAG) -fPIE -nostdlib -Wl,-pie -x c /dev/null -o /dev/null >/dev/null 2>&1 && echo y || echo n)
 
@@ -173,6 +176,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the assembler and the compiler support the privileged architecture option (used by OpenSBI)
+CC_SUPPORT_PRIV_SPEC_LATEST := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC) -x c -c /dev/null -o /dev/null >/dev/null 2>&1 && echo y || echo n)
+
 # Check whether the assembler support the H extension with .option arch,+h
 AS_SUPPORT_H_EXT_BY_OPTION_ARCH := $(shell echo ".option arch,+h" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
 
@@ -352,6 +358,9 @@ CFLAGS		+=	-mno-save-restore
 endif
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 CFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
+ifeq ($(CC_SUPPORT_PRIV_SPEC_LATEST),y)
+CFLAGS		+=	-Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC)
+endif
 CFLAGS		+=	$(RELAX_FLAG)
 CFLAGS		+=	$(GENFLAGS)
 CFLAGS		+=	$(platform-cflags-y)
@@ -370,6 +379,9 @@ ASFLAGS		+=	-mno-save-restore
 endif
 ASFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 ASFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
+ifeq ($(CC_SUPPORT_PRIV_SPEC_LATEST),y)
+ASFLAGS		+=	-Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC)
+endif
 ASFLAGS		+=	$(RELAX_FLAG)
 ifneq ($(CC_IS_CLANG),y)
 ifneq ($(RELAX_FLAG),)
-- 
2.38.1



From wxjstz at 126.com  Sat Nov 26 04:51:59 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:51:59 +0800
Subject: [PATCH 4/5] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221125140827.47018-5-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
	 <20221125140827.47018-5-heinrich.schuchardt@canonical.com>
Message-ID: <9803bae1f9df8419ca7726ca478f8e5e82ffe651.camel@126.com>

? 2022-11-25???? 15:08 +0100?Heinrich Schuchardt???
> cpu_offset and cpu_intc_offset must be int to detect failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
https://github.com/riscv-software-src/opensbi/blob/master/lib/utils/fdt/fdt_helper.c#L891
if (cpu_intc_offset < 0) should be if (cpu_offset < 0)

Regards,
Xiang W
> ---
> ?lib/utils/fdt/fdt_helper.c | 4 +++-
> ?1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index ea969e5..da96282 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -861,7 +861,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plicsw_base ||
> @@ -882,6 +882,8 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:54:37 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:54:37 +0800
Subject: [PATCH 1/5] lib: simplify fdt_parse_plmt_node()
In-Reply-To: <20221125140827.47018-2-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
	 <20221125140827.47018-2-heinrich.schuchardt@canonical.com>
Message-ID: <8b7f158aee9ba2dcbd8751e8bd403cd82c804607.camel@126.com>

? 2022-11-25???? 15:08 +0100?Heinrich Schuchardt???
> We should not check !plmt_base || !plmt_size twice.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/fdt/fdt_helper.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 89b8bba..dbd7484 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -814,7 +814,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?
> ????????rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
> ??????????????????????????????????? &reg_addr, &reg_size);
> -???????if (rc < 0 || !plmt_base || !plmt_size)
> +???????if (rc < 0)
> ????????????????return SBI_ENODEV;
> ????????*plmt_base = reg_addr;
> ????????*plmt_size = reg_size;
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:55:07 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:55:07 +0800
Subject: [PATCH 5/5] lib: simplify fdt_translate_address()
In-Reply-To: <20221125140827.47018-6-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
	 <20221125140827.47018-6-heinrich.schuchardt@canonical.com>
Message-ID: <43e031b0705b54b0179d1dbbd85e11e8dbd22846.camel@126.com>

? 2022-11-25???? 15:08 +0100?Heinrich Schuchardt???
> Don't assign a value to offset which is never used.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/fdt/fdt_helper.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index da96282..b8d0eea 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -124,7 +124,7 @@ static int fdt_translate_address(void *fdt, uint64_t reg, int parent,
> ????????int i, rlen;
> ????????int cell_addr, cell_size;
> ????????const fdt32_t *ranges;
> -???????uint64_t offset = 0, caddr = 0, paddr = 0, rsize = 0;
> +???????uint64_t offset, caddr = 0, paddr = 0, rsize = 0;
> ?
> ????????cell_addr = fdt_address_cells(fdt, parent);
> ????????if (cell_addr < 1)
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:55:25 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:55:25 +0800
Subject: [PATCH v3 4/6] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221124132906.257732-5-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
	 <20221124132906.257732-5-apatel@ventanamicro.com>
Message-ID: <92244753807252e4c77632e99965e38e6d1b6da0.camel@126.com>

? 2022-11-24???? 18:59 +0530?Anup Patel???
> We implement SBI debug console extension as one of the replacement
> SBI extensions. This extension is only available when OpenSBI platform
> provides a console device to generic library.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/sbi/Kconfig????????? |? 4 +++
> ?lib/sbi/objects.mk?????? |? 3 ++
> ?lib/sbi/sbi_ecall_dbcn.c | 62 ++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 69 insertions(+)
> ?create mode 100644 lib/sbi/sbi_ecall_dbcn.c
> 
> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> index df74bba..ef6728b 100644
> --- a/lib/sbi/Kconfig
> +++ b/lib/sbi/Kconfig
> @@ -26,6 +26,10 @@ config SBI_ECALL_PMU
> ????????bool "Performance Monitoring Unit extension"
> ????????default y
> ?
> +config SBI_ECALL_DBCN
> +???????bool "Debug Console extension"
> +???????default y
> +
> ?config SBI_ECALL_LEGACY
> ????????bool "SBI v0.1 legacy extensions"
> ????????default y
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index c774ebb..319f38d 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -37,6 +37,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_SRST) += sbi_ecall_srst.o
> ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_PMU) += ecall_pmu
> ?libsbi-objs-$(CONFIG_SBI_ECALL_PMU) += sbi_ecall_pmu.o
> ?
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBCN) += ecall_dbcn
> +libsbi-objs-$(CONFIG_SBI_ECALL_DBCN) += sbi_ecall_dbcn.o
> +
> ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_LEGACY) += ecall_legacy
> ?libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
> ?
> diff --git a/lib/sbi/sbi_ecall_dbcn.c b/lib/sbi/sbi_ecall_dbcn.c
> new file mode 100644
> index 0000000..19ac021
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_dbcn.c
> @@ -0,0 +1,62 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Ventana Micro Systems Inc.
> + *
> + * Authors:
> + *?? Anup Patel <apatel at ventanamicro.com>
> + */
> +
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/riscv_asm.h>
> +
> +static int sbi_ecall_dbcn_handler(unsigned long extid, unsigned long funcid,
> +???????????????????????????????? const struct sbi_trap_regs *regs,
> +???????????????????????????????? unsigned long *out_val,
> +???????????????????????????????? struct sbi_trap_info *out_trap)
> +{
> +???????ulong smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
> +???????????????????????MSTATUS_MPP_SHIFT;
> +
> +???????if (funcid == SBI_EXT_DBCN_CONSOLE_PUTS) {
> +???????????????/*
> +??????????????? * On RV32, the M-mode can only access the first 4GB of
> +??????????????? * the physical address space because M-mode does not have
> +??????????????? * MMU to access full 34-bit physical address space.
> +??????????????? *
> +??????????????? * Based on above, we simply fail if the upper 32bits of
> +??????????????? * the physical address (i.e. a2 register) is non-zero on
> +??????????????? * RV32.
> +??????????????? */
> +#if __riscv_xlen == 32
> +???????????????if (regs->a2)
> +???????????????????????return SBI_ERR_FAILED;
> +#endif
> +???????????????if (!sbi_domain_check_addr_range(sbi_domain_thishart_ptr(),
> +???????????????????????????????????????regs->a1, regs->a0, smode,
> +???????????????????????????????????????SBI_DOMAIN_READ|SBI_DOMAIN_WRITE))
> +???????????????????????return SBI_EINVALID_ADDR;
> +???????????????sbi_nputs((const char *)regs->a1, regs->a0);
> +???????????????return 0;
> +???????}
> +
> +???????return SBI_ENOTSUPP;
> +}
> +
> +static int sbi_ecall_dbcn_probe(unsigned long extid, unsigned long *out_val)
> +{
> +???????*out_val = (sbi_console_get_device()) ? 1 : 0;
> +???????return 0;
> +}
> +
> +struct sbi_ecall_extension ecall_dbcn = {
> +???????.extid_start = SBI_EXT_DBCN,
> +???????.extid_end = SBI_EXT_DBCN,
> +???????.handle = sbi_ecall_dbcn_handler,
> +???????.probe = sbi_ecall_dbcn_probe,
> +};
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:55:38 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:55:38 +0800
Subject: [PATCH v3 5/6] lib: sbi: Add console_puts() callback in the
 console device
In-Reply-To: <20221124132906.257732-6-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
	 <20221124132906.257732-6-apatel@ventanamicro.com>
Message-ID: <d0e993686d02c1ea1381b4af18aac73740e5d9ce.camel@126.com>

? 2022-11-24???? 18:59 +0530?Anup Patel???
> We add console_puts() callback in the console device which allows
> console drivers (such as semihosting) to implement a specialized
> way to output character string.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?include/sbi/sbi_console.h |? 3 +++
> ?lib/sbi/sbi_console.c???? | 19 ++++++++++++++-----
> ?2 files changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/include/sbi/sbi_console.h b/include/sbi/sbi_console.h
> index 1bdeeb9..7e757a7 100644
> --- a/include/sbi/sbi_console.h
> +++ b/include/sbi/sbi_console.h
> @@ -19,6 +19,9 @@ struct sbi_console_device {
> ????????/** Write a character to the console output */
> ????????void (*console_putc)(char ch);
> ?
> +???????/** Write a character string to the console output */
> +???????void (*console_puts)(const char *str, unsigned long len);
> +
> ????????/** Read a character from the console input */
> ????????int (*console_getc)(void);
> ?};
> diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
> index a975708..3c98f4e 100644
> --- a/lib/sbi/sbi_console.c
> +++ b/lib/sbi/sbi_console.c
> @@ -12,6 +12,7 @@
> ?#include <sbi/sbi_hart.h>
> ?#include <sbi/sbi_platform.h>
> ?#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_string.h>
> ?
> ?static const struct sbi_console_device *console_dev = NULL;
> ?static spinlock_t console_out_lock??????????? = SPIN_LOCK_INITIALIZER;
> @@ -44,9 +45,13 @@ void sbi_putc(char ch)
> ?void sbi_puts(const char *str)
> ?{
> ????????spin_lock(&console_out_lock);
> -???????while (*str) {
> -???????????????sbi_putc(*str);
> -???????????????str++;
> +???????if (console_dev && console_dev->console_puts) {
> +???????????????console_dev->console_puts(str, sbi_strlen(str));
> +???????} else {
> +???????????????while (*str) {
> +???????????????????????sbi_putc(*str);
> +???????????????????????str++;
> +???????????????}
> ????????}
> ????????spin_unlock(&console_out_lock);
> ?}
> @@ -56,8 +61,12 @@ void sbi_nputs(const char *str, unsigned long len)
> ????????unsigned long i;
> ?
> ????????spin_lock(&console_out_lock);
> -???????for (i = 0; i < len; i++)
> -???????????????sbi_putc(str[i]);
> +???????if (console_dev && console_dev->console_puts) {
> +???????????????console_dev->console_puts(str, len);
> +???????} else {
> +???????????????for (i = 0; i < len; i++)
> +???????????????????????sbi_putc(str[i]);
> +???????}
> ????????spin_unlock(&console_out_lock);
> ?}
> ?
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:54:54 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:54:54 +0800
Subject: [PATCH 2/5] lib: simplify fdt_parse_plicsw_node()
In-Reply-To: <20221125140827.47018-3-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
	 <20221125140827.47018-3-heinrich.schuchardt@canonical.com>
Message-ID: <0f2d09d80f80ef296edd6be11a7f2c5c6d865200.camel@126.com>

? 2022-11-25???? 15:08 +0100?Heinrich Schuchardt???
> We should not check !plicsw_base || !size twice.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/fdt/fdt_helper.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index dbd7484..57c0248 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -868,7 +868,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?
> ????????rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
> ??????????????????????????????????? &reg_addr, &reg_size);
> -???????if (rc < 0 || !plicsw_base || !size)
> +???????if (rc < 0)
> ????????????????return SBI_ENODEV;
> ????????*plicsw_base = reg_addr;
> ????????*size = reg_size;
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:55:49 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:55:49 +0800
Subject: [PATCH v3 6/6] lib: utils/serial: Implement console_puts() for
 semihosting
In-Reply-To: <20221124132906.257732-7-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
	 <20221124132906.257732-7-apatel@ventanamicro.com>
Message-ID: <7b24b7d7ad9774aaee256abd3164cbf17a208b1f.camel@126.com>

? 2022-11-24???? 18:59 +0530?Anup Patel???
> We implement console_puts() for semihosting serial driver to speed-up
> semihosting based prints.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/serial/semihosting.c | 33 +++++++++++++++++++++++++++++++++
> ?1 file changed, 33 insertions(+)
> 
> diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
> index 86fa296..773b75e 100644
> --- a/lib/utils/serial/semihosting.c
> +++ b/lib/utils/serial/semihosting.c
> @@ -15,6 +15,7 @@
> ?
> ?#define SYSOPEN???? 0x01
> ?#define SYSWRITEC?? 0x03
> +#define SYSWRITE??? 0x05
> ?#define SYSREAD???? 0x06
> ?#define SYSREADC??? 0x07
> ?#define SYSERRNO???????0x13
> @@ -93,6 +94,7 @@ static int semihosting_errno(void)
> ?}
> ?
> ?static int semihosting_infd = SBI_ENODEV;
> +static int semihosting_outfd = SBI_ENODEV;
> ?
> ?static long semihosting_open(const char *fname, enum semihosting_open_mode mode)
> ?{
> @@ -141,6 +143,21 @@ static long semihosting_read(long fd, void *memp, size_t len)
> ????????return len - ret;
> ?}
> ?
> +static long semihosting_write(long fd, const void *memp, size_t len)
> +{
> +???????long ret;
> +???????struct semihosting_rdwr_s write;
> +
> +???????write.fd = fd;
> +???????write.memp = (void *)memp;
> +???????write.len = len;
> +
> +???????ret = semihosting_trap(SYSWRITE, &write);
> +???????if (ret < 0)
> +???????????????return semihosting_errno();
> +???????return len - ret;
> +}
> +
> ?/* clang-format on */
> ?
> ?static void semihosting_putc(char ch)
> @@ -148,6 +165,20 @@ static void semihosting_putc(char ch)
> ????????semihosting_trap(SYSWRITEC, &ch);
> ?}
> ?
> +static void semihosting_puts(const char *str, unsigned long len)
> +{
> +???????char ch;
> +???????unsigned long i;
> +
> +???????if (semihosting_outfd < 0) {
> +???????????????for (i = 0; i < len; i++) {
> +???????????????????????ch = str[i];
> +???????????????????????semihosting_trap(SYSWRITEC, &ch);
> +???????????????}
> +???????} else
> +???????????????semihosting_write(semihosting_outfd, str, len);
> +}
> +
> ?static int semihosting_getc(void)
> ?{
> ????????char ch = 0;
> @@ -165,12 +196,14 @@ static int semihosting_getc(void)
> ?static struct sbi_console_device semihosting_console = {
> ????????.name = "semihosting",
> ????????.console_putc = semihosting_putc,
> +???????.console_puts = semihosting_puts,
> ????????.console_getc = semihosting_getc
> ?};
> ?
> ?int semihosting_init(void)
> ?{
> ????????semihosting_infd = semihosting_open(":tt", MODE_READ);
> +???????semihosting_outfd = semihosting_open(":tt", MODE_WRITE);
> ?
> ????????sbi_console_set_device(&semihosting_console);
> ?
> -- 
> 2.34.1
> 
> 




From wxjstz at 126.com  Sat Nov 26 04:49:55 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 26 Nov 2022 20:49:55 +0800
Subject: [PATCH 3/5] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221125140827.47018-4-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
	 <20221125140827.47018-4-heinrich.schuchardt@canonical.com>
Message-ID: <52b2e02b3de19605d3816c9ebbfd520561d94055.camel@126.com>

? 2022-11-25???? 15:08 +0100?Heinrich Schuchardt???
> cpu_offset, cpu_intc_offset must int to discover failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
https://github.com/riscv-software-src/opensbi/blob/master/lib/utils/fdt/fdt_helper.c#L837
if (cpu_intc_offset < 0) should be if (cpu_offset < 0)

Regards,
Xiang W
> ---
> ?lib/utils/fdt/fdt_helper.c | 4 +++-
> ?1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 57c0248..ea969e5 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -805,7 +805,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plmt_base ||
> @@ -826,6 +826,8 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> -- 
> 2.37.2
> 
> 




From research_trasio at irq.a4lg.com  Sat Nov 26 19:04:29 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 03:04:29 +0000
Subject: [PATCH v2 0/3] Query Compiler Features for Better Disassembling
In-Reply-To: <cover.1669452733.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com>
Message-ID: <cover.1669518264.git.research_trasio@irq.a4lg.com>

Hello,

This is a minor fix to the patchset
"Query Compiler Features for Better Disassembling".

c.f. PATCH v1 (including backgrounds):
<http://lists.infradead.org/pipermail/opensbi/2022-November/003659.html>

[Changes: v1 -> v2]
-   PATCH 2/2: Make feature detection more robust
    (detect warnings generated by GAS or Clang)

Thanks,
Tsukasa




Tsukasa OI (3):
  lib: sbi: Optionally use ".insn" instead of ".word"
  lib: sbi: Optionally use ".option arch,+h"
  Makefile: Optionally specify latest privileged specification

 Makefile             | 26 ++++++++++++++++++++++++++
 lib/sbi/sbi_hfence.S | 20 ++++++++++++--------
 2 files changed, 38 insertions(+), 8 deletions(-)


base-commit: 1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 19:04:30 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 03:04:30 +0000
Subject: [PATCH v2 1/3] lib: sbi: Optionally use ".insn" instead of ".word"
In-Reply-To: <cover.1669518264.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com> <cover.1669518264.git.research_trasio@irq.a4lg.com>
Message-ID: <9c7044fc3660a02d86729cd5873468d376235262.1669518264.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

".word" is used to emit a data word (32-bits) and recent GNU assembler
adds mapping symbol "$d" before ".word" to make sure that this is a data
word.  However, in lib/sbi/sbi_hfence.S, we use this to emit hfence.*
instructions (for assemblers that do not support hfence.*).  The mapping
symbol "$d" prevents these instructions being disassembled as code.

Instead, ".insn" is available to emit raw instructions but not all
assemblers with ".insn" support raw values.

This commit tests support of ".insn" with raw value in the Makefile
(AS_SUPPORT_INSN_RAW_DIRECTIVE) and optionally replaces ".word" with ".insn"
when ".insn" with raw value is supported.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 Makefile             |  8 ++++++++
 lib/sbi/sbi_hfence.S | 16 ++++++++--------
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 8db6eabe9fda..e942dfdc00bc 100644
--- a/Makefile
+++ b/Makefile
@@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the ".insn" directive on the assembler (with raw value) is supported
+AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
+
 # Build Info:
 # OPENSBI_BUILD_TIME_STAMP -- the compilation time stamp
 # OPENSBI_BUILD_COMPILER_VERSION -- the compiler version info
@@ -323,6 +326,11 @@ ifeq ($(BUILD_INFO),y)
 GENFLAGS	+=	-DOPENSBI_BUILD_TIME_STAMP="\"$(OPENSBI_BUILD_TIME_STAMP)\""
 GENFLAGS	+=	-DOPENSBI_BUILD_COMPILER_VERSION="\"$(OPENSBI_BUILD_COMPILER_VERSION)\""
 endif
+ifeq ($(AS_SUPPORT_INSN_RAW_DIRECTIVE),y)
+GENFLAGS    +=  -DRAW_INSN=".insn"
+else
+GENFLAGS    +=  -DRAW_INSN=".word"
+endif
 ifdef PLATFORM
 GENFLAGS	+=	-include $(KCONFIG_AUTOHEADER)
 endif
diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
index e11e6505383d..40882e036932 100644
--- a/lib/sbi/sbi_hfence.S
+++ b/lib/sbi/sbi_hfence.S
@@ -32,7 +32,7 @@ __sbi_hfence_gvma_vmid_gpa:
 	 * HFENCE.GVMA a0, a1
 	 * 0110001 01011 01010 000 00000 1110011
 	 */
-	.word 0x62b50073
+	RAW_INSN 0x62b50073
 	ret
 
 	.align 3
@@ -44,7 +44,7 @@ __sbi_hfence_gvma_vmid:
 	 * HFENCE.GVMA zero, a0
 	 * 0110001 01010 00000 000 00000 1110011
 	 */
-	.word 0x62a00073
+	RAW_INSN 0x62a00073
 	ret
 
 	.align 3
@@ -56,7 +56,7 @@ __sbi_hfence_gvma_gpa:
 	 * HFENCE.GVMA a0
 	 * 0110001 00000 01010 000 00000 1110011
 	 */
-	.word 0x62050073
+	RAW_INSN 0x62050073
 	ret
 
 	.align 3
@@ -68,7 +68,7 @@ __sbi_hfence_gvma_all:
 	 * HFENCE.GVMA
 	 * 0110001 00000 00000 000 00000 1110011
 	 */
-	.word 0x62000073
+	RAW_INSN 0x62000073
 	ret
 
 	/*
@@ -95,7 +95,7 @@ __sbi_hfence_vvma_asid_va:
 	 * HFENCE.VVMA a0, a1
 	 * 0010001 01011 01010 000 00000 1110011
 	 */
-	.word 0x22b50073
+	RAW_INSN 0x22b50073
 	ret
 
 	.align 3
@@ -107,7 +107,7 @@ __sbi_hfence_vvma_asid:
 	 * HFENCE.VVMA zero, a0
 	 * 0010001 01010 00000 000 00000 1110011
 	 */
-	.word 0x22a00073
+	RAW_INSN 0x22a00073
 	ret
 
 	.align 3
@@ -119,7 +119,7 @@ __sbi_hfence_vvma_va:
 	 * HFENCE.VVMA zero, a0
 	 * 0010001 00000 01010 000 00000 1110011
 	 */
-	.word 0x22050073
+	RAW_INSN 0x22050073
 	ret
 
 	.align 3
@@ -131,5 +131,5 @@ __sbi_hfence_vvma_all:
 	 * HFENCE.VVMA
 	 * 0010001 00000 00000 000 00000 1110011
 	 */
-	.word 0x22000073
+	RAW_INSN 0x22000073
 	ret
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 19:04:31 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 03:04:31 +0000
Subject: [PATCH v2 2/3] lib: sbi: Optionally use ".option arch,+h"
In-Reply-To: <cover.1669518264.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com> <cover.1669518264.git.research_trasio@irq.a4lg.com>
Message-ID: <688110cfcf63a3b70562d58daa095fcbb6a7820b.1669518264.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

On the debugger / disassembler, disassembling hfence.* as hfence.* requires
indication of the 'H'-extension use.

".option arch,+[EXT_NAME]" is one of the such ways and this commit
optionally inserts this assembler directive when supported.

It enables disassembling on the software which supports "$x[arch]" (mapping
symbols with ISA string) - latest GNU Binutils (will be released as 2.40).
Note that this commit alone won't make disassembler behavior correct on
GNU Binutils 2.39 because of a linker issue.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 Makefile             | 6 ++++++
 lib/sbi/sbi_hfence.S | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/Makefile b/Makefile
index e942dfdc00bc..d8b85f0497aa 100644
--- a/Makefile
+++ b/Makefile
@@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the assembler support the H extension with .option arch,+h
+AS_SUPPORT_H_EXT_BY_OPTION_ARCH := $(shell echo ".option arch,+h" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null 2>&1 | grep -i "warning:.*option" > /dev/null && echo n || echo y)
+
 # Check whether the ".insn" directive on the assembler (with raw value) is supported
 AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
 
@@ -331,6 +334,9 @@ GENFLAGS    +=  -DRAW_INSN=".insn"
 else
 GENFLAGS    +=  -DRAW_INSN=".word"
 endif
+ifeq ($(AS_SUPPORT_H_EXT_BY_OPTION_ARCH),y)
+GENFLAGS    +=  -DOPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
+endif
 ifdef PLATFORM
 GENFLAGS	+=	-include $(KCONFIG_AUTOHEADER)
 endif
diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
index 40882e036932..146a41959a67 100644
--- a/lib/sbi/sbi_hfence.S
+++ b/lib/sbi/sbi_hfence.S
@@ -8,6 +8,10 @@
  *   Atish Patra <anup.patel at wdc.com>
  */
 
+#ifdef OPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
+	.option arch,+h
+#endif
+
 	/*
 	 * HFENCE.GVMA rs1, rs2
 	 * HFENCE.GVMA zero, rs2
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 19:04:32 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 03:04:32 +0000
Subject: [PATCH v2 3/3] Makefile: Optionally specify latest privileged specification
In-Reply-To: <cover.1669518264.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com> <cover.1669518264.git.research_trasio@irq.a4lg.com>
Message-ID: <00e8722474dfabc5cd6cebcf902868be98a0c43a.1669518264.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

Although that OpenSBI can be compiled with compiler with the privileged
architecture version 1.11, it partially uses CSRs from the latest
privileged specification, version 1.12.

To enable fully-featured disassembling (through ELF attributes), this commit
queries whether the assembler supports -mpriv-spec=1.12 and adds
"-Wa,-mpriv-spec=1.12" to CFLAGS and ASFLAGS when supported.
---
 Makefile | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Makefile b/Makefile
index d8b85f0497aa..62162486d340 100644
--- a/Makefile
+++ b/Makefile
@@ -164,6 +164,9 @@ else
 USE_LD_FLAG	=	-fuse-ld=bfd
 endif
 
+# Setup privileged architecture
+OPENSBI_PRIV_SPEC = 1.12
+
 # Check whether the linker supports creating PIEs
 OPENSBI_LD_PIE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) $(USE_LD_FLAG) -fPIE -nostdlib -Wl,-pie -x c /dev/null -o /dev/null >/dev/null 2>&1 && echo y || echo n)
 
@@ -173,6 +176,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
 # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
 CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
 
+# Check whether the assembler and the compiler support the privileged architecture option (used by OpenSBI)
+CC_SUPPORT_PRIV_SPEC_LATEST := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC) -x c -c /dev/null -o /dev/null >/dev/null 2>&1 && echo y || echo n)
+
 # Check whether the assembler support the H extension with .option arch,+h
 AS_SUPPORT_H_EXT_BY_OPTION_ARCH := $(shell echo ".option arch,+h" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null 2>&1 | grep -i "warning:.*option" > /dev/null && echo n || echo y)
 
@@ -352,6 +358,9 @@ CFLAGS		+=	-mno-save-restore
 endif
 CFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 CFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
+ifeq ($(CC_SUPPORT_PRIV_SPEC_LATEST),y)
+CFLAGS		+=	-Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC)
+endif
 CFLAGS		+=	$(RELAX_FLAG)
 CFLAGS		+=	$(GENFLAGS)
 CFLAGS		+=	$(platform-cflags-y)
@@ -370,6 +379,9 @@ ASFLAGS		+=	-mno-save-restore
 endif
 ASFLAGS		+=	-mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA)
 ASFLAGS		+=	-mcmodel=$(PLATFORM_RISCV_CODE_MODEL)
+ifeq ($(CC_SUPPORT_PRIV_SPEC_LATEST),y)
+ASFLAGS		+=	-Wa,-mpriv-spec=$(OPENSBI_PRIV_SPEC)
+endif
 ASFLAGS		+=	$(RELAX_FLAG)
 ifneq ($(CC_IS_CLANG),y)
 ifneq ($(RELAX_FLAG),)
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 19:46:42 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 03:46:42 +0000
Subject: [RFC PATCH] lib: sbi: Disambiguation between ISA and misa register
Message-ID: <ed69e83978817232e2bf966817818bf190bfcc1d.1669520736.git.research_trasio@irq.a4lg.com>

From: Tsukasa OI <research_trasio at irq.a4lg.com>

This commit makes disambiguation between named base ISA (and extensions
implemented) and contents of "misa" CSR (ISA, some major extensions and
implemented privilege modes).

For instance, 'S' and 'U' are valid bits in the "misa" CSR (denoting
existence of supervisor mode and user mode, respectively) but not valid
extensions.

The author proposes calling "Boot HART Base ISA" something else.

Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
---
 lib/sbi/sbi_init.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e592742..fc00cd81f6ef 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -146,7 +146,7 @@ static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
 	sbi_hart_get_priv_version_str(scratch, str, sizeof(str));
 	sbi_printf("Boot HART Priv Version    : %s\n", str);
 	misa_string(xlen, str, sizeof(str));
-	sbi_printf("Boot HART Base ISA        : %s\n", str);
+	sbi_printf("Boot HART MISA Register   : %s\n", str);
 	sbi_hart_get_extensions_str(scratch, str, sizeof(str));
 	sbi_printf("Boot HART ISA Extensions  : %s\n", str);
 	sbi_printf("Boot HART PMP Count       : %d\n",

base-commit: 1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e
-- 
2.38.1



From research_trasio at irq.a4lg.com  Sat Nov 26 20:25:38 2022
From: research_trasio at irq.a4lg.com (Tsukasa OI)
Date: Sun, 27 Nov 2022 13:25:38 +0900
Subject: [RFC PATCH] lib: sbi: Disambiguation between ISA and misa
 register
In-Reply-To: <ed69e83978817232e2bf966817818bf190bfcc1d.1669520736.git.research_trasio@irq.a4lg.com>
References: <ed69e83978817232e2bf966817818bf190bfcc1d.1669520736.git.research_trasio@irq.a4lg.com>
Message-ID: <ee1b0049-a2ce-2b87-727d-acbc7c99d592@irq.a4lg.com>

I'm withdrawing this because I missed one important commit:
5a6be99cc53b "lib: sbi: Remove 's' and 'u' from misa_string() output"

My original proposal (the first version) was made long before this
commit is merged (Nov 2021) and I didn't notice this when submitting this.

With this removal of 'S' and 'U', (although it wouldn't be always good)
we don't need to worry about mixing "misa" and Base ISA since we don't
have "Base ISA" invalid as an ISA string.

Thanks,
Tsukasa

On 2022/11/27 12:46, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio at irq.a4lg.com>
> 
> This commit makes disambiguation between named base ISA (and extensions
> implemented) and contents of "misa" CSR (ISA, some major extensions and
> implemented privilege modes).
> 
> For instance, 'S' and 'U' are valid bits in the "misa" CSR (denoting
> existence of supervisor mode and user mode, respectively) but not valid
> extensions.
> 
> The author proposes calling "Boot HART Base ISA" something else.
> 
> Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
> ---
>  lib/sbi/sbi_init.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e592742..fc00cd81f6ef 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -146,7 +146,7 @@ static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
>  	sbi_hart_get_priv_version_str(scratch, str, sizeof(str));
>  	sbi_printf("Boot HART Priv Version    : %s\n", str);
>  	misa_string(xlen, str, sizeof(str));
> -	sbi_printf("Boot HART Base ISA        : %s\n", str);
> +	sbi_printf("Boot HART MISA Register   : %s\n", str);
>  	sbi_hart_get_extensions_str(scratch, str, sizeof(str));
>  	sbi_printf("Boot HART ISA Extensions  : %s\n", str);
>  	sbi_printf("Boot HART PMP Count       : %d\n",
> 
> base-commit: 1b0d71bb9ff9180c4ae0026de5f4a92a88f1884e


From peterlin at andestech.com  Sun Nov 27 23:50:22 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 07:50:22 +0000
Subject: [PATCH 1/5] lib: simplify fdt_parse_plmt_node()
In-Reply-To: <20221125140827.47018-2-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
 <20221125140827.47018-2-heinrich.schuchardt@canonical.com>
Message-ID: <Y4RoPh9nle+sLOmY@APC323>

On Fri, Nov 25, 2022 at 03:08:23PM +0100, Heinrich Schuchardt wrote:
> We should not check !plmt_base || !plmt_size twice.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.
Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>

> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 89b8bba..dbd7484 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -814,7 +814,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
>  
>  	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
>  				    &reg_addr, &reg_size);
> -	if (rc < 0 || !plmt_base || !plmt_size)
> +	if (rc < 0)
>  		return SBI_ENODEV;
>  	*plmt_base = reg_addr;
>  	*plmt_size = reg_size;
> -- 
> 2.37.2


From peterlin at andestech.com  Mon Nov 28 00:05:27 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 08:05:27 +0000
Subject: [PATCH 2/5] lib: simplify fdt_parse_plicsw_node()
In-Reply-To: <20221125140827.47018-3-heinrich.schuchardt@canonical.com>
References: <20221125140827.47018-1-heinrich.schuchardt@canonical.com>
 <20221125140827.47018-3-heinrich.schuchardt@canonical.com>
Message-ID: <Y4RrxzbdtVvmxzao@APC323>

On Fri, Nov 25, 2022 at 03:08:24PM +0100, Heinrich Schuchardt wrote:
> We should not check !plicsw_base || !size twice.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me
Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>

> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index dbd7484..57c0248 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -868,7 +868,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
>  
>  	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
>  				    &reg_addr, &reg_size);
> -	if (rc < 0 || !plicsw_base || !size)
> +	if (rc < 0)
>  		return SBI_ENODEV;
>  	*plicsw_base = reg_addr;
>  	*size = reg_size;
> -- 
> 2.37.2
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From peterlin at andestech.com  Mon Nov 28 00:20:23 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 08:20:23 +0000
Subject: [PATCH] platform: andes/ae350: Avoid repeated inclusion of
 header files
In-Reply-To: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>
References: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>
Message-ID: <Y4RvR2ui4Lh2zDqe@APC323>

On Wed, Nov 16, 2022 at 03:27:16PM +0800, zhangleizheng at eswincomputing.com wrote:
> From: zhangleizheng <zhangleizheng at eswincomputing.com>
> 
> Avoid cache.h reuse when compiling.
> 
> Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>

Looks good to me,
Thanks.

Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>

> ---
>  platform/andes/ae350/cache.h | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
> index e1c1826..8e00a1d 100644
> --- a/platform/andes/ae350/cache.h
> +++ b/platform/andes/ae350/cache.h
> @@ -7,6 +7,9 @@
>   *   Nylon Chen <nylon7 at andestech.com>
>   */
>  
> +#ifndef _AE350_CACHE_H_
> +#define _AE350_CACHE_H_
> +
>  uintptr_t mcall_set_mcache_ctl(unsigned long input);
>  uintptr_t mcall_set_mmisc_ctl(unsigned long input);
>  uintptr_t mcall_icache_op(unsigned int enable);
> @@ -15,3 +18,5 @@ uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
>  uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
>  uintptr_t mcall_non_blocking_load_store(unsigned long enable);
>  uintptr_t mcall_write_around(unsigned long enable);
> +
> +#endif /* _AE350_CACHE_H_ */
> -- 
> 2.17.1
> 


From peterlin at andestech.com  Mon Nov 28 01:23:04 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 09:23:04 +0000
Subject: [PATCH v2 5/7] platform: Add Renesas RZ/Five initial support
In-Reply-To: <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <Y4R9+NxyafIbka8Q@APC323>

Hi Prabhakar,

> > The fact that you have to compile ae350/cache.c as part of this platform
> > shows we need to improve code re-use.
> >
> > Further, the platform.c added by this patch is very similar to platform.c
> > of andes/ae350. Both platform.c files are subset of what is already there
> > in generic/platform.c.
> >
> > I suggest you do the following:
> > 1) Move andes/ae350 as a platform override under generic/platform/andes/ae350
> > 2) Add rzfive as platform override under generic/platform/renesas/rzfive
> > 3) The common Andes cache operations will be a library under
> >     generic/platform/andes/ae350 which can be selected by renesas/rzfive
> > 4) The common Andes header can be under generic/include/andes/ae350
> > 5) Enable drivers required by andes/ae350 and renesas/rzfive platform
> >     overrides in generic/configs/defconfig
> >
> - The reason for not using generic is because the FW_TEXT_START is different.
> -  I came across the thread where because the generic FW uses FW_PIC
> it doesn matter about the FW_TEXT_START, is this correct?

We will use generic platform as Anup suggested. I'll send our patch soon.
When FW_PIC=y (default), set CONFIG_SPL_OPENSBI_LOAD_ADDR to 0x44000000
in U-boot should be able to run OpenSBI.

> -  Moving forward I built rz/five as part of generic override successfully
> - But when I try and build the u-boot with fw_dynamic.bin I get the
> below errors:
>   - Image 'main-section' is missing external blobs and is
> non-functional: opensbi
>   - Image 'main-section' has faked external blobs and is
> non-functional: fw_dynamic.bin
> - Ignoring the warning and still flashing the image I dont get any
> output from opensbi.

The error message looks like the fw_dynamic.bin is not copied to top
directory of U-boot, so a dummy one is created.
The load/entry addresses and binary of OpenSBI can be observed by using
`dtc u-boot.itb`.

> Am I missing something here?
> 
> Cheers,
> Prabhakar
>

Best regards,
Peter Lin


From anup at brainfault.org  Sun Nov 27 19:37:51 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 28 Nov 2022 09:07:51 +0530
Subject: [PATCH v2 5/7] platform: Add Renesas RZ/Five initial support
In-Reply-To: <Y4R9+NxyafIbka8Q@APC323>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-6-prabhakar.mahadev-lad.rj@bp.renesas.com> <Y4R9+NxyafIbka8Q@APC323>
Message-ID: <CAAhSdy1zqjGv=cvLOkiaFz9gGzKBWCGPHdPwP8WTP0tv1N+=0Q@mail.gmail.com>

On Mon, Nov 28, 2022 at 6:56 AM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> Hi Prabhakar,
>
> > > The fact that you have to compile ae350/cache.c as part of this platform
> > > shows we need to improve code re-use.
> > >
> > > Further, the platform.c added by this patch is very similar to platform.c
> > > of andes/ae350. Both platform.c files are subset of what is already there
> > > in generic/platform.c.
> > >
> > > I suggest you do the following:
> > > 1) Move andes/ae350 as a platform override under generic/platform/andes/ae350
> > > 2) Add rzfive as platform override under generic/platform/renesas/rzfive
> > > 3) The common Andes cache operations will be a library under
> > >     generic/platform/andes/ae350 which can be selected by renesas/rzfive
> > > 4) The common Andes header can be under generic/include/andes/ae350
> > > 5) Enable drivers required by andes/ae350 and renesas/rzfive platform
> > >     overrides in generic/configs/defconfig
> > >
> > - The reason for not using generic is because the FW_TEXT_START is different.
> > -  I came across the thread where because the generic FW uses FW_PIC
> > it doesn matter about the FW_TEXT_START, is this correct?
>
> We will use generic platform as Anup suggested. I'll send our patch soon.
> When FW_PIC=y (default), set CONFIG_SPL_OPENSBI_LOAD_ADDR to 0x44000000
> in U-boot should be able to run OpenSBI.

Thanks for taking this up.

Please keep in mind that OpenSBI v1.2 release will be towards the end
of Dec 2022. It will be nice to support both andes/ae350 and RZ/Five
in this upcoming release.

>
> > -  Moving forward I built rz/five as part of generic override successfully
> > - But when I try and build the u-boot with fw_dynamic.bin I get the
> > below errors:
> >   - Image 'main-section' is missing external blobs and is
> > non-functional: opensbi
> >   - Image 'main-section' has faked external blobs and is
> > non-functional: fw_dynamic.bin
> > - Ignoring the warning and still flashing the image I dont get any
> > output from opensbi.
>
> The error message looks like the fw_dynamic.bin is not copied to top
> directory of U-boot, so a dummy one is created.
> The load/entry addresses and binary of OpenSBI can be observed by using
> `dtc u-boot.itb`.
>
> > Am I missing something here?
> >
> > Cheers,
> > Prabhakar
> >
>
> Best regards,
> Peter Lin

Regards,
Anup


From peterlin at andestech.com  Mon Nov 28 00:30:42 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:30:42 +0800
Subject: [PATCH 0/4] Enable generic platform support for AE350
Message-ID: <20221128083046.6799-1-peterlin@andestech.com>

The fdt drivers used by AE350 are provided, we can now use generic
platform sharing with other vendors and remove the duplicate code.
This patchset also updates the documentation of AE350.

Yu Chien Peter Lin (4):
  platform: generic/andes: Enable generic platform support for AE350
  docs: platform: Update AE350 and generic platform documentation
  docs: andes-ae350.md: fix watchdog nodename in dts example
  scripts/create-binary-archive.sh: remove andes/ae350 build directory

 docs/platform/andes-ae350.md           |   7 +-
 docs/platform/generic.md               |   2 +
 platform/andes/ae350/Kconfig           |  34 -----
 platform/andes/ae350/cache.c           |  89 -------------
 platform/andes/ae350/cache.h           |  17 ---
 platform/andes/ae350/configs/defconfig |   0
 platform/andes/ae350/objects.mk        |  40 ------
 platform/andes/ae350/platform.c        | 169 -------------------------
 platform/andes/ae350/platform.h        | 109 ----------------
 platform/generic/Kconfig               |   4 +
 platform/generic/andes/ae350.c         |  21 +++
 platform/generic/andes/objects.mk      |   6 +
 platform/generic/configs/defconfig     |   4 +
 scripts/create-binary-archive.sh       |   1 -
 14 files changed, 41 insertions(+), 462 deletions(-)
 delete mode 100644 platform/andes/ae350/Kconfig
 delete mode 100644 platform/andes/ae350/cache.c
 delete mode 100644 platform/andes/ae350/cache.h
 delete mode 100644 platform/andes/ae350/configs/defconfig
 delete mode 100644 platform/andes/ae350/objects.mk
 delete mode 100644 platform/andes/ae350/platform.c
 delete mode 100644 platform/andes/ae350/platform.h
 create mode 100644 platform/generic/andes/ae350.c
 create mode 100644 platform/generic/andes/objects.mk

-- 
2.34.1



From peterlin at andestech.com  Mon Nov 28 00:30:43 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:30:43 +0800
Subject: [PATCH 1/4] platform: generic/andes: Enable generic platform support for AE350
In-Reply-To: <20221128083046.6799-1-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
Message-ID: <20221128083046.6799-2-peterlin@andestech.com>

We move andes directory to platform/generic since the necessary fdt
drivers are available, the users can enable the console, timer, ipi,
irqchip and reset devices by adding device tree nodes stated in the
docs/platform/andes-ae350.md.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
Although generic/platform.c has been able to boot the system
on AE350, we will add HSM device for it soon so let's keep
ae350.c as a placeholder.
---
 platform/andes/ae350/Kconfig           |  34 -----
 platform/andes/ae350/cache.c           |  89 -------------
 platform/andes/ae350/cache.h           |  17 ---
 platform/andes/ae350/configs/defconfig |   0
 platform/andes/ae350/objects.mk        |  40 ------
 platform/andes/ae350/platform.c        | 169 -------------------------
 platform/andes/ae350/platform.h        | 109 ----------------
 platform/generic/Kconfig               |   4 +
 platform/generic/andes/ae350.c         |  21 +++
 platform/generic/andes/objects.mk      |   6 +
 platform/generic/configs/defconfig     |   4 +
 11 files changed, 35 insertions(+), 458 deletions(-)
 delete mode 100644 platform/andes/ae350/Kconfig
 delete mode 100644 platform/andes/ae350/cache.c
 delete mode 100644 platform/andes/ae350/cache.h
 delete mode 100644 platform/andes/ae350/configs/defconfig
 delete mode 100644 platform/andes/ae350/objects.mk
 delete mode 100644 platform/andes/ae350/platform.c
 delete mode 100644 platform/andes/ae350/platform.h
 create mode 100644 platform/generic/andes/ae350.c
 create mode 100644 platform/generic/andes/objects.mk

diff --git a/platform/andes/ae350/Kconfig b/platform/andes/ae350/Kconfig
deleted file mode 100644
index 38e4001..0000000
--- a/platform/andes/ae350/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-config PLATFORM_ANDES_AE350
-	bool
-	select FDT
-	select FDT_SERIAL
-	select FDT_SERIAL_UART8250
-	select FDT_TIMER
-	select FDT_TIMER_PLMT
-	select FDT_RESET
-	select FDT_RESET_ATCWDT200
-	select FDT_IRQCHIP
-	select FDT_IRQCHIP_PLIC
-	select FDT_IPI
-	select FDT_IPI_PLICSW
-	default y
-
-if PLATFORM_ANDES_AE350
-
-config PLATFORM_ANDES_AE350_NAME
-	string "Platform default name"
-	default "Andes AE350"
-
-config PLATFORM_ANDES_AE350_MAJOR_VER
-	int "Platform major version"
-	range 0 65535
-	default 0
-
-config PLATFORM_ANDES_AE350_MINOR_VER
-	int "Platform minor version"
-	range 0 65535
-	default 1
-
-endif
diff --git a/platform/andes/ae350/cache.c b/platform/andes/ae350/cache.c
deleted file mode 100644
index af724c5..0000000
--- a/platform/andes/ae350/cache.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Andes Technology Corporation
- *
- * Authors:
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_io.h>
-#include <sbi/sbi_types.h>
-#include "platform.h"
-
-uintptr_t mcall_set_mcache_ctl(unsigned long input)
-{
-	csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
-	csr_write(CSR_MCACHECTL, input);
-	return 0;
-}
-
-uintptr_t mcall_set_mmisc_ctl(unsigned long input)
-{
-	csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
-	csr_write(CSR_MMISCCTL, input);
-	return 0;
-}
-
-uintptr_t mcall_icache_op(unsigned int enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
-		asm volatile("fence.i\n\t");
-	}
-	return 0;
-}
-
-uintptr_t mcall_dcache_op(unsigned int enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
-		csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
-	}
-	return 0;
-}
-
-uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_non_blocking_load_store(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_write_around(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
-	}
-	return 0;
-}
diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
deleted file mode 100644
index e1c1826..0000000
--- a/platform/andes/ae350/cache.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Andes Technology Corporation
- *
- * Authors:
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-uintptr_t mcall_set_mcache_ctl(unsigned long input);
-uintptr_t mcall_set_mmisc_ctl(unsigned long input);
-uintptr_t mcall_icache_op(unsigned int enable);
-uintptr_t mcall_dcache_op(unsigned int enable);
-uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
-uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
-uintptr_t mcall_non_blocking_load_store(unsigned long enable);
-uintptr_t mcall_write_around(unsigned long enable);
diff --git a/platform/andes/ae350/configs/defconfig b/platform/andes/ae350/configs/defconfig
deleted file mode 100644
index e69de29..0000000
diff --git a/platform/andes/ae350/objects.mk b/platform/andes/ae350/objects.mk
deleted file mode 100644
index a4a2332..0000000
--- a/platform/andes/ae350/objects.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-# Copyright (c) 2019 Andes Technology Corporation
-#
-# Authors:
-#   Zong Li <zong at andestech.com>
-#   Nylon Chen <nylon7 at andestech.com>
-#
-
-# Compiler flags
-platform-cppflags-y =
-platform-cflags-y =
-platform-asflags-y =
-platform-ldflags-y =
-
-# Objects to build
-platform-objs-y += cache.o platform.o
-
-# Blobs to build
-FW_TEXT_START=0x00000000
-
-FW_DYNAMIC=y
-
-FW_JUMP=y
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
-  FW_JUMP_ADDR=0x400000
-else
-  FW_JUMP_ADDR=0x200000
-endif
-FW_JUMP_FDT_ADDR=0x2000000
-
-FW_PAYLOAD=y
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
-  FW_PAYLOAD_OFFSET=0x400000
-else
-  FW_PAYLOAD_OFFSET=0x200000
-endif
-
-FW_PAYLOAD_FDT_ADDR=0x2000000
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c
deleted file mode 100644
index d36d11e..0000000
--- a/platform/andes/ae350/platform.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong at andestech.com>
- *   Nylon Chen <nylon7 at andestech.com>
- *   Yu Chien Peter Lin <peterlin at andestech.com>
- */
-
-#include <libfdt.h>
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_console.h>
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_hartmask.h>
-#include <sbi/sbi_ipi.h>
-#include <sbi/sbi_platform.h>
-#include <sbi/sbi_string.h>
-#include <sbi/sbi_trap.h>
-#include <sbi_utils/fdt/fdt_domain.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/ipi/fdt_ipi.h>
-#include <sbi_utils/irqchip/fdt_irqchip.h>
-#include <sbi_utils/reset/fdt_reset.h>
-#include <sbi_utils/serial/fdt_serial.h>
-#include <sbi_utils/timer/fdt_timer.h>
-#include "platform.h"
-#include "cache.h"
-
-struct sbi_platform platform;
-unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
-				unsigned long arg2, unsigned long arg3,
-				unsigned long arg4)
-{
-	const char *model;
-	void *fdt = (void *)arg1;
-	u32 hartid, hart_count = 0;
-	int rc, root_offset, cpus_offset, cpu_offset, len;
-
-	root_offset = fdt_path_offset(fdt, "/");
-	if (root_offset < 0)
-		goto fail;
-
-	model = fdt_getprop(fdt, root_offset, "model", &len);
-	if (model)
-		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
-
-	cpus_offset = fdt_path_offset(fdt, "/cpus");
-	if (cpus_offset < 0)
-		goto fail;
-
-	fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
-		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-		if (rc)
-			continue;
-
-		if (SBI_HARTMASK_MAX_BITS <= hartid)
-			continue;
-
-		hart_count++;
-	}
-
-	platform.hart_count = hart_count;
-
-	/* Return original FDT pointer */
-	return arg1;
-
-fail:
-	while (1)
-		wfi();
-}
-
-/* Platform final initialization. */
-static int ae350_final_init(bool cold_boot)
-{
-	void *fdt;
-
-	if (!cold_boot)
-		return 0;
-
-	fdt_reset_init();
-
-	fdt = fdt_get_address();
-	fdt_fixups(fdt);
-	fdt_domain_fixup(fdt);
-
-	return 0;
-}
-
-/* Vendor-Specific SBI handler */
-static int ae350_vendor_ext_provider(long extid, long funcid,
-	const struct sbi_trap_regs *regs, unsigned long *out_value,
-	struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-	switch (funcid) {
-	case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
-		*out_value = csr_read(CSR_MCACHECTL);
-		break;
-	case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
-		*out_value = csr_read(CSR_MMISCCTL);
-		break;
-	case SBI_EXT_ANDES_SET_MCACHE_CTL:
-		ret = mcall_set_mcache_ctl(regs->a0);
-		break;
-	case SBI_EXT_ANDES_SET_MMISC_CTL:
-		ret = mcall_set_mmisc_ctl(regs->a0);
-		break;
-	case SBI_EXT_ANDES_ICACHE_OP:
-		ret = mcall_icache_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_DCACHE_OP:
-		ret = mcall_dcache_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
-		ret = mcall_l1_cache_i_prefetch_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
-		ret = mcall_l1_cache_d_prefetch_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
-		ret = mcall_non_blocking_load_store(regs->a0);
-		break;
-	case SBI_EXT_ANDES_WRITE_AROUND:
-		ret = mcall_write_around(regs->a0);
-		break;
-	default:
-		sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
-		asm volatile("ebreak");
-	}
-	return ret;
-}
-
-static int ae350_domains_init(void)
-{
-	return fdt_domains_populate(fdt_get_address());
-}
-
-/* Platform descriptor. */
-const struct sbi_platform_operations platform_ops = {
-	.final_init = ae350_final_init,
-
-	.domains_init = ae350_domains_init,
-
-	.console_init = fdt_serial_init,
-
-	.irqchip_init = fdt_irqchip_init,
-
-	.ipi_init     = fdt_ipi_init,
-
-	.timer_init	   = fdt_timer_init,
-
-	.vendor_ext_provider = ae350_vendor_ext_provider
-};
-
-struct sbi_platform platform = {
-	.opensbi_version = OPENSBI_VERSION,
-	.platform_version =
-		SBI_PLATFORM_VERSION(CONFIG_PLATFORM_ANDES_AE350_MAJOR_VER,
-				     CONFIG_PLATFORM_ANDES_AE350_MINOR_VER),
-	.name = CONFIG_PLATFORM_ANDES_AE350_NAME,
-	.features = SBI_PLATFORM_DEFAULT_FEATURES,
-	.hart_count = SBI_HARTMASK_MAX_BITS,
-	.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
-	.platform_ops_addr = (unsigned long)&platform_ops
-};
diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h
deleted file mode 100644
index 903bef0..0000000
--- a/platform/andes/ae350/platform.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong at andestech.com>
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-#ifndef _AE350_PLATFORM_H_
-#define _AE350_PLATFORM_H_
-
-#define AE350_L2C_ADDR			0xe0500000
-
-/*Memory and Miscellaneous Registers*/
-#define CSR_MILMB		0x7c0
-#define CSR_MDLMB		0x7c1
-#define CSR_MECC_CDOE		0x7c2
-#define CSR_MNVEC		0x7c3
-#define CSR_MPFTCTL		0x7c5
-#define CSR_MCACHECTL		0x7ca
-#define CSR_MCCTLBEGINADDR	0x7cb
-#define CSR_MCCTLCOMMAND	0x7cc
-#define CSR_MCCTLDATA		0x7cc
-#define CSR_SCCTLDATA		0x9cd
-#define CSR_UCCTLBEGINADDR	0x80c
-#define CSR_MMISCCTL		0x7d0
-
-enum sbi_ext_andes_fid {
-	SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
-	SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
-	SBI_EXT_ANDES_SET_MCACHE_CTL,
-	SBI_EXT_ANDES_SET_MMISC_CTL,
-	SBI_EXT_ANDES_ICACHE_OP,
-	SBI_EXT_ANDES_DCACHE_OP,
-	SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
-	SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
-	SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
-	SBI_EXT_ANDES_WRITE_AROUND,
-};
-
-/* nds v5 mmisc_ctl register*/
-#define V5_MMISC_CTL_VEC_PLIC_OFFSET            1
-#define V5_MMISC_CTL_RVCOMPM_OFFSET             2
-#define V5_MMISC_CTL_BRPE_OFFSET                3
-#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET          6
-#define V5_MMISC_CTL_NON_BLOCKING_OFFSET        8
-#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET       9
-#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET       10
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1       13
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2       14
-
-#define V5_MMISC_CTL_VEC_PLIC_EN        (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
-#define V5_MMISC_CTL_RVCOMPM_EN         (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
-#define V5_MMISC_CTL_BRPE_EN            (1UL << V5_MMISC_CTL_BRPE_OFFSET)
-#define V5_MMISC_CTL_MSA_OR_UNA_EN      (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
-#define V5_MMISC_CTL_NON_BLOCKING_EN    (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
-#define V5_MCACHE_CTL_L1I_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_L1D_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_DC_WAROUND_1_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
-#define V5_MCACHE_CTL_DC_WAROUND_2_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
-
-#define V5_MMISC_CTL_MASK  (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
-	| V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
-
-/* nds mcache_ctl register*/
-#define V5_MCACHE_CTL_IC_EN_OFFSET      0
-#define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_IC_ECCEN_OFFSET   2
-#define V5_MCACHE_CTL_DC_ECCEN_OFFSET   4
-#define V5_MCACHE_CTL_IC_RWECC_OFFSET   6
-#define V5_MCACHE_CTL_DC_RWECC_OFFSET   7
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET  8
-
-/*nds cctl command*/
-#define V5_UCCTL_L1D_WBINVAL_ALL 6
-#define V5_UCCTL_L1D_WB_ALL 7
-
-#define V5_MCACHE_CTL_IC_EN     (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN     (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_IC_RWECC  (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_DC_RWECC  (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-
-#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
-	| V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
-	| V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
-	| V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
-	| V5_MCACHE_CTL_DC_WAROUND_2_EN)
-
-#define V5_L2C_CTL_OFFSET           0x8
-#define V5_L2C_CTL_ENABLE_OFFSET    0
-#define V5_L2C_CTL_IPFDPT_OFFSET    3
-#define V5_L2C_CTL_DPFDPT_OFFSET    5
-#define V5_L2C_CTL_TRAMOCTL_OFFSET  8
-#define V5_L2C_CTL_TRAMICTL_OFFSET  10
-#define V5_L2C_CTL_DRAMOCTL_OFFSET  11
-#define V5_L2C_CTL_DRAMICTL_OFFSET  13
-
-#define V5_L2C_CTL_ENABLE_MASK      (1UL << V5_L2C_CTL_ENABLE_OFFSET)
-#define V5_L2C_CTL_IPFDPT_MASK      (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
-#define V5_L2C_CTL_DPFDPT_MASK      (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
-#define V5_L2C_CTL_TRAMOCTL_MASK    (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
-#define V5_L2C_CTL_TRAMICTL_MASK    (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
-#define V5_L2C_CTL_DRAMOCTL_MASK    (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
-#define V5_L2C_CTL_DRAMICTL_MASK    (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
-
-#endif /* _AE350_PLATFORM_H_ */
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 63d1be4..4b5d2cd 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -28,6 +28,10 @@ config PLATFORM_ALLWINNER_D1
 	depends on FDT_IRQCHIP_PLIC
 	default n
 
+config PLATFORM_ANDES_AE350
+	bool "Andes AE350 support"
+	default n
+
 config PLATFORM_SIFIVE_FU540
 	bool "SiFive FU540 support"
 	default n
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
new file mode 100644
index 0000000..cf7f6f2
--- /dev/null
+++ b/platform/generic/andes/ae350.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Andes Technology Corporation
+ *
+ * Authors:
+ *   Yu Chien Peter Lin <peterlin at andestech.com>
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static const struct fdt_match andes_ae350_match[] = {
+	{ .compatible = "andestech,ae350" },
+	{ },
+};
+
+const struct platform_override andes_ae350 = {
+	.match_table = andes_ae350_match,
+};
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
new file mode 100644
index 0000000..dd6408d
--- /dev/null
+++ b/platform/generic/andes/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_ANDES_AE350) += andes_ae350
+platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c95b7fa..2eaeeb7 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -1,4 +1,5 @@
 CONFIG_PLATFORM_ALLWINNER_D1=y
+CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
 CONFIG_FDT_GPIO=y
@@ -7,11 +8,13 @@ CONFIG_FDT_I2C=y
 CONFIG_FDT_I2C_SIFIVE=y
 CONFIG_FDT_IPI=y
 CONFIG_FDT_IPI_MSWI=y
+CONFIG_FDT_IPI_PLICSW=y
 CONFIG_FDT_IRQCHIP=y
 CONFIG_FDT_IRQCHIP_APLIC=y
 CONFIG_FDT_IRQCHIP_IMSIC=y
 CONFIG_FDT_IRQCHIP_PLIC=y
 CONFIG_FDT_RESET=y
+CONFIG_FDT_RESET_ATCWDT200=y
 CONFIG_FDT_RESET_GPIO=y
 CONFIG_FDT_RESET_HTIF=y
 CONFIG_FDT_RESET_SIFIVE_TEST=y
@@ -28,4 +31,5 @@ CONFIG_FDT_SERIAL_UART8250=y
 CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
 CONFIG_FDT_TIMER=y
 CONFIG_FDT_TIMER_MTIMER=y
+CONFIG_FDT_TIMER_PLMT=y
 CONFIG_SERIAL_SEMIHOSTING=y
-- 
2.34.1



From peterlin at andestech.com  Mon Nov 28 00:30:44 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:30:44 +0800
Subject: [PATCH 2/4] docs: platform: Update AE350 and generic platform documentation
In-Reply-To: <20221128083046.6799-1-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
Message-ID: <20221128083046.6799-3-peterlin@andestech.com>

Update compile option and platform compatible string for AE350 and
add it to the generic platform list.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
 docs/platform/andes-ae350.md | 5 +++--
 docs/platform/generic.md     | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
index ec241ec..4739951 100644
--- a/docs/platform/andes-ae350.md
+++ b/docs/platform/andes-ae350.md
@@ -8,7 +8,7 @@ AHB/APB IPs suites a majority embedded systems, and the verified platform serves
 as a starting point to jump start SoC designs.
 
 To build platform specific library and firmwares, provide the
-*PLATFORM=andes/ae350* parameter to the top level make command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -23,13 +23,14 @@ AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5
 **Linux Kernel Payload**
 
 ```
-make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
 ```
 
 DTS Example: (Quad-core AX45MP)
 -------------------------------
 
 ```
+	compatible = "andestech,ae350";
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index 73a8afa..bd3c8ab 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -50,9 +50,11 @@ RISC-V Platforms Using Generic Platform
 * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
 * **Spike** (*[spike.md]*)
 * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
+* **Andes AE350 Platform** (*[andes-ae350.md]*)
 
 [qemu_virt.md]: qemu_virt.md
 [shakti_cclass.md]: shakti_cclass.md
 [sifive_fu540.md]: sifive_fu540.md
 [spike.md]: spike.md
 [thead-c9xx.md]: thead-c9xx.md
+[andes-ae350.md]: andse-ae350.md
-- 
2.34.1



From peterlin at andestech.com  Mon Nov 28 00:30:45 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:30:45 +0800
Subject: [PATCH 3/4] docs: andes-ae350.md: fix watchdog nodename in dts example
In-Reply-To: <20221128083046.6799-1-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
Message-ID: <20221128083046.6799-4-peterlin@andestech.com>

The example should use watchdog as nodename instead of wdt.
This is defined in watchdog common schemas:
https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
 docs/platform/andes-ae350.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
index 4739951..8fc8ec6 100644
--- a/docs/platform/andes-ae350.md
+++ b/docs/platform/andes-ae350.md
@@ -178,7 +178,7 @@ DTS Example: (Quad-core AX45MP)
 			                        &CPU3_intc 7 >;
 		};
 
-		wdt: wdt at f0500000 {
+		wdt: watchdog at f0500000 {
 			compatible = "andestech,atcwdt200";
 			reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
 			interrupts = <3 4>;
-- 
2.34.1



From peterlin at andestech.com  Mon Nov 28 00:30:46 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:30:46 +0800
Subject: [PATCH 4/4] scripts/create-binary-archive.sh: remove andes/ae350 build directory
In-Reply-To: <20221128083046.6799-1-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
Message-ID: <20221128083046.6799-5-peterlin@andestech.com>

The andes-specific files have been moved to generic platform so we
can drop this line.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
 scripts/create-binary-archive.sh | 1 -
 1 file changed, 1 deletion(-)

diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index 261a45a..4dda7b4 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -103,7 +103,6 @@ build_opensbi() {
 		BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
 		BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
 		BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
-		BUILD_PLATFORM_SUBDIR+=("andes/ae350")
 		BUILD_PLATFORM_SUBDIR+=("generic")
 		;;
 	*)
-- 
2.34.1



From peterlin at andestech.com  Mon Nov 28 08:37:41 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 16:37:41 +0000
Subject: [PATCH] platform: andes/ae350: Avoid repeated inclusion of
 header files
In-Reply-To: <Y4RvR2ui4Lh2zDqe@APC323>
References: <20221116072716.1763-1-zhangleizheng@eswincomputing.com>
 <Y4RvR2ui4Lh2zDqe@APC323>
Message-ID: <Y4Tj1Sl5ZM/jPe4m@APC323>

On Mon, Nov 28, 2022 at 08:20:24AM +0000, Yu-Chien Peter Lin wrote:
> On Wed, Nov 16, 2022 at 03:27:16PM +0800, zhangleizheng at eswincomputing.com wrote:
> > From: zhangleizheng <zhangleizheng at eswincomputing.com>
> > 
> > Avoid cache.h reuse when compiling.
> > 
> > Signed-off-by: zhangleizheng <zhangleizheng at eswincomputing.com>
> 
> Looks good to me,
> Thanks.
> 
> Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>

Hi all,

I just removed andes/ae350 folder so let's skip this patch.
Thanks for your fix. 

Best regards,
Peter Lin

> 
> > ---
> >  platform/andes/ae350/cache.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
> > index e1c1826..8e00a1d 100644
> > --- a/platform/andes/ae350/cache.h
> > +++ b/platform/andes/ae350/cache.h
> > @@ -7,6 +7,9 @@
> >   *   Nylon Chen <nylon7 at andestech.com>
> >   */
> >  
> > +#ifndef _AE350_CACHE_H_
> > +#define _AE350_CACHE_H_
> > +
> >  uintptr_t mcall_set_mcache_ctl(unsigned long input);
> >  uintptr_t mcall_set_mmisc_ctl(unsigned long input);
> >  uintptr_t mcall_icache_op(unsigned int enable);
> > @@ -15,3 +18,5 @@ uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
> >  uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
> >  uintptr_t mcall_non_blocking_load_store(unsigned long enable);
> >  uintptr_t mcall_write_around(unsigned long enable);
> > +
> > +#endif /* _AE350_CACHE_H_ */
> > -- 
> > 2.17.1
> > 


From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:16 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:16 +0100
Subject: [PATCH v2 2/6] lib: simplify fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-3-heinrich.schuchardt@canonical.com>

We should not check !plicsw_base || !size twice.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
v2:
	Reviewed-by added
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index dbd7484..87b9fb2 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -868,7 +868,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !plicsw_base || !size)
+	if (rc < 0)
 		return SBI_ENODEV;
 	*plicsw_base = reg_addr;
 	*size = reg_size;
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:17 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:17 +0100
Subject: [PATCH v2 3/6] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-4-heinrich.schuchardt@canonical.com>

cpu_offset, cpu_intc_offset must be int to discover failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().

After determining cpu_offset we have to check this value and not
cpu_intc_offset.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
v2:
	check correct variable
---
 lib/utils/fdt/fdt_helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 87b9fb2..976c96e 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -805,7 +805,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 {
 	const fdt32_t *val;
 	int rc, i, count;
-	uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
+	uint64_t reg_addr, reg_size;
 	u32 phandle, hwirq, hartid, hcount;
 
 	if (nodeoffset < 0 || !fdt || !plmt_base ||
@@ -826,6 +826,8 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 
 	hcount = 0;
 	for (i = 0; i < (count / 2); i++) {
+		int cpu_offset, cpu_intc_offset;
+
 		phandle = fdt32_to_cpu(val[2 * i]);
 		hwirq = fdt32_to_cpu(val[2 * i + 1]);
 
@@ -834,7 +836,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 			continue;
 
 		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
-		if (cpu_intc_offset < 0)
+		if (cpu_offset < 0)
 			continue;
 
 		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:14 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:14 +0100
Subject: [PATCH v2 0/6] lib: fixes for fdt functions
Message-ID: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>

* Use correct type for variables used in error checks
* Check correct variables
* Avoid duplicates checks
* Don't assign values that are never used.

v2:
	check correct variables
	fix fdt_parse_aclint_node() too

Heinrich Schuchardt (6):
  lib: simplify fdt_parse_plmt_node()
  lib: simplify fdt_parse_plicsw_node()
  lib: fix fdt_parse_plmt_node()
  lib: fix fdt_parse_plicsw_node()
  lib: simplify fdt_translate_address()
  lib: fix fdt_parse_aclint_node()

 lib/utils/fdt/fdt_helper.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:15 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:15 +0100
Subject: [PATCH v2 1/6] lib: simplify fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-2-heinrich.schuchardt@canonical.com>

We should not check !plmt_base || !plmt_size twice.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
v2:
	Reviewed-by added
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 89b8bba..dbd7484 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -814,7 +814,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
 
 	rc = fdt_get_node_addr_size(fdt, nodeoffset, 0,
 				    &reg_addr, &reg_size);
-	if (rc < 0 || !plmt_base || !plmt_size)
+	if (rc < 0)
 		return SBI_ENODEV;
 	*plmt_base = reg_addr;
 	*plmt_size = reg_size;
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:18 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:18 +0100
Subject: [PATCH v2 4/6] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-5-heinrich.schuchardt@canonical.com>

cpu_offset and cpu_intc_offset must be int to detect failed invocations of
fdt_node_offset_by_phandle() or fdt_parent_offset().

After determining cpu_offset we have to check this value and not
cpu_intc_offset.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
v2:
	check correct variable
---
 lib/utils/fdt/fdt_helper.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 976c96e..674f17b 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -861,7 +861,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 {
 	const fdt32_t *val;
 	int rc, i, count;
-	uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
+	uint64_t reg_addr, reg_size;
 	u32 phandle, hwirq, hartid, hcount;
 
 	if (nodeoffset < 0 || !fdt || !plicsw_base ||
@@ -882,6 +882,8 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 
 	hcount = 0;
 	for (i = 0; i < (count / 2); i++) {
+		int cpu_offset, cpu_intc_offset;
+
 		phandle = fdt32_to_cpu(val[2 * i]);
 		hwirq = fdt32_to_cpu(val[2 * i + 1]);
 
@@ -890,7 +892,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
 			continue;
 
 		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
-		if (cpu_intc_offset < 0)
+		if (cpu_offset < 0)
 			continue;
 
 		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:20 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:20 +0100
Subject: [PATCH v2 6/6] lib: fix fdt_parse_aclint_node()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-7-heinrich.schuchardt@canonical.com>

After determining cpu_offset we have to check this variable and not
cpu_intc_offset.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
v2:
	new patch
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 43d7857..d4b38dc 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -772,7 +772,7 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
 			continue;
 
 		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
-		if (cpu_intc_offset < 0)
+		if (cpu_offset < 0)
 			continue;
 
 		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Mon Nov 28 01:14:19 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Mon, 28 Nov 2022 10:14:19 +0100
Subject: [PATCH v2 5/6] lib: simplify fdt_translate_address()
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221128091420.30391-6-heinrich.schuchardt@canonical.com>

Don't assign a value to offset which is never used.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
---
v2:
	Reviewed-by added
---
 lib/utils/fdt/fdt_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index 674f17b..43d7857 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -124,7 +124,7 @@ static int fdt_translate_address(void *fdt, uint64_t reg, int parent,
 	int i, rlen;
 	int cell_addr, cell_size;
 	const fdt32_t *ranges;
-	uint64_t offset = 0, caddr = 0, paddr = 0, rsize = 0;
+	uint64_t offset, caddr = 0, paddr = 0, rsize = 0;
 
 	cell_addr = fdt_address_cells(fdt, parent);
 	if (cell_addr < 1)
-- 
2.37.2



From prabhakar.csengg at gmail.com  Mon Nov 28 02:34:06 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Mon, 28 Nov 2022 10:34:06 +0000
Subject: [PATCH 1/4] platform: generic/andes: Enable generic platform
 support for AE350
In-Reply-To: <20221128083046.6799-2-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-2-peterlin@andestech.com>
Message-ID: <CA+V-a8urkMz-Fwj9OFLEp2FAYG9_ZpFG9S_QBNK1=zR1g4svFg@mail.gmail.com>

Hi Lin-san,

On Mon, Nov 28, 2022 at 8:32 AM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> We move andes directory to platform/generic since the necessary fdt
> drivers are available, the users can enable the console, timer, ipi,
> irqchip and reset devices by adding device tree nodes stated in the
> docs/platform/andes-ae350.md.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
> Although generic/platform.c has been able to boot the system
> on AE350, we will add HSM device for it soon so let's keep
> ae350.c as a placeholder.
> ---
>  platform/andes/ae350/Kconfig           |  34 -----
>  platform/andes/ae350/cache.c           |  89 -------------
>  platform/andes/ae350/cache.h           |  17 ---
>  platform/andes/ae350/configs/defconfig |   0
>  platform/andes/ae350/objects.mk        |  40 ------
>  platform/andes/ae350/platform.c        | 169 -------------------------
>  platform/andes/ae350/platform.h        | 109 ----------------
>  platform/generic/Kconfig               |   4 +
>  platform/generic/andes/ae350.c         |  21 +++
>  platform/generic/andes/objects.mk      |   6 +
>  platform/generic/configs/defconfig     |   4 +
>  11 files changed, 35 insertions(+), 458 deletions(-)
>  delete mode 100644 platform/andes/ae350/Kconfig
>  delete mode 100644 platform/andes/ae350/cache.c
>  delete mode 100644 platform/andes/ae350/cache.h
You have got rid of cache functions and also the vendor specific EXT
handler, wouldn't that break things?

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Mon Nov 28 04:08:14 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Mon, 28 Nov 2022 12:08:14 +0000
Subject: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC
In-Reply-To: <CAMuHMdWQO_usrJwmVYDx6o-CpzmotVZLt176eKbqLzY-GXiDng@mail.gmail.com>
References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <bf8e33fd-a752-d5d5-859e-14302d069f2d@sholland.org> <CA+V-a8sz4i_wenTyA5tVTVB8dQWLmuXCf3CGYOPC+C07GJ8WTw@mail.gmail.com>
 <CAMuHMdWQO_usrJwmVYDx6o-CpzmotVZLt176eKbqLzY-GXiDng@mail.gmail.com>
Message-ID: <CA+V-a8s5mZoLMhjjpo_89taaBx+M_EwXMZUu-TUpZc8Q3bw4ug@mail.gmail.com>

Hi Geert,

On Sun, Nov 27, 2022 at 9:55 AM Geert Uytterhoeven <geert at linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sat, Nov 26, 2022 at 10:10 PM Lad, Prabhakar
> <prabhakar.csengg at gmail.com> wrote:
> > On Fri, Nov 25, 2022 at 7:43 PM Samuel Holland <samuel at sholland.org> wrote:
> > > On 11/24/22 11:22, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > >
> > > > On the AX45MP core, cache coherency is a specification option so it may
> > > > not be supported. In this case DMA will fail. As a workaround, firstly we
> > > > allocate a global dma coherent pool from which DMA allocations are taken
> > > > and marked as non-cacheable + bufferable using the PMA region as specified
> > > > in the device tree. Synchronization callbacks are implemented to
> > > > synchronize when doing DMA transactions.
> > > >
> > > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
> > > > block that allows dynamic adjustment of memory attributes in the runtime.
> > > > It contains a configurable amount of PMA entries implemented as CSR
> > > > registers to control the attributes of memory locations in interest.
> > > >
> > > > Below are the memory attributes supported:
> > > > * Device, Non-bufferable
> > > > * Device, bufferable
> > > > * Memory, Non-cacheable, Non-bufferable
> > > > * Memory, Non-cacheable, Bufferable
> > > > * Memory, Write-back, No-allocate
> > > > * Memory, Write-back, Read-allocate
> > > > * Memory, Write-back, Write-allocate
> > > > * Memory, Write-back, Read and Write-allocate
> > > >
> > > > This patch adds support to configure the memory attributes of the memory
> > > > regions as passed from the l2 cache node and exposes the cache management
> > > > ops.
> > >
> > > Forgive my ignorance, but why do you need both a DMA pool and explicit
> > > cache maintenance? Wouldn't the purpose of marking a memory region as
> > > permanently non-cacheable be to avoid cache maintenance? And likewise,
> > > if you are doing cache maintenance anyway, why does it matter if/how the
> > > memory is cacheable?
> > >
> > "Memory, Non-cacheable, Bufferable" raises an AXI signal for
> > transactions hence needing SW implementation for cache maintenance.
> >
> > > > More info about PMA (section 10.3):
> > > > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> > > > +static int ax45mp_configure_pma_regions(struct device_node *np)
> > > > +{
> > > > +     const char *propname = "andestech,pma-regions";
> > > > +     u32 start, size, flags;
> > > > +     unsigned int entry_id;
> > > > +     unsigned int i;
> > > > +     int count;
> > > > +     int ret;
> > > > +
> > > > +     count = of_property_count_elems_of_size(np, propname, sizeof(u32) * 3);
> > > > +     if (count < 0)
> > > > +             return count;
> > > > +
> > > > +     if (count > AX45MP_MAX_PMA_REGIONS)
> > > > +             return -EINVAL;
> > > > +
> > > > +     for (i = 0, entry_id = 0 ; entry_id < count ; i += 3, entry_id++) {
> > > > +             of_property_read_u32_index(np, propname, i, &start);
> > > > +             of_property_read_u32_index(np, propname, i + 1, &size);
> > > > +             of_property_read_u32_index(np, propname, i + 2, &flags);
> > > > +             ret = ax45mp_sbi_set_pma(start, size, flags, entry_id);
> > > > +             if (!ret)
> > > > +                     pr_err("Failed to setup PMA region 0x%x - 0x%x flags: 0x%x",
> > > > +                            start, start + size, flags);
> > > > +     }
> > > > +
> > > > +     return 0;
> > > > +}
> > >
> > > If firmware support is required to set up these PMA regions, why is
> > > Linux doing this at all? The firmware has access to the devicetree as
> > > well. It can set this up before entering S-mode, and then you don't need
> > > to expose this capability via an SBI extension. In fact, firmware could
> > > generate the reserved-memory node based on these regions at runtime (or
> > > vice versa).
> > >
> > That's a good point. I'll do some research on this and get back.
> >
> > Btw are there any existing examples where the firmware adds DT nodes?
>
> /memory, reserved-memory, optee on ARM, RPC status on R-Car Gen3/4, ...
>
On the TF-A we pass the FDT blob to u-boot and this does the magic.

On the RISC-V what would be the correct approach?
- We setup the PMA regions in OpenSBI
- We provide a vendor specific EXT to check if the PMA is setup
- In u-boot ft_board_setup() callback add the reserved-memory node

Does the above approach sound good or is there a better approach I'm missing?

Cheers,
Prabhakar


From peterlin at andestech.com  Mon Nov 28 12:28:42 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 28 Nov 2022 20:28:42 +0000
Subject: [PATCH 1/4] platform: generic/andes: Enable generic platform
 support for AE350
In-Reply-To: <CA+V-a8urkMz-Fwj9OFLEp2FAYG9_ZpFG9S_QBNK1=zR1g4svFg@mail.gmail.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
 <20221128083046.6799-2-peterlin@andestech.com>
 <CA+V-a8urkMz-Fwj9OFLEp2FAYG9_ZpFG9S_QBNK1=zR1g4svFg@mail.gmail.com>
Message-ID: <Y4UZ+rcUBTUG152q@APC323>

On Mon, Nov 28, 2022 at 10:34:06AM +0000, Lad, Prabhakar wrote:
> Hi Lin-san,
> 
> On Mon, Nov 28, 2022 at 8:32 AM Yu Chien Peter Lin
> <peterlin at andestech.com> wrote:
> >
> > We move andes directory to platform/generic since the necessary fdt
> > drivers are available, the users can enable the console, timer, ipi,
> > irqchip and reset devices by adding device tree nodes stated in the
> > docs/platform/andes-ae350.md.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> > ---
> > Although generic/platform.c has been able to boot the system
> > on AE350, we will add HSM device for it soon so let's keep
> > ae350.c as a placeholder.
> > ---
> >  platform/andes/ae350/Kconfig           |  34 -----
> >  platform/andes/ae350/cache.c           |  89 -------------
> >  platform/andes/ae350/cache.h           |  17 ---
> >  platform/andes/ae350/configs/defconfig |   0
> >  platform/andes/ae350/objects.mk        |  40 ------
> >  platform/andes/ae350/platform.c        | 169 -------------------------
> >  platform/andes/ae350/platform.h        | 109 ----------------
> >  platform/generic/Kconfig               |   4 +
> >  platform/generic/andes/ae350.c         |  21 +++
> >  platform/generic/andes/objects.mk      |   6 +
> >  platform/generic/configs/defconfig     |   4 +
> >  11 files changed, 35 insertions(+), 458 deletions(-)
> >  delete mode 100644 platform/andes/ae350/Kconfig
> >  delete mode 100644 platform/andes/ae350/cache.c
> >  delete mode 100644 platform/andes/ae350/cache.h
> You have got rid of cache functions and also the vendor specific EXT
> handler, wouldn't that break things?

Hi Prabhakar,

I want to take this opportunity to drop unnecessary functions, most of
the andes SBI calls were experimental/debugging features in kernel that
won't affact the boot flow.

You can still keep them in generic/renesas/rzfive.c. The renesas vendor
SBI call fid does not need to be the same as ours.

As for common Andes CSR which you separated into andes/ae350/common-platform.h
can be moved to generic/include/andes45.h.

Best regards,
Peter Lin

> Cheers,
> Prabhakar


From wxjstz at 126.com  Mon Nov 28 04:53:04 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:53:04 +0800
Subject: [PATCH v2 4/6] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
Message-ID: <895183657835d6cf62bac0075f10d59ad0a4517d.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> cpu_offset and cpu_intc_offset must be int to detect failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????check correct variable
> ---
> ?lib/utils/fdt/fdt_helper.c | 6 ++++--
> ?1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 976c96e..674f17b 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -861,7 +861,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plicsw_base ||
> @@ -882,6 +882,8 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> @@ -890,7 +892,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);




From wxjstz at 126.com  Mon Nov 28 04:53:27 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:53:27 +0800
Subject: [PATCH v2 4/6] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
Message-ID: <47756b1028503c2940eeed060cb1d2c12313d2cf.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> cpu_offset and cpu_intc_offset must be int to detect failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????check correct variable
> ---
> ?lib/utils/fdt/fdt_helper.c | 6 ++++--
> ?1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 976c96e..674f17b 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -861,7 +861,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plicsw_base ||
> @@ -882,6 +882,8 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> @@ -890,7 +892,7 @@ int fdt_parse_plicsw_node(void *fdt, int nodeoffset, unsigned long *plicsw_base,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Mon Nov 28 04:52:14 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:52:14 +0800
Subject: [PATCH v2 3/6] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
Message-ID: <29fdc1fc5a5bf663ba7daa95757b2afbb71ab39d.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> cpu_offset, cpu_intc_offset must be int to discover failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????check correct variable
> ---
> ?lib/utils/fdt/fdt_helper.c | 6 ++++--
> ?1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 87b9fb2..976c96e 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -805,7 +805,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plmt_base ||
> @@ -826,6 +826,8 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> @@ -834,7 +836,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);




From wxjstz at 126.com  Mon Nov 28 04:54:21 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:54:21 +0800
Subject: [PATCH v2 6/6] lib: fix fdt_parse_aclint_node()
In-Reply-To: <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
Message-ID: <06d32d35d4410554dce99ae0abf8c14b488012ed.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> After determining cpu_offset we have to check this variable and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????new patch
> ---
> ?lib/utils/fdt/fdt_helper.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 43d7857..d4b38dc 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -772,7 +772,7 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);




From wxjstz at 126.com  Mon Nov 28 04:54:37 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:54:37 +0800
Subject: [PATCH v2 6/6] lib: fix fdt_parse_aclint_node()
In-Reply-To: <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
Message-ID: <bc4f35dc30cff77dd9b1a411e5d68a62c74d43c3.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> After determining cpu_offset we have to check this variable and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????new patch
> ---
> ?lib/utils/fdt/fdt_helper.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 43d7857..d4b38dc 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -772,7 +772,7 @@ int fdt_parse_aclint_node(void *fdt, int nodeoffset, bool for_timer,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> -- 
> 2.37.2
> 
> 




From bmeng at tinylab.org  Mon Nov 28 05:21:29 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Mon, 28 Nov 2022 21:21:29 +0800
Subject: [PATCH] lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers
Message-ID: <20221128132129.58558-1-bmeng@tinylab.org>

Interrupt source 0 is reserved. Hence the irq should start from 1.

Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 73d7788..4df9020 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 
 void plic_priority_save(const struct plic_data *plic, u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
-- 
2.34.1



From wxjstz at 126.com  Mon Nov 28 04:52:35 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 28 Nov 2022 20:52:35 +0800
Subject: [PATCH v2 3/6] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
	 <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
Message-ID: <ca27a6535ff9b554ec0327ae2f5029736eda1766.camel@126.com>

? 2022-11-28???? 10:14 +0100?Heinrich Schuchardt???
> cpu_offset, cpu_intc_offset must be int to discover failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????check correct variable
> ---
> ?lib/utils/fdt/fdt_helper.c | 6 ++++--
> ?1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index 87b9fb2..976c96e 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -805,7 +805,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?{
> ????????const fdt32_t *val;
> ????????int rc, i, count;
> -???????uint64_t reg_addr, reg_size, cpu_offset, cpu_intc_offset;
> +???????uint64_t reg_addr, reg_size;
> ????????u32 phandle, hwirq, hartid, hcount;
> ?
> ????????if (nodeoffset < 0 || !fdt || !plmt_base ||
> @@ -826,6 +826,8 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ?
> ????????hcount = 0;
> ????????for (i = 0; i < (count / 2); i++) {
> +???????????????int cpu_offset, cpu_intc_offset;
> +
> ????????????????phandle = fdt32_to_cpu(val[2 * i]);
> ????????????????hwirq = fdt32_to_cpu(val[2 * i + 1]);
> ?
> @@ -834,7 +836,7 @@ int fdt_parse_plmt_node(void *fdt, int nodeoffset, unsigned long *plmt_base,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> -- 
> 2.37.2
> 
> 




From schwab at suse.de  Mon Nov 28 05:36:24 2022
From: schwab at suse.de (Andreas Schwab)
Date: Mon, 28 Nov 2022 14:36:24 +0100
Subject: [PATCH] lib: utils/irqchip: plic: Fix the off-by-one error in
 priority save/restore helpers
In-Reply-To: <20221128132129.58558-1-bmeng@tinylab.org> (Bin Meng's message of
	"Mon, 28 Nov 2022 21:21:29 +0800")
References: <20221128132129.58558-1-bmeng@tinylab.org>
Message-ID: <mvmpmd78alj.fsf@suse.de>

On Nov 28 2022, Bin Meng wrote:

> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 73d7788..4df9020 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>  
>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>  {
> -	for (u32 i = 0; i < plic->num_src; i++)
> +	for (u32 i = 1; i <= plic->num_src; i++)
>  		priority[i] = plic_get_priority(plic, i);

That requires updating the size of the priority array.

-- 
Andreas Schwab, SUSE Labs, schwab at suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."


From bmeng at tinylab.org  Mon Nov 28 05:50:12 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Mon, 28 Nov 2022 13:50:12 +0000
Subject: [PATCH] lib: utils/irqchip: plic: Fix the off-by-one error in priority
 save/restore helpers
In-Reply-To: <mvmpmd78alj.fsf@suse.de>
References: <20221128132129.58558-1-bmeng@tinylab.org> <mvmpmd78alj.fsf@suse.de>
Message-ID: <em4a6d0865-4451-41b3-a618-4040b4134ca2@c060526d.com>

On 2022/11/28 21:36:24, "Andreas Schwab" <schwab at suse.de> wrote:

>On Nov 28 2022, Bin Meng wrote:
>
>>  diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
>>  index 73d7788..4df9020 100644
>>  --- a/lib/utils/irqchip/plic.c
>>  +++ b/lib/utils/irqchip/plic.c
>>  @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>>
>>   void plic_priority_save(const struct plic_data *plic, u8 *priority)
>>   {
>>  -	for (u32 i = 0; i < plic->num_src; i++)
>>  +	for (u32 i = 1; i <= plic->num_src; i++)
>>   		priority[i] = plic_get_priority(plic, i);
>
>That requires updating the size of the priority array.
These 2 APIs are really poorly designed. The index to the priority array 
is controlled by plic->num_src which comes from DTS, so there is 
potentially a mismatch between the DTS property value and the size of 
the priority array.

Currently the only user of these 2 APIs in OpenSBI is D1 and the size of 
the priority array is set to 176. There is no problem if DTS provides a 
less than 176 value. Otherwise it can cause out-of-bound access in 
OpenSBI.

Regards,
Bin


From peterlin at andestech.com  Tue Nov 29 02:42:02 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Tue, 29 Nov 2022 10:42:02 +0000
Subject: [PATCH v2 3/6] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
 <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
Message-ID: <Y4Xh+hoyaEORyc34@APC323>

On Mon, Nov 28, 2022 at 10:14:17AM +0100, Heinrich Schuchardt wrote:
> cpu_offset, cpu_intc_offset must be int to discover failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>



From peterlin at andestech.com  Tue Nov 29 02:44:41 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Tue, 29 Nov 2022 10:44:41 +0000
Subject: [PATCH v2 4/6] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
 <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
Message-ID: <Y4Ximb7MKOP0+5DG@APC323>

On Mon, Nov 28, 2022 at 10:14:18AM +0100, Heinrich Schuchardt wrote:
> cpu_offset and cpu_intc_offset must be int to detect failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
> 
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me

Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>


From zhangdongdong at eswincomputing.com  Mon Nov 28 19:54:06 2022
From: zhangdongdong at eswincomputing.com (Dongdong Zhang)
Date: Tue, 29 Nov 2022 11:54:06 +0800
Subject: [PATCH 0/1] firmware: Minor optimization for relocate
Message-ID: <20221129035407.28946-1-zhangdongdong@eswincomputing.com>

The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end.

This can reduce the operation time of two instructions.

Dongdong Zhang (1):
  firmware: Minor optimization for relocate

 firmware/fw_base.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.1



From zhangdongdong at eswincomputing.com  Mon Nov 28 19:54:07 2022
From: zhangdongdong at eswincomputing.com (Dongdong Zhang)
Date: Tue, 29 Nov 2022 11:54:07 +0800
Subject: [PATCH 1/1] firmware: Minor optimization for relocate
In-Reply-To: <20221129035407.28946-1-zhangdongdong@eswincomputing.com>
References: <20221129035407.28946-1-zhangdongdong@eswincomputing.com>
Message-ID: <20221129035407.28946-2-zhangdongdong@eswincomputing.com>

The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end.

This can reduce the operation time of two instructions.

Signed-off-by: Dongdong Zhang <zhangdongdong at eswincomputing.com>
---
 firmware/fw_base.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index 07be4c4..3f622b3 100644
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -128,9 +128,9 @@ _relocate:
 	REG_L	t1, 0(t1)
 	lla	t2, _load_start
 	REG_L	t2, 0(t2)
+	beq	t0, t2, _relocate_done
 	sub	t3, t1, t0
 	add	t3, t3, t2
-	beq	t0, t2, _relocate_done
 	lla	t4, _relocate_done
 	sub	t4, t4, t2
 	add	t4, t4, t0
-- 
2.17.1



From weiliang.lim at starfivetech.com  Mon Nov 28 21:21:19 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Tue, 29 Nov 2022 13:21:19 +0800
Subject: [PATCH] lib: sbi: Add option to select boot hart
Message-ID: <20221129052119.379830-1-weiliang.lim@starfivetech.com>

In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the preferred boot hart.

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 firmware/objects.mk | 4 ++++
 lib/sbi/sbi_init.c  | 9 ++++++++-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/firmware/objects.mk b/firmware/objects.mk
index a1704c4..2b41718 100644
--- a/firmware/objects.mk
+++ b/firmware/objects.mk
@@ -28,6 +28,10 @@ ifdef FW_TEXT_START
 firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
 endif
 
+ifdef FW_BOOT_HART_ID
+firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
+endif
+
 ifdef FW_FDT_PATH
 firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
 ifdef FW_FDT_PADDING
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index d57efa7..5abfa79 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 			     scratch->next_mode, FALSE);
 }
 
+#ifndef FW_BOOT_HART_ID
 static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
+#endif
 
 /**
  * Initialize OpenSBI library for current HART and jump to next
@@ -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
+	if (next_mode_supported &&
+#ifdef FW_BOOT_HART_ID
+		hartid == FW_BOOT_HART_ID)
+#else
+		atomic_xchg(&coldboot_lottery, 1) == 0)
+#endif
 		coldboot = TRUE;
 
 	/*
-- 
2.25.1



From samuel at sholland.org  Mon Nov 28 21:48:32 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 28 Nov 2022 23:48:32 -0600
Subject: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five
 SoC
In-Reply-To: <CA+V-a8s5mZoLMhjjpo_89taaBx+M_EwXMZUu-TUpZc8Q3bw4ug@mail.gmail.com>
References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <bf8e33fd-a752-d5d5-859e-14302d069f2d@sholland.org>
 <CA+V-a8sz4i_wenTyA5tVTVB8dQWLmuXCf3CGYOPC+C07GJ8WTw@mail.gmail.com>
 <CAMuHMdWQO_usrJwmVYDx6o-CpzmotVZLt176eKbqLzY-GXiDng@mail.gmail.com>
 <CA+V-a8s5mZoLMhjjpo_89taaBx+M_EwXMZUu-TUpZc8Q3bw4ug@mail.gmail.com>
Message-ID: <df0fed9d-6d0a-3e76-1ebf-920e4d19d624@sholland.org>

On 11/28/22 06:08, Lad, Prabhakar wrote:
> Hi Geert,
> 
> On Sun, Nov 27, 2022 at 9:55 AM Geert Uytterhoeven <geert at linux-m68k.org> wrote:
>>
>> Hi Prabhakar,
>>
>> On Sat, Nov 26, 2022 at 10:10 PM Lad, Prabhakar
>> <prabhakar.csengg at gmail.com> wrote:
>>> On Fri, Nov 25, 2022 at 7:43 PM Samuel Holland <samuel at sholland.org> wrote:
>>>> On 11/24/22 11:22, Prabhakar wrote:
>>>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>>>>>
>>>>> On the AX45MP core, cache coherency is a specification option so it may
>>>>> not be supported. In this case DMA will fail. As a workaround, firstly we
>>>>> allocate a global dma coherent pool from which DMA allocations are taken
>>>>> and marked as non-cacheable + bufferable using the PMA region as specified
>>>>> in the device tree. Synchronization callbacks are implemented to
>>>>> synchronize when doing DMA transactions.
>>>>>
>>>>> The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
>>>>> block that allows dynamic adjustment of memory attributes in the runtime.
>>>>> It contains a configurable amount of PMA entries implemented as CSR
>>>>> registers to control the attributes of memory locations in interest.
>>>>>
>>>>> Below are the memory attributes supported:
>>>>> * Device, Non-bufferable
>>>>> * Device, bufferable
>>>>> * Memory, Non-cacheable, Non-bufferable
>>>>> * Memory, Non-cacheable, Bufferable
>>>>> * Memory, Write-back, No-allocate
>>>>> * Memory, Write-back, Read-allocate
>>>>> * Memory, Write-back, Write-allocate
>>>>> * Memory, Write-back, Read and Write-allocate
>>>>>
>>>>> This patch adds support to configure the memory attributes of the memory
>>>>> regions as passed from the l2 cache node and exposes the cache management
>>>>> ops.
>>>>
>>>> Forgive my ignorance, but why do you need both a DMA pool and explicit
>>>> cache maintenance? Wouldn't the purpose of marking a memory region as
>>>> permanently non-cacheable be to avoid cache maintenance? And likewise,
>>>> if you are doing cache maintenance anyway, why does it matter if/how the
>>>> memory is cacheable?
>>>>
>>> "Memory, Non-cacheable, Bufferable" raises an AXI signal for
>>> transactions hence needing SW implementation for cache maintenance.
>>>
>>>>> More info about PMA (section 10.3):
>>>>> Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>>
>>>>> +static int ax45mp_configure_pma_regions(struct device_node *np)
>>>>> +{
>>>>> +     const char *propname = "andestech,pma-regions";
>>>>> +     u32 start, size, flags;
>>>>> +     unsigned int entry_id;
>>>>> +     unsigned int i;
>>>>> +     int count;
>>>>> +     int ret;
>>>>> +
>>>>> +     count = of_property_count_elems_of_size(np, propname, sizeof(u32) * 3);
>>>>> +     if (count < 0)
>>>>> +             return count;
>>>>> +
>>>>> +     if (count > AX45MP_MAX_PMA_REGIONS)
>>>>> +             return -EINVAL;
>>>>> +
>>>>> +     for (i = 0, entry_id = 0 ; entry_id < count ; i += 3, entry_id++) {
>>>>> +             of_property_read_u32_index(np, propname, i, &start);
>>>>> +             of_property_read_u32_index(np, propname, i + 1, &size);
>>>>> +             of_property_read_u32_index(np, propname, i + 2, &flags);
>>>>> +             ret = ax45mp_sbi_set_pma(start, size, flags, entry_id);
>>>>> +             if (!ret)
>>>>> +                     pr_err("Failed to setup PMA region 0x%x - 0x%x flags: 0x%x",
>>>>> +                            start, start + size, flags);
>>>>> +     }
>>>>> +
>>>>> +     return 0;
>>>>> +}
>>>>
>>>> If firmware support is required to set up these PMA regions, why is
>>>> Linux doing this at all? The firmware has access to the devicetree as
>>>> well. It can set this up before entering S-mode, and then you don't need
>>>> to expose this capability via an SBI extension. In fact, firmware could
>>>> generate the reserved-memory node based on these regions at runtime (or
>>>> vice versa).
>>>>
>>> That's a good point. I'll do some research on this and get back.
>>>
>>> Btw are there any existing examples where the firmware adds DT nodes?
>>
>> /memory, reserved-memory, optee on ARM, RPC status on R-Car Gen3/4, ...
>>
> On the TF-A we pass the FDT blob to u-boot and this does the magic.
> 
> On the RISC-V what would be the correct approach?
> - We setup the PMA regions in OpenSBI
> - We provide a vendor specific EXT to check if the PMA is setup
> - In u-boot ft_board_setup() callback add the reserved-memory node
> 
> Does the above approach sound good or is there a better approach I'm missing?

My suggestion was to fix up the DT in OpenSBI itself. See
lib/utils/fdt/fdt_fixup.c in the OpenSBI source tree. There is also a
platform hook for this. Then OpenSBI passes the FDT to U-Boot, and
U-Boot passes it on to Linux. No SBI extension is needed in that case.

If you optionally want your U-Boot to support loading a replacement FDT
from disk, then ft_board_setup() would need to copy the reserved-memory
nodes from U-Boot's control FDT to the loaded FDT. But this logic is the
same for all reserved-memory nodes, including the one OpenSBI adds
already. U-Boot has some code for this copying which you could reuse.

Regards,
Samuel



From bmeng.cn at gmail.com  Mon Nov 28 23:51:33 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 29 Nov 2022 15:51:33 +0800
Subject: [PATCH 1/1] firmware: Minor optimization for relocate
In-Reply-To: <20221129035407.28946-2-zhangdongdong@eswincomputing.com>
References: <20221129035407.28946-1-zhangdongdong@eswincomputing.com> <20221129035407.28946-2-zhangdongdong@eswincomputing.com>
Message-ID: <CAEUhbmUiAn=gqTq1m-A-+9jKZRmCCvRPT=k7QHEA4a293onRpA@mail.gmail.com>

On Tue, Nov 29, 2022 at 11:57 AM Dongdong Zhang
<zhangdongdong at eswincomputing.com> wrote:
>
> The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end.

nits: commit messages should be written like about 70 characters per line.

>
> This can reduce the operation time of two instructions.
>
> Signed-off-by: Dongdong Zhang <zhangdongdong at eswincomputing.com>
> ---
>  firmware/fw_base.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From wxjstz at 126.com  Tue Nov 29 00:16:53 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 29 Nov 2022 16:16:53 +0800
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
Message-ID: <c7969edd4515971647ea85bdc08f4cc9a0f24aac.camel@126.com>

? 2022-11-29???? 13:21 +0800?Wei Liang Lim???
> In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the
> preferred boot hart.
> 
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
> ?firmware/objects.mk | 4 ++++
> ?lib/sbi/sbi_init.c? | 9 ++++++++-
> ?2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/firmware/objects.mk b/firmware/objects.mk
> index a1704c4..2b41718 100644
> --- a/firmware/objects.mk
> +++ b/firmware/objects.mk
> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START
> ?firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
> ?endif
> ?
> +ifdef FW_BOOT_HART_ID
> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> +endif
> +
> ?ifdef FW_FDT_PATH
> ?firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> ?ifdef FW_FDT_PADDING
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index d57efa7..5abfa79 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
> ???????????????????????????? scratch->next_mode, FALSE);
> ?}
> ?
> +#ifndef FW_BOOT_HART_ID
> ?static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> +#endif
> ?
> ?/**
> ? * Initialize OpenSBI library for current HART and jump to next
> @@ -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> ???????? * HARTs which satisfy above condition.
> ???????? */
> ?
> -???????if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> +???????if (next_mode_supported &&
> +#ifdef FW_BOOT_HART_ID
> +???????????????hartid == FW_BOOT_HART_ID)
> +#else
> +???????????????atomic_xchg(&coldboot_lottery, 1) == 0)
> +#endif
Look good to me. I recommend

#ifdef FW_BOOT_HART_ID
               if (next_mode_supported && hartid == FW_BOOT_HART_ID)
#else
               if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
endif

Reviewed-by: Xiang W <wxjstz at 126.com>
> ????????????????coldboot = TRUE;
> ?
> ????????/*
> -- 
> 2.25.1
> 
> 




From zhangdongdong at eswincomputing.com  Tue Nov 29 01:10:31 2022
From: zhangdongdong at eswincomputing.com (Dongdong Zhang)
Date: Tue, 29 Nov 2022 17:10:31 +0800 (GMT+08:00)
Subject: [PATCH 1/1] firmware: Minor optimization for relocate
In-Reply-To: <CAEUhbmUiAn=gqTq1m-A-+9jKZRmCCvRPT=k7QHEA4a293onRpA@mail.gmail.com>
References: <20221129035407.28946-1-zhangdongdong@eswincomputing.com>
 <20221129035407.28946-2-zhangdongdong@eswincomputing.com>
 <CAEUhbmUiAn=gqTq1m-A-+9jKZRmCCvRPT=k7QHEA4a293onRpA@mail.gmail.com>
Message-ID: <3960020f.aa5e.184c2a6f2c1.Coremail.zhangdongdong@eswincomputing.com>

Hi, Bin

Thank you for your review, and I will pay attention to the style of the commit message next time.

> -----????-----???:"Bin Meng" <bmeng.cn at gmail.com>????:2022-11-29 15:51:33 (???)???:"Dongdong Zhang" <zhangdongdong at eswincomputing.com>??:opensbi at lists.infradead.org??:Re: [PATCH 1/1] firmware: Minor optimization for relocate
> 
> On Tue, Nov 29, 2022 at 11:57 AM Dongdong Zhang
> <zhangdongdong at eswincomputing.com> wrote:
> >
> > The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end.
> 
> nits: commit messages should be written like about 70 characters per line.
> 
> >
> > This can reduce the operation time of two instructions.
> >
> > Signed-off-by: Dongdong Zhang <zhangdongdong at eswincomputing.com>
> > ---
> >  firmware/fw_base.S | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> 
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

From prabhakar.csengg at gmail.com  Tue Nov 29 04:13:21 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Tue, 29 Nov 2022 12:13:21 +0000
Subject: [PATCH v2 1/7] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <CAEUhbmV=vg4iap1h9h1Q0Ejvad4e2ZwVETjLqOarc-ajZYjTag@mail.gmail.com>
References: <20221111182105.614094-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221111182105.614094-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmX82_EhkF62GbvYyAsztK1XpJ4XcG+XwzWrQ1gBV2P7QA@mail.gmail.com>
 <CA+V-a8urvQf+53sjSR3kLsyLTZjhhKYJYLshA98Js3PnkDH9uA@mail.gmail.com>
 <CAEUhbmVAtQ+MScY4V6UpjZD+nURCvC7T-2fLC1diz_5GVURsZQ@mail.gmail.com>
 <CA+V-a8sJFTQE4xErgjKhZ_7-U9xMqApei1sR6r5GgtzPKK4Mkw@mail.gmail.com> <CAEUhbmV=vg4iap1h9h1Q0Ejvad4e2ZwVETjLqOarc-ajZYjTag@mail.gmail.com>
Message-ID: <CA+V-a8sjE_pnFncA4o2Fc7B6vEhNbUhFXGzqYxLWeL3wxf=T5A@mail.gmail.com>

Hi Bin,

On Sun, Nov 20, 2022 at 11:59 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> Hi Prabhakar,
>
> On Fri, Nov 18, 2022 at 9:08 PM Lad, Prabhakar
> <prabhakar.csengg at gmail.com> wrote:
> >
> > Hi Bin,
> >
> > On Thu, Nov 17, 2022 at 7:52 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > On Wed, Nov 16, 2022 at 1:34 AM Lad, Prabhakar
> > > <prabhakar.csengg at gmail.com> wrote:
> > > >
> > > > Hi Bin,
<snip>
> > > > > > +static void renesas_scif_putc(char ch)
> > > > > > +{
> > > > > > +       uint16_t reg;
> > > > > > +
> > > > > > +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> > > > > > +               ;
> > > > > > +
> > > > > > +       set_reg(SCIF_REG_FTDR, ch);
> > > > > > +       reg = get_reg(SCIF_REG_FSR);
> > > > > > +       reg &= ~SCIF_FSR_TXD_CHK;
> > > > > > +       set_reg(SCIF_REG_FSR, reg);
> > > > >
> > > > > The FSR Tx status bits clear should happen before writing a new char
> > > > > to the Tx fifo, no?
> > > > >
> > > > No, this has to be cleared only after char write.
> > >
> > > Based on my read of the user manual, after the while () check, we can
> > > clear the status bits. After you write a new char to the FIFO, the
> > > status bits might be triggered by the new char write, instead of the
> > > previous one. Hence clearing status bits after writing char will cause
> > > the status bits check next time fail.
> > >
> > From the HW manual..
> > [Clearing conditions]
> > ? TDFE is cleared to 0 when 0 is written in the TDFE bit after reading TDFE = 1.
> > ? When transmit data is written to the FTDR register
> > ^^ hence its cleared after the write here.
>
> These 2 conditions are OR, not AND, right?
>
> So when the while loop breaks, it satisfies the first condition, and
> we can clear the TDFE bit by writing zero to FSR.
>
> But if you write the tx data to the FTDR register, after you do
>
> set_reg(SCIF_REG_FTDR, ch);
>
> There is a possibility that the TDFE bit is generated before before you do
>
> reg = get_reg(SCIF_REG_FSR);
> reg &= ~SCIF_FSR_TXD_CHK;
> set_reg(SCIF_REG_FSR, reg);
>
> then the TDFE bit gets cleared unexpectedly.
>
> Next time when you want to write another char to the serial port the
> while loop will never break.
>
I altered the code sequence as per your suggestion and haven't seen
any issue with some limited testing.

Here are references [0]/[1] for why the sequence should be as in the
current patch. Looking at [1] I'm not seeing the issue mentioned there
if I re-order the code sequence.
(I am awaiting a response from the HW team yet.)

As the current code sequence has been there in Linux/u-boot ([2]/[3]
and our flashwriter code too) for many years and haven't seen an issue
of infinite looping I would like to stick with the current code
sequence. And if in future if we see any issue we can provide a patch
to fix this.

I hope this is OK with you.

[0] https://pasteboard.co/fXHV51yQD8zU.png
[1] https://patchwork.kernel.org/project/linux-sh/patch/4.2.0.58.J.20090601123439.00b52740 at router.itonet.co.jp/#63581
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/sh-sci.c?h=v6.1-rc7#n698
[3] https://source.denx.de/u-boot/u-boot/-/blob/master/drivers/serial/serial_sh.c#L83

Cheers,
Prabhakar


From jrtc27 at jrtc27.com  Tue Nov 29 08:17:54 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Tue, 29 Nov 2022 16:17:54 +0000
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
Message-ID: <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>

On 29 Nov 2022, at 05:21, Wei Liang Lim <weiliang.lim at starfivetech.com> wrote:
> 
> In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the preferred boot hart.

Why? What?s wrong with the others?

Jess

> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
> firmware/objects.mk | 4 ++++
> lib/sbi/sbi_init.c  | 9 ++++++++-
> 2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/firmware/objects.mk b/firmware/objects.mk
> index a1704c4..2b41718 100644
> --- a/firmware/objects.mk
> +++ b/firmware/objects.mk
> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START
> firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
> endif
> 
> +ifdef FW_BOOT_HART_ID
> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> +endif
> +
> ifdef FW_FDT_PATH
> firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> ifdef FW_FDT_PADDING
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index d57efa7..5abfa79 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
> 			     scratch->next_mode, FALSE);
> }
> 
> +#ifndef FW_BOOT_HART_ID
> static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> +#endif
> 
> /**
>  * Initialize OpenSBI library for current HART and jump to next
> @@ -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> 	 * HARTs which satisfy above condition.
> 	 */
> 
> -	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> +	if (next_mode_supported &&
> +#ifdef FW_BOOT_HART_ID
> +		hartid == FW_BOOT_HART_ID)
> +#else
> +		atomic_xchg(&coldboot_lottery, 1) == 0)
> +#endif
> 		coldboot = TRUE;
> 
> 	/*
> -- 
> 2.25.1
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



From weiliang.lim at starfivetech.com  Tue Nov 29 19:33:30 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Wed, 30 Nov 2022 03:33:30 +0000
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>
Message-ID: <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>

> -----Original Message-----
> From: Jessica Clarke <jrtc27 at jrtc27.com>
> Sent: Wednesday, November 30, 2022 12:18 AM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi at lists.infradead.org; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
> 
> On 29 Nov 2022, at 05:21, Wei Liang Lim <weiliang.lim at starfivetech.com>
> wrote:
> >
> > In certain scenario, user needs to select a particular hart ID as the boot hart.
> This option provide the flexibility for user to select the preferred boot hart.
> 
> Why? What?s wrong with the others?
> 
> Jess
> 
We need this patch for 2 scenarios below:
1) On our architecture, there are some harts supporting MMU sv39/sv48 and some harts only supporting sv39. When those harts with sv48 support is picked as boot hart, the OS automatically assumes all the other non-boot harts support sv48 as well. Therefore, we need to select the harts with sv39 supports only as the boot hart to avoid the incorrect page table issues in non-boot harts.

2) We have use case which requires the same boot hart to save OS context before going into 'hibernation' mode and to restore the OS context after resuming from 'hibernation' mode.

> > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > ---
> > firmware/objects.mk | 4 ++++
> > lib/sbi/sbi_init.c  | 9 ++++++++-
> > 2 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/firmware/objects.mk b/firmware/objects.mk index
> > a1704c4..2b41718 100644
> > --- a/firmware/objects.mk
> > +++ b/firmware/objects.mk
> > @@ -28,6 +28,10 @@ ifdef FW_TEXT_START firmware-genflags-y +=
> > -DFW_TEXT_START=$(FW_TEXT_START) endif
> >
> > +ifdef FW_BOOT_HART_ID
> > +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> > +endif
> > +
> > ifdef FW_FDT_PATH
> > firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> > ifdef FW_FDT_PADDING
> > diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> > d57efa7..5abfa79 100644
> > --- a/lib/sbi/sbi_init.c
> > +++ b/lib/sbi/sbi_init.c
> > @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct
> sbi_scratch *scratch, u32 hartid)
> > 			     scratch->next_mode, FALSE);
> > }
> >
> > +#ifndef FW_BOOT_HART_ID
> > static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> > +#endif
> >
> > /**
> >  * Initialize OpenSBI library for current HART and jump to next @@
> > -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> > 	 * HARTs which satisfy above condition.
> > 	 */
> >
> > -	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> > +	if (next_mode_supported &&
> > +#ifdef FW_BOOT_HART_ID
> > +		hartid == FW_BOOT_HART_ID)
> > +#else
> > +		atomic_xchg(&coldboot_lottery, 1) == 0) #endif
> > 		coldboot = TRUE;
> >
> > 	/*
> > --
> > 2.25.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi


From jrtc27 at jrtc27.com  Tue Nov 29 19:41:02 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Wed, 30 Nov 2022 03:41:02 +0000
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>
 <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
Message-ID: <E8E51DF3-AD41-4D59-AD1F-2630C4358AAA@jrtc27.com>

On 30 Nov 2022, at 03:33, WeiLiang Lim <weiliang.lim at starfivetech.com> wrote:
> 
>> -----Original Message-----
>> From: Jessica Clarke <jrtc27 at jrtc27.com>
>> Sent: Wednesday, November 30, 2022 12:18 AM
>> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
>> Cc: opensbi at lists.infradead.org; Cheehong Ang
>> <cheehong.ang at starfivetech.com>; JunLiang Tan
>> <junliang.tan at starfivetech.com>
>> Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
>> 
>> On 29 Nov 2022, at 05:21, Wei Liang Lim <weiliang.lim at starfivetech.com>
>> wrote:
>>> 
>>> In certain scenario, user needs to select a particular hart ID as the boot hart.
>> This option provide the flexibility for user to select the preferred boot hart.
>> 
>> Why? What?s wrong with the others?
>> 
>> Jess
>> 
> We need this patch for 2 scenarios below:
> 1) On our architecture, there are some harts supporting MMU sv39/sv48 and some harts only supporting sv39. When those harts with sv48 support is picked as boot hart, the OS automatically assumes all the other non-boot harts support sv48 as well. Therefore, we need to select the harts with sv39 supports only as the boot hart to avoid the incorrect page table issues in non-boot harts.

If you have a heterogenous environment then this isn?t the right fix,
OSes need to be aware of heterogeneity otherwise other things can
easily go wrong. And if they?re aware of that then you don?t need to
control which OS boots. Nothing in the RISC-V world currently says that
OSes should do their feature detection on the first hart that boots...

> 2) We have use case which requires the same boot hart to save OS context before going into 'hibernation' mode and to restore the OS context after resuming from 'hibernation' mode.

I can?t imagine current OpenSBI+Linux is at all prepared for
hibernation so don?t think that?s a sufficient justification for it
today?

Jess

>>> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
>>> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
>>> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
>>> ---
>>> firmware/objects.mk | 4 ++++
>>> lib/sbi/sbi_init.c  | 9 ++++++++-
>>> 2 files changed, 12 insertions(+), 1 deletion(-)
>>> 
>>> diff --git a/firmware/objects.mk b/firmware/objects.mk index
>>> a1704c4..2b41718 100644
>>> --- a/firmware/objects.mk
>>> +++ b/firmware/objects.mk
>>> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START firmware-genflags-y +=
>>> -DFW_TEXT_START=$(FW_TEXT_START) endif
>>> 
>>> +ifdef FW_BOOT_HART_ID
>>> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
>>> +endif
>>> +
>>> ifdef FW_FDT_PATH
>>> firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
>>> ifdef FW_FDT_PADDING
>>> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
>>> d57efa7..5abfa79 100644
>>> --- a/lib/sbi/sbi_init.c
>>> +++ b/lib/sbi/sbi_init.c
>>> @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct
>> sbi_scratch *scratch, u32 hartid)
>>> 			     scratch->next_mode, FALSE);
>>> }
>>> 
>>> +#ifndef FW_BOOT_HART_ID
>>> static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
>>> +#endif
>>> 
>>> /**
>>> * Initialize OpenSBI library for current HART and jump to next @@
>>> -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
>>> 	 * HARTs which satisfy above condition.
>>> 	 */
>>> 
>>> -	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
>>> +	if (next_mode_supported &&
>>> +#ifdef FW_BOOT_HART_ID
>>> +		hartid == FW_BOOT_HART_ID)
>>> +#else
>>> +		atomic_xchg(&coldboot_lottery, 1) == 0) #endif
>>> 		coldboot = TRUE;
>>> 
>>> 	/*
>>> --
>>> 2.25.1
>>> 
>>> 
>>> --
>>> opensbi mailing list
>>> opensbi at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/opensbi
> 



From bmeng.cn at gmail.com  Tue Nov 29 19:47:52 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 30 Nov 2022 11:47:52 +0800
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com> <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
Message-ID: <CAEUhbmUF0V=jKkwPyQXe4VOtyL=x6fyGOh1U14Tk49ATG1rVhw@mail.gmail.com>

On Wed, Nov 30, 2022 at 11:35 AM WeiLiang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> > -----Original Message-----
> > From: Jessica Clarke <jrtc27 at jrtc27.com>
> > Sent: Wednesday, November 30, 2022 12:18 AM
> > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > <junliang.tan at starfivetech.com>
> > Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
> >
> > On 29 Nov 2022, at 05:21, Wei Liang Lim <weiliang.lim at starfivetech.com>
> > wrote:
> > >
> > > In certain scenario, user needs to select a particular hart ID as the boot hart.
> > This option provide the flexibility for user to select the preferred boot hart.
> >
> > Why? What?s wrong with the others?
> >
> > Jess
> >
> We need this patch for 2 scenarios below:
> 1) On our architecture, there are some harts supporting MMU sv39/sv48 and some harts only supporting sv39. When those harts with sv48 support is picked as boot hart, the OS automatically assumes all the other non-boot harts support sv48 as well. Therefore, we need to select the harts with sv39 supports only as the boot hart to avoid the incorrect page table issues in non-boot harts.

For such a case, you probably need to add a CONFIG option in the Linux
kernel to force an MMU type instead of auto probing the highest MMU
type on the boot hart.

>
> 2) We have use case which requires the same boot hart to save OS context before going into 'hibernation' mode and to restore the OS context after resuming from 'hibernation' mode.
>
> > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > ---
> > > firmware/objects.mk | 4 ++++
> > > lib/sbi/sbi_init.c  | 9 ++++++++-
> > > 2 files changed, 12 insertions(+), 1 deletion(-)
> > >

Regards,
Bin


From cheehong.ang at starfivetech.com  Tue Nov 29 21:26:22 2022
From: cheehong.ang at starfivetech.com (Cheehong Ang)
Date: Wed, 30 Nov 2022 05:26:22 +0000
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <E8E51DF3-AD41-4D59-AD1F-2630C4358AAA@jrtc27.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>
 <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
 <E8E51DF3-AD41-4D59-AD1F-2630C4358AAA@jrtc27.com>
Message-ID: <516644919c75492198d5e50379d7fdb3@EXMBX068.cuchost.com>

> >> -----Original Message-----
> >> From: Jessica Clarke <jrtc27 at jrtc27.com>
> >> Sent: Wednesday, November 30, 2022 12:18 AM
> >> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> >> Cc: opensbi at lists.infradead.org; Cheehong Ang
> >> <cheehong.ang at starfivetech.com>; JunLiang Tan
> >> <junliang.tan at starfivetech.com>
> >> Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
> >>
> >> On 29 Nov 2022, at 05:21, Wei Liang Lim
> >> <weiliang.lim at starfivetech.com>
> >> wrote:
> >>>
> >>> In certain scenario, user needs to select a particular hart ID as the boot
> hart.
> >> This option provide the flexibility for user to select the preferred boot
> hart.
> >>
> >> Why? What?s wrong with the others?
> >>
> >> Jess
> >>
> > We need this patch for 2 scenarios below:
> > 1) On our architecture, there are some harts supporting MMU sv39/sv48
> and some harts only supporting sv39. When those harts with sv48 support is
> picked as boot hart, the OS automatically assumes all the other non-boot
> harts support sv48 as well. Therefore, we need to select the harts with sv39
> supports only as the boot hart to avoid the incorrect page table issues in
> non-boot harts.
> 
> If you have a heterogenous environment then this isn?t the right fix, OSes
> need to be aware of heterogeneity otherwise other things can easily go
> wrong. And if they?re aware of that then you don?t need to control which OS
> boots. Nothing in the RISC-V world currently says that OSes should do their
> feature detection on the first hart that boots...
> 
> > 2) We have use case which requires the same boot hart to save OS context
> before going into 'hibernation' mode and to restore the OS context after
> resuming from 'hibernation' mode.
> 
> I can?t imagine current OpenSBI+Linux is at all prepared for hibernation so
> don?t think that?s a sufficient justification for it today?
> 

Appreciate the comments and responses.
We agree that there are other better/proper ways to fix the issues that we have encountered above.
Just like Bin Meng highlighted in other threads that instead of fixing the boot hart order, CONFIG options can be added to kernel code to enforce certain MMU type.
There is nothing wrong with lottery mechanism boot flow. We are not trying fix the boot hart selection mechanism in OpenSBI to resolve our problems. We just try to provide another option for user to specify a boot hart for certain use cases.
In some cases, we may also need to select certain hart as boot hart for debugging the SMP issues especially during hardware development stages.
My question here is do we think providing another option to select certain hart ID as boot hart is something unnecessary in RISC-V world at all ?

> Jess
> 
> >>> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> >>> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> >>> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> >>> ---
> >>> firmware/objects.mk | 4 ++++
> >>> lib/sbi/sbi_init.c  | 9 ++++++++-
> >>> 2 files changed, 12 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/firmware/objects.mk b/firmware/objects.mk index
> >>> a1704c4..2b41718 100644
> >>> --- a/firmware/objects.mk
> >>> +++ b/firmware/objects.mk
> >>> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START firmware-genflags-y +=
> >>> -DFW_TEXT_START=$(FW_TEXT_START) endif
> >>>
> >>> +ifdef FW_BOOT_HART_ID
> >>> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> >>> +endif
> >>> +
> >>> ifdef FW_FDT_PATH
> >>> firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> >>> ifdef FW_FDT_PADDING
> >>> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> >>> d57efa7..5abfa79 100644
> >>> --- a/lib/sbi/sbi_init.c
> >>> +++ b/lib/sbi/sbi_init.c
> >>> @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct
> >> sbi_scratch *scratch, u32 hartid)
> >>> 			     scratch->next_mode, FALSE);
> >>> }
> >>>
> >>> +#ifndef FW_BOOT_HART_ID
> >>> static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> >>> +#endif
> >>>
> >>> /**
> >>> * Initialize OpenSBI library for current HART and jump to next @@
> >>> -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> >>> 	 * HARTs which satisfy above condition.
> >>> 	 */
> >>>
> >>> -	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) ==
> 0)
> >>> +	if (next_mode_supported &&
> >>> +#ifdef FW_BOOT_HART_ID
> >>> +		hartid == FW_BOOT_HART_ID)
> >>> +#else
> >>> +		atomic_xchg(&coldboot_lottery, 1) == 0) #endif
> >>> 		coldboot = TRUE;
> >>>
> >>> 	/*
> >>> --
> >>> 2.25.1
> >>>
> >>>
> >>> --
> >>> opensbi mailing list
> >>> opensbi at lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/opensbi
> >


From weiliang.lim at starfivetech.com  Tue Nov 29 22:04:10 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Wed, 30 Nov 2022 06:04:10 +0000
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <516644919c75492198d5e50379d7fdb3@EXMBX068.cuchost.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com>
 <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
 <E8E51DF3-AD41-4D59-AD1F-2630C4358AAA@jrtc27.com>
 <516644919c75492198d5e50379d7fdb3@EXMBX068.cuchost.com>
Message-ID: <77b26112c4134edea95f5eb381b6c5a1@EXMBX163.cuchost.com>

> -----Original Message-----
> From: Cheehong Ang <cheehong.ang at starfivetech.com>
> Sent: Wednesday, November 30, 2022 1:26 PM
> To: Jessica Clarke <jrtc27 at jrtc27.com>; WeiLiang Lim
> <weiliang.lim at starfivetech.com>; Bin Meng <bmeng.cn at gmail.com>
> Cc: opensbi at lists.infradead.org; JunLiang Tan <junliang.tan at starfivetech.com>
> Subject: RE: [PATCH] lib: sbi: Add option to select boot hart
> 
> > >> -----Original Message-----
> > >> From: Jessica Clarke <jrtc27 at jrtc27.com>
> > >> Sent: Wednesday, November 30, 2022 12:18 AM
> > >> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > >> Cc: opensbi at lists.infradead.org; Cheehong Ang
> > >> <cheehong.ang at starfivetech.com>; JunLiang Tan
> > >> <junliang.tan at starfivetech.com>
> > >> Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
> > >>
> > >> On 29 Nov 2022, at 05:21, Wei Liang Lim
> > >> <weiliang.lim at starfivetech.com>
> > >> wrote:
> > >>>
> > >>> In certain scenario, user needs to select a particular hart ID as
> > >>> the boot
> > hart.
> > >> This option provide the flexibility for user to select the
> > >> preferred boot
> > hart.
> > >>
> > >> Why? What?s wrong with the others?
> > >>
> > >> Jess
> > >>
> > > We need this patch for 2 scenarios below:
> > > 1) On our architecture, there are some harts supporting MMU
> > > sv39/sv48
> > and some harts only supporting sv39. When those harts with sv48
> > support is picked as boot hart, the OS automatically assumes all the
> > other non-boot harts support sv48 as well. Therefore, we need to
> > select the harts with sv39 supports only as the boot hart to avoid the
> > incorrect page table issues in non-boot harts.
> >
> > If you have a heterogenous environment then this isn?t the right fix,
> > OSes need to be aware of heterogeneity otherwise other things can
> > easily go wrong. And if they?re aware of that then you don?t need to
> > control which OS boots. Nothing in the RISC-V world currently says
> > that OSes should do their feature detection on the first hart that boots...
> >
> > > 2) We have use case which requires the same boot hart to save OS
> > > context
> > before going into 'hibernation' mode and to restore the OS context
> > after resuming from 'hibernation' mode.
> >
> > I can?t imagine current OpenSBI+Linux is at all prepared for
> > hibernation so don?t think that?s a sufficient justification for it today?
> >
> 
> Appreciate the comments and responses.
> We agree that there are other better/proper ways to fix the issues that we
> have encountered above.
> Just like Bin Meng highlighted in other threads that instead of fixing the boot
> hart order, CONFIG options can be added to kernel code to enforce certain
> MMU type.
> There is nothing wrong with lottery mechanism boot flow. We are not trying
> fix the boot hart selection mechanism in OpenSBI to resolve our problems. We
> just try to provide another option for user to specify a boot hart for certain use
> cases.
> In some cases, we may also need to select certain hart as boot hart for
> debugging the SMP issues especially during hardware development stages.
> My question here is do we think providing another option to select certain hart
> ID as boot hart is something unnecessary in RISC-V world at all ?
> 

Thanks for all the great feedbacks and suggestions.
Just want to clarify that the intention is not to alter the existing boot flow lottery mechanism.
But to provide an additional option/flexibility for user to specify the preferred boot hart for whatever reason. 

> > Jess
> >
> > >>> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > >>> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > >>> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > >>> ---
> > >>> firmware/objects.mk | 4 ++++
> > >>> lib/sbi/sbi_init.c  | 9 ++++++++-
> > >>> 2 files changed, 12 insertions(+), 1 deletion(-)
> > >>>
> > >>> diff --git a/firmware/objects.mk b/firmware/objects.mk index
> > >>> a1704c4..2b41718 100644
> > >>> --- a/firmware/objects.mk
> > >>> +++ b/firmware/objects.mk
> > >>> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START firmware-genflags-y +=
> > >>> -DFW_TEXT_START=$(FW_TEXT_START) endif
> > >>>
> > >>> +ifdef FW_BOOT_HART_ID
> > >>> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> > >>> +endif
> > >>> +
> > >>> ifdef FW_FDT_PATH
> > >>> firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> > >>> ifdef FW_FDT_PADDING
> > >>> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> > >>> d57efa7..5abfa79 100644
> > >>> --- a/lib/sbi/sbi_init.c
> > >>> +++ b/lib/sbi/sbi_init.c
> > >>> @@ -443,7 +443,9 @@ static void __noreturn init_warmboot(struct
> > >> sbi_scratch *scratch, u32 hartid)
> > >>> 			     scratch->next_mode, FALSE); }
> > >>>
> > >>> +#ifndef FW_BOOT_HART_ID
> > >>> static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> > >>> +#endif
> > >>>
> > >>> /**
> > >>> * Initialize OpenSBI library for current HART and jump to next @@
> > >>> -494,7 +496,12 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> > >>> 	 * HARTs which satisfy above condition.
> > >>> 	 */
> > >>>
> > >>> -	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) ==
> > 0)
> > >>> +	if (next_mode_supported &&
> > >>> +#ifdef FW_BOOT_HART_ID
> > >>> +		hartid == FW_BOOT_HART_ID)
> > >>> +#else
> > >>> +		atomic_xchg(&coldboot_lottery, 1) == 0) #endif
> > >>> 		coldboot = TRUE;
> > >>>
> > >>> 	/*
> > >>> --
> > >>> 2.25.1
> > >>>
> > >>>
> > >>> --
> > >>> opensbi mailing list
> > >>> opensbi at lists.infradead.org
> > >>> http://lists.infradead.org/mailman/listinfo/opensbi
> > >


From prabhakar.csengg at gmail.com  Wed Nov 30 04:40:53 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Wed, 30 Nov 2022 12:40:53 +0000
Subject: [PATCH 1/4] platform: generic/andes: Enable generic platform
 support for AE350
In-Reply-To: <Y4UZ+rcUBTUG152q@APC323>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-2-peterlin@andestech.com>
 <CA+V-a8urkMz-Fwj9OFLEp2FAYG9_ZpFG9S_QBNK1=zR1g4svFg@mail.gmail.com> <Y4UZ+rcUBTUG152q@APC323>
Message-ID: <CA+V-a8vWWVAgRZsZA+62CCUYs2rS_eoEtB9_dZDdFK90W6swOA@mail.gmail.com>

Hi Lin-san,

On Mon, Nov 28, 2022 at 12:32 PM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> On Mon, Nov 28, 2022 at 10:34:06AM +0000, Lad, Prabhakar wrote:
> > Hi Lin-san,
> >
> > On Mon, Nov 28, 2022 at 8:32 AM Yu Chien Peter Lin
> > <peterlin at andestech.com> wrote:
> > >
> > > We move andes directory to platform/generic since the necessary fdt
> > > drivers are available, the users can enable the console, timer, ipi,
> > > irqchip and reset devices by adding device tree nodes stated in the
> > > docs/platform/andes-ae350.md.
> > >
> > > Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> > > ---
> > > Although generic/platform.c has been able to boot the system
> > > on AE350, we will add HSM device for it soon so let's keep
> > > ae350.c as a placeholder.
> > > ---
> > >  platform/andes/ae350/Kconfig           |  34 -----
> > >  platform/andes/ae350/cache.c           |  89 -------------
> > >  platform/andes/ae350/cache.h           |  17 ---
> > >  platform/andes/ae350/configs/defconfig |   0
> > >  platform/andes/ae350/objects.mk        |  40 ------
> > >  platform/andes/ae350/platform.c        | 169 -------------------------
> > >  platform/andes/ae350/platform.h        | 109 ----------------
> > >  platform/generic/Kconfig               |   4 +
> > >  platform/generic/andes/ae350.c         |  21 +++
> > >  platform/generic/andes/objects.mk      |   6 +
> > >  platform/generic/configs/defconfig     |   4 +
> > >  11 files changed, 35 insertions(+), 458 deletions(-)
> > >  delete mode 100644 platform/andes/ae350/Kconfig
> > >  delete mode 100644 platform/andes/ae350/cache.c
> > >  delete mode 100644 platform/andes/ae350/cache.h
> > You have got rid of cache functions and also the vendor specific EXT
> > handler, wouldn't that break things?
>
> Hi Prabhakar,
>
> I want to take this opportunity to drop unnecessary functions, most of
> the andes SBI calls were experimental/debugging features in kernel that
> won't affact the boot flow.
>
Thanks for the clarification.

> You can still keep them in generic/renesas/rzfive.c. The renesas vendor
> SBI call fid does not need to be the same as ours.
>
Agreed, that's the reason RZ/Five had a different enum for SBI vendor IDs.

> As for common Andes CSR which you separated into andes/ae350/common-platform.h
> can be moved to generic/include/andes45.h.
>
Agreed.

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:21 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:21 +0000
Subject: [PATCH v3 2/6] lib: utils: serial: Add FDT driver for Renesas SCIF
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial at 1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = <0 0x1004b800 0 0x400>;
                    interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
                                 <414 IRQ_TYPE_LEVEL_HIGH>,
                                 <415 IRQ_TYPE_LEVEL_HIGH>,
                                 <413 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
                    clock-names = "fck";
                    power-domains = <&cpg>;
                    resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v2->v3
* No change

RFC->v2
* Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and
  DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros.

DT binding [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80
---
 include/sbi_utils/fdt/fdt_helper.h         |  3 +++
 lib/utils/fdt/fdt_helper.c                 | 11 ++++++++
 lib/utils/serial/Kconfig                   |  5 ++++
 lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++
 lib/utils/serial/objects.mk                |  3 +++
 5 files changed, 53 insertions(+)
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c

diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
index c39f77a..09f3095 100644
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
 int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 				struct platform_uart_data *uart);
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart);
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);
 
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index d4b38dc..48bc2fe 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -23,6 +23,9 @@
 #define DEFAULT_UART_REG_IO_WIDTH	1
 #define DEFAULT_UART_REG_OFFSET		0
 
+#define DEFAULT_RENESAS_SCIF_FREQ		100000000
+#define DEFAULT_RENESAS_SCIF_BAUD		115200
+
 #define DEFAULT_SIFIVE_UART_FREQ		0
 #define DEFAULT_SIFIVE_UART_BAUD		115200
 
@@ -355,6 +358,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 					DEFAULT_UART_BAUD);
 }
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart)
+{
+	return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
+					  DEFAULT_RENESAS_SCIF_FREQ,
+					  DEFAULT_RENESAS_SCIF_BAUD);
+}
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart)
 {
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index f6ed803..e3589ca 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF
 	select SYS_HTIF
 	default n
 
+config FDT_SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF FDT driver"
+	select SERIAL_RENESAS_SCIF
+	default n
+
 config FDT_SERIAL_SHAKTI
 	bool "Shakti UART FDT driver"
 	select SERIAL_SHAKTI
diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c
new file mode 100644
index 0000000..c331ca1
--- /dev/null
+++ b/lib/utils/serial/fdt_serial_renesas_scif.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+static int serial_renesas_scif_init(void *fdt, int nodeoff,
+				    const struct fdt_match *match)
+{
+	struct platform_uart_data uart = { 0 };
+	int ret;
+
+	ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart);
+	if (ret)
+		return ret;
+
+	return renesas_scif_init(uart.addr, uart.freq, uart.baud);
+}
+
+static const struct fdt_match serial_renesas_scif_match[] = {
+	{ .compatible = "renesas,scif-r9a07g043" },
+	{ /* sentinel */ }
+};
+
+struct fdt_serial fdt_serial_renesas_scif = {
+	.match_table = serial_renesas_scif_match,
+	.init = serial_renesas_scif_init
+};
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 6520424..1e6bd2e 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o
 
+carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif
+libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o
+
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o
 
-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:19 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:19 +0000
Subject: [PATCH v3 0/6] Add support for Renesas RZ/Five SoC
Message-ID: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Hi All,

This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
is equipped with AX45MP AndesCore). Platform supports DT based probing.

Linux support is currently being upstreamed the latest patchset can be
found at [0](currently in linux-next, DT bindings can be seen here)

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

- PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
- PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
  and is used in a similar manner as compared Andes AE350 [1]
  [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
- SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79

Note:
- The PMA implementation is still in discussion [1] once its decided
corresponding patch to OpenSBI will be added to reserve the memory nodes
and vendor specific SBI EXT.
- U-boot from BSP release wont work with these patches, it requires additional
  patches (happy to share the u-boot branch if anyone wants to test this patchset)
- Patches apply on top of [2]

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
[2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/

v2->v3
* Switched to generic platform
* Dropped all vendor specific SBI EXT
* Fixed review comments pointed by Bin for SCIF driver
* Updated doc

RFC->v2
* Fixed comments pointed by Xiang W
* Included RB tag from Yu Chien Peter Lin for patch #3

RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
-----------------------------------------------------------
U-Boot SPL 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
Trying to boot from NOR

OpenSBI v1.1-109-gfa85d48
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : Renesas SMARC EVK based on r9a07g043f01
Platform Features         : medeleg
Platform HART Count       : 1
Platform IPI Device       : andes_plicsw
Platform Timer Device     : andes_plmt @ 12000000Hz
Platform Console Device   : renesas_scif
Platform HSM Device       : ---
Platform PMU Device       : ---
Platform Reboot Device    : ---
Platform Shutdown Device  : ---
Firmware Base             : 0x44000000
Firmware Size             : 212 KB
Runtime SBI Version       : 1.0

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000050000000
Domain0 Next Arg1         : 0x00000000500bdee0
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART Priv Version    : v1.11
Boot HART Base ISA        : rv64imafdcnx
Boot HART ISA Extensions  : none
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 8
Boot HART PMP Address Bits: 36
Boot HART MHPM Count      : 4
Boot HART MIDELEG         : 0x0000000000000222
Boot HART MEDELEG         : 0x000000000000b109


U-Boot 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)

CPU:   rv64imafdc
Model: Renesas SMARC EVK based on r9a07g043f01
DRAM:  896 MiB
SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
MMC:   sd at 11c00000: 0, sd at 11c10000: 1
Loading Environment from MMC... OK
In:    serial at 1004b800
Out:   serial at 1004b800
Err:   serial at 1004b800
Net:   eth0: ethernet at 11c30000
Hit any key to stop autoboot:  0
=> run prafat;run pranfs;run bootimage
7153012 bytes read in 445 ms (15.3 MiB/s)
22510 bytes read in 3 ms (7.2 MiB/s)
Uncompressed size: 19854848 = 0x12EF600
Moving Image from 0x48080000 to 0x48200000, end=49569000
## Flattened Device Tree blob at 48000000
   Booting using the fdt blob at 0x48000000
   Loading Device Tree to 0000000077f00000, end 0000000077f087ed ... OK

Starting kernel ...

[    0.000000] Linux version 6.1.0-rc4-00292-ga3c6b529ec9f-dirty (prasmi at prasmi) (riscv64-unknown-linux-gnu-gcc (g2ee5e430018) 12.2.0, GNU ld (GNU Binutils) 2.39) #69 SMP Wed Nov 30 17:36:35 GMT 2022
[    0.000000] OF: fdt: Ignoring memory range 0x48000000 - 0x48200000
[    0.000000] Machine model: Renesas SMARC EVK based on r9a07g043f01
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x0000000058000000, size 128 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma at 58000000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA32    [mem 0x0000000048200000-0x000000007fffffff]
[    0.000000]   Normal   empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000048200000-0x0000000057ffffff]
[    0.000000]   node   0: [mem 0x0000000058000000-0x000000005fffffff]
[    0.000000]   node   0: [mem 0x0000000060000000-0x000000007fffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000048200000-0x000000007fffffff]
[    0.000000] SBI specification v1.0 detected
[    0.000000] SBI implementation ID=0x1 Version=0x10001
[    0.000000] SBI TIME extension detected
[    0.000000] SBI IPI extension detected
[    0.000000] SBI RFENCE extension detected
[    0.000000] SBI HSM extension detected
[    0.000000] riscv: base ISA extensions acdfim
[    0.000000] riscv: ELF capabilities acdfim
[    0.000000] percpu: Embedded 18 pages/cpu s34744 r8192 d30792 u73728
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 225288
[    0.000000] Kernel command line: root=/dev/nfs rw rootwait ip=dhcp nfsroot=192.168.10.1:/mnt/rzfive,vers=4,tcp console=ttySC0,115200n8 earlycon=sbi debug loglevel=7 deferred_probe_timeout=5
[    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Virtual kernel memory layout:
[    0.000000]       fixmap : 0xffffffc6fee00000 - 0xffffffc6ff000000   (2048 kB)
[    0.000000]       pci io : 0xffffffc6ff000000 - 0xffffffc700000000   (  16 MB)
[    0.000000]      vmemmap : 0xffffffc700000000 - 0xffffffc800000000   (4096 MB)
[    0.000000]      vmalloc : 0xffffffc800000000 - 0xffffffd800000000   (  64 GB)
[    0.000000]      modules : 0xffffffff01369000 - 0xffffffff80000000   (2028 MB)
[    0.000000]       lowmem : 0xffffffd800000000 - 0xffffffd837e00000   ( 894 MB)
[    0.000000]       kernel : 0xffffffff80000000 - 0xffffffffffffffff   (2047 MB)
[    0.000000] Memory: 747812K/915456K available (7394K kernel code, 3746K rwdata, 4096K rodata, 3355K init, 480K bss, 167644K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1.
[    0.000000] rcu:     RCU debug extended QS entry/exit.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] riscv-intc: 64 local interrupts mapped
[    0.000000] plic: interrupt-controller at 12c00000: mapped 511 interrupts with 1 handlers for 2 contexts.
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] riscv-timer: riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
[    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x2c47f4ee7, max_idle_ns: 440795202497 ns
[    0.000003] sched_clock: 64 bits at 12MHz, resolution 83ns, wraps every 4398046511096ns
[    0.000242] Console: colour dummy device 80x25
[    0.000345] Calibrating delay loop (skipped), value calculated using timer frequency.. 24.00 BogoMIPS (lpj=48000)
[    0.000367] pid_max: default: 32768 minimum: 301
[    0.000472] LSM: Security Framework initializing
[    0.000684] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    0.000712] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    0.002601] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    0.003937] cblist_init_generic: Setting adjustable number of callback queues.
[    0.003956] cblist_init_generic: Setting shift to 0 and lim to 1.
[    0.004235] riscv: ELF compat mode unsupported
[    0.004316] ASID allocator using 9 bits (512 entries)
[    0.004576] rcu: Hierarchical SRCU implementation.
[    0.004587] rcu:     Max phase no-delay instances is 1000.
[    0.005204] Detected Renesas RZ/Five r9a07g043 Rev 0
[    0.005221] EFI services will not be available.
[    0.005728] smp: Bringing up secondary CPUs ...
[    0.005740] smp: Brought up 1 node, 1 CPU
[    0.006644] devtmpfs: initialized
[    0.013628] DMA: default coherent area is set
[    0.013648] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.013678] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
[    0.013951] pinctrl core: initialized pinctrl subsystem
[    0.015869] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.016359] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
[    0.016413] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.016526] audit: initializing netlink subsys (disabled)
[    0.017387] thermal_sys: Registered thermal governor 'step_wise'
[    0.017504] cpuidle: using governor menu
[    0.033712] audit: type=2000 audit(0.020:1): state=initialized audit_enabled=0 res=1
[    0.034608] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.034623] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.038322] SCSI subsystem initialized
[    0.038641] usbcore: registered new interface driver usbfs
[    0.038707] usbcore: registered new interface driver hub
[    0.038766] usbcore: registered new device driver usb
[    0.039808] Advanced Linux Sound Architecture Driver Initialized.
[    0.041311] clocksource: Switched to clocksource riscv_clocksource
[    0.054917] NET: Registered PF_INET protocol family
[    0.055223] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
[    0.057347] tcp_listen_portaddr_hash hash table entries: 512 (order: 2, 16384 bytes, linear)
[    0.057402] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.057430] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
[    0.057523] TCP bind hash table entries: 8192 (order: 7, 524288 bytes, linear)
[    0.058595] TCP: Hash tables configured (established 8192 bind 8192)
[    0.058814] UDP hash table entries: 512 (order: 3, 49152 bytes, linear)
[    0.058951] UDP-Lite hash table entries: 512 (order: 3, 49152 bytes, linear)
[    0.059394] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.060323] RPC: Registered named UNIX socket transport module.
[    0.060342] RPC: Registered udp transport module.
[    0.060348] RPC: Registered tcp transport module.
[    0.060354] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.069907] workingset: timestamp_bits=46 max_order=18 bucket_order=0
[    0.094416] NFS: Registering the id_resolver key type
[    0.094498] Key type id_resolver registered
[    0.094507] Key type id_legacy registered
[    0.094665] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    0.094675] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    0.095031] 9p: Installing v9fs 9p2000 file system support
[    0.095642] NET: Registered PF_ALG protocol family
[    0.095756] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248)
[    0.095769] io scheduler mq-deadline registered
[    0.095776] io scheduler kyber registered
[    0.211112] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.213011] SuperH (H)SCI(F) driver initialized
[    0.213764] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    0.223531] loop: module loaded
[    0.227640] usbcore: registered new interface driver uas
[    0.227742] usbcore: registered new interface driver usb-storage
[    0.228103] mousedev: PS/2 mouse device common for all mice
[    0.279088] sdhci: Secure Digital Host Controller Interface driver
[    0.279104] sdhci: Copyright(c) Pierre Ossman
[    0.279281] sdhci-pltfm: SDHCI platform and OF driver helper
[    0.279596] usbcore: registered new interface driver usbhid
[    0.279607] usbhid: USB HID core driver
[    0.280169] riscv-pmu-sbi: SBI PMU extension is available
[    0.280214] riscv-pmu-sbi: 16 firmware and 6 hardware counters
[    0.280225] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available
[    0.282558] NET: Registered PF_INET6 protocol family
[    0.284457] Segment Routing with IPv6
[    0.284537] In-situ OAM (IOAM) with IPv6
[    0.284639] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    0.285632] NET: Registered PF_PACKET protocol family
[    0.285879] 9pnet: Installing 9P2000 support
[    0.286004] Key type dns_resolver registered
[    0.290080] debug_vm_pgtable: [debug_vm_pgtable         ]: Validating architecture page table helpers
[    0.305477] gpio-378 (can0_stb): hogged as output/low
[    0.305517] gpio-379 (can1_stb): hogged as output/low
[    0.305549] gpio-363 (sd1_pwr_en): hogged as output/high
[    0.306264] pinctrl-rzg2l 11030000.pinctrl: pinctrl-rzg2l support registered
[    0.307379] 1004b800.serial: ttySC0 at MMIO 0x1004b800 (irq = 2, base_baud = 0) is a scif
[    1.169958] printk: console [ttySC0] enabled
[    1.176321] i2c-riic 10058000.i2c: registered with 100000Hz bus speed
[    1.185005] i2c-riic 10058400.i2c: registered with 100000Hz bus speed
[    1.193147] Trying to probe devices needed for running init ...
[   13.481453] ALSA device list:
[   13.484433]   No soundcards found.
[   13.490459] Freeing unused kernel image (initmem) memory: 3352K
[   13.496415] Run /init as init process
This is for testing KEXEC!
mount: mounting /dev/sda1 on /mnt/root failed: No such file or directory
Dropping to a shell.
sh: can't access tty; job control turned off
/ #
/ #
-------------------------------------------------------------------------------

Cheers,
Prabhakar

Lad Prabhakar (6):
  lib: utils: serial: Add Renesas SCIF driver
  lib: utils: serial: Add FDT driver for Renesas SCIF
  lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
  platform: generic: Add Renesas RZ/Five initial support
  docs: platform: Add documentation for Renesas RZ/Five SoC
  platform: generic: Drop root_offset parameter from
    fw_platform_lookup_special()

 docs/platform/platform.md                  |   5 +
 docs/platform/renesas-rzfive.md            | 145 +++++++++++++++++++++
 include/sbi_utils/fdt/fdt_helper.h         |   3 +
 include/sbi_utils/serial/renesas-scif.h    |  11 ++
 lib/utils/fdt/fdt_helper.c                 |  11 ++
 lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
 lib/utils/serial/Kconfig                   |   9 ++
 lib/utils/serial/fdt_serial_renesas_scif.c |  31 +++++
 lib/utils/serial/objects.mk                |   4 +
 lib/utils/serial/renesas_scif.c            | 116 +++++++++++++++++
 platform/generic/Kconfig                   |   4 +
 platform/generic/configs/defconfig         |   2 +
 platform/generic/platform.c                |   4 +-
 platform/generic/renesas/rzfive/objects.mk |   8 ++
 platform/generic/renesas/rzfive/rzfive.c   |  17 +++
 15 files changed, 370 insertions(+), 3 deletions(-)
 create mode 100644 docs/platform/renesas-rzfive.md
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
 create mode 100644 lib/utils/serial/renesas_scif.c
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:22 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:22 +0000
Subject: [PATCH v3 3/6] lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.

While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.

dts example (Single-core AX45MP):

    soc: soc {
          ....
          plic: interrupt-controller at 12c00000 {
              compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
              #interrupt-cells = <2>;
              #address-cells = <0>;
              riscv,ndev = <511>;
              interrupt-controller;
              reg = <0x0 0x12c00000 0 0x400000>;
              clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
              power-domains = <&cpg>;
              resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
              interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
          };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
v2->v3
* Included RB tags

RFC->v2
* No change

DT binding [0]
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..83d091a 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -163,7 +163,8 @@ static const struct fdt_match irqchip_plic_match[] = {
 	{ .compatible = "sifive,plic-1.0.0" },
 	{ .compatible = "thead,c900-plic",
 	  .data = thead_plic_plat_init },
-	{ },
+	{ .compatible = "andestech,nceplic100" },
+	{ /* sentinel */ }
 };
 
 struct fdt_irqchip fdt_irqchip_plic = {
-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:23 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:23 +0000
Subject: [PATCH v3 4/6] platform: generic: Add Renesas RZ/Five initial support
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v2->v3
* New patch
---
 platform/generic/Kconfig                   |  4 ++++
 platform/generic/configs/defconfig         |  2 ++
 platform/generic/renesas/rzfive/objects.mk |  8 ++++++++
 platform/generic/renesas/rzfive/rzfive.c   | 17 +++++++++++++++++
 4 files changed, 31 insertions(+)
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 4b5d2cd..62c7a2d 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -32,6 +32,10 @@ config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
 	default n
 
+config PLATFORM_RENESAS_RZFIVE
+	bool "Renesas RZ/Five support"
+	default n
+
 config PLATFORM_SIFIVE_FU540
 	bool "SiFive FU540 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 2eaeeb7..47fca95 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -1,5 +1,6 @@
 CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
+CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
 CONFIG_FDT_GPIO=y
@@ -24,6 +25,7 @@ CONFIG_FDT_SERIAL=y
 CONFIG_FDT_SERIAL_CADENCE=y
 CONFIG_FDT_SERIAL_GAISLER=y
 CONFIG_FDT_SERIAL_HTIF=y
+CONFIG_FDT_SERIAL_RENESAS_SCIF=y
 CONFIG_FDT_SERIAL_SHAKTI=y
 CONFIG_FDT_SERIAL_SIFIVE=y
 CONFIG_FDT_SERIAL_LITEX=y
diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
new file mode 100644
index 0000000..2e7e37f
--- /dev/null
+++ b/platform/generic/renesas/rzfive/objects.mk
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2022 Renesas Electronics Corp.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
+platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
new file mode 100644
index 0000000..2b82bc6
--- /dev/null
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static const struct fdt_match renesas_rzfive_match[] = {
+	{ .compatible = "renesas,r9a07g043" },
+	{ /* sentinel */ }
+};
+
+const struct platform_override renesas_rzfive = {
+	.match_table = renesas_rzfive_match,
+};
-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:20 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:20 +0000
Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
<takeki.hamada.ak at bp.renesas.com>
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v2->v3
* Fixed review comments pointed by Bin

RFC->v2
* Fixed comments pointed by Xiang W
---
 include/sbi_utils/serial/renesas-scif.h |  11 +++
 lib/utils/serial/Kconfig                |   4 +
 lib/utils/serial/objects.mk             |   1 +
 lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
 4 files changed, 132 insertions(+)
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/renesas_scif.c

diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
new file mode 100644
index 0000000..0002a1a
--- /dev/null
+++ b/include/sbi_utils/serial/renesas-scif.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#ifndef __SERIAL_RENESAS_SCIF_H__
+#define __SERIAL_RENESAS_SCIF_H__
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif /* __SERIAL_RENESAS_SCIF_H__ */
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index da549a7..f6ed803 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -59,6 +59,10 @@ config SERIAL_GAISLER
 	bool "Gaisler UART support"
 	default n
 
+config SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF support"
+	default n
+
 config SERIAL_SHAKTI
 	bool "Shakti UART support"
 	default n
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 98f3f9a..6520424 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
 
 libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
+libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
 libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
new file mode 100644
index 0000000..cf6b53c
--- /dev/null
+++ b/lib/utils/serial/renesas_scif.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_timer.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+/* clang-format off */
+
+#define SCIF_REG_SMR		0x0
+#define SCIF_REG_BRR		0x2
+#define SCIF_REG_SCR		0x4
+#define SCIF_REG_FTDR		0x6
+#define SCIF_REG_FSR		0x8
+#define SCIF_REG_FCR		0xc
+#define SCIF_REG_LSR		0x12
+#define SCIF_REG_SEMR		0x14
+
+#define SCIF_FCR_RFRST		0x2 /* Reset assert receive-FIFO (bit[1]) */
+#define SCIF_FCR_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2]) */
+
+#define SCIF_FCR_RST_ASSRT_RFTF	(SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
+#define SCIF_FCR_RST_NGATE_RFTF	0x0 /* Reset negate tx-FIFO & rx-FIFO */
+
+#define SCIF_SCR_RE		0x10 /* Enable receive (bit[4]) */
+#define SCIF_SCR_TE		0x20 /* Enable transmit(bit[5]) */
+#define SCIF_SCR_RCV_TRN_EN	(SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
+#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
+
+#define SCIF_FSR_ER		0x80 /* Receive error flag */
+#define SCIF_FSR_TEND		0x40 /* Transmit End Flag */
+#define SCIF_FSR_TDFE		0x20 /* Transmit FIFO Data Empty Flag */
+#define SCIF_FSR_BRK		0x10 /* Detect break flag */
+#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
+
+#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
+
+#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
+
+#define SCIF_REG_8BIT(reg)	((reg == SCIF_REG_BRR) || \
+				 (reg == SCIF_REG_FTDR) || \
+				 (reg == SCIF_REG_SEMR))
+
+#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
+
+/* clang-format on */
+
+static volatile char *scif_base;
+
+static u32 get_reg(u32 offset)
+{
+	if (SCIF_REG_8BIT(offset))
+		return readb(scif_base + offset);
+
+	return readw(scif_base + offset);
+}
+
+static void set_reg(u32 offset, u32 val)
+{
+	if (SCIF_REG_8BIT(offset))
+		return writeb(val, scif_base + offset);
+
+	return writew(val, scif_base + offset);
+}
+
+static void renesas_scif_putc(char ch)
+{
+	uint16_t reg;
+
+	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
+		;
+
+	set_reg(SCIF_REG_FTDR, ch);
+	reg = get_reg(SCIF_REG_FSR);
+	reg &= ~SCIF_FSR_TXD_CHK;
+	set_reg(SCIF_REG_FSR, reg);
+}
+
+static struct sbi_console_device renesas_scif_console = {
+	.name		= "renesas_scif",
+	.console_putc	= renesas_scif_putc,
+};
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
+{
+	volatile uint16_t data16;
+
+	scif_base = (volatile char *)base;
+
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
+
+	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
+	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
+
+	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
+	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
+
+	set_reg(SCIF_REG_SCR, 0x0);
+
+	set_reg(SCIF_REG_SMR, 0x0);
+
+	data16 = get_reg(SCIF_REG_SEMR);
+	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
+	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
+
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
+
+	sbi_console_set_device(&renesas_scif_console);
+
+	return 0;
+}
-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:24 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:24 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas RZ/Five SoC
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v2->v3
* Updated doc with new build command

RFC->v2
* Updated doc
---
 docs/platform/platform.md       |   5 ++
 docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
 2 files changed, 150 insertions(+)
 create mode 100644 docs/platform/renesas-rzfive.md

diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index f291931..4504d87 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
 
+* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
+  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
+  be found in the file *[renesas-rzfive.md]*.
+
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *objects.mk*,
@@ -54,3 +58,4 @@ comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
+[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
new file mode 100644
index 0000000..a900cc7
--- /dev/null
+++ b/docs/platform/renesas-rzfive.md
@@ -0,0 +1,145 @@
+Renesas RZ/Five SoC (R9A07G043F) Platform
+=========================================
+The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
+1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
+- Gigabit Ethernet 2ch
+- CAN interface (CAN-FD) 2ch
+- USB 2.0 interface 2ch
+- SD interface 2ch
+- AD converter 2ch
+making it ideal for applications such as entry-class social infrastructure
+gateway control and industrial gateway control.
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=generic* parameter to the top level make command.
+
+Platform Options
+----------------
+
+The Renesas RZ/Five platform does not have any platform-specific options.
+
+Building Renesas RZ/Five Platform
+---------------------------------
+
+```
+make PLATFORM=generic
+```
+
+DTS Example: (RZ/Five AX45MP)
+-----------------------------
+
+```
+	compatible = "renesas,r9a07g043";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <12000000>;
+
+		cpu0: cpu at 0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ranges;
+
+		scif0: serial at 1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller at 11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller at 11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl at 11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plmt0: plmt0 at 110c0000 {
+			compatible = "andestech,plmt0", "riscv,plmt0";
+			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
+			interrupts-extended = <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller at 12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <511>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+
+		plicsw: interrupt-controller at 13000000 {
+			compatible = "andestech,plicsw";
+			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
+			interrupts-extended = <&cpu0_intc 3>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+		};
+	};
+```
-- 
2.17.1



From prabhakar.csengg at gmail.com  Wed Nov 30 14:08:25 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Wed, 30 Nov 2022 22:08:25 +0000
Subject: [PATCH v3 6/6] platform: generic: Drop root_offset parameter from fw_platform_lookup_special()
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221130220825.193693-7-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

root_offset parameter isn't used in fw_platform_lookup_special() so
just drop it.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v2->v3
* New patch
---
 platform/generic/platform.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 595b0fd..fb5f476 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -32,7 +32,7 @@ extern unsigned long platform_override_modules_size;
 static const struct platform_override *generic_plat = NULL;
 static const struct fdt_match *generic_plat_match = NULL;
 
-static void fw_platform_lookup_special(void *fdt, int root_offset)
+static void fw_platform_lookup_special(void *fdt)
 {
 	int pos, noff;
 	const struct platform_override *plat;
@@ -83,7 +83,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
 	if (root_offset < 0)
 		goto fail;
 
-	fw_platform_lookup_special(fdt, root_offset);
+	fw_platform_lookup_special(fdt);
 
 	model = fdt_getprop(fdt, root_offset, "model", &len);
 	if (model)
-- 
2.17.1



