From atishp at atishpatra.org  Sat Mar  5 01:26:23 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Sat, 5 Mar 2022 01:26:23 -0800
Subject: [PATCH v1 2/2] lib: sbi: Implement Sstc extension
In-Reply-To: <23FC9827-CE39-430A-B529-A17E39C2B6BD@jrtc27.com>
References: <20220228082604.3649231-1-atishp@rivosinc.com>
 <20220228082604.3649231-3-atishp@rivosinc.com>
 <17C1041E-B6B4-406F-8DB7-B703F74E8400@jrtc27.com>
 <CAHBxVyGvj+7Z=9mxdyayP-xc+=_QNRVznsqXX7wBPDCRecpxvQ@mail.gmail.com>
 <490A275F-85D2-4A76-A105-0F5AC46C9414@jrtc27.com>
 <CAHBxVyERWidrca9Vp9Jc14XYfkV1B9pPWVvrcY1ZgEBVxzHfjA@mail.gmail.com>
 <23FC9827-CE39-430A-B529-A17E39C2B6BD@jrtc27.com>
Message-ID: <CAOnJCU+xsqa263sJw8wjdWhn9=Hj6f-yeT2=L45z9Nd+y=suow@mail.gmail.com>

On Mon, Feb 28, 2022 at 11:59 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>
> On 28 Feb 2022, at 19:51, Atish Kumar Patra <atishp at rivosinc.com> wrote:
> >
> > On Mon, Feb 28, 2022 at 11:42 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
> >>
> >> On 28 Feb 2022, at 18:52, Atish Kumar Patra <atishp at rivosinc.com> wrote:
> >>>
> >>> On Mon, Feb 28, 2022 at 9:03 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
> >>>>
> >>>> On 28 Feb 2022, at 08:26, Atish Patra <atishp at rivosinc.com> wrote:
> >>>>>
> >>>>> Recently, Sstc extension was ratified. It defines stimecmp which allows
> >>>>> the supervisor mode to directly update the timecmp value without the
> >>>>> need of the SBI call. The hardware also can inject the S-mode timer
> >>>>> interrupt direclty to the supervisor without going through the M-mode.
> >>>>> To maintain backward compatibility with the older software, SBI call
> >>>>> now uses stimecmp directly if the hardware supports.
> >>>>>
> >>>>> Implement the Sstc extension.
> >>>>>
> >>>>> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> >>>>
> >>>> M-mode changing behaviour and clobbering S-mode state seems wrong; how
> >>>> do you know Sstimecmp isn?t in use too?
> >>>
> >>> <Fixed Anup's email address>
> >>>
> >>> Because, S-mode will either use the stimecmp or SBI call. It will not
> >>> use both randomly.
> >>
> >> S-mode can do what it likes. You?re changing semantics for an existing
> >> interface from ?just injects a timer interrupt at the requested point?
> >> to ?... and also clobbers S-mode-writable state?.
> >>
> >
> > If S-mode does whatever it likes, it will end up in a suboptimal
> > performance which nobody wants.
> > I don't understand why or how S-mode would want to switch between
> > stimecmp or SBI calls randomly.
> >
> > Do you have a use case in mind ?
> >
> >>> This is also suggested in the sstc spec[1] as well.
> >>
> >> This is non-normative and not up to that spec to decide.
> >>
> >
> > Yes. But if both parties(S-mode & M-mode) have a sane implementation,
> > it can result in a better performant system.
>
> I don?t care about use cases or ?sane? implementations, I care about
> not doing things the spec doesn?t say will happen. M-mode state is
> invisible to S-mode so does not need to be specified as being changed.
> S-mode state is completely visible to, and controlled by, S-mode, so
> changing it without the spec saying so (a spec you?ve frozen and want
> to ratify) is totally wrong, regardless of whether ?sane? software
> should care. The only way it?s allowed to mess with stimecmp from
> M-mode is if you don't expose it at all to S-mode, which is clearly a
> bad idea. So leave it alone, don?t change the semantics of existing
> frozen interfaces, and avoid this unnecessary complexity in OpenSBI
> that exists solely to make legacy software go faster.
>

The Sstc spec also made STIP bit in mip as read only. Here is exact
snippet from the spec

"If the stimecmp (supervisor-mode timer compare) register is implemented,
STIP is read-only in mip and reflects the supervisor-level timer
interrupt signal resulting from
stimecmp."

Thus, M-mode can't update the STIP bit if sstc is enabled.

> Jess
>
> >>> In systems in which a supervisor execution environment (SEE) provides
> >>> timer facilities via an SBI
> >>> function call, this SBI call will continue to support requests to
> >>> schedule a timer interrupt. The SEE
> >>> will simply make use of stimecmp, changing its value as appropriate.
> >>> This ensures compatibility
> >>> with existing S-mode software that uses this SEE facility, while new
> >>> S-mode software takes
> >>> advantage of stimecmp directly.)
> >>>
> >>> [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
> >>>
> >>>> It?s owned by S-mode, leave it
> >>>> alone and use M-mode-only methods to implement the firmware calls.
> >>>>
> >>>> Jess
> >>>>
> >>>>> ---
> >>>>> include/sbi/riscv_encoding.h |  4 ++++
> >>>>> include/sbi/sbi_hart.h       |  4 +++-
> >>>>> lib/sbi/sbi_hart.c           | 28 ++++++++++++++++++++++++++++
> >>>>> lib/sbi/sbi_timer.c          | 25 ++++++++++++++++++++++---
> >>>>> 4 files changed, 57 insertions(+), 4 deletions(-)
> >>>>>
> >>>>> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> >>>>> index c0020f43f022..cce66ddc8b12 100644
> >>>>> --- a/include/sbi/riscv_encoding.h
> >>>>> +++ b/include/sbi/riscv_encoding.h
> >>>>> @@ -312,6 +312,10 @@
> >>>>> #define CSR_STVAL                     0x143
> >>>>> #define CSR_SIP                               0x144
> >>>>>
> >>>>> +/* Sstc extension */
> >>>>> +#define CSR_STIMECMP                 0x14D
> >>>>> +#define CSR_STIMECMPH                        0x15D
> >>>>> +
> >>>>> /* Supervisor Protection and Translation */
> >>>>> #define CSR_SATP                      0x180
> >>>>>
> >>>>> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> >>>>> index 9e5a2b416017..93be7eddd6f1 100644
> >>>>> --- a/include/sbi/sbi_hart.h
> >>>>> +++ b/include/sbi/sbi_hart.h
> >>>>> @@ -28,9 +28,11 @@ enum sbi_hart_features {
> >>>>>     SBI_HART_HAS_AIA = (1 << 5),
> >>>>>     /** HART has MENVCFG CSR */
> >>>>>     SBI_HART_HAS_MENVCFG = (1 << 6),
> >>>>> +     /** HART has SSTC extension implemented in hardware */
> >>>>> +     SBI_HART_HAS_SSTC = (1 << 7),
> >>>>>
> >>>>>     /** Last index of Hart features*/
> >>>>> -     SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
> >>>>> +     SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SSTC,
> >>>>> };
> >>>>>
> >>>>> struct sbi_scratch;
> >>>>> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> >>>>> index e08d9d32266a..8c9cad219c71 100644
> >>>>> --- a/lib/sbi/sbi_hart.c
> >>>>> +++ b/lib/sbi/sbi_hart.c
> >>>>> @@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
> >>>>>     int cidx;
> >>>>>     unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
> >>>>>     uint64_t mhpmevent_init_val = 0;
> >>>>> +     unsigned long menvcfg_val = 0;
> >>>>>
> >>>>>     /* Enable FPU */
> >>>>>     if (misa_extension('D') || misa_extension('F'))
> >>>>> @@ -54,6 +55,23 @@ static void mstatus_init(struct sbi_scratch *scratch)
> >>>>>
> >>>>>     csr_write(CSR_MSTATUS, mstatus_val);
> >>>>>
> >>>>> +     /*
> >>>>> +      * The spec doesn't explicitly describe the reset value of menvcfg.
> >>>>> +      * Enable access to stimecmp if sstc extension is present in the
> >>>>> +      * hardware.
> >>>>> +      */
> >>>>> +     if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSTC)) {
> >>>>> +#if __riscv_xlen == 32
> >>>>> +             menvcfg_val = csr_read(CSR_MENVCFGH);
> >>>>> +             menvcfg_val |= MENVCFGH_STCE;
> >>>>> +             csr_write(CSR_MENVCFGH, menvcfg_val);
> >>>>> +#else
> >>>>> +             menvcfg_val = csr_read(CSR_MENVCFG);
> >>>>> +             menvcfg_val |= MENVCFG_STCE;
> >>>>> +             csr_write(CSR_MENVCFG, menvcfg_val);
> >>>>> +#endif
> >>>>> +     }
> >>>>> +
> >>>>>     /* Disable user mode usage of all perf counters except default ones (CY, TM, IR) */
> >>>>>     if (misa_extension('S') &&
> >>>>>         sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
> >>>>> @@ -303,6 +321,8 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
> >>>>>             break;
> >>>>>     case SBI_HART_HAS_AIA:
> >>>>>             fstr = "aia";
> >>>>> +     case SBI_HART_HAS_SSTC:
> >>>>> +             fstr = "sstc";
> >>>>>             break;
> >>>>>     default:
> >>>>>             break;
> >>>>> @@ -533,6 +553,14 @@ __mhpm_skip:
> >>>>>     if (!trap.cause)
> >>>>>             hfeatures->features |= SBI_HART_HAS_MENVCFG;
> >>>>>
> >>>>> +     /**
> >>>>> +      * Detect if hart supports stimecmp CSR(Sstc extension) and menvcfg is
> >>>>> +      * implemented.
> >>>>> +      */
> >>>>> +     csr_read_allowed(CSR_STIMECMP, (unsigned long)&trap);
> >>>>> +     if (!trap.cause && sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
> >>>>> +             hfeatures->features |= SBI_HART_HAS_SSTC;
> >>>>> +
> >>>>>     /* Detect if hart has AIA local interrupt CSRs */
> >>>>>     csr_read_allowed(CSR_MTOPI, (unsigned long)&trap);
> >>>>>     if (trap.cause)
> >>>>> diff --git a/lib/sbi/sbi_timer.c b/lib/sbi/sbi_timer.c
> >>>>> index acdba922b1e9..c89c7ca51100 100644
> >>>>> --- a/lib/sbi/sbi_timer.c
> >>>>> +++ b/lib/sbi/sbi_timer.c
> >>>>> @@ -124,16 +124,35 @@ void sbi_timer_set_delta_upper(ulong delta_upper)
> >>>>> void sbi_timer_event_start(u64 next_event)
> >>>>> {
> >>>>>     sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SET_TIMER);
> >>>>> -     if (timer_dev && timer_dev->timer_event_start)
> >>>>> +
> >>>>> +     /**
> >>>>> +      * Update the stimecmp directly if available. This allows
> >>>>> +      * the older software to leverage sstc extension on newer hardware.
> >>>>> +      */
> >>>>> +     if (sbi_hart_has_feature(sbi_scratch_thishart_ptr(), SBI_HART_HAS_SSTC)) {
> >>>>> +#if __riscv_xlen == 32
> >>>>> +             csr_write(CSR_STIMECMP, next_event & 0xFFFFFFFF);
> >>>>> +             csr_write(CSR_STIMECMPH, next_event >> 32);
> >>>>> +#else
> >>>>> +             csr_write(CSR_STIMECMP, next_event);
> >>>>> +#endif
> >>>>> +     } else if (timer_dev && timer_dev->timer_event_start) {
> >>>>>             timer_dev->timer_event_start(next_event);
> >>>>> -     csr_clear(CSR_MIP, MIP_STIP);
> >>>>> +             csr_clear(CSR_MIP, MIP_STIP);
> >>>>> +     }
> >>>>>     csr_set(CSR_MIE, MIP_MTIP);
> >>>>> }
> >>>>>
> >>>>> void sbi_timer_process(void)
> >>>>> {
> >>>>>     csr_clear(CSR_MIE, MIP_MTIP);
> >>>>> -     csr_set(CSR_MIP, MIP_STIP);
> >>>>> +     /*
> >>>>> +      * If sstc extension is available, supervisor can receive the timer
> >>>>> +      * direclty without M-mode come in between. This function should
> >>>>> +      * only invoked if M-mode programs the timer for its own purpose.
> >>>>> +      */
> >>>>> +     if (!sbi_hart_has_feature(sbi_scratch_thishart_ptr(), SBI_HART_HAS_SSTC))
> >>>>> +             csr_set(CSR_MIP, MIP_STIP);
> >>>>> }
> >>>>>
> >>>>> const struct sbi_timer_device *sbi_timer_get_device(void)
> >>>>> --
> >>>>> 2.30.2
> >>>>>
> >>>>>
> >>>>> --
> >>>>> opensbi mailing list
> >>>>> opensbi at lists.infradead.org
> >>>>> http://lists.infradead.org/mailman/listinfo/opensbi
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



--
Regards,
Atish


From jrtc27 at jrtc27.com  Sat Mar  5 10:43:42 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Sat, 5 Mar 2022 18:43:42 +0000
Subject: [PATCH v1 2/2] lib: sbi: Implement Sstc extension
In-Reply-To: <CAOnJCU+xsqa263sJw8wjdWhn9=Hj6f-yeT2=L45z9Nd+y=suow@mail.gmail.com>
References: <20220228082604.3649231-1-atishp@rivosinc.com>
 <20220228082604.3649231-3-atishp@rivosinc.com>
 <17C1041E-B6B4-406F-8DB7-B703F74E8400@jrtc27.com>
 <CAHBxVyGvj+7Z=9mxdyayP-xc+=_QNRVznsqXX7wBPDCRecpxvQ@mail.gmail.com>
 <490A275F-85D2-4A76-A105-0F5AC46C9414@jrtc27.com>
 <CAHBxVyERWidrca9Vp9Jc14XYfkV1B9pPWVvrcY1ZgEBVxzHfjA@mail.gmail.com>
 <23FC9827-CE39-430A-B529-A17E39C2B6BD@jrtc27.com>
 <CAOnJCU+xsqa263sJw8wjdWhn9=Hj6f-yeT2=L45z9Nd+y=suow@mail.gmail.com>
Message-ID: <70A2DBA6-0110-4549-AC50-E29F9446C8B9@jrtc27.com>

On 5 Mar 2022, at 09:26, Atish Patra <atishp at atishpatra.org> wrote:
> 
> On Mon, Feb 28, 2022 at 11:59 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>> 
>> On 28 Feb 2022, at 19:51, Atish Kumar Patra <atishp at rivosinc.com> wrote:
>>> 
>>> On Mon, Feb 28, 2022 at 11:42 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>>>> 
>>>> On 28 Feb 2022, at 18:52, Atish Kumar Patra <atishp at rivosinc.com> wrote:
>>>>> 
>>>>> On Mon, Feb 28, 2022 at 9:03 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>>>>>> 
>>>>>> On 28 Feb 2022, at 08:26, Atish Patra <atishp at rivosinc.com> wrote:
>>>>>>> 
>>>>>>> Recently, Sstc extension was ratified. It defines stimecmp which allows
>>>>>>> the supervisor mode to directly update the timecmp value without the
>>>>>>> need of the SBI call. The hardware also can inject the S-mode timer
>>>>>>> interrupt direclty to the supervisor without going through the M-mode.
>>>>>>> To maintain backward compatibility with the older software, SBI call
>>>>>>> now uses stimecmp directly if the hardware supports.
>>>>>>> 
>>>>>>> Implement the Sstc extension.
>>>>>>> 
>>>>>>> Signed-off-by: Atish Patra <atishp at rivosinc.com>
>>>>>> 
>>>>>> M-mode changing behaviour and clobbering S-mode state seems wrong; how
>>>>>> do you know Sstimecmp isn?t in use too?
>>>>> 
>>>>> <Fixed Anup's email address>
>>>>> 
>>>>> Because, S-mode will either use the stimecmp or SBI call. It will not
>>>>> use both randomly.
>>>> 
>>>> S-mode can do what it likes. You?re changing semantics for an existing
>>>> interface from ?just injects a timer interrupt at the requested point?
>>>> to ?... and also clobbers S-mode-writable state?.
>>>> 
>>> 
>>> If S-mode does whatever it likes, it will end up in a suboptimal
>>> performance which nobody wants.
>>> I don't understand why or how S-mode would want to switch between
>>> stimecmp or SBI calls randomly.
>>> 
>>> Do you have a use case in mind ?
>>> 
>>>>> This is also suggested in the sstc spec[1] as well.
>>>> 
>>>> This is non-normative and not up to that spec to decide.
>>>> 
>>> 
>>> Yes. But if both parties(S-mode & M-mode) have a sane implementation,
>>> it can result in a better performant system.
>> 
>> I don?t care about use cases or ?sane? implementations, I care about
>> not doing things the spec doesn?t say will happen. M-mode state is
>> invisible to S-mode so does not need to be specified as being changed.
>> S-mode state is completely visible to, and controlled by, S-mode, so
>> changing it without the spec saying so (a spec you?ve frozen and want
>> to ratify) is totally wrong, regardless of whether ?sane? software
>> should care. The only way it?s allowed to mess with stimecmp from
>> M-mode is if you don't expose it at all to S-mode, which is clearly a
>> bad idea. So leave it alone, don?t change the semantics of existing
>> frozen interfaces, and avoid this unnecessary complexity in OpenSBI
>> that exists solely to make legacy software go faster.
>> 
> 
> The Sstc spec also made STIP bit in mip as read only. Here is exact
> snippet from the spec
> 
> "If the stimecmp (supervisor-mode timer compare) register is implemented,
> STIP is read-only in mip and reflects the supervisor-level timer
> interrupt signal resulting from
> stimecmp."
> 
> Thus, M-mode can't update the STIP bit if sstc is enabled.

This directly contradicts text from ratified privileged specs (quoting
Volume 2, Privileged Spec v. 20211203, the current version linked from
riscv.org):

"If supervisor mode is implemented, bits mip.STIP and mie.STIE are the
interrupt-pending and interrupt-enable bits for supervisor-level timer
interrupts. STIP is writable in mip, and may be written by M-mode
software to deliver timer interrupts to S-mode.?

That makes Sstc in direct violation of the existing privileged spec and
not a compatible extension, being completely backwards-incompatible
with every software stack that exists today. What a mess. No wonder we
get mocked by everyone outside the community if we can?t even get this
kind of thing right.

Jess

>>>>> In systems in which a supervisor execution environment (SEE) provides
>>>>> timer facilities via an SBI
>>>>> function call, this SBI call will continue to support requests to
>>>>> schedule a timer interrupt. The SEE
>>>>> will simply make use of stimecmp, changing its value as appropriate.
>>>>> This ensures compatibility
>>>>> with existing S-mode software that uses this SEE facility, while new
>>>>> S-mode software takes
>>>>> advantage of stimecmp directly.)
>>>>> 
>>>>> [1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
>>>>> 
>>>>>> It?s owned by S-mode, leave it
>>>>>> alone and use M-mode-only methods to implement the firmware calls.
>>>>>> 
>>>>>> Jess
>>>>>> 
>>>>>>> ---
>>>>>>> include/sbi/riscv_encoding.h |  4 ++++
>>>>>>> include/sbi/sbi_hart.h       |  4 +++-
>>>>>>> lib/sbi/sbi_hart.c           | 28 ++++++++++++++++++++++++++++
>>>>>>> lib/sbi/sbi_timer.c          | 25 ++++++++++++++++++++++---
>>>>>>> 4 files changed, 57 insertions(+), 4 deletions(-)
>>>>>>> 
>>>>>>> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
>>>>>>> index c0020f43f022..cce66ddc8b12 100644
>>>>>>> --- a/include/sbi/riscv_encoding.h
>>>>>>> +++ b/include/sbi/riscv_encoding.h
>>>>>>> @@ -312,6 +312,10 @@
>>>>>>> #define CSR_STVAL                     0x143
>>>>>>> #define CSR_SIP                               0x144
>>>>>>> 
>>>>>>> +/* Sstc extension */
>>>>>>> +#define CSR_STIMECMP                 0x14D
>>>>>>> +#define CSR_STIMECMPH                        0x15D
>>>>>>> +
>>>>>>> /* Supervisor Protection and Translation */
>>>>>>> #define CSR_SATP                      0x180
>>>>>>> 
>>>>>>> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
>>>>>>> index 9e5a2b416017..93be7eddd6f1 100644
>>>>>>> --- a/include/sbi/sbi_hart.h
>>>>>>> +++ b/include/sbi/sbi_hart.h
>>>>>>> @@ -28,9 +28,11 @@ enum sbi_hart_features {
>>>>>>>    SBI_HART_HAS_AIA = (1 << 5),
>>>>>>>    /** HART has MENVCFG CSR */
>>>>>>>    SBI_HART_HAS_MENVCFG = (1 << 6),
>>>>>>> +     /** HART has SSTC extension implemented in hardware */
>>>>>>> +     SBI_HART_HAS_SSTC = (1 << 7),
>>>>>>> 
>>>>>>>    /** Last index of Hart features*/
>>>>>>> -     SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
>>>>>>> +     SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SSTC,
>>>>>>> };
>>>>>>> 
>>>>>>> struct sbi_scratch;
>>>>>>> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
>>>>>>> index e08d9d32266a..8c9cad219c71 100644
>>>>>>> --- a/lib/sbi/sbi_hart.c
>>>>>>> +++ b/lib/sbi/sbi_hart.c
>>>>>>> @@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
>>>>>>>    int cidx;
>>>>>>>    unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
>>>>>>>    uint64_t mhpmevent_init_val = 0;
>>>>>>> +     unsigned long menvcfg_val = 0;
>>>>>>> 
>>>>>>>    /* Enable FPU */
>>>>>>>    if (misa_extension('D') || misa_extension('F'))
>>>>>>> @@ -54,6 +55,23 @@ static void mstatus_init(struct sbi_scratch *scratch)
>>>>>>> 
>>>>>>>    csr_write(CSR_MSTATUS, mstatus_val);
>>>>>>> 
>>>>>>> +     /*
>>>>>>> +      * The spec doesn't explicitly describe the reset value of menvcfg.
>>>>>>> +      * Enable access to stimecmp if sstc extension is present in the
>>>>>>> +      * hardware.
>>>>>>> +      */
>>>>>>> +     if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SSTC)) {
>>>>>>> +#if __riscv_xlen == 32
>>>>>>> +             menvcfg_val = csr_read(CSR_MENVCFGH);
>>>>>>> +             menvcfg_val |= MENVCFGH_STCE;
>>>>>>> +             csr_write(CSR_MENVCFGH, menvcfg_val);
>>>>>>> +#else
>>>>>>> +             menvcfg_val = csr_read(CSR_MENVCFG);
>>>>>>> +             menvcfg_val |= MENVCFG_STCE;
>>>>>>> +             csr_write(CSR_MENVCFG, menvcfg_val);
>>>>>>> +#endif
>>>>>>> +     }
>>>>>>> +
>>>>>>>    /* Disable user mode usage of all perf counters except default ones (CY, TM, IR) */
>>>>>>>    if (misa_extension('S') &&
>>>>>>>        sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
>>>>>>> @@ -303,6 +321,8 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
>>>>>>>            break;
>>>>>>>    case SBI_HART_HAS_AIA:
>>>>>>>            fstr = "aia";
>>>>>>> +     case SBI_HART_HAS_SSTC:
>>>>>>> +             fstr = "sstc";
>>>>>>>            break;
>>>>>>>    default:
>>>>>>>            break;
>>>>>>> @@ -533,6 +553,14 @@ __mhpm_skip:
>>>>>>>    if (!trap.cause)
>>>>>>>            hfeatures->features |= SBI_HART_HAS_MENVCFG;
>>>>>>> 
>>>>>>> +     /**
>>>>>>> +      * Detect if hart supports stimecmp CSR(Sstc extension) and menvcfg is
>>>>>>> +      * implemented.
>>>>>>> +      */
>>>>>>> +     csr_read_allowed(CSR_STIMECMP, (unsigned long)&trap);
>>>>>>> +     if (!trap.cause && sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
>>>>>>> +             hfeatures->features |= SBI_HART_HAS_SSTC;
>>>>>>> +
>>>>>>>    /* Detect if hart has AIA local interrupt CSRs */
>>>>>>>    csr_read_allowed(CSR_MTOPI, (unsigned long)&trap);
>>>>>>>    if (trap.cause)
>>>>>>> diff --git a/lib/sbi/sbi_timer.c b/lib/sbi/sbi_timer.c
>>>>>>> index acdba922b1e9..c89c7ca51100 100644
>>>>>>> --- a/lib/sbi/sbi_timer.c
>>>>>>> +++ b/lib/sbi/sbi_timer.c
>>>>>>> @@ -124,16 +124,35 @@ void sbi_timer_set_delta_upper(ulong delta_upper)
>>>>>>> void sbi_timer_event_start(u64 next_event)
>>>>>>> {
>>>>>>>    sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SET_TIMER);
>>>>>>> -     if (timer_dev && timer_dev->timer_event_start)
>>>>>>> +
>>>>>>> +     /**
>>>>>>> +      * Update the stimecmp directly if available. This allows
>>>>>>> +      * the older software to leverage sstc extension on newer hardware.
>>>>>>> +      */
>>>>>>> +     if (sbi_hart_has_feature(sbi_scratch_thishart_ptr(), SBI_HART_HAS_SSTC)) {
>>>>>>> +#if __riscv_xlen == 32
>>>>>>> +             csr_write(CSR_STIMECMP, next_event & 0xFFFFFFFF);
>>>>>>> +             csr_write(CSR_STIMECMPH, next_event >> 32);
>>>>>>> +#else
>>>>>>> +             csr_write(CSR_STIMECMP, next_event);
>>>>>>> +#endif
>>>>>>> +     } else if (timer_dev && timer_dev->timer_event_start) {
>>>>>>>            timer_dev->timer_event_start(next_event);
>>>>>>> -     csr_clear(CSR_MIP, MIP_STIP);
>>>>>>> +             csr_clear(CSR_MIP, MIP_STIP);
>>>>>>> +     }
>>>>>>>    csr_set(CSR_MIE, MIP_MTIP);
>>>>>>> }
>>>>>>> 
>>>>>>> void sbi_timer_process(void)
>>>>>>> {
>>>>>>>    csr_clear(CSR_MIE, MIP_MTIP);
>>>>>>> -     csr_set(CSR_MIP, MIP_STIP);
>>>>>>> +     /*
>>>>>>> +      * If sstc extension is available, supervisor can receive the timer
>>>>>>> +      * direclty without M-mode come in between. This function should
>>>>>>> +      * only invoked if M-mode programs the timer for its own purpose.
>>>>>>> +      */
>>>>>>> +     if (!sbi_hart_has_feature(sbi_scratch_thishart_ptr(), SBI_HART_HAS_SSTC))
>>>>>>> +             csr_set(CSR_MIP, MIP_STIP);
>>>>>>> }
>>>>>>> 
>>>>>>> const struct sbi_timer_device *sbi_timer_get_device(void)
>>>>>>> --
>>>>>>> 2.30.2
>>>>>>> 
>>>>>>> 
>>>>>>> --
>>>>>>> opensbi mailing list
>>>>>>> opensbi at lists.infradead.org
>>>>>>> http://lists.infradead.org/mailman/listinfo/opensbi
>> 
>> 
>> --
>> opensbi mailing list
>> opensbi at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/opensbi
> 
> 
> 
> --
> Regards,
> Atish



From jrtc27 at jrtc27.com  Sun Mar  6 08:13:19 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Sun, 6 Mar 2022 16:13:19 +0000
Subject: [PATCH v1 2/2] lib: sbi: Implement Sstc extension
In-Reply-To: <CA+Qh7Tm4GspwKsYudmYRHSGz66maSZNgu1cLj-Ykuubjc-xLmg@mail.gmail.com>
References: <20220228082604.3649231-1-atishp@rivosinc.com>
 <20220228082604.3649231-3-atishp@rivosinc.com>
 <17C1041E-B6B4-406F-8DB7-B703F74E8400@jrtc27.com>
 <CAHBxVyGvj+7Z=9mxdyayP-xc+=_QNRVznsqXX7wBPDCRecpxvQ@mail.gmail.com>
 <490A275F-85D2-4A76-A105-0F5AC46C9414@jrtc27.com>
 <CAHBxVyERWidrca9Vp9Jc14XYfkV1B9pPWVvrcY1ZgEBVxzHfjA@mail.gmail.com>
 <23FC9827-CE39-430A-B529-A17E39C2B6BD@jrtc27.com>
 <CAOnJCU+xsqa263sJw8wjdWhn9=Hj6f-yeT2=L45z9Nd+y=suow@mail.gmail.com>
 <70A2DBA6-0110-4549-AC50-E29F9446C8B9@jrtc27.com>
 <CAOnJCULUnsvzDtj7TipQ6_K3ep_qgpeswzEQyJ3F5kojkc98Ww@mail.gmail.com>
 <CA+Qh7Tm4GspwKsYudmYRHSGz66maSZNgu1cLj-Ykuubjc-xLmg@mail.gmail.com>
Message-ID: <8544E35C-06E2-4790-955A-A29C5A3F72CE@jrtc27.com>

On 6 Mar 2022, at 16:08, Greg Favor <gfavor at ventanamicro.com> wrote:
> 
> On Sat, Mar 5, 2022 at 3:04 PM Atish Patra <atishp at atishpatra.org> wrote:
> > The Sstc spec also made STIP bit in mip as read only. Here is exact
> > snippet from the spec
> > 
> > "If the stimecmp (supervisor-mode timer compare) register is implemented,
> > STIP is read-only in mip and reflects the supervisor-level timer
> > interrupt signal resulting from
> > stimecmp."
> > 
> > Thus, M-mode can't update the STIP bit if sstc is enabled.
> 
> This directly contradicts text from ratified privileged specs (quoting
> Volume 2, Privileged Spec v. 20211203, the current version linked from
> riscv.org):
> 
> +Greg who may shed some light behind the reasoning for this sstc requirement. 
> 
> The proper way to interpret Sstc or any new arch extension that modifies existing arch functionality, is simply that the new extension modifies or overrides the existing functionality.  As new arch extensions get integrated into the same document as existing documents (for which there is a lot of outstanding integration work for both the Unpriv and Priv documents, mixed in with all the work to convert all that stuff to adoc), that will be more readily apparent in one document and, as appropriate, existing ratified architecture text will be modified (aka "clarified") to include forward reference to being modified by an optional arch extension.  The H extension is a big example of modifying (as well as adding to) the pre-existing architecture.  If one doesn't support the H extension, then one can read the existing M and S chapters as is.  But if one does support the H extension, then they and the H chapter need to be read and comprehended together since the pre-existing arch text doesn't directly incorporate all the modifications (as, of course, conditional modifications).


That?s not the question. The question is how an architectural extension can remove an explicitly specified feature from the base privileged spec that all software stacks ({BBL, OpenSBI} x {FreeBSD, Linux, others}) running on Unix-class hardware rely on, thereby making priv+Sstc explicitly backwards incompatible with base priv. Ratified specifications are supposed to provide a compatibility guarantee, and extensions are supposed to add not remove (except where it?s removing choice).

Jess



From jrtc27 at jrtc27.com  Sun Mar  6 08:47:54 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Sun, 6 Mar 2022 16:47:54 +0000
Subject: [PATCH v1 2/2] lib: sbi: Implement Sstc extension
In-Reply-To: <CA+Qh7TmmcNb+6U98fKoNq247d9YgKjBYCY_2szZ-rGwNixcY5g@mail.gmail.com>
References: <20220228082604.3649231-1-atishp@rivosinc.com>
 <20220228082604.3649231-3-atishp@rivosinc.com>
 <17C1041E-B6B4-406F-8DB7-B703F74E8400@jrtc27.com>
 <CAHBxVyGvj+7Z=9mxdyayP-xc+=_QNRVznsqXX7wBPDCRecpxvQ@mail.gmail.com>
 <490A275F-85D2-4A76-A105-0F5AC46C9414@jrtc27.com>
 <CAHBxVyERWidrca9Vp9Jc14XYfkV1B9pPWVvrcY1ZgEBVxzHfjA@mail.gmail.com>
 <23FC9827-CE39-430A-B529-A17E39C2B6BD@jrtc27.com>
 <CAOnJCU+xsqa263sJw8wjdWhn9=Hj6f-yeT2=L45z9Nd+y=suow@mail.gmail.com>
 <70A2DBA6-0110-4549-AC50-E29F9446C8B9@jrtc27.com>
 <CAOnJCULUnsvzDtj7TipQ6_K3ep_qgpeswzEQyJ3F5kojkc98Ww@mail.gmail.com>
 <CA+Qh7Tm4GspwKsYudmYRHSGz66maSZNgu1cLj-Ykuubjc-xLmg@mail.gmail.com>
 <8544E35C-06E2-4790-955A-A29C5A3F72CE@jrtc27.com>
 <CA+Qh7TmmcNb+6U98fKoNq247d9YgKjBYCY_2szZ-rGwNixcY5g@mail.gmail.com>
Message-ID: <437B20A4-FB9D-4208-A4C9-E3F610864276@jrtc27.com>

[Resending as plain text for the OpenSBI list, and fixing a typo]

On 6 Mar 2022, at 16:28, Greg Favor <gfavor at ventanamicro.com> wrote:
> 
> On Sun, Mar 6, 2022 at 8:13 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>> That?s not the question. The question is how an architectural extension can remove an explicitly specified feature from the base privileged spec that all software stacks ({BBL, OpenSBI} x {FreeBSD, Linux, others}) running on Unix-class hardware rely on, thereby making priv+Sstc explicitly backwards incompatible with base priv. Ratified specifications are supposed to provide a compatibility guarantee, and extensions are supposed to add not remove (except where it?s removing choice).
> 
> As to why Sstc couldn't have instead "added" to the STIP definition by OR'ing in a new interrupt signal with the existing writable CSR bit, that was decided by Andrew and John (and ultimately the AR Committee).  I don't remember off-hand the architectural problem with simply doing that, but they were clear at the time about that being a problem (and it made sense to me at the time as well).  Which then led to the current specification.
> 
> Also note that backward compatibility is provided through the *envcfg.STCE bits.  The same backward compatibility issue exists for the Svpbmt extension - which leads to having the *envcfg PBMTE bits.  This was one of the reasons for creation of the *envcfg CSRs.

That works for Svpbmt where S-mode is the only thing responsible, but for Sstc the interaction between M-mode and S-mode means that?s not enough. STCE is an M-mode bit, so either you have firmware that never exposes Sstc to S-mode and keeps using mip.STIP, rendering Sstc useless, or you have firmware that always exposes Sstc to S-mode but then has no clue if S-mode is using it or not, meaning it has to assume that S-mode has control of stimecmp and thus it cannot be used by M-mode for SBI calls (since the SBI spec only states a0 and sometimes a1 as being clobbered, with the exception of sepc/scause/stval in the case of faults for some of the legacy SBI 0.1 calls that require dereferencing S-mode-provided pointers).

And the ?OR?ing in [an] interrupt signal with the [?] writable CSR bit? behaviour already exists for SEIP and, if such a platform-specific method exists, SSIP, so STIP is now inconsistent with the other two core S-mode interrupt sources (i.e. excluding Sscofpmf).

Jess



From wxjstz at 126.com  Tue Mar 15 09:22:38 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 00:22:38 +0800
Subject: [PATCH 1/3] lib: pmp_set/pmp_get moved errors from runtime to compile
 time
Message-ID: <20220315162240.40990-1-wxjstz@126.com>

pmp_set/pmp_get calculates the location of the CSR register separately
through conditional compilation. In the case of non-32-bit and 64-bit,
we can report an error directly through #error without putting it at
runtime

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/riscv_asm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c
index 847bdba..5eab1ed 100644
--- a/lib/sbi/riscv_asm.c
+++ b/lib/sbi/riscv_asm.c
@@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
 	pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
 	pmpcfg_shift = (n & 7) << 3;
 #else
-	return SBI_ENOTSUPP;
+# error "Unexpected __riscv_xlen"
 #endif
 	pmpaddr_csr = CSR_PMPADDR0 + n;
 
@@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
 	pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
 	pmpcfg_shift = (n & 7) << 3;
 #else
-	return SBI_ENOTSUPP;
+# error "Unexpected __riscv_xlen"
 #endif
 	pmpaddr_csr = CSR_PMPADDR0 + n;
 
-- 
2.30.2



From wxjstz at 126.com  Tue Mar 15 09:22:39 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 00:22:39 +0800
Subject: [PATCH 2/3] firmware: Fix code for accessing hart_count and
 stack_size to be more flexible
In-Reply-To: <20220315162240.40990-1-wxjstz@126.com>
References: <20220315162240.40990-1-wxjstz@126.com>
Message-ID: <20220315162240.40990-2-wxjstz@126.com>

lwu exists under the current rv64 and should also exist under the rv128
in the future, so I modified the conditions of conditional compilation
so that it can adapt to the future situation

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 firmware/fw_base.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/firmware/fw_base.S b/firmware/fw_base.S
index ab3e1b3..07be4c4 100644
--- a/firmware/fw_base.S
+++ b/firmware/fw_base.S
@@ -259,7 +259,7 @@ _bss_zero:
 	 * s8 -> HART Stack Size
 	 */
 	lla	a4, platform
-#if __riscv_xlen == 64
+#if __riscv_xlen > 32
 	lwu	s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
 	lwu	s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
 #else
-- 
2.30.2



From wxjstz at 126.com  Tue Mar 15 09:22:40 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 00:22:40 +0800
Subject: [PATCH 3/3] lib: Add error messages via conditional compilation for
 the future
In-Reply-To: <20220315162240.40990-1-wxjstz@126.com>
References: <20220315162240.40990-1-wxjstz@126.com>
Message-ID: <20220315162240.40990-3-wxjstz@126.com>

On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved.
Through this conditional compile, the corresponding implementation
can be prompted to be added.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/sbi/sbi_unpriv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c
index 4246124..73b530c 100644
--- a/lib/sbi/sbi_unpriv.c
+++ b/lib/sbi/sbi_unpriv.c
@@ -83,7 +83,7 @@ DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
 DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
-#else
+#elif __riscv_xlen == 32
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
 DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
 
@@ -112,6 +112,8 @@ void sbi_store_u64(u64 *addr, u64 val,
 	if (trap->cause)
 		return;
 }
+#else
+# error "Unexpected __riscv_xlen"
 #endif
 
 ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
-- 
2.30.2



From wxjstz at 126.com  Tue Mar 15 18:45:25 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 09:45:25 +0800
Subject: [PATCH] sbi: Prevent modification of struct sbi_platform from
 affecting SBI_PLATFORM_xxx_OFFSET
Message-ID: <20220316014525.57326-1-wxjstz@126.com>

Add static detection to prevent the modification of struct sbi_platform
from forgetting the modification of SBI_PLATFORM_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_platform.h | 48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 0b5ae4b..87b582e 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -175,6 +175,54 @@ struct sbi_platform {
 	const u32 *hart_index2id;
 };
 
+/** Prevent modification of struct sbi_platform from affecting
+ * SBI_PLATFORM_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct sbi_platform, opensbi_version)
+		== SBI_PLATFORM_OPENSBI_VERSION_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_OPENSBI_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, platform_version)
+		== SBI_PLATFORM_VERSION_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, name)
+		== SBI_PLATFORM_NAME_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_NAME_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, features)
+		== SBI_PLATFORM_FEATURES_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_FEATURES_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_count)
+		== SBI_PLATFORM_HART_COUNT_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_COUNT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_stack_size)
+		== SBI_PLATFORM_HART_STACK_SIZE_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_STACK_SIZE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, platform_ops_addr)
+		== SBI_PLATFORM_OPS_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_OPS_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, firmware_context)
+		== SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_index2id)
+		== SBI_PLATFORM_HART_INDEX2ID_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_INDEX2ID_OFFSET");
+
 /** Get pointer to sbi_platform for sbi_scratch pointer */
 #define sbi_platform_ptr(__s) \
 	((const struct sbi_platform *)((__s)->platform_addr))
-- 
2.30.2



From wxjstz at 126.com  Tue Mar 15 21:35:14 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 12:35:14 +0800
Subject: [PATCH] sbi: Prevent modification of struct sbi_scratch from
 affecting SBI_SCRATCH_xxx_OFFSET
Message-ID: <20220316043514.64181-1-wxjstz@126.com>

Add static detection to prevent the modification of struct sbi_scratch
from forgetting the modification of SBI_SCRATCH_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/sbi_scratch.h | 57 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index 0c27307..a3065e8 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -72,6 +72,63 @@ struct sbi_scratch {
 	/** Options for OpenSBI library */
 	unsigned long options;
 };
+/** Prevent modification of struct sbi_scratch from affecting
+ * SBI_SCRATCH_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_start)
+		== SBI_SCRATCH_FW_START_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_FW_START_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_size)
+		== SBI_SCRATCH_FW_SIZE_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_FW_SIZE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_arg1)
+		== SBI_SCRATCH_NEXT_ARG1_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ARG1_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_addr)
+		== SBI_SCRATCH_NEXT_ADDR_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_mode)
+		== SBI_SCRATCH_NEXT_MODE_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, warmboot_addr)
+		== SBI_SCRATCH_WARMBOOT_ADDR_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_WARMBOOT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, platform_addr)
+		== SBI_SCRATCH_PLATFORM_ADDR_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_PLATFORM_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, hartid_to_scratch)
+		== SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, trap_exit)
+		== SBI_SCRATCH_TRAP_EXIT_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_TRAP_EXIT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, tmp0)
+		== SBI_SCRATCH_TMP0_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_TMP0_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, options)
+		== SBI_SCRATCH_OPTIONS_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_SCRATCH_OPTIONS_OFFSET");
 
 /** Possible options for OpenSBI library */
 enum sbi_scratch_options {
-- 
2.30.2



From wxjstz at 126.com  Tue Mar 15 21:49:42 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 12:49:42 +0800
Subject: [PATCH] sbi: Prevent modification of struct fw_dynamic_info from
 affecting FW_DYNAMIC_INFO_xxx_OFFSET
Message-ID: <20220316044942.66140-1-wxjstz@126.com>

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 include/sbi/fw_dynamic.h | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
index dea207b..e38e688 100644
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -74,7 +74,39 @@ struct fw_dynamic_info {
 	 */
 	unsigned long boot_hart;
 } __packed;
-
+/** Prevent modification of struct fw_dynamic_info from affecting
+ * FW_DYNAMIC_INFO_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct fw_dynamic_info, magic)
+		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, version)
+		== FW_DYNAMIC_INFO_VERSION_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_addr)
+		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_mode)
+		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, options)
+		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, boot_hart)
+		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
+	
 #endif
 
 #endif
-- 
2.30.2



From wxjstz at 126.com  Wed Mar 16 03:16:48 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 18:16:48 +0800
Subject: [PATCH V2] sbi: Prevent modification of struct sbi_scratch from
 affecting SBI_SCRATCH_xxx_OFFSET
Message-ID: <20220316101648.79880-1-wxjstz@126.com>

Add static detection to prevent the modification of struct sbi_scratch
from forgetting the modification of SBI_SCRATCH_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V1 change:
* Modify prompt information

 include/sbi/sbi_scratch.h | 57 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index 0c27307..67b71cd 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -72,6 +72,63 @@ struct sbi_scratch {
 	/** Options for OpenSBI library */
 	unsigned long options;
 };
+/** Prevent modification of struct sbi_scratch from affecting
+ * SBI_SCRATCH_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_start)
+		== SBI_SCRATCH_FW_START_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_FW_START_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_size)
+		== SBI_SCRATCH_FW_SIZE_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_FW_SIZE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_arg1)
+		== SBI_SCRATCH_NEXT_ARG1_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ARG1_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_addr)
+		== SBI_SCRATCH_NEXT_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_mode)
+		== SBI_SCRATCH_NEXT_MODE_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, warmboot_addr)
+		== SBI_SCRATCH_WARMBOOT_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_WARMBOOT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, platform_addr)
+		== SBI_SCRATCH_PLATFORM_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_PLATFORM_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, hartid_to_scratch)
+		== SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, trap_exit)
+		== SBI_SCRATCH_TRAP_EXIT_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_TRAP_EXIT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, tmp0)
+		== SBI_SCRATCH_TMP0_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_TMP0_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, options)
+		== SBI_SCRATCH_OPTIONS_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_OPTIONS_OFFSET");
 
 /** Possible options for OpenSBI library */
 enum sbi_scratch_options {
-- 
2.30.2



From wxjstz at 126.com  Wed Mar 16 03:19:18 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 16 Mar 2022 18:19:18 +0800
Subject: [PATCH V2] sbi: Prevent modification of struct fw_dynamic_info from
 affecting FW_DYNAMIC_INFO_xxx_OFFSET
Message-ID: <20220316101918.80665-1-wxjstz@126.com>

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V1 change:
* Modify prompt information

 include/sbi/fw_dynamic.h | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
index dea207b..978f10b 100644
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -74,6 +74,38 @@ struct fw_dynamic_info {
 	 */
 	unsigned long boot_hart;
 } __packed;
+/** Prevent modification of struct fw_dynamic_info from affecting
+ * FW_DYNAMIC_INFO_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct fw_dynamic_info, magic)
+		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, version)
+		== FW_DYNAMIC_INFO_VERSION_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_addr)
+		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_mode)
+		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, options)
+		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, boot_hart)
+		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
 
 #endif
 
-- 
2.30.2



From mchitale at ventanamicro.com  Sun Mar 20 22:15:25 2022
From: mchitale at ventanamicro.com (Mayuresh Chitale)
Date: Mon, 21 Mar 2022 10:45:25 +0530
Subject: [RFC PATCH v1 0/3] RISC-V Smstateen support
Message-ID: <20220321051528.20143-1-mchitale@ventanamicro.com>

This series adds support for the Smstateen specification which provides
a mechanism to plug potential covert channels which are opened by extensions
which add to processor state that may not get context-switched. Currently
access to AIA registers and *envcfg registers is controlled via
smstateen.

Mayuresh Chitale (3):
  lib: sbi: Add Smstateen extension defines
  lib: sbi: Detect Smstateen CSRs at boot-time
  lib: sbi: configure mstateen

 include/sbi/riscv_encoding.h | 37 ++++++++++++++++++++++++++++++++++++
 include/sbi/sbi_hart.h       |  4 +++-
 lib/sbi/sbi_hart.c           | 29 +++++++++++++++++++++++++++-
 3 files changed, 68 insertions(+), 2 deletions(-)

-- 
2.17.1



From mchitale at ventanamicro.com  Sun Mar 20 22:15:26 2022
From: mchitale at ventanamicro.com (Mayuresh Chitale)
Date: Mon, 21 Mar 2022 10:45:26 +0530
Subject: [RFC PATCH v1 1/3] lib: sbi: Add Smstateen extension defines
In-Reply-To: <20220321051528.20143-1-mchitale@ventanamicro.com>
References: <20220321051528.20143-1-mchitale@ventanamicro.com>
Message-ID: <20220321051528.20143-2-mchitale@ventanamicro.com>

Smstateen extension provides a mechanism to plug potential
covert channels which are opened by extensions that add to
processor state that may not get context-switched.

Signed-off-by: Mayuresh Chitale <mchitale at ventanamicro.com>
---
 include/sbi/riscv_encoding.h | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index cce66dd..fefd3de 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -337,6 +337,12 @@
 #define CSR_SIEH			0x114
 #define CSR_SIPH			0x154
 
+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0       0x10C
+#define CSR_SSTATEEN1       0x10D
+#define CSR_SSTATEEN2       0x10E
+#define CSR_SSTATEEN3       0x10F
+
 /* ===== Hypervisor-level CSRs ===== */
 
 /* Hypervisor Trap Setup (H-extension) */
@@ -401,6 +407,16 @@
 #define CSR_VSIEH			0x214
 #define CSR_VSIPH			0x254
 
+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0       0x60C
+#define CSR_HSTATEEN0H      0x61C
+#define CSR_HSTATEEN1       0x60D
+#define CSR_HSTATEEN1H      0x61D
+#define CSR_HSTATEEN2       0x60E
+#define CSR_HSTATEEN2H      0x61E
+#define CSR_HSTATEEN3       0x60F
+#define CSR_HSTATEEN3H      0x61F
+
 /* ===== Machine-level CSRs ===== */
 
 /* Machine Information Registers */
@@ -674,6 +690,17 @@
 #define CSR_MVIEN			0x308
 #define CSR_MVIP			0x309
 
+/* Smstateen extension registers */
+/* Machine stateen CSRs */
+#define CSR_MSTATEEN0       0x30C
+#define CSR_MSTATEEN0H      0x31C
+#define CSR_MSTATEEN1       0x30D
+#define CSR_MSTATEEN1H      0x31D
+#define CSR_MSTATEEN2       0x30E
+#define CSR_MSTATEEN2H      0x31E
+#define CSR_MSTATEEN3       0x30F
+#define CSR_MSTATEEN3H      0x31F
+
 /* Machine-Level High-Half CSRs (AIA) */
 #define CSR_MIDELEGH			0x313
 #define CSR_MIEH			0x314
@@ -703,6 +730,16 @@
 #define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17
 
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT 4
+#define SMSTATEEN0_CS       0
+#define SMSTATEEN0_FCSR     0
+#define SMSTATEEN0_IMSIC    58
+#define SMSTATEEN0_AIA      59
+#define SMSTATEEN0_SVSLCT   60
+#define SMSTATEEN0_HSENVCFG 62
+#define SMSTATEEN_STATEN    63
+
 /* ===== Instruction Encodings ===== */
 
 #define INSN_MATCH_LB			0x3
-- 
2.17.1



From mchitale at ventanamicro.com  Sun Mar 20 22:15:27 2022
From: mchitale at ventanamicro.com (Mayuresh Chitale)
Date: Mon, 21 Mar 2022 10:45:27 +0530
Subject: [RFC PATCH v1 2/3] lib: sbi: Detect Smstateen CSRs at boot-time
In-Reply-To: <20220321051528.20143-1-mchitale@ventanamicro.com>
References: <20220321051528.20143-1-mchitale@ventanamicro.com>
Message-ID: <20220321051528.20143-3-mchitale@ventanamicro.com>

Extend HART feature detection to discover Smstateen CSRs at boot-time
and configure mstateen envcfg bit depending on availability of
menvcfg CSR.

Signed-off-by: Mayuresh Chitale <mchitale at ventanamicro.com>
---
 include/sbi/sbi_hart.h |  4 +++-
 lib/sbi/sbi_hart.c     | 20 +++++++++++++++++++-
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 93be7ed..b5345f4 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -30,9 +30,11 @@ enum sbi_hart_features {
 	SBI_HART_HAS_MENVCFG = (1 << 6),
 	/** HART has SSTC extension implemented in hardware */
 	SBI_HART_HAS_SSTC = (1 << 7),
+	/** HART has mstateen CSR **/
+	SBI_HART_HAS_SMSTATEEN = (1 << 8),
 
 	/** Last index of Hart features*/
-	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SSTC,
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
 };
 
 struct sbi_scratch;
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 8c9cad2..9d0c435 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -44,6 +44,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
 	unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 	uint64_t mhpmevent_init_val = 0;
 	unsigned long menvcfg_val = 0;
+	unsigned long mstateen_val = 0;
 
 	/* Enable FPU */
 	if (misa_extension('D') || misa_extension('F'))
@@ -72,6 +73,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
 	}
 
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
+		mstateen_val = csr_read(CSR_MSTATEEN0);
+		mstateen_val |= (1UL << SMSTATEEN_STATEN);
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
+			mstateen_val |= (1UL << SMSTATEEN0_HSENVCFG);
+		else
+			mstateen_val &= ~(1UL << SMSTATEEN0_HSENVCFG);
+		csr_write(CSR_MSTATEEN0, mstateen_val);
+	}
+
 	/* Disable user mode usage of all perf counters except default ones (CY, TM, IR) */
 	if (misa_extension('S') &&
 	    sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
@@ -324,6 +335,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
 	case SBI_HART_HAS_SSTC:
 		fstr = "sstc";
 		break;
+	case SBI_HART_HAS_SMSTATEEN:
+		fstr = "smstateen";
+		break;
 	default:
 		break;
 	}
@@ -552,7 +566,6 @@ __mhpm_skip:
 	csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
 	if (!trap.cause)
 		hfeatures->features |= SBI_HART_HAS_MENVCFG;
-
 	/**
 	 * Detect if hart supports stimecmp CSR(Sstc extension) and menvcfg is
 	 * implemented.
@@ -561,6 +574,11 @@ __mhpm_skip:
 	if (!trap.cause && sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
 		hfeatures->features |= SBI_HART_HAS_SSTC;
 
+	/* Detect if hart supports mstateen CSRs */
+	val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
+
 	/* Detect if hart has AIA local interrupt CSRs */
 	csr_read_allowed(CSR_MTOPI, (unsigned long)&trap);
 	if (trap.cause)
-- 
2.17.1



From mchitale at ventanamicro.com  Sun Mar 20 22:15:28 2022
From: mchitale at ventanamicro.com (Mayuresh Chitale)
Date: Mon, 21 Mar 2022 10:45:28 +0530
Subject: [RFC PATCH v1 3/3] lib: sbi: configure mstateen
In-Reply-To: <20220321051528.20143-1-mchitale@ventanamicro.com>
References: <20220321051528.20143-1-mchitale@ventanamicro.com>
Message-ID: <20220321051528.20143-4-mchitale@ventanamicro.com>

When mstateen registers are implemented, the AIA related
configurations need to be done in mstateen for the IMSIC
initialization to succeed.

Signed-off-by: Mayuresh Chitale <mchitale at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 9d0c435..f5c44e1 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -80,6 +80,15 @@ static void mstatus_init(struct sbi_scratch *scratch)
 			mstateen_val |= (1UL << SMSTATEEN0_HSENVCFG);
 		else
 			mstateen_val &= ~(1UL << SMSTATEEN0_HSENVCFG);
+
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
+			mstateen_val |= (1UL << SMSTATEEN0_AIA |
+					1UL << SMSTATEEN0_SVSLCT |
+					1UL << SMSTATEEN0_IMSIC);
+		else
+			mstateen_val &= ~(1UL << SMSTATEEN0_AIA |
+					1UL << SMSTATEEN0_SVSLCT |
+					1UL << SMSTATEEN0_IMSIC);
 		csr_write(CSR_MSTATEEN0, mstateen_val);
 	}
 
-- 
2.17.1



From anup at brainfault.org  Mon Mar 21 05:45:33 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 21 Mar 2022 18:15:33 +0530
Subject: [PATCH 1/3] lib: pmp_set/pmp_get moved errors from runtime to
 compile time
In-Reply-To: <20220315162240.40990-1-wxjstz@126.com>
References: <20220315162240.40990-1-wxjstz@126.com>
Message-ID: <CAAhSdy1pmeBDsv=AD4AYC-Oq1RfMdgtycQcb+hEaKsA3_YZfkw@mail.gmail.com>

On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz at 126.com> wrote:
>
> pmp_set/pmp_get calculates the location of the CSR register separately
> through conditional compilation. In the case of non-32-bit and 64-bit,
> we can report an error directly through #error without putting it at
> runtime
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  lib/sbi/riscv_asm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c
> index 847bdba..5eab1ed 100644
> --- a/lib/sbi/riscv_asm.c
> +++ b/lib/sbi/riscv_asm.c
> @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
>         pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
>         pmpcfg_shift = (n & 7) << 3;
>  #else
> -       return SBI_ENOTSUPP;
> +# error "Unexpected __riscv_xlen"
>  #endif
>         pmpaddr_csr = CSR_PMPADDR0 + n;
>
> @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
>         pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
>         pmpcfg_shift = (n & 7) << 3;
>  #else
> -       return SBI_ENOTSUPP;
> +# error "Unexpected __riscv_xlen"
>  #endif
>         pmpaddr_csr = CSR_PMPADDR0 + n;
>
> --
> 2.30.2
>


From anup at brainfault.org  Mon Mar 21 05:48:50 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 21 Mar 2022 18:18:50 +0530
Subject: [PATCH 2/3] firmware: Fix code for accessing hart_count and
 stack_size to be more flexible
In-Reply-To: <20220315162240.40990-2-wxjstz@126.com>
References: <20220315162240.40990-1-wxjstz@126.com>
 <20220315162240.40990-2-wxjstz@126.com>
Message-ID: <CAAhSdy1qmTazCHYqQ=BNuBnHOFdNvedvGUikLMhAgqqLctU5YQ@mail.gmail.com>

On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz at 126.com> wrote:
>
> lwu exists under the current rv64 and should also exist under the rv128
> in the future, so I modified the conditions of conditional compilation
> so that it can adapt to the future situation
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

The PATCH subject is too long (almost 80 characters). If possible
simplify this.

Otherwise, it looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  firmware/fw_base.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index ab3e1b3..07be4c4 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -259,7 +259,7 @@ _bss_zero:
>          * s8 -> HART Stack Size
>          */
>         lla     a4, platform
> -#if __riscv_xlen == 64
> +#if __riscv_xlen > 32
>         lwu     s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
>         lwu     s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
>  #else
> --
> 2.30.2
>


From anup at brainfault.org  Mon Mar 21 05:50:18 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 21 Mar 2022 18:20:18 +0530
Subject: [PATCH 3/3] lib: Add error messages via conditional compilation
 for the future
In-Reply-To: <20220315162240.40990-3-wxjstz@126.com>
References: <20220315162240.40990-1-wxjstz@126.com>
 <20220315162240.40990-3-wxjstz@126.com>
Message-ID: <CAAhSdy3eJgRTui1fQ=nLuvop8Kw55u7Cb=u2pVtYiDOo1g5e9w@mail.gmail.com>

On Tue, Mar 15, 2022 at 9:53 PM Xiang W <wxjstz at 126.com> wrote:
>
> On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved.
> Through this conditional compile, the corresponding implementation
> can be prompted to be added.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  lib/sbi/sbi_unpriv.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c
> index 4246124..73b530c 100644
> --- a/lib/sbi/sbi_unpriv.c
> +++ b/lib/sbi/sbi_unpriv.c
> @@ -83,7 +83,7 @@ DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
>  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
>  DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
>  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
> -#else
> +#elif __riscv_xlen == 32
>  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
>  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
>
> @@ -112,6 +112,8 @@ void sbi_store_u64(u64 *addr, u64 val,
>         if (trap->cause)
>                 return;
>  }
> +#else
> +# error "Unexpected __riscv_xlen"
>  #endif
>
>  ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
> --
> 2.30.2
>


From anup at brainfault.org  Sat Mar 26 20:29:31 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 08:59:31 +0530
Subject: [PATCH 1/3] lib: pmp_set/pmp_get moved errors from runtime to
 compile time
In-Reply-To: <CAAhSdy1pmeBDsv=AD4AYC-Oq1RfMdgtycQcb+hEaKsA3_YZfkw@mail.gmail.com>
References: <20220315162240.40990-1-wxjstz@126.com>
 <CAAhSdy1pmeBDsv=AD4AYC-Oq1RfMdgtycQcb+hEaKsA3_YZfkw@mail.gmail.com>
Message-ID: <CAAhSdy103FAk6JbW30RjxCm+AvvHwCXZg9gHYS4yYAKheNb1Ww@mail.gmail.com>

On Mon, Mar 21, 2022 at 6:15 PM Anup Patel <anup at brainfault.org> wrote:
>
> On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz at 126.com> wrote:
> >
> > pmp_set/pmp_get calculates the location of the CSR register separately
> > through conditional compilation. In the case of non-32-bit and 64-bit,
> > we can report an error directly through #error without putting it at
> > runtime
> >
> > Signed-off-by: Xiang W <wxjstz at 126.com>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> Regards,
> Anup
>
> > ---
> >  lib/sbi/riscv_asm.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c
> > index 847bdba..5eab1ed 100644
> > --- a/lib/sbi/riscv_asm.c
> > +++ b/lib/sbi/riscv_asm.c
> > @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
> >         pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
> >         pmpcfg_shift = (n & 7) << 3;
> >  #else
> > -       return SBI_ENOTSUPP;
> > +# error "Unexpected __riscv_xlen"
> >  #endif
> >         pmpaddr_csr = CSR_PMPADDR0 + n;
> >
> > @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
> >         pmpcfg_csr   = (CSR_PMPCFG0 + (n >> 2)) & ~1;
> >         pmpcfg_shift = (n & 7) << 3;
> >  #else
> > -       return SBI_ENOTSUPP;
> > +# error "Unexpected __riscv_xlen"
> >  #endif
> >         pmpaddr_csr = CSR_PMPADDR0 + n;
> >
> > --
> > 2.30.2
> >


From anup at brainfault.org  Sat Mar 26 20:29:49 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 08:59:49 +0530
Subject: [PATCH 2/3] firmware: Fix code for accessing hart_count and
 stack_size to be more flexible
In-Reply-To: <CAAhSdy1qmTazCHYqQ=BNuBnHOFdNvedvGUikLMhAgqqLctU5YQ@mail.gmail.com>
References: <20220315162240.40990-1-wxjstz@126.com>
 <20220315162240.40990-2-wxjstz@126.com>
 <CAAhSdy1qmTazCHYqQ=BNuBnHOFdNvedvGUikLMhAgqqLctU5YQ@mail.gmail.com>
Message-ID: <CAAhSdy3Ypa6d1syOTv6s3JjeBdpAvb=YSeqct34H=Y9da8bf_w@mail.gmail.com>

On Mon, Mar 21, 2022 at 6:18 PM Anup Patel <anup at brainfault.org> wrote:
>
> On Tue, Mar 15, 2022 at 9:52 PM Xiang W <wxjstz at 126.com> wrote:
> >
> > lwu exists under the current rv64 and should also exist under the rv128
> > in the future, so I modified the conditions of conditional compilation
> > so that it can adapt to the future situation
> >
> > Signed-off-by: Xiang W <wxjstz at 126.com>
>
> The PATCH subject is too long (almost 80 characters). If possible
> simplify this.
>
> Otherwise, it looks good to me.
>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> Regards,
> Anup
>
> > ---
> >  firmware/fw_base.S | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> > index ab3e1b3..07be4c4 100644
> > --- a/firmware/fw_base.S
> > +++ b/firmware/fw_base.S
> > @@ -259,7 +259,7 @@ _bss_zero:
> >          * s8 -> HART Stack Size
> >          */
> >         lla     a4, platform
> > -#if __riscv_xlen == 64
> > +#if __riscv_xlen > 32
> >         lwu     s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
> >         lwu     s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
> >  #else
> > --
> > 2.30.2
> >


From anup at brainfault.org  Sat Mar 26 20:30:03 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 09:00:03 +0530
Subject: [PATCH 3/3] lib: Add error messages via conditional compilation
 for the future
In-Reply-To: <CAAhSdy3eJgRTui1fQ=nLuvop8Kw55u7Cb=u2pVtYiDOo1g5e9w@mail.gmail.com>
References: <20220315162240.40990-1-wxjstz@126.com>
 <20220315162240.40990-3-wxjstz@126.com>
 <CAAhSdy3eJgRTui1fQ=nLuvop8Kw55u7Cb=u2pVtYiDOo1g5e9w@mail.gmail.com>
Message-ID: <CAAhSdy0MkT2F7QW1oV9bkRUR60tE9cmtTzY2DagEwU2nOm4m+w@mail.gmail.com>

On Mon, Mar 21, 2022 at 6:20 PM Anup Patel <anup at brainfault.org> wrote:
>
> On Tue, Mar 15, 2022 at 9:53 PM Xiang W <wxjstz at 126.com> wrote:
> >
> > On 128-bit machines, sbi_load_xx/sbi_store_xx needs to be improved.
> > Through this conditional compile, the corresponding implementation
> > can be prompted to be added.
> >
> > Signed-off-by: Xiang W <wxjstz at 126.com>
>
> Looks good to me.
>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> Regards,
> Anup
>
> > ---
> >  lib/sbi/sbi_unpriv.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c
> > index 4246124..73b530c 100644
> > --- a/lib/sbi/sbi_unpriv.c
> > +++ b/lib/sbi/sbi_unpriv.c
> > @@ -83,7 +83,7 @@ DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu)
> >  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld)
> >  DEFINE_UNPRIVILEGED_STORE_FUNCTION(u64, sd)
> >  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld)
> > -#else
> > +#elif __riscv_xlen == 32
> >  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw)
> >  DEFINE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw)
> >
> > @@ -112,6 +112,8 @@ void sbi_store_u64(u64 *addr, u64 val,
> >         if (trap->cause)
> >                 return;
> >  }
> > +#else
> > +# error "Unexpected __riscv_xlen"
> >  #endif
> >
> >  ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
> > --
> > 2.30.2
> >


From anup at brainfault.org  Sat Mar 26 21:27:56 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 09:57:56 +0530
Subject: [PATCH] sbi: Prevent modification of struct sbi_platform from
 affecting SBI_PLATFORM_xxx_OFFSET
In-Reply-To: <20220316014525.57326-1-wxjstz@126.com>
References: <20220316014525.57326-1-wxjstz@126.com>
Message-ID: <CAAhSdy3E=BSW9kta4UAySqNar8PfSEKG5s1YHUyOVZ8E9coBbQ@mail.gmail.com>

On Wed, Mar 16, 2022 at 7:15 AM Xiang W <wxjstz at 126.com> wrote:
>
> Add static detection to prevent the modification of struct sbi_platform
> from forgetting the modification of SBI_PLATFORM_xxx_OFFSET
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Please use a shorter patch subject and "include: " prefix.

> ---
>  include/sbi/sbi_platform.h | 48 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
>
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 0b5ae4b..87b582e 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -175,6 +175,54 @@ struct sbi_platform {
>         const u32 *hart_index2id;
>  };
>
> +/** Prevent modification of struct sbi_platform from affecting
> + * SBI_PLATFORM_xxx_OFFSET */

This comment block should follow multi-line comment block style
/**
 *  __ xyz __
 */

> +_Static_assert(
> +       offsetof(struct sbi_platform, opensbi_version)
> +               == SBI_PLATFORM_OPENSBI_VERSION_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_OPENSBI_VERSION_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, platform_version)
> +               == SBI_PLATFORM_VERSION_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_VERSION_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, name)
> +               == SBI_PLATFORM_NAME_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_NAME_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, features)
> +               == SBI_PLATFORM_FEATURES_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_FEATURES_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, hart_count)
> +               == SBI_PLATFORM_HART_COUNT_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_HART_COUNT_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, hart_stack_size)
> +               == SBI_PLATFORM_HART_STACK_SIZE_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_HART_STACK_SIZE_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, platform_ops_addr)
> +               == SBI_PLATFORM_OPS_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_OPS_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, firmware_context)
> +               == SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_platform, hart_index2id)
> +               == SBI_PLATFORM_HART_INDEX2ID_OFFSET,
> +       "struct sbi_platform definition has changed, please redefine "
> +       "SBI_PLATFORM_HART_INDEX2ID_OFFSET");
> +
>  /** Get pointer to sbi_platform for sbi_scratch pointer */
>  #define sbi_platform_ptr(__s) \
>         ((const struct sbi_platform *)((__s)->platform_addr))
> --
> 2.30.2
>

Otherwise, this looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

I have taken care of the above comments at the time of merging
this patch.

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From anup at brainfault.org  Sat Mar 26 21:29:55 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 09:59:55 +0530
Subject: [PATCH V2] sbi: Prevent modification of struct sbi_scratch from
 affecting SBI_SCRATCH_xxx_OFFSET
In-Reply-To: <20220316101648.79880-1-wxjstz@126.com>
References: <20220316101648.79880-1-wxjstz@126.com>
Message-ID: <CAAhSdy17Qt50U4iAtxMbF0UBiA4d1z3fTBaim7qEvpT9xJKEdA@mail.gmail.com>

On Wed, Mar 16, 2022 at 3:47 PM Xiang W <wxjstz at 126.com> wrote:
>
> Add static detection to prevent the modification of struct sbi_scratch
> from forgetting the modification of SBI_SCRATCH_xxx_OFFSET
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
> V1 change:
> * Modify prompt information

Please use a shorter patch subject and "include: " prefix.

>
>  include/sbi/sbi_scratch.h | 57 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
>
> diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> index 0c27307..67b71cd 100644
> --- a/include/sbi/sbi_scratch.h
> +++ b/include/sbi/sbi_scratch.h
> @@ -72,6 +72,63 @@ struct sbi_scratch {
>         /** Options for OpenSBI library */
>         unsigned long options;
>  };
> +/** Prevent modification of struct sbi_scratch from affecting
> + * SBI_SCRATCH_xxx_OFFSET */

This comment block should follow multi-line comment block style
/**
 *  __ xyz __
 */

> +_Static_assert(
> +       offsetof(struct sbi_scratch, fw_start)
> +               == SBI_SCRATCH_FW_START_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_FW_START_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, fw_size)
> +               == SBI_SCRATCH_FW_SIZE_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_FW_SIZE_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, next_arg1)
> +               == SBI_SCRATCH_NEXT_ARG1_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_NEXT_ARG1_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, next_addr)
> +               == SBI_SCRATCH_NEXT_ADDR_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_NEXT_ADDR_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, next_mode)
> +               == SBI_SCRATCH_NEXT_MODE_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_NEXT_MODE_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, warmboot_addr)
> +               == SBI_SCRATCH_WARMBOOT_ADDR_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_WARMBOOT_ADDR_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, platform_addr)
> +               == SBI_SCRATCH_PLATFORM_ADDR_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_PLATFORM_ADDR_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, hartid_to_scratch)
> +               == SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, trap_exit)
> +               == SBI_SCRATCH_TRAP_EXIT_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_TRAP_EXIT_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, tmp0)
> +               == SBI_SCRATCH_TMP0_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_TMP0_OFFSET");
> +_Static_assert(
> +       offsetof(struct sbi_scratch, options)
> +               == SBI_SCRATCH_OPTIONS_OFFSET,
> +       "struct sbi_scratch definition has changed, please redefine "
> +       "SBI_SCRATCH_OPTIONS_OFFSET");
>
>  /** Possible options for OpenSBI library */
>  enum sbi_scratch_options {
> --
> 2.30.2
>

Otherwise, this looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

I have taken care of the above comments at the time of merging
this patch.

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From anup at brainfault.org  Sat Mar 26 21:30:49 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 10:00:49 +0530
Subject: [PATCH V2] sbi: Prevent modification of struct fw_dynamic_info
 from affecting FW_DYNAMIC_INFO_xxx_OFFSET
In-Reply-To: <20220316101918.80665-1-wxjstz@126.com>
References: <20220316101918.80665-1-wxjstz@126.com>
Message-ID: <CAAhSdy2_pv220eB6myDPW0vw+hiZOACQTpg-5pa8czbC7_kGMQ@mail.gmail.com>

On Wed, Mar 16, 2022 at 3:50 PM Xiang W <wxjstz at 126.com> wrote:
>
> Add static detection to prevent the modification of struct fw_dynamic_info
> from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
> V1 change:
> * Modify prompt information

Please use a shorter patch subject and "include: " prefix.

>
>  include/sbi/fw_dynamic.h | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
>
> diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
> index dea207b..978f10b 100644
> --- a/include/sbi/fw_dynamic.h
> +++ b/include/sbi/fw_dynamic.h
> @@ -74,6 +74,38 @@ struct fw_dynamic_info {
>          */
>         unsigned long boot_hart;
>  } __packed;
> +/** Prevent modification of struct fw_dynamic_info from affecting
> + * FW_DYNAMIC_INFO_xxx_OFFSET */

This comment block should follow multi-line comment block style
/**
 *  __ xyz __
 */

> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, magic)
> +               == FW_DYNAMIC_INFO_MAGIC_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_MAGIC_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, version)
> +               == FW_DYNAMIC_INFO_VERSION_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_VERSION_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, next_addr)
> +               == FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, next_mode)
> +               == FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, options)
> +               == FW_DYNAMIC_INFO_OPTIONS_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_OPTIONS_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, boot_hart)
> +               == FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
>
>  #endif
>
> --
> 2.30.2
>

Otherwise, this looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

I have taken care of the above comments at the time of merging
this patch.

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From wxjstz at 126.com  Sun Mar 27 01:22:13 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 27 Mar 2022 16:22:13 +0800
Subject: [PATCH V3] include: Add check for offset fw_dynamic_info
Message-ID: <20220327082213.65469-1-wxjstz@126.com>

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V3 change:
* reword commit message

 include/sbi/fw_dynamic.h | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
index dea207b..978f10b 100644
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -74,6 +74,38 @@ struct fw_dynamic_info {
 	 */
 	unsigned long boot_hart;
 } __packed;
+/** Prevent modification of struct fw_dynamic_info from affecting
+ * FW_DYNAMIC_INFO_xxx_OFFSET */
+_Static_assert(
+	offsetof(struct fw_dynamic_info, magic)
+		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, version)
+		== FW_DYNAMIC_INFO_VERSION_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_addr)
+		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_mode)
+		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, options)
+		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, boot_hart)
+		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
 
 #endif
 
-- 
2.30.2



From wxjstz at 126.com  Sun Mar 27 01:25:20 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 27 Mar 2022 16:25:20 +0800
Subject: [PATCH V4] include: Add check for offset fw_dynamic_info
Message-ID: <20220327082520.66613-1-wxjstz@126.com>

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V4 change:
* comment style change

 include/sbi/fw_dynamic.h | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
index dea207b..d007b05 100644
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -74,6 +74,40 @@ struct fw_dynamic_info {
 	 */
 	unsigned long boot_hart;
 } __packed;
+/**
+ * Prevent modification of struct fw_dynamic_info from affecting
+ * FW_DYNAMIC_INFO_xxx_OFFSET
+ */
+_Static_assert(
+	offsetof(struct fw_dynamic_info, magic)
+		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, version)
+		== FW_DYNAMIC_INFO_VERSION_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_addr)
+		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_mode)
+		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, options)
+		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, boot_hart)
+		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
 
 #endif
 
-- 
2.30.2



From wxjstz at 126.com  Sun Mar 27 01:29:43 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 27 Mar 2022 16:29:43 +0800
Subject: [PATCH V5] include: Add check for offset of fw_dynamic_info
Message-ID: <20220327082943.66976-1-wxjstz@126.com>

Add static detection to prevent the modification of struct fw_dynamic_info
from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V5 change:
* reword commit message

I'm sorry for my careless, change to much

 include/sbi/fw_dynamic.h | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
index dea207b..d007b05 100644
--- a/include/sbi/fw_dynamic.h
+++ b/include/sbi/fw_dynamic.h
@@ -74,6 +74,40 @@ struct fw_dynamic_info {
 	 */
 	unsigned long boot_hart;
 } __packed;
+/**
+ * Prevent modification of struct fw_dynamic_info from affecting
+ * FW_DYNAMIC_INFO_xxx_OFFSET
+ */
+_Static_assert(
+	offsetof(struct fw_dynamic_info, magic)
+		== FW_DYNAMIC_INFO_MAGIC_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_MAGIC_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, version)
+		== FW_DYNAMIC_INFO_VERSION_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_addr)
+		== FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, next_mode)
+		== FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, options)
+		== FW_DYNAMIC_INFO_OPTIONS_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_OPTIONS_OFFSET");
+_Static_assert(
+	offsetof(struct fw_dynamic_info, boot_hart)
+		== FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
+	"struct fw_dynamic_info definition has changed, please redefine "
+	"FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
 
 #endif
 
-- 
2.30.2



From wxjstz at 126.com  Sun Mar 27 01:33:59 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 27 Mar 2022 16:33:59 +0800
Subject: [PATCH V3] include: Add check for offset of sbi_scratch
Message-ID: <20220327083359.67711-1-wxjstz@126.com>

Add static detection to prevent the modification of struct sbi_scratch
from forgetting the modification of SBI_SCRATCH_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V3 change:
* reword commit message
* change comment style

 include/sbi/sbi_scratch.h | 59 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index 0c27307..b08cdea 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -72,6 +72,65 @@ struct sbi_scratch {
 	/** Options for OpenSBI library */
 	unsigned long options;
 };
+/**
+ * Prevent modification of struct sbi_scratch from affecting
+ * SBI_SCRATCH_xxx_OFFSET 
+ */
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_start)
+		== SBI_SCRATCH_FW_START_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_FW_START_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, fw_size)
+		== SBI_SCRATCH_FW_SIZE_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_FW_SIZE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_arg1)
+		== SBI_SCRATCH_NEXT_ARG1_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ARG1_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_addr)
+		== SBI_SCRATCH_NEXT_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, next_mode)
+		== SBI_SCRATCH_NEXT_MODE_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_NEXT_MODE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, warmboot_addr)
+		== SBI_SCRATCH_WARMBOOT_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_WARMBOOT_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, platform_addr)
+		== SBI_SCRATCH_PLATFORM_ADDR_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_PLATFORM_ADDR_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, hartid_to_scratch)
+		== SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, trap_exit)
+		== SBI_SCRATCH_TRAP_EXIT_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_TRAP_EXIT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, tmp0)
+		== SBI_SCRATCH_TMP0_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_TMP0_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_scratch, options)
+		== SBI_SCRATCH_OPTIONS_OFFSET,
+	"struct sbi_scratch definition has changed, please redefine "
+	"SBI_SCRATCH_OPTIONS_OFFSET");
 
 /** Possible options for OpenSBI library */
 enum sbi_scratch_options {
-- 
2.30.2



From wxjstz at 126.com  Sun Mar 27 01:36:05 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 27 Mar 2022 16:36:05 +0800
Subject: [PATCH V2] include: Add check for offset of sbi_platform
Message-ID: <20220327083605.68218-1-wxjstz@126.com>

Add static detection to prevent the modification of struct sbi_platform
from forgetting the modification of SBI_PLATFORM_xxx_OFFSET

Signed-off-by: Xiang W <wxjstz at 126.com>
---
V2 change:
* reword commit message
* change comment style

 include/sbi/sbi_platform.h | 50 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 0b5ae4b..2c777ac 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -175,6 +175,56 @@ struct sbi_platform {
 	const u32 *hart_index2id;
 };
 
+/**
+ * Prevent modification of struct sbi_platform from affecting
+ * SBI_PLATFORM_xxx_OFFSET
+ */
+_Static_assert(
+	offsetof(struct sbi_platform, opensbi_version)
+		== SBI_PLATFORM_OPENSBI_VERSION_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_OPENSBI_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, platform_version)
+		== SBI_PLATFORM_VERSION_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_VERSION_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, name)
+		== SBI_PLATFORM_NAME_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_NAME_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, features)
+		== SBI_PLATFORM_FEATURES_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_FEATURES_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_count)
+		== SBI_PLATFORM_HART_COUNT_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_COUNT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_stack_size)
+		== SBI_PLATFORM_HART_STACK_SIZE_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_STACK_SIZE_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, platform_ops_addr)
+		== SBI_PLATFORM_OPS_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_OPS_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, firmware_context)
+		== SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET");
+_Static_assert(
+	offsetof(struct sbi_platform, hart_index2id)
+		== SBI_PLATFORM_HART_INDEX2ID_OFFSET,
+	"struct sbi_platform definition has changed, please redefine "
+	"SBI_PLATFORM_HART_INDEX2ID_OFFSET");
+
 /** Get pointer to sbi_platform for sbi_scratch pointer */
 #define sbi_platform_ptr(__s) \
 	((const struct sbi_platform *)((__s)->platform_addr))
-- 
2.30.2



From anup at brainfault.org  Sun Mar 27 08:29:54 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 27 Mar 2022 20:59:54 +0530
Subject: [PATCH V4] include: Add check for offset fw_dynamic_info
In-Reply-To: <20220327082520.66613-1-wxjstz@126.com>
References: <20220327082520.66613-1-wxjstz@126.com>
Message-ID: <CAAhSdy1Vt9nWcsSekE4=2R9AZgiixiNqoE8wEy4Da1tidAH5Vg@mail.gmail.com>

On Sun, Mar 27, 2022 at 1:55 PM Xiang W <wxjstz at 126.com> wrote:
>
> Add static detection to prevent the modification of struct fw_dynamic_info
> from forgetting the modification of FW_DYNAMIC_INFO_xxx_OFFSET
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
> V4 change:
> * comment style change

This and other patches adding static_assert() are already merged.

Regards,
Anup

>
>  include/sbi/fw_dynamic.h | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>
> diff --git a/include/sbi/fw_dynamic.h b/include/sbi/fw_dynamic.h
> index dea207b..d007b05 100644
> --- a/include/sbi/fw_dynamic.h
> +++ b/include/sbi/fw_dynamic.h
> @@ -74,6 +74,40 @@ struct fw_dynamic_info {
>          */
>         unsigned long boot_hart;
>  } __packed;
> +/**
> + * Prevent modification of struct fw_dynamic_info from affecting
> + * FW_DYNAMIC_INFO_xxx_OFFSET
> + */
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, magic)
> +               == FW_DYNAMIC_INFO_MAGIC_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_MAGIC_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, version)
> +               == FW_DYNAMIC_INFO_VERSION_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_VERSION_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, next_addr)
> +               == FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, next_mode)
> +               == FW_DYNAMIC_INFO_NEXT_MODE_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_NEXT_MODE_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, options)
> +               == FW_DYNAMIC_INFO_OPTIONS_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_OPTIONS_OFFSET");
> +_Static_assert(
> +       offsetof(struct fw_dynamic_info, boot_hart)
> +               == FW_DYNAMIC_INFO_BOOT_HART_OFFSET,
> +       "struct fw_dynamic_info definition has changed, please redefine "
> +       "FW_DYNAMIC_INFO_BOOT_HART_OFFSET");
>
>  #endif
>
> --
> 2.30.2
>


From apatel at ventanamicro.com  Tue Mar 29 08:52:14 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 29 Mar 2022 21:22:14 +0530
Subject: [PATCH 0/4] Configure Zicbo[m|z] and Svpbmt in menvcfg CSR
Message-ID: <20220329155218.118580-1-apatel@ventanamicro.com>

Lower privilege modes (S and U) can use Zicbo[m|z] and Svpbmt extensions
only if these extensions are configured/enabled by M-mode firmware hence
this series.

The PATCH2 is adapted from Atish's Sstc series to avoid duplicate work.

These patches can be found in pbmt_cbo_v1 branch at:
https://github.com/avpatel/opensbi.git

Anup Patel (3):
  include: Add defines for [m|h|s]envcfg CSRs
  lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR
  lib: sbi: Enable Svpbmt extension in the menvcfg CSR

Atish Patra (1):
  lib: sbi: Detect menvcfg CSR at boot time

 include/sbi/riscv_encoding.h | 27 +++++++++++++++++++
 include/sbi/sbi_hart.h       |  4 ++-
 lib/sbi/sbi_hart.c           | 52 +++++++++++++++++++++++++++++++++++-
 3 files changed, 81 insertions(+), 2 deletions(-)

-- 
2.25.1



From apatel at ventanamicro.com  Tue Mar 29 08:52:15 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 29 Mar 2022 21:22:15 +0530
Subject: [PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs
In-Reply-To: <20220329155218.118580-1-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
Message-ID: <20220329155218.118580-2-apatel@ventanamicro.com>

The latest RISC-V privileged specification introduces xenvcfg CSRs
to enable/disable certain features/extensions for lower privilege
modes. This patch adds defines for these new [m|h|s]envcfg CSRs.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 574d1c3..c02aa8f 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -203,6 +203,22 @@
 
 #define MHPMEVENT_SSCOF_MASK		_ULL(0xFFFF000000000000)
 
+#if __riscv_xlen > 32
+#define ENVCFG_STCE			(_ULL(1) << 63)
+#define ENVCFG_PBMTE			(_ULL(1) << 62)
+#else
+#define ENVCFGH_STCE			(_UL(1) << 31)
+#define ENVCFGH_PBMTE			(_UL(1) << 30)
+#endif
+#define ENVCFG_CBZE			(_UL(1) << 7)
+#define ENVCFG_CBCFE			(_UL(1) << 6)
+#define ENVCFG_CBIE_SHIFT		4
+#define ENVCFG_CBIE			(_UL(0x3) << ENVCFG_CBIE_SHIFT)
+#define ENVCFG_CBIE_ILL			_UL(0x0)
+#define ENVCFG_CBIE_FLUSH		_UL(0x1)
+#define ENVCFG_CBIE_INV			_UL(0x3)
+#define ENVCFG_FIOM			_UL(0x1)
+
 /* ===== User-level CSRs ===== */
 
 /* User Trap Setup (N-extension) */
@@ -298,6 +314,9 @@
 #define CSR_STVEC			0x105
 #define CSR_SCOUNTEREN			0x106
 
+/* Supervisor Configuration */
+#define CSR_SENVCFG			0x10a
+
 /* Supervisor Trap Handling */
 #define CSR_SSCRATCH			0x140
 #define CSR_SEPC			0x141
@@ -336,6 +355,10 @@
 #define CSR_HCOUNTEREN			0x606
 #define CSR_HGEIE			0x607
 
+/* Hypervisor Configuration */
+#define CSR_HENVCFG			0x60a
+#define CSR_HENVCFGH			0x61a
+
 /* Hypervisor Trap Handling (H-extension) */
 #define CSR_HTVAL			0x643
 #define CSR_HIP				0x644
@@ -408,6 +431,10 @@
 #define CSR_MCOUNTEREN			0x306
 #define CSR_MSTATUSH			0x310
 
+/* Machine Configuration */
+#define CSR_MENVCFG			0x30a
+#define CSR_MENVCFGH			0x31a
+
 /* Machine Trap Handling */
 #define CSR_MSCRATCH			0x340
 #define CSR_MEPC			0x341
-- 
2.25.1



From apatel at ventanamicro.com  Tue Mar 29 08:52:16 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 29 Mar 2022 21:22:16 +0530
Subject: [PATCH 2/4] lib: sbi: Detect menvcfg CSR at boot time
In-Reply-To: <20220329155218.118580-1-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
Message-ID: <20220329155218.118580-3-apatel@ventanamicro.com>

From: Atish Patra <atishp at rivosinc.com>

We add the menvcfg CSR as a HART feature and detect it at boot time
using traping mechanism.

Signed-off-by: Atish Patra <atishp at rivosinc.com>
Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_hart.h | 4 +++-
 lib/sbi/sbi_hart.c     | 9 +++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index a83b45b..57f80bc 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -26,9 +26,11 @@ enum sbi_hart_features {
 	SBI_HART_HAS_TIME = (1 << 4),
 	/** HART has AIA local interrupt CSRs */
 	SBI_HART_HAS_AIA = (1 << 5),
+	/** HART has menvcfg CSR */
+	SBI_HART_HAS_MENVCFG = (1 << 6),
 
 	/** Last index of Hart features*/
-	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_AIA,
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
 };
 
 struct sbi_scratch;
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index e028540..31c8f39 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -304,6 +304,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
 	case SBI_HART_HAS_AIA:
 		fstr = "aia";
 		break;
+	case SBI_HART_HAS_MENVCFG:
+		fstr = "menvcfg";
+		break;
 	default:
 		break;
 	}
@@ -534,6 +537,12 @@ __mhpm_skip:
 		goto __aia_skip;
 	hfeatures->features |= SBI_HART_HAS_AIA;
 __aia_skip:
+
+	/* Detect if hart has menvcfg CSR */
+	csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_MENVCFG;
+
 	return;
 }
 
-- 
2.25.1



From apatel at ventanamicro.com  Tue Mar 29 08:52:17 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 29 Mar 2022 21:22:17 +0530
Subject: [PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR
In-Reply-To: <20220329155218.118580-1-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
Message-ID: <20220329155218.118580-4-apatel@ventanamicro.com>

The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
CSR are WARL. We try to enable these bits irrespective whether
these extensions are available or not because writes to these
bits will be ignored if these extensions are not available.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 31c8f39..d2c7aba 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
 
 static void mstatus_init(struct sbi_scratch *scratch)
 {
-	unsigned long mstatus_val = 0;
+	unsigned long menvcfg_val, mstatus_val = 0;
 	int cidx;
 	unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 	uint64_t mhpmevent_init_val = 0;
@@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		csr_write_num(CSR_MHPMEVENT3 + cidx, mhpmevent_init_val);
 #endif
 	}
+
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
+		menvcfg_val = csr_read(CSR_MENVCFG);
+
+		/*
+		 * Set menvcfg.CBZE == 1
+		 *
+		 * If Zicboz extension is not available then writes to
+		 * menvcfg.CBZE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBZE;
+
+		/*
+		 * Set menvcfg.CBCFE == 1
+		 *
+		 * If Zicbom extension is not available then writes to
+		 * menvcfg.CBCFE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBCFE;
+
+		/*
+		 * Set menvcfg.CBIE == 3
+		 *
+		 * If Zicbom extension is not available then writes to
+		 * menvcfg.CBIE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
+
+		csr_write(CSR_MENVCFG, menvcfg_val);
+	}
+
 	/* Disable all interrupts */
 	csr_write(CSR_MIE, 0);
 
-- 
2.25.1



From apatel at ventanamicro.com  Tue Mar 29 08:52:18 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 29 Mar 2022 21:22:18 +0530
Subject: [PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR
In-Reply-To: <20220329155218.118580-1-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
Message-ID: <20220329155218.118580-5-apatel@ventanamicro.com>

The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
available so we try to enable menvcfg.PBMTE bit irrespective whether
Svpbmt is available or not.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index d2c7aba..6be9286 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		 */
 		menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
 
+		/*
+		 * Set menvcfg.PBMTE == 1 for RV64 or RV128
+		 *
+		 * If Svpbmt extension is not available then menvcfg.PBMTE
+		 * will be read-only zero.
+		 */
+#if __riscv_xlen > 32
+		menvcfg_val |= ENVCFG_PBMTE;
+#endif
+
 		csr_write(CSR_MENVCFG, menvcfg_val);
 	}
 
-- 
2.25.1



From atishp at atishpatra.org  Tue Mar 29 16:48:46 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Tue, 29 Mar 2022 16:48:46 -0700
Subject: [PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs
In-Reply-To: <20220329155218.118580-2-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-2-apatel@ventanamicro.com>
Message-ID: <CAOnJCU+nGAtMimB3gFOQhDn6bMLJH=ujKOdFZuorXnzQe4EyBw@mail.gmail.com>

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> The latest RISC-V privileged specification introduces xenvcfg CSRs
> to enable/disable certain features/extensions for lower privilege
> modes. This patch adds defines for these new [m|h|s]envcfg CSRs.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 574d1c3..c02aa8f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -203,6 +203,22 @@
>
>  #define MHPMEVENT_SSCOF_MASK           _ULL(0xFFFF000000000000)
>
> +#if __riscv_xlen > 32
> +#define ENVCFG_STCE                    (_ULL(1) << 63)
> +#define ENVCFG_PBMTE                   (_ULL(1) << 62)
> +#else
> +#define ENVCFGH_STCE                   (_UL(1) << 31)
> +#define ENVCFGH_PBMTE                  (_UL(1) << 30)
> +#endif
> +#define ENVCFG_CBZE                    (_UL(1) << 7)
> +#define ENVCFG_CBCFE                   (_UL(1) << 6)
> +#define ENVCFG_CBIE_SHIFT              4
> +#define ENVCFG_CBIE                    (_UL(0x3) << ENVCFG_CBIE_SHIFT)
> +#define ENVCFG_CBIE_ILL                        _UL(0x0)
> +#define ENVCFG_CBIE_FLUSH              _UL(0x1)
> +#define ENVCFG_CBIE_INV                        _UL(0x3)
> +#define ENVCFG_FIOM                    _UL(0x1)
> +
>  /* ===== User-level CSRs ===== */
>
>  /* User Trap Setup (N-extension) */
> @@ -298,6 +314,9 @@
>  #define CSR_STVEC                      0x105
>  #define CSR_SCOUNTEREN                 0x106
>
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG                    0x10a
> +
>  /* Supervisor Trap Handling */
>  #define CSR_SSCRATCH                   0x140
>  #define CSR_SEPC                       0x141
> @@ -336,6 +355,10 @@
>  #define CSR_HCOUNTEREN                 0x606
>  #define CSR_HGEIE                      0x607
>
> +/* Hypervisor Configuration */
> +#define CSR_HENVCFG                    0x60a
> +#define CSR_HENVCFGH                   0x61a
> +
>  /* Hypervisor Trap Handling (H-extension) */
>  #define CSR_HTVAL                      0x643
>  #define CSR_HIP                                0x644
> @@ -408,6 +431,10 @@
>  #define CSR_MCOUNTEREN                 0x306
>  #define CSR_MSTATUSH                   0x310
>
> +/* Machine Configuration */
> +#define CSR_MENVCFG                    0x30a
> +#define CSR_MENVCFGH                   0x31a
> +
>  /* Machine Trap Handling */
>  #define CSR_MSCRATCH                   0x340
>  #define CSR_MEPC                       0x341
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp at rivosinc.com>

--
Regards,
Atish


From atishp at atishpatra.org  Tue Mar 29 17:04:46 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Tue, 29 Mar 2022 17:04:46 -0700
Subject: [PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg
 CSR
In-Reply-To: <20220329155218.118580-4-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-4-apatel@ventanamicro.com>
Message-ID: <CAOnJCUKi_64Qon0s0983gwgA6TZRN=0YEBn_gOUY0JjALVkgPQ@mail.gmail.com>

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
> CSR are WARL. We try to enable these bits irrespective whether
> these extensions are available or not because writes to these
> bits will be ignored if these extensions are not available.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 31c8f39..d2c7aba 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
>
>  static void mstatus_init(struct sbi_scratch *scratch)
>  {
> -       unsigned long mstatus_val = 0;
> +       unsigned long menvcfg_val, mstatus_val = 0;
>         int cidx;
>         unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
>         uint64_t mhpmevent_init_val = 0;
> @@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                 csr_write_num(CSR_MHPMEVENT3 + cidx, mhpmevent_init_val);
>  #endif
>         }
> +
> +       if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> +               menvcfg_val = csr_read(CSR_MENVCFG);
> +
> +               /*
> +                * Set menvcfg.CBZE == 1
> +                *
> +                * If Zicboz extension is not available then writes to
> +                * menvcfg.CBZE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBZE;
> +
> +               /*
> +                * Set menvcfg.CBCFE == 1
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBCFE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBCFE;
> +
> +               /*
> +                * Set menvcfg.CBIE == 3
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBIE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> +
> +               csr_write(CSR_MENVCFG, menvcfg_val);
> +       }
> +
>         /* Disable all interrupts */
>         csr_write(CSR_MIE, 0);
>
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp at rivosinc.com>

--
Regards,
Atish


From atishp at atishpatra.org  Tue Mar 29 17:04:58 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Tue, 29 Mar 2022 17:04:58 -0700
Subject: [PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR
In-Reply-To: <20220329155218.118580-5-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-5-apatel@ventanamicro.com>
Message-ID: <CAOnJCUJuYXY1S6SZU+tCKiEHPe=30M_6EzKxZVoiKn4dsUiy9A@mail.gmail.com>

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel at ventanamicro.com> wrote:
>
> The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
> available so we try to enable menvcfg.PBMTE bit irrespective whether
> Svpbmt is available or not.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/sbi/sbi_hart.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d2c7aba..6be9286 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                  */
>                 menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
>
> +               /*
> +                * Set menvcfg.PBMTE == 1 for RV64 or RV128
> +                *
> +                * If Svpbmt extension is not available then menvcfg.PBMTE
> +                * will be read-only zero.
> +                */
> +#if __riscv_xlen > 32
> +               menvcfg_val |= ENVCFG_PBMTE;
> +#endif
> +
>                 csr_write(CSR_MENVCFG, menvcfg_val);
>         }
>
> --
> 2.25.1
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>
-- 
Regards,
Atish


From wxjstz at 126.com  Wed Mar 30 07:48:07 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 30 Mar 2022 22:48:07 +0800
Subject: [PATCH 2/4] lib: sbi: Detect menvcfg CSR at boot time
In-Reply-To: <20220329155218.118580-3-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-3-apatel@ventanamicro.com>
Message-ID: <2f5a96a2e21dcad86d3570c7dc7bab4f16aae146.camel@126.com>

? 2022-03-29???? 21:22 +0530?Anup Patel???
> From: Atish Patra <atishp at rivosinc.com>
> 
> We add the menvcfg CSR as a HART feature and detect it at boot time
> using traping mechanism.
> 
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>

Regards,
Xiang W
> ---
> ?include/sbi/sbi_hart.h | 4 +++-
> ?lib/sbi/sbi_hart.c???? | 9 +++++++++
> ?2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index a83b45b..57f80bc 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -26,9 +26,11 @@ enum sbi_hart_features {
> ????????SBI_HART_HAS_TIME = (1 << 4),
> ????????/** HART has AIA local interrupt CSRs */
> ????????SBI_HART_HAS_AIA = (1 << 5),
> +???????/** HART has menvcfg CSR */
> +???????SBI_HART_HAS_MENVCFG = (1 << 6),
> ?
> ????????/** Last index of Hart features*/
> -???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_AIA,
> +???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
> ?};
> ?
> ?struct sbi_scratch;
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index e028540..31c8f39 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -304,6 +304,9 @@ static inline char
> *sbi_hart_feature_id2string(unsigned long feature)
> ????????case SBI_HART_HAS_AIA:
> ????????????????fstr = "aia";
> ????????????????break;
> +???????case SBI_HART_HAS_MENVCFG:
> +???????????????fstr = "menvcfg";
> +???????????????break;
> ????????default:
> ????????????????break;
> ????????}
> @@ -534,6 +537,12 @@ __mhpm_skip:
> ????????????????goto __aia_skip;
> ????????hfeatures->features |= SBI_HART_HAS_AIA;
> ?__aia_skip:
> +
> +???????/* Detect if hart has menvcfg CSR */
> +???????csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
> +???????if (!trap.cause)
> +???????????????hfeatures->features |= SBI_HART_HAS_MENVCFG;
> +
> ????????return;
> ?}
> ?
> -- 
> 2.25.1
> 
> 




From wxjstz at 126.com  Wed Mar 30 07:47:25 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 30 Mar 2022 22:47:25 +0800
Subject: [PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs
In-Reply-To: <20220329155218.118580-2-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-2-apatel@ventanamicro.com>
Message-ID: <4729d098859cea0c77a5105b085d33bd156f0275.camel@126.com>

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The latest RISC-V privileged specification introduces xenvcfg CSRs
> to enable/disable certain features/extensions for lower privilege
> modes. This patch adds defines for these new [m|h|s]envcfg CSRs.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>

Regards,
Xiang W
> ---
> ?include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
> ?1 file changed, 27 insertions(+)
> 
> diff --git a/include/sbi/riscv_encoding.h
> b/include/sbi/riscv_encoding.h
> index 574d1c3..c02aa8f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -203,6 +203,22 @@
> ?
> ?#define MHPMEVENT_SSCOF_MASK???????????_ULL(0xFFFF000000000000)
> ?
> +#if __riscv_xlen > 32
> +#define ENVCFG_STCE????????????????????(_ULL(1) << 63)
> +#define ENVCFG_PBMTE???????????????????(_ULL(1) << 62)
> +#else
> +#define ENVCFGH_STCE???????????????????(_UL(1) << 31)
> +#define ENVCFGH_PBMTE??????????????????(_UL(1) << 30)
> +#endif
> +#define ENVCFG_CBZE????????????????????(_UL(1) << 7)
> +#define ENVCFG_CBCFE???????????????????(_UL(1) << 6)
> +#define ENVCFG_CBIE_SHIFT??????????????4
> +#define ENVCFG_CBIE????????????????????(_UL(0x3) <<
> ENVCFG_CBIE_SHIFT)
> +#define ENVCFG_CBIE_ILL????????????????????????_UL(0x0)
> +#define ENVCFG_CBIE_FLUSH??????????????_UL(0x1)
> +#define ENVCFG_CBIE_INV????????????????????????_UL(0x3)
> +#define ENVCFG_FIOM????????????????????_UL(0x1)
> +
> ?/* ===== User-level CSRs ===== */
> ?
> ?/* User Trap Setup (N-extension) */
> @@ -298,6 +314,9 @@
> ?#define CSR_STVEC??????????????????????0x105
> ?#define CSR_SCOUNTEREN?????????????????0x106
> ?
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG????????????????????0x10a
> +
> ?/* Supervisor Trap Handling */
> ?#define CSR_SSCRATCH???????????????????0x140
> ?#define CSR_SEPC???????????????????????0x141
> @@ -336,6 +355,10 @@
> ?#define CSR_HCOUNTEREN?????????????????0x606
> ?#define CSR_HGEIE??????????????????????0x607
> ?
> +/* Hypervisor Configuration */
> +#define CSR_HENVCFG????????????????????0x60a
> +#define CSR_HENVCFGH???????????????????0x61a
> +
> ?/* Hypervisor Trap Handling (H-extension) */
> ?#define CSR_HTVAL??????????????????????0x643
> ?#define CSR_HIP????????????????????????????????0x644
> @@ -408,6 +431,10 @@
> ?#define CSR_MCOUNTEREN?????????????????0x306
> ?#define CSR_MSTATUSH???????????????????0x310
> ?
> +/* Machine Configuration */
> +#define CSR_MENVCFG????????????????????0x30a
> +#define CSR_MENVCFGH???????????????????0x31a
> +
> ?/* Machine Trap Handling */
> ?#define CSR_MSCRATCH???????????????????0x340
> ?#define CSR_MEPC???????????????????????0x341
> -- 
> 2.25.1
> 
> 




From wxjstz at 126.com  Wed Mar 30 07:49:37 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 30 Mar 2022 22:49:37 +0800
Subject: [PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the
 menvcfg CSR
In-Reply-To: <20220329155218.118580-4-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-4-apatel@ventanamicro.com>
Message-ID: <5ae3b522edf32c3b65dc77ceafde2de4c15e393f.camel@126.com>

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
> CSR are WARL. We try to enable these bits irrespective whether
> these extensions are available or not because writes to these
> bits will be ignored if these extensions are not available.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>

Regards,
Xiang W
> ---
> ?lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
> ?1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 31c8f39..d2c7aba 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
> ?
> ?static void mstatus_init(struct sbi_scratch *scratch)
> ?{
> -???????unsigned long mstatus_val = 0;
> +???????unsigned long menvcfg_val, mstatus_val = 0;
> ????????int cidx;
> ????????unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
> ????????uint64_t mhpmevent_init_val = 0;
> @@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ????????????????csr_write_num(CSR_MHPMEVENT3 + cidx,
> mhpmevent_init_val);
> ?#endif
> ????????}
> +
> +???????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> +???????????????menvcfg_val = csr_read(CSR_MENVCFG);
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBZE == 1
> +??????????????? *
> +??????????????? * If Zicboz extension is not available then writes to
> +??????????????? * menvcfg.CBZE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBZE;
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBCFE == 1
> +??????????????? *
> +??????????????? * If Zicbom extension is not available then writes to
> +??????????????? * menvcfg.CBCFE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBCFE;
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBIE == 3
> +??????????????? *
> +??????????????? * If Zicbom extension is not available then writes to
> +??????????????? * menvcfg.CBIE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> +
> +???????????????csr_write(CSR_MENVCFG, menvcfg_val);
> +???????}
> +
> ????????/* Disable all interrupts */
> ????????csr_write(CSR_MIE, 0);
> ?
> -- 
> 2.25.1
> 
> 




From wxjstz at 126.com  Wed Mar 30 07:49:59 2022
From: wxjstz at 126.com (Xiang W)
Date: Wed, 30 Mar 2022 22:49:59 +0800
Subject: [PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR
In-Reply-To: <20220329155218.118580-5-apatel@ventanamicro.com>
References: <20220329155218.118580-1-apatel@ventanamicro.com>
 <20220329155218.118580-5-apatel@ventanamicro.com>
Message-ID: <2790aba472449e27e0bcf97a553949aa8d5137e6.camel@126.com>

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
> available so we try to enable menvcfg.PBMTE bit irrespective whether
> Svpbmt is available or not.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>

Regards,
Xiang W
> ---
> ?lib/sbi/sbi_hart.c | 10 ++++++++++
> ?1 file changed, 10 insertions(+)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d2c7aba..6be9286 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ???????????????? */
> ????????????????menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> ?
> +???????????????/*
> +??????????????? * Set menvcfg.PBMTE == 1 for RV64 or RV128
> +??????????????? *
> +??????????????? * If Svpbmt extension is not available then
> menvcfg.PBMTE
> +??????????????? * will be read-only zero.
> +??????????????? */
> +#if __riscv_xlen > 32
> +???????????????menvcfg_val |= ENVCFG_PBMTE;
> +#endif
> +
> ????????????????csr_write(CSR_MENVCFG, menvcfg_val);
> ????????}
> ?
> -- 
> 2.25.1
> 
> 




From heiko at sntech.de  Thu Mar 31 18:08:38 2022
From: heiko at sntech.de (Heiko Stuebner)
Date: Fri,  1 Apr 2022 03:08:38 +0200
Subject: [PATCH 1/2] platform: add a vendor_ext_provider override
Message-ID: <20220401010839.1343551-1-heiko@sntech.de>

The vendor_ext_provider is already meant to allow
vendor extensions to ecalls, so allow fdt-matched
platforms to define their own override.

Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 platform/generic/include/platform_override.h |  5 +++++
 platform/generic/platform.c                  | 13 +++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 4af8754..3d41a19 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -10,6 +10,7 @@
 #ifndef __PLATFORM_OVERRIDE_H__
 #define __PLATFORM_OVERRIDE_H__
 
+#include <sbi/sbi_trap.h>
 #include <sbi/sbi_types.h>
 
 struct platform_override {
@@ -21,6 +22,10 @@ struct platform_override {
 	void (*early_exit)(const struct fdt_match *match);
 	void (*final_exit)(const struct fdt_match *match);
 	int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
+	int (*vendor_ext_provider)(long extid, long funcid,
+				   const struct sbi_trap_regs *regs,
+				   unsigned long *out_value,
+				   struct sbi_trap_info *out_trap);
 };
 
 #endif
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bc6e761..f05da8e 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -209,6 +209,18 @@ static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
 	return evt_val;
 }
 
+static int generic_vendor_ext_provider(long extid, long funcid,
+				       const struct sbi_trap_regs *regs,
+				       unsigned long *out_value,
+				       struct sbi_trap_info *out_trap)
+{
+	if (generic_plat && generic_plat->vendor_ext_provider)
+		return generic_plat->vendor_ext_provider(extid, funcid, regs,
+							 out_value, out_trap);
+
+	return SBI_ENOTSUPP;
+}
+
 const struct sbi_platform_operations platform_ops = {
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
@@ -225,6 +237,7 @@ const struct sbi_platform_operations platform_ops = {
 	.get_tlbr_flush_limit	= generic_tlbr_flush_limit,
 	.timer_init		= fdt_timer_init,
 	.timer_exit		= fdt_timer_exit,
+	.vendor_ext_provider	= generic_vendor_ext_provider,
 };
 
 struct sbi_platform platform = {
-- 
2.35.1



From heiko at sntech.de  Thu Mar 31 18:08:39 2022
From: heiko at sntech.de (Heiko Stuebner)
Date: Fri,  1 Apr 2022 03:08:39 +0200
Subject: [PATCH 2/2] platform: add thead-c9xx specific platform-overrides
In-Reply-To: <20220401010839.1343551-1-heiko@sntech.de>
References: <20220401010839.1343551-1-heiko@sntech.de>
Message-ID: <20220401010839.1343551-2-heiko@sntech.de>

From: Guo Ren <guoren at linux.alibaba.com>

The PMU on T-Head C9xx SoCs works differently with additional
CSRs and needs additional vendor ecalls to function correctly
both for initializing and mapping events to counters.

Add a fdt-matched T-Head platform for this and
disable the SBI PMU extension for it.

Signed-off-by: Guo Ren <guoren at linux.alibaba.com>
Signed-off-by: Heiko Stuebner <heiko at sntech.de>
---
 lib/sbi/sbi_ecall_pmu.c       |  7 +++
 platform/generic/objects.mk   |  1 +
 platform/generic/platform.c   |  2 +
 platform/generic/thead_c9xx.c | 91 +++++++++++++++++++++++++++++++++++
 4 files changed, 101 insertions(+)
 create mode 100644 platform/generic/thead_c9xx.c

diff --git a/lib/sbi/sbi_ecall_pmu.c b/lib/sbi/sbi_ecall_pmu.c
index 9ee9e81..5f6f7c9 100644
--- a/lib/sbi/sbi_ecall_pmu.c
+++ b/lib/sbi/sbi_ecall_pmu.c
@@ -76,6 +76,13 @@ static int sbi_ecall_pmu_probe(unsigned long extid, unsigned long *out_val)
 {
 	/* PMU extension is always enabled */
 	*out_val = 1;
+
+	/* Some T-Head socs have a non-spec PMU */
+	if (csr_read(CSR_MVENDORID) == 0x5b7 &&
+	    csr_read(CSR_MARCHID) == 0 &&
+	    csr_read(CSR_MIMPID) == 0)
+		*out_val = 0;
+
 	return 0;
 }
 
diff --git a/platform/generic/objects.mk b/platform/generic/objects.mk
index cb15a18..0d6c228 100644
--- a/platform/generic/objects.mk
+++ b/platform/generic/objects.mk
@@ -10,3 +10,4 @@
 platform-objs-y += platform.o
 platform-objs-y += sifive_fu540.o
 platform-objs-y += sifive_fu740.o
+platform-objs-y += thead_c9xx.o
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index f05da8e..1a797dc 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -25,10 +25,12 @@
 
 extern const struct platform_override sifive_fu540;
 extern const struct platform_override sifive_fu740;
+extern const struct platform_override thead_c9xx;
 
 static const struct platform_override *special_platforms[] = {
 	&sifive_fu540,
 	&sifive_fu740,
+	&thead_c9xx,
 };
 
 static const struct platform_override *generic_plat = NULL;
diff --git a/platform/generic/thead_c9xx.c b/platform/generic/thead_c9xx.c
new file mode 100644
index 0000000..782d4e7
--- /dev/null
+++ b/platform/generic/thead_c9xx.c
@@ -0,0 +1,91 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Heiko Stuebner <heiko at sntech.de>
+ *
+ * Authors:
+ *   Heiko Stuebner <heiko at sntech.de>
+ */
+
+#include <platform_override.h>
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_trap.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+enum sbi_ext_thead_fid {
+	SBI_EXT_THEAD_PMU_INIT = 0,
+	SBI_EXT_THEAD_PMU_MAP,
+};
+
+#define CSR_MCOUNTERWEN	0x7c9
+
+static void thead_c9xx_pmu_init(void)
+{
+	unsigned long interrupts;
+
+	interrupts = csr_read(CSR_MIDELEG) | (1 << 17);
+	csr_write(CSR_MIDELEG, interrupts);
+
+	/* CSR_MCOUNTEREN has already been set in mstatus_init() */
+	csr_write(CSR_MCOUNTERWEN, 0xffffffff);
+	csr_write(CSR_MHPMEVENT3, 1);
+	csr_write(CSR_MHPMEVENT4, 2);
+	csr_write(CSR_MHPMEVENT5, 3);
+	csr_write(CSR_MHPMEVENT6, 4);
+	csr_write(CSR_MHPMEVENT7, 5);
+	csr_write(CSR_MHPMEVENT8, 6);
+	csr_write(CSR_MHPMEVENT9, 7);
+	csr_write(CSR_MHPMEVENT10, 8);
+	csr_write(CSR_MHPMEVENT11, 9);
+	csr_write(CSR_MHPMEVENT12, 10);
+	csr_write(CSR_MHPMEVENT13, 11);
+	csr_write(CSR_MHPMEVENT14, 12);
+	csr_write(CSR_MHPMEVENT15, 13);
+	csr_write(CSR_MHPMEVENT16, 14);
+	csr_write(CSR_MHPMEVENT17, 15);
+	csr_write(CSR_MHPMEVENT18, 16);
+	csr_write(CSR_MHPMEVENT19, 17);
+	csr_write(CSR_MHPMEVENT20, 18);
+	csr_write(CSR_MHPMEVENT21, 19);
+	csr_write(CSR_MHPMEVENT22, 20);
+	csr_write(CSR_MHPMEVENT23, 21);
+	csr_write(CSR_MHPMEVENT24, 22);
+	csr_write(CSR_MHPMEVENT25, 23);
+	csr_write(CSR_MHPMEVENT26, 24);
+	csr_write(CSR_MHPMEVENT27, 25);
+	csr_write(CSR_MHPMEVENT28, 26);
+}
+
+static void thead_c9xx_pmu_map(unsigned long idx, unsigned long event_id)
+{
+	if (idx >= 3 && idx <= 31)
+		csr_write_num(CSR_MHPMEVENT3 + idx - 3, event_id);
+}
+
+#include <sbi/sbi_console.h>
+static int thead_c9xx_vendor_ext_provider(long extid, long funcid,
+					  const struct sbi_trap_regs *regs,
+					  unsigned long *out_value,
+					  struct sbi_trap_info *out_trap)
+{
+	switch (funcid) {
+	case SBI_EXT_THEAD_PMU_MAP:
+		thead_c9xx_pmu_map(regs->a0, regs->a1);
+		break;
+	case SBI_EXT_THEAD_PMU_INIT:
+		thead_c9xx_pmu_init();
+		break;
+	}
+	return 0;
+}
+
+static const struct fdt_match thead_c9xx_match[] = {
+	{ .compatible = "allwinner,sun20i-d1" },
+	{ },
+};
+
+const struct platform_override thead_c9xx = {
+	.match_table = thead_c9xx_match,
+	.vendor_ext_provider = thead_c9xx_vendor_ext_provider,
+};
-- 
2.35.1



