[PATCH v2] lib: sbi_trap: Redirect exception based on hedeleg

[Anup Patel]

On Sun, Jun 12, 2022 at 11:31 AM dramforever <dramforever at live.com> wrote:
>
> HS-mode software can choose what exceptions to delegate to VS-mode using
> the hedeleg CSR. Synthetic VS/VU-mode exceptions should also honor
> hedeleg. They should be redirected to VS-mode if and only if delegated
> by HS-mode.
>
> Signed-off-by: dramforever <dramforever at live.com>

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Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>
> Changes since v1:
>  - Use BIT() macro instead of (1 << trap->cause)
>
>  lib/sbi/sbi_trap.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
> index 2c509e5..a54a131 100644
> --- a/lib/sbi/sbi_trap.c
> +++ b/lib/sbi/sbi_trap.c
> @@ -99,17 +99,14 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>         if (prev_mode != PRV_S && prev_mode != PRV_U)
>                 return SBI_ENOTSUPP;
>
> -       /* For certain exceptions from VS/VU-mode we redirect to VS-mode */
> +       /* If exceptions came from VS/VU-mode, redirect to VS-mode if
> +        * delegated in hedeleg
> +        */
>         if (misa_extension('H') && prev_virt) {
> -               switch (trap->cause) {
> -               case CAUSE_FETCH_PAGE_FAULT:
> -               case CAUSE_LOAD_PAGE_FAULT:
> -               case CAUSE_STORE_PAGE_FAULT:
> +               if (trap->cause < __riscv_xlen &&
> +                   csr_read(CSR_HEDELEG) & BIT(trap->cause)) {
>                         next_virt = TRUE;
> -                       break;
> -               default:
> -                       break;
> -               };
> +               }
>         }
>
>         /* Update MSTATUS MPV bits */
> --
> 2.36.1
>