From biju.das.jz at bp.renesas.com  Thu Dec  1 00:27:41 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 08:27:41 +0000
Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <OS0PR01MB59228AE0FC48525FD8F255DE86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>

Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg at gmail.com>
> Sent: 30 November 2022 22:08
> To: Anup Patel <anup at brainfault.org>; Atish Patra
> <atishp at atishpatra.org>; opensbi at lists.infradead.org
> Cc: Yu Chien Peter Lin <peterlin at andestech.com>; Bin Meng
> <bmeng.cn at gmail.com>; Andrew Jones <ajones at ventanamicro.com>; Prabhakar
> <prabhakar.csengg at gmail.com>; Biju Das <biju.das.jz at bp.renesas.com>;
> Chris Paterson <Chris.Paterson2 at renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add Renesas SCIF driver.
> 
> Based on a patch in the BSP by Takeki Hamada
> <takeki.hamada.ak at bp.renesas.com>
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v2->v3
> * Fixed review comments pointed by Bin
> 
> RFC->v2
> * Fixed comments pointed by Xiang W
> ---
>  include/sbi_utils/serial/renesas-scif.h |  11 +++
>  lib/utils/serial/Kconfig                |   4 +
>  lib/utils/serial/objects.mk             |   1 +
>  lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
>  4 files changed, 132 insertions(+)
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/renesas_scif.c
> 
> diff --git a/include/sbi_utils/serial/renesas-scif.h
> b/include/sbi_utils/serial/renesas-scif.h
> new file mode 100644
> index 0000000..0002a1a
> --- /dev/null
> +++ b/include/sbi_utils/serial/renesas-scif.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation  */
> +
> +#ifndef __SERIAL_RENESAS_SCIF_H__
> +#define __SERIAL_RENESAS_SCIF_H__
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> +
> +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig index
> da549a7..f6ed803 100644
> --- a/lib/utils/serial/Kconfig
> +++ b/lib/utils/serial/Kconfig
> @@ -59,6 +59,10 @@ config SERIAL_GAISLER
>  	bool "Gaisler UART support"
>  	default n
> 
> +config SERIAL_RENESAS_SCIF
> +	bool "Renesas SCIF support"
> +	default n
> +
>  config SERIAL_SHAKTI
>  	bool "Shakti UART support"
>  	default n
> diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> index 98f3f9a..6520424 100644
> --- a/lib/utils/serial/objects.mk
> +++ b/lib/utils/serial/objects.mk
> @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE)
> += serial/fdt_serial_xlnx_
> 
>  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o diff --
> git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> new file mode 100644 index 0000000..cf6b53c
> --- /dev/null
> +++ b/lib/utils/serial/renesas_scif.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation  */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_timer.h>
> +#include <sbi_utils/serial/renesas-scif.h>
> +
> +/* clang-format off */
> +
> +#define SCIF_REG_SMR		0x0
> +#define SCIF_REG_BRR		0x2
> +#define SCIF_REG_SCR		0x4
> +#define SCIF_REG_FTDR		0x6
> +#define SCIF_REG_FSR		0x8
> +#define SCIF_REG_FCR		0xc
> +#define SCIF_REG_LSR		0x12
> +#define SCIF_REG_SEMR		0x14
> +
> +#define SCIF_FCR_RFRST		0x2 /* Reset assert receive-FIFO (bit[1])
> */
> +#define SCIF_FCR_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2])
> */
> +
> +#define SCIF_FCR_RST_ASSRT_RFTF	(SCIF_FCR_RFRST | SCIF_FCR_TFRST) /*
> Reset assert tx-FIFO & rx-FIFO */
> +#define SCIF_FCR_RST_NGATE_RFTF	0x0 /* Reset negate tx-FIFO & rx-FIFO
> */
> +
> +#define SCIF_SCR_RE		0x10 /* Enable receive (bit[4]) */
> +#define SCIF_SCR_TE		0x20 /* Enable transmit(bit[5]) */
> +#define SCIF_SCR_RCV_TRN_EN	(SCIF_SCR_RE | SCIF_SCR_TE) /* Enable
> receive & transmit */
> +#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
> +
> +#define SCIF_FSR_ER		0x80 /* Receive error flag */
> +#define SCIF_FSR_TEND		0x40 /* Transmit End Flag */
> +#define SCIF_FSR_TDFE		0x20 /* Transmit FIFO Data Empty Flag */
> +#define SCIF_FSR_BRK		0x10 /* Detect break flag */
> +#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
> +
> +#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
> +
> +#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
> +
> +#define SCIF_REG_8BIT(reg)	((reg == SCIF_REG_BRR) || \
> +				 (reg == SCIF_REG_FTDR) || \
> +				 (reg == SCIF_REG_SEMR))
> +
> +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> +
> +/* clang-format on */
> +
> +static volatile char *scif_base;
> +
> +static u32 get_reg(u32 offset)
> +{
> +	if (SCIF_REG_8BIT(offset))
> +		return readb(scif_base + offset);
> +
> +	return readw(scif_base + offset);
> +}
> +
> +static void set_reg(u32 offset, u32 val) {
> +	if (SCIF_REG_8BIT(offset))
> +		return writeb(val, scif_base + offset);

You are returning from void function. Same below as well.

> +
> +	return writew(val, scif_base + offset);

Cheers,
Biju
 }
> +
> +static void renesas_scif_putc(char ch)
> +{
> +	uint16_t reg;
> +
> +	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> +		;

> +
> +	set_reg(SCIF_REG_FTDR, ch);
> +	reg = get_reg(SCIF_REG_FSR);
> +	reg &= ~SCIF_FSR_TXD_CHK;
> +	set_reg(SCIF_REG_FSR, reg);
> +}
> +
> +static struct sbi_console_device renesas_scif_console = {
> +	.name		= "renesas_scif",
> +	.console_putc	= renesas_scif_putc,
> +};
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate) {
> +	volatile uint16_t data16;
> +
> +	scif_base = (volatile char *)base;
> +
> +	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
> +	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
> +
> +	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> +	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> +
> +	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> +	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> +
> +	set_reg(SCIF_REG_SCR, 0x0);
> +
> +	set_reg(SCIF_REG_SMR, 0x0);
> +
> +	data16 = get_reg(SCIF_REG_SEMR);
> +	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
> +	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> +
> +	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
> +	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
> +
> +	sbi_console_set_device(&renesas_scif_console);
> +
> +	return 0;
> +}
> --
> 2.17.1



From biju.das.jz at bp.renesas.com  Thu Dec  1 00:29:23 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 08:29:23 +0000
Subject: [PATCH v3 3/6] lib: utils/irqchip: Add compatible string for
 Andestech NCEPLIC100
In-Reply-To: <20221130220825.193693-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <OS0PR01MB5922D6966D7DE0687CD36C7C86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>

Hi Prabhakar,

> Subject: [PATCH v3 3/6] lib: utils/irqchip: Add compatible string for
> Andestech NCEPLIC100
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five
> SoC which is equipped with AX45MP AndesCore.
> 
> While at it drop the comma after the sentinel as it does not make sense
> to have a comma after a sentinel, as any new elements must be added
> before the sentinel.
> 
> dts example (Single-core AX45MP):
> 
>     soc: soc {
>           ....
>           plic: interrupt-controller at 12c00000 {
>               compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
>               #interrupt-cells = <2>;
>               #address-cells = <0>;
>               riscv,ndev = <511>;
>               interrupt-controller;
>               reg = <0x0 0x12c00000 0 0x400000>;
>               clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
>               power-domains = <&cpg>;
>               resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
>               interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
>           };
>           ....
>     };
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> Reviewed-by: Bin Meng <bmeng at tinylab.org>
> ---
> v2->v3
> * Included RB tags
> 
> RFC->v2
> * No change
> 
> DT binding [0]

> ---
>  lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c
> b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..83d091a 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -163,7 +163,8 @@ static const struct fdt_match irqchip_plic_match[] =
> {
>  	{ .compatible = "sifive,plic-1.0.0" },
>  	{ .compatible = "thead,c900-plic",
>  	  .data = thead_plic_plat_init },
> -	{ },
> +	{ .compatible = "andestech,nceplic100" },
> +	{ /* sentinel */ }

Maybe sort alphabetically.

Cheers,
Biju
>  };
> 
>  struct fdt_irqchip fdt_irqchip_plic = {
> --
> 2.17.1



From biju.das.jz at bp.renesas.com  Thu Dec  1 00:33:16 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 08:33:16 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>

Hi Prabhakar,

Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> RZ/Five SoC
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v2->v3
> * Updated doc with new build command
> 
> RFC->v2
> * Updated doc
> ---
>  docs/platform/platform.md       |   5 ++
>  docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
>  2 files changed, 150 insertions(+)
>  create mode 100644 docs/platform/renesas-rzfive.md
> 
> diff --git a/docs/platform/platform.md b/docs/platform/platform.md index
> f291931..4504d87 100644
> --- a/docs/platform/platform.md
> +++ b/docs/platform/platform.md
> @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and
> hardware platforms:
>    processor based SOCs. More details on this platform can be found in
> the
>    file *[shakti_cclass.md]*.
> 
> +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> +(R9A07G043F) SoC
> +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> +platform can
> +  be found in the file *[renesas-rzfive.md]*.
> +
>  The code for these supported platforms can be used as example to
> implement  support for other platforms. The *platform/template*
> directory also provides  template files for implementing support for a
> new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to facilitate
> the implementation.
>  [spike.md]: spike.md
>  [fpga-openpiton.md]: fpga-openpiton.md
>  [shakti_cclass.md]: shakti_cclass.md
> +[renesas-rzfive.md]: renesas-rzfive.md
> diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> rzfive.md new file mode 100644 index 0000000..a900cc7
> --- /dev/null
> +++ b/docs/platform/renesas-rzfive.md
> @@ -0,0 +1,145 @@
> +Renesas RZ/Five SoC (R9A07G043F) Platform
> +=========================================
> +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> +AX45MP)
> +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> +- Gigabit Ethernet 2ch
> +- CAN interface (CAN-FD) 2ch
> +- USB 2.0 interface 2ch
> +- SD interface 2ch
> +- AD converter 2ch
> +making it ideal for applications such as entry-class social
> +infrastructure gateway control and industrial gateway control.
> +
> +To build platform specific library and firmwares, provide the
> +*PLATFORM=generic* parameter to the top level make command.
> +
> +Platform Options
> +----------------
> +
> +The Renesas RZ/Five platform does not have any platform-specific
> options.
> +
> +Building Renesas RZ/Five Platform
> +---------------------------------
> +
> +```
> +make PLATFORM=generic
> +```
> +
> +DTS Example: (RZ/Five AX45MP)
> +-----------------------------
> +
> +```
> +	compatible = "renesas,r9a07g043";
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <12000000>;
> +
> +		cpu0: cpu at 0 {
> +			compatible = "andestech,ax45mp", "riscv";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			status = "okay";
> +			riscv,isa = "rv64imafdc";
> +			mmu-type = "riscv,sv39";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <0x40>;
> +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;

Missing clock names.

> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				compatible = "riscv,cpu-intc";
> +				interrupt-controller;
> +			};
> +		};
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		ranges;
> +
> +		scif0: serial at 1004b800 {
> +			compatible = "renesas,scif-r9a07g043",
> +				     "renesas,scif-r9a07g044";
> +			reg = <0 0x1004b800 0 0x400>;
> +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";
> +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> +			clock-names = "fck";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> +			status = "disabled";
> +		};
> +
> +		cpg: clock-controller at 11010000 {
> +			compatible = "renesas,r9a07g043-cpg";
> +			reg = <0 0x11010000 0 0x10000>;
> +			clocks = <&extal_clk>;
> +			clock-names = "extal";
> +			#clock-cells = <2>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <0>;
> +		};
> +
> +		sysc: system-controller at 11020000 {
> +			compatible = "renesas,r9a07g043-sysc";
> +			reg = <0 0x11020000 0 0x10000>;
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl at 11030000 {
> +			compatible = "renesas,r9a07g043-pinctrl";
> +			reg = <0 0x11030000 0 0x10000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			gpio-ranges = <&pinctrl 0 0 152>;
> +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
Missing reset names.

Cheers,
Biju
> +		};
> +
> +		plmt0: plmt0 at 110c0000 {
> +			compatible = "andestech,plmt0", "riscv,plmt0";
> +			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
> +			interrupts-extended = <&cpu0_intc 7>;
> +		};
> +
> +		plic: interrupt-controller at 12c00000 {
> +			compatible = "renesas,r9a07g043-plic",
> "andestech,nceplic100";
> +			#interrupt-cells = <2>;
> +			#address-cells = <0>;
> +			riscv,ndev = <511>;
> +			interrupt-controller;
> +			reg = <0x0 0x12c00000 0 0x400000>;
> +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> +		};
> +
> +		plicsw: interrupt-controller at 13000000 {
> +			compatible = "andestech,plicsw";
> +			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
> +			interrupts-extended = <&cpu0_intc 3>;
> +			interrupt-controller;
> +			#address-cells = <2>;
> +			#interrupt-cells = <2>;
> +		};
> +	};
> +```
> --
> 2.17.1



From biju.das.jz at bp.renesas.com  Thu Dec  1 00:41:30 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 08:41:30 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <OS0PR01MB592250B3E8AA94226E1DE36B86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>

Hi Prabhakar,

> Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Prabhakar,
> 
> Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > v2->v3
> > * Updated doc with new build command
> >
> > RFC->v2
> > * Updated doc
> > ---
> >  docs/platform/platform.md       |   5 ++
> >  docs/platform/renesas-rzfive.md | 145
> > ++++++++++++++++++++++++++++++++
> >  2 files changed, 150 insertions(+)
> >  create mode 100644 docs/platform/renesas-rzfive.md
> >
> > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > index
> > f291931..4504d87 100644
> > --- a/docs/platform/platform.md
> > +++ b/docs/platform/platform.md
> > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > and hardware platforms:
> >    processor based SOCs. More details on this platform can be found in
> > the
> >    file *[shakti_cclass.md]*.
> >
> > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > +(R9A07G043F) SoC
> > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > +platform can
> > +  be found in the file *[renesas-rzfive.md]*.
> > +
> >  The code for these supported platforms can be used as example to
> > implement  support for other platforms. The *platform/template*
> > directory also provides  template files for implementing support for a
> > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > facilitate the implementation.
> >  [spike.md]: spike.md
> >  [fpga-openpiton.md]: fpga-openpiton.md
> >  [shakti_cclass.md]: shakti_cclass.md
> > +[renesas-rzfive.md]: renesas-rzfive.md
> > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > rzfive.md new file mode 100644 index 0000000..a900cc7
> > --- /dev/null
> > +++ b/docs/platform/renesas-rzfive.md
> > @@ -0,0 +1,145 @@
> > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > +=========================================
> > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > +AX45MP)
> > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > +- Gigabit Ethernet 2ch
> > +- CAN interface (CAN-FD) 2ch
> > +- USB 2.0 interface 2ch
> > +- SD interface 2ch
> > +- AD converter 2ch

Only few interfaces. Maybe better add remaining one to avoid updating
this document every time.

Cheers,
Biju

> > +making it ideal for applications such as entry-class social
> > +infrastructure gateway control and industrial gateway control.
> > +
> > +To build platform specific library and firmwares, provide the
> > +*PLATFORM=generic* parameter to the top level make command.
> > +
> > +Platform Options
> > +----------------
> > +
> > +The Renesas RZ/Five platform does not have any platform-specific
> > options.
> > +
> > +Building Renesas RZ/Five Platform
> > +---------------------------------
> > +
> > +```
> > +make PLATFORM=generic
> > +```
> > +
> > +DTS Example: (RZ/Five AX45MP)
> > +-----------------------------
> > +
> > +```
> > +	compatible = "renesas,r9a07g043";
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		timebase-frequency = <12000000>;
> > +
> > +		cpu0: cpu at 0 {
> > +			compatible = "andestech,ax45mp", "riscv";
> > +			device_type = "cpu";
> > +			reg = <0x0>;
> > +			status = "okay";
> > +			riscv,isa = "rv64imafdc";
> > +			mmu-type = "riscv,sv39";
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <0x40>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <0x40>;
> > +			clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > +				 <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> 
> Missing clock names.
> 
> > +			cpu0_intc: interrupt-controller {
> > +				#interrupt-cells = <1>;
> > +				compatible = "riscv,cpu-intc";
> > +				interrupt-controller;
> > +			};
> > +		};
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		ranges;
> > +
> > +		scif0: serial at 1004b800 {
> > +			compatible = "renesas,scif-r9a07g043",
> > +				     "renesas,scif-r9a07g044";
> > +			reg = <0 0x1004b800 0 0x400>;
> > +			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <414 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <415 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <413 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <416 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <416 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "eri", "rxi", "txi",
> > +					  "bri", "dri", "tei";
> > +			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > +			clock-names = "fck";
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > +			status = "disabled";
> > +		};
> > +
> > +		cpg: clock-controller at 11010000 {
> > +			compatible = "renesas,r9a07g043-cpg";
> > +			reg = <0 0x11010000 0 0x10000>;
> > +			clocks = <&extal_clk>;
> > +			clock-names = "extal";
> > +			#clock-cells = <2>;
> > +			#reset-cells = <1>;
> > +			#power-domain-cells = <0>;
> > +		};
> > +
> > +		sysc: system-controller at 11020000 {
> > +			compatible = "renesas,r9a07g043-sysc";
> > +			reg = <0 0x11020000 0 0x10000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		pinctrl: pinctrl at 11030000 {
> > +			compatible = "renesas,r9a07g043-pinctrl";
> > +			reg = <0 0x11030000 0 0x10000>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			#interrupt-cells = <2>;
> > +			interrupt-controller;
> > +			gpio-ranges = <&pinctrl 0 0 152>;
> > +			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_GPIO_RSTN>,
> > +				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > +				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> Missing reset names.
> 
> Cheers,
> Biju
> > +		};
> > +
> > +		plmt0: plmt0 at 110c0000 {
> > +			compatible = "andestech,plmt0", "riscv,plmt0";
> > +			reg = <0x00000000 0x110c0000 0x00000000 0x00100000>;
> > +			interrupts-extended = <&cpu0_intc 7>;
> > +		};
> > +
> > +		plic: interrupt-controller at 12c00000 {
> > +			compatible = "renesas,r9a07g043-plic",
> > "andestech,nceplic100";
> > +			#interrupt-cells = <2>;
> > +			#address-cells = <0>;
> > +			riscv,ndev = <511>;
> > +			interrupt-controller;
> > +			reg = <0x0 0x12c00000 0 0x400000>;
> > +			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> > +			power-domains = <&cpg>;
> > +			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> > +			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> > +		};
> > +
> > +		plicsw: interrupt-controller at 13000000 {
> > +			compatible = "andestech,plicsw";
> > +			reg = <0x00000000 0x13000000 0x00000000 0x00400000>;
> > +			interrupts-extended = <&cpu0_intc 3>;
> > +			interrupt-controller;
> > +			#address-cells = <2>;
> > +			#interrupt-cells = <2>;
> > +		};
> > +	};
> > +```
> > --
> > 2.17.1



From prabhakar.csengg at gmail.com  Thu Dec  1 01:05:18 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 09:05:18 +0000
Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <OS0PR01MB59228AE0FC48525FD8F255DE86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <OS0PR01MB59228AE0FC48525FD8F255DE86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8uoi+FZVQhrNqmvv+MKhtOZsUuUeWZgFUBVkobtO3sUcA@mail.gmail.com>

Hi Biju,

Thank you for the review.

On Thu, Dec 1, 2022 at 8:27 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg at gmail.com>
> > Sent: 30 November 2022 22:08
> > To: Anup Patel <anup at brainfault.org>; Atish Patra
> > <atishp at atishpatra.org>; opensbi at lists.infradead.org
> > Cc: Yu Chien Peter Lin <peterlin at andestech.com>; Bin Meng
> > <bmeng.cn at gmail.com>; Andrew Jones <ajones at ventanamicro.com>; Prabhakar
> > <prabhakar.csengg at gmail.com>; Biju Das <biju.das.jz at bp.renesas.com>;
> > Chris Paterson <Chris.Paterson2 at renesas.com>; Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > Add Renesas SCIF driver.
<snip>
> > +static u32 get_reg(u32 offset)
> > +{
> > +     if (SCIF_REG_8BIT(offset))
> > +             return readb(scif_base + offset);
> > +
> > +     return readw(scif_base + offset);
> > +}
> > +
> > +static void set_reg(u32 offset, u32 val) {
> > +     if (SCIF_REG_8BIT(offset))
> > +             return writeb(val, scif_base + offset);
>
> You are returning from void function. Same below as well.
>
Good catch, the compiler didn't warn me.

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Thu Dec  1 01:06:06 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 09:06:06 +0000
Subject: [PATCH v3 3/6] lib: utils/irqchip: Add compatible string for
 Andestech NCEPLIC100
In-Reply-To: <OS0PR01MB5922D6966D7DE0687CD36C7C86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-4-prabhakar.mahadev-lad.rj@bp.renesas.com> <OS0PR01MB5922D6966D7DE0687CD36C7C86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8tTnEHAUoSMhSYoJTNcy8xjNbSpbwqa=9iP2oTfo2AHAg@mail.gmail.com>

Hi Biju,

Thank you for the review.

On Thu, Dec 1, 2022 at 8:29 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: [PATCH v3 3/6] lib: utils/irqchip: Add compatible string for
> > Andestech NCEPLIC100
> >
<snip>
> > index a6e185c..83d091a 100644
> > --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> > +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> > @@ -163,7 +163,8 @@ static const struct fdt_match irqchip_plic_match[] =
> > {
> >       { .compatible = "sifive,plic-1.0.0" },
> >       { .compatible = "thead,c900-plic",
> >         .data = thead_plic_plat_init },
> > -     { },
> > +     { .compatible = "andestech,nceplic100" },
> > +     { /* sentinel */ }
>
> Maybe sort alphabetically.
>
Ok.

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Thu Dec  1 01:09:55 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 09:09:55 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com> <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8ssxnXdU4_sCqMqtCSqsxTFjaa8gULwQyXmhZ9QdQYmxQ@mail.gmail.com>

Hi Biju,

Thank you for the review.

On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Prabhakar Mahadev Lad
> > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > v2->v3
> > * Updated doc with new build command
> >
> > RFC->v2
> > * Updated doc
> > ---
> >  docs/platform/platform.md       |   5 ++
> >  docs/platform/renesas-rzfive.md | 145 ++++++++++++++++++++++++++++++++
> >  2 files changed, 150 insertions(+)
> >  create mode 100644 docs/platform/renesas-rzfive.md
> >
> > diff --git a/docs/platform/platform.md b/docs/platform/platform.md index
> > f291931..4504d87 100644
> > --- a/docs/platform/platform.md
> > +++ b/docs/platform/platform.md
> > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and
> > hardware platforms:
> >    processor based SOCs. More details on this platform can be found in
> > the
> >    file *[shakti_cclass.md]*.
> >
> > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > +(R9A07G043F) SoC
> > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > +platform can
> > +  be found in the file *[renesas-rzfive.md]*.
> > +
> >  The code for these supported platforms can be used as example to
> > implement  support for other platforms. The *platform/template*
> > directory also provides  template files for implementing support for a
> > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to facilitate
> > the implementation.
> >  [spike.md]: spike.md
> >  [fpga-openpiton.md]: fpga-openpiton.md
> >  [shakti_cclass.md]: shakti_cclass.md
> > +[renesas-rzfive.md]: renesas-rzfive.md
> > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > rzfive.md new file mode 100644 index 0000000..a900cc7
> > --- /dev/null
> > +++ b/docs/platform/renesas-rzfive.md
> > @@ -0,0 +1,145 @@
> > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > +=========================================
> > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > +AX45MP)
> > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > +- Gigabit Ethernet 2ch
> > +- CAN interface (CAN-FD) 2ch
> > +- USB 2.0 interface 2ch
> > +- SD interface 2ch
> > +- AD converter 2ch
> > +making it ideal for applications such as entry-class social
> > +infrastructure gateway control and industrial gateway control.
> > +
> > +To build platform specific library and firmwares, provide the
> > +*PLATFORM=generic* parameter to the top level make command.
> > +
> > +Platform Options
> > +----------------
> > +
> > +The Renesas RZ/Five platform does not have any platform-specific
> > options.
> > +
> > +Building Renesas RZ/Five Platform
> > +---------------------------------
> > +
> > +```
> > +make PLATFORM=generic
> > +```
> > +
> > +DTS Example: (RZ/Five AX45MP)
> > +-----------------------------
> > +
> > +```
> > +     compatible = "renesas,r9a07g043";
> > +
> > +     cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             timebase-frequency = <12000000>;
> > +
> > +             cpu0: cpu at 0 {
> > +                     compatible = "andestech,ax45mp", "riscv";
> > +                     device_type = "cpu";
> > +                     reg = <0x0>;
> > +                     status = "okay";
> > +                     riscv,isa = "rv64imafdc";
> > +                     mmu-type = "riscv,sv39";
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-line-size = <0x40>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-line-size = <0x40>;
> > +                     clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > +                              <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
>
> Missing clock names.
>
> > +                     cpu0_intc: interrupt-controller {
> > +                             #interrupt-cells = <1>;
> > +                             compatible = "riscv,cpu-intc";
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +     };
> > +
> > +     soc {
> > +             compatible = "simple-bus";
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             ranges;
> > +
> > +             scif0: serial at 1004b800 {
> > +                     compatible = "renesas,scif-r9a07g043",
> > +                                  "renesas,scif-r9a07g044";
> > +                     reg = <0 0x1004b800 0 0x400>;
> > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > +                     interrupt-names = "eri", "rxi", "txi",
> > +                                       "bri", "dri", "tei";
> > +                     clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > +                     clock-names = "fck";
> > +                     power-domains = <&cpg>;
> > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             cpg: clock-controller at 11010000 {
> > +                     compatible = "renesas,r9a07g043-cpg";
> > +                     reg = <0 0x11010000 0 0x10000>;
> > +                     clocks = <&extal_clk>;
> > +                     clock-names = "extal";
> > +                     #clock-cells = <2>;
> > +                     #reset-cells = <1>;
> > +                     #power-domain-cells = <0>;
> > +             };
> > +
> > +             sysc: system-controller at 11020000 {
> > +                     compatible = "renesas,r9a07g043-sysc";
> > +                     reg = <0 0x11020000 0 0x10000>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             pinctrl: pinctrl at 11030000 {
> > +                     compatible = "renesas,r9a07g043-pinctrl";
> > +                     reg = <0 0x11030000 0 0x10000>;
> > +                     gpio-controller;
> > +                     #gpio-cells = <2>;
> > +                     #interrupt-cells = <2>;
> > +                     interrupt-controller;
> > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > +                     power-domains = <&cpg>;
> > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> Missing reset names.
>
Binding doesn't have reset names.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml?h=next-20221201

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Thu Dec  1 01:12:03 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 09:12:03 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <OS0PR01MB592250B3E8AA94226E1DE36B86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <OS0PR01MB592250B3E8AA94226E1DE36B86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8tBtMfRJVs9m9Zhjv3ew9nFwPBLNq+=xvG=L0Cp3PywEw@mail.gmail.com>

Hi Biju,

On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Prabhakar,
> >
> > Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
> > > RZ/Five SoC
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> > SoC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > ---
> > > v2->v3
> > > * Updated doc with new build command
> > >
> > > RFC->v2
> > > * Updated doc
> > > ---
> > >  docs/platform/platform.md       |   5 ++
> > >  docs/platform/renesas-rzfive.md | 145
> > > ++++++++++++++++++++++++++++++++
> > >  2 files changed, 150 insertions(+)
> > >  create mode 100644 docs/platform/renesas-rzfive.md
> > >
> > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > index
> > > f291931..4504d87 100644
> > > --- a/docs/platform/platform.md
> > > +++ b/docs/platform/platform.md
> > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > and hardware platforms:
> > >    processor based SOCs. More details on this platform can be found in
> > > the
> > >    file *[shakti_cclass.md]*.
> > >
> > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > +(R9A07G043F) SoC
> > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > +platform can
> > > +  be found in the file *[renesas-rzfive.md]*.
> > > +
> > >  The code for these supported platforms can be used as example to
> > > implement  support for other platforms. The *platform/template*
> > > directory also provides  template files for implementing support for a
> > > new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > facilitate the implementation.
> > >  [spike.md]: spike.md
> > >  [fpga-openpiton.md]: fpga-openpiton.md
> > >  [shakti_cclass.md]: shakti_cclass.md
> > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-
> > > rzfive.md new file mode 100644 index 0000000..a900cc7
> > > --- /dev/null
> > > +++ b/docs/platform/renesas-rzfive.md
> > > @@ -0,0 +1,145 @@
> > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > +=========================================
> > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > +AX45MP)
> > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > +- Gigabit Ethernet 2ch
> > > +- CAN interface (CAN-FD) 2ch
> > > +- USB 2.0 interface 2ch
> > > +- SD interface 2ch
> > > +- AD converter 2ch
>
> Only few interfaces. Maybe better add remaining one to avoid updating
> this document every time.
>
The above list is from the Renesas website [0] (Features tab)

Can you please list out which all you want me to add?

[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet#overview

Cheers,
Prabhakar


From biju.das.jz at bp.renesas.com  Thu Dec  1 01:13:22 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 09:13:22 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <CA+V-a8ssxnXdU4_sCqMqtCSqsxTFjaa8gULwQyXmhZ9QdQYmxQ@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8ssxnXdU4_sCqMqtCSqsxTFjaa8gULwQyXmhZ9QdQYmxQ@mail.gmail.com>
Message-ID: <OS0PR01MB59222316BFBB77BBFF448CE986149@OS0PR01MB5922.jpnprd01.prod.outlook.com>

Hi Prabhakar,

> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz at bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> SoC.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > ---
> > > v2->v3
> > > * Updated doc with new build command
> > >
> > > RFC->v2
> > > * Updated doc
> > > ---
> > >  docs/platform/platform.md       |   5 ++
> > >  docs/platform/renesas-rzfive.md | 145
> > > ++++++++++++++++++++++++++++++++
> > >  2 files changed, 150 insertions(+)
> > >  create mode 100644 docs/platform/renesas-rzfive.md
> > >
> > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > index
> > > f291931..4504d87 100644
> > > --- a/docs/platform/platform.md
> > > +++ b/docs/platform/platform.md
> > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > and hardware platforms:
> > >    processor based SOCs. More details on this platform can be found
> > > in the
> > >    file *[shakti_cclass.md]*.
> > >
> > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > +(R9A07G043F) SoC
> > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > +platform can
> > > +  be found in the file *[renesas-rzfive.md]*.
> > > +
> > >  The code for these supported platforms can be used as example to
> > > implement  support for other platforms. The *platform/template*
> > > directory also provides  template files for implementing support for
> > > a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > facilitate the implementation.
> > >  [spike.md]: spike.md
> > >  [fpga-openpiton.md]: fpga-openpiton.md
> > >  [shakti_cclass.md]: shakti_cclass.md
> > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > diff --git a/docs/platform/renesas-rzfive.md
> > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > 0000000..a900cc7
> > > --- /dev/null
> > > +++ b/docs/platform/renesas-rzfive.md
> > > @@ -0,0 +1,145 @@
> > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > +=========================================
> > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > +AX45MP)
> > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > +- Gigabit Ethernet 2ch
> > > +- CAN interface (CAN-FD) 2ch
> > > +- USB 2.0 interface 2ch
> > > +- SD interface 2ch
> > > +- AD converter 2ch
> > > +making it ideal for applications such as entry-class social
> > > +infrastructure gateway control and industrial gateway control.
> > > +
> > > +To build platform specific library and firmwares, provide the
> > > +*PLATFORM=generic* parameter to the top level make command.
> > > +
> > > +Platform Options
> > > +----------------
> > > +
> > > +The Renesas RZ/Five platform does not have any platform-specific
> > > options.
> > > +
> > > +Building Renesas RZ/Five Platform
> > > +---------------------------------
> > > +
> > > +```
> > > +make PLATFORM=generic
> > > +```
> > > +
> > > +DTS Example: (RZ/Five AX45MP)
> > > +-----------------------------
> > > +
> > > +```
> > > +     compatible = "renesas,r9a07g043";
> > > +
> > > +     cpus {
> > > +             #address-cells = <1>;
> > > +             #size-cells = <0>;
> > > +             timebase-frequency = <12000000>;
> > > +
> > > +             cpu0: cpu at 0 {
> > > +                     compatible = "andestech,ax45mp", "riscv";
> > > +                     device_type = "cpu";
> > > +                     reg = <0x0>;
> > > +                     status = "okay";
> > > +                     riscv,isa = "rv64imafdc";
> > > +                     mmu-type = "riscv,sv39";
> > > +                     i-cache-size = <0x8000>;
> > > +                     i-cache-line-size = <0x40>;
> > > +                     d-cache-size = <0x8000>;
> > > +                     d-cache-line-size = <0x40>;
> > > +                     clocks = <&cpg CPG_CORE
> R9A07G043_AX45MP_CORE0_CLK>,
> > > +                              <&cpg CPG_CORE
> > > + R9A07G043_AX45MP_ACLK>;
> >
> > Missing clock names.
> >
> > > +                     cpu0_intc: interrupt-controller {
> > > +                             #interrupt-cells = <1>;
> > > +                             compatible = "riscv,cpu-intc";
> > > +                             interrupt-controller;
> > > +                     };
> > > +             };
> > > +     };
> > > +
> > > +     soc {
> > > +             compatible = "simple-bus";
> > > +             #address-cells = <1>;
> > > +             #size-cells = <0>;
> > > +             ranges;
> > > +
> > > +             scif0: serial at 1004b800 {
> > > +                     compatible = "renesas,scif-r9a07g043",
> > > +                                  "renesas,scif-r9a07g044";
> > > +                     reg = <0 0x1004b800 0 0x400>;
> > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > +                     interrupt-names = "eri", "rxi", "txi",
> > > +                                       "bri", "dri", "tei";
> > > +                     clocks = <&cpg CPG_MOD
> R9A07G043_SCIF0_CLK_PCK>;
> > > +                     clock-names = "fck";
> > > +                     power-domains = <&cpg>;
> > > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > > +             cpg: clock-controller at 11010000 {
> > > +                     compatible = "renesas,r9a07g043-cpg";
> > > +                     reg = <0 0x11010000 0 0x10000>;
> > > +                     clocks = <&extal_clk>;
> > > +                     clock-names = "extal";
> > > +                     #clock-cells = <2>;
> > > +                     #reset-cells = <1>;
> > > +                     #power-domain-cells = <0>;
> > > +             };
> > > +
> > > +             sysc: system-controller at 11020000 {
> > > +                     compatible = "renesas,r9a07g043-sysc";
> > > +                     reg = <0 0x11020000 0 0x10000>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > > +             pinctrl: pinctrl at 11030000 {
> > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > +                     reg = <0 0x11030000 0 0x10000>;
> > > +                     gpio-controller;
> > > +                     #gpio-cells = <2>;
> > > +                     #interrupt-cells = <2>;
> > > +                     interrupt-controller;
> > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > > +                     power-domains = <&cpg>;
> > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > Missing reset names.
> >
> Binding doesn't have reset names.

Maybe add here and upstream the same patch to Linux.

Cheers,
Biju


From prabhakar.csengg at gmail.com  Thu Dec  1 01:19:32 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 09:19:32 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <OS0PR01MB59222316BFBB77BBFF448CE986149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8ssxnXdU4_sCqMqtCSqsxTFjaa8gULwQyXmhZ9QdQYmxQ@mail.gmail.com> <OS0PR01MB59222316BFBB77BBFF448CE986149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8tposUvzW+Z_BrUq8jFEmiVhEz61a4Ki75LNYg5ryJKew@mail.gmail.com>

Hi Biju,

On Thu, Dec 1, 2022 at 9:13 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz at bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > >
> > > > This patch adds documentation to build Renesas RZ/Five (R9A07G043F)
> > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > ---
> > > > v2->v3
> > > > * Updated doc with new build command
> > > >
> > > > RFC->v2
> > > > * Updated doc
> > > > ---
> > > >  docs/platform/platform.md       |   5 ++
> > > >  docs/platform/renesas-rzfive.md | 145
> > > > ++++++++++++++++++++++++++++++++
> > > >  2 files changed, 150 insertions(+)
> > > >  create mode 100644 docs/platform/renesas-rzfive.md
> > > >
> > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > index
> > > > f291931..4504d87 100644
> > > > --- a/docs/platform/platform.md
> > > > +++ b/docs/platform/platform.md
> > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual
> > > > and hardware platforms:
> > > >    processor based SOCs. More details on this platform can be found
> > > > in the
> > > >    file *[shakti_cclass.md]*.
> > > >
> > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > +(R9A07G043F) SoC
> > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on this
> > > > +platform can
> > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > +
> > > >  The code for these supported platforms can be used as example to
> > > > implement  support for other platforms. The *platform/template*
> > > > directory also provides  template files for implementing support for
> > > > a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments to
> > > > facilitate the implementation.
> > > >  [spike.md]: spike.md
> > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > 0000000..a900cc7
> > > > --- /dev/null
> > > > +++ b/docs/platform/renesas-rzfive.md
> > > > @@ -0,0 +1,145 @@
> > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > +=========================================
> > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes
> > > > +AX45MP)
> > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> > > > +- Gigabit Ethernet 2ch
> > > > +- CAN interface (CAN-FD) 2ch
> > > > +- USB 2.0 interface 2ch
> > > > +- SD interface 2ch
> > > > +- AD converter 2ch
> > > > +making it ideal for applications such as entry-class social
> > > > +infrastructure gateway control and industrial gateway control.
> > > > +
> > > > +To build platform specific library and firmwares, provide the
> > > > +*PLATFORM=generic* parameter to the top level make command.
> > > > +
> > > > +Platform Options
> > > > +----------------
> > > > +
> > > > +The Renesas RZ/Five platform does not have any platform-specific
> > > > options.
> > > > +
> > > > +Building Renesas RZ/Five Platform
> > > > +---------------------------------
> > > > +
> > > > +```
> > > > +make PLATFORM=generic
> > > > +```
> > > > +
> > > > +DTS Example: (RZ/Five AX45MP)
> > > > +-----------------------------
> > > > +
> > > > +```
> > > > +     compatible = "renesas,r9a07g043";
> > > > +
> > > > +     cpus {
> > > > +             #address-cells = <1>;
> > > > +             #size-cells = <0>;
> > > > +             timebase-frequency = <12000000>;
> > > > +
> > > > +             cpu0: cpu at 0 {
> > > > +                     compatible = "andestech,ax45mp", "riscv";
> > > > +                     device_type = "cpu";
> > > > +                     reg = <0x0>;
> > > > +                     status = "okay";
> > > > +                     riscv,isa = "rv64imafdc";
> > > > +                     mmu-type = "riscv,sv39";
> > > > +                     i-cache-size = <0x8000>;
> > > > +                     i-cache-line-size = <0x40>;
> > > > +                     d-cache-size = <0x8000>;
> > > > +                     d-cache-line-size = <0x40>;
> > > > +                     clocks = <&cpg CPG_CORE
> > R9A07G043_AX45MP_CORE0_CLK>,
> > > > +                              <&cpg CPG_CORE
> > > > + R9A07G043_AX45MP_ACLK>;
> > >
> > > Missing clock names.
> > >
> > > > +                     cpu0_intc: interrupt-controller {
> > > > +                             #interrupt-cells = <1>;
> > > > +                             compatible = "riscv,cpu-intc";
> > > > +                             interrupt-controller;
> > > > +                     };
> > > > +             };
> > > > +     };
> > > > +
> > > > +     soc {
> > > > +             compatible = "simple-bus";
> > > > +             #address-cells = <1>;
> > > > +             #size-cells = <0>;
> > > > +             ranges;
> > > > +
> > > > +             scif0: serial at 1004b800 {
> > > > +                     compatible = "renesas,scif-r9a07g043",
> > > > +                                  "renesas,scif-r9a07g044";
> > > > +                     reg = <0 0x1004b800 0 0x400>;
> > > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > > +                     interrupt-names = "eri", "rxi", "txi",
> > > > +                                       "bri", "dri", "tei";
> > > > +                     clocks = <&cpg CPG_MOD
> > R9A07G043_SCIF0_CLK_PCK>;
> > > > +                     clock-names = "fck";
> > > > +                     power-domains = <&cpg>;
> > > > +                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > > +             cpg: clock-controller at 11010000 {
> > > > +                     compatible = "renesas,r9a07g043-cpg";
> > > > +                     reg = <0 0x11010000 0 0x10000>;
> > > > +                     clocks = <&extal_clk>;
> > > > +                     clock-names = "extal";
> > > > +                     #clock-cells = <2>;
> > > > +                     #reset-cells = <1>;
> > > > +                     #power-domain-cells = <0>;
> > > > +             };
> > > > +
> > > > +             sysc: system-controller at 11020000 {
> > > > +                     compatible = "renesas,r9a07g043-sysc";
> > > > +                     reg = <0 0x11020000 0 0x10000>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > > +             pinctrl: pinctrl at 11030000 {
> > > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > > +                     reg = <0 0x11030000 0 0x10000>;
> > > > +                     gpio-controller;
> > > > +                     #gpio-cells = <2>;
> > > > +                     #interrupt-cells = <2>;
> > > > +                     interrupt-controller;
> > > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > > +                     clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > > +                              <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > > > +                              <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > > Missing reset names.
> > >
> > Binding doesn't have reset names.
>
> Maybe add here and upstream the same patch to Linux.
>
OK, I'll only add here once it's accepted in upstream Linux (as what
if it's not accepted there I dont want to misguide).

Cheers,
Prabhakar


From biju.das.jz at bp.renesas.com  Thu Dec  1 01:21:44 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 09:21:44 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <CA+V-a8tposUvzW+Z_BrUq8jFEmiVhEz61a4Ki75LNYg5ryJKew@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8ssxnXdU4_sCqMqtCSqsxTFjaa8gULwQyXmhZ9QdQYmxQ@mail.gmail.com>
 <OS0PR01MB59222316BFBB77BBFF448CE986149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8tposUvzW+Z_BrUq8jFEmiVhEz61a4Ki75LNYg5ryJKew@mail.gmail.com>
Message-ID: <OS0PR01MB5922B21AC1AC7145F43EE1CF86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>



> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> Sent: 01 December 2022 09:20
> To: Biju Das <biju.das.jz at bp.renesas.com>
> Cc: Anup Patel <anup at brainfault.org>; Atish Patra
> <atishp at atishpatra.org>; opensbi at lists.infradead.org; Yu Chien Peter Lin
> <peterlin at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; Andrew Jones
> <ajones at ventanamicro.com>; Chris Paterson <Chris.Paterson2 at renesas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> On Thu, Dec 1, 2022 at 9:13 AM Biju Das <biju.das.jz at bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > Hi Biju,
> > >
> > > Thank you for the review.
> > >
> > > On Thu, Dec 1, 2022 at 8:33 AM Biju Das <biju.das.jz at bp.renesas.com>
> > > wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Prabhakar Mahadev Lad
> > > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > > Renesas RZ/Five SoC
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > >
> > > > > This patch adds documentation to build Renesas RZ/Five
> > > > > (R9A07G043F)
> > > SoC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > > ---
> > > > > v2->v3
> > > > > * Updated doc with new build command
> > > > >
> > > > > RFC->v2
> > > > > * Updated doc
> > > > > ---
> > > > >  docs/platform/platform.md       |   5 ++
> > > > >  docs/platform/renesas-rzfive.md | 145
> > > > > ++++++++++++++++++++++++++++++++
> > > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > > docs/platform/renesas-rzfive.md
> > > > >
> > > > > diff --git a/docs/platform/platform.md
> > > > > b/docs/platform/platform.md index
> > > > > f291931..4504d87 100644
> > > > > --- a/docs/platform/platform.md
> > > > > +++ b/docs/platform/platform.md
> > > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > > virtual and hardware platforms:
> > > > >    processor based SOCs. More details on this platform can be
> > > > > found in the
> > > > >    file *[shakti_cclass.md]*.
> > > > >
> > > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > > +(R9A07G043F) SoC
> > > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > > +this platform can
> > > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > > +
> > > > >  The code for these supported platforms can be used as example
> > > > > to implement  support for other platforms. The
> > > > > *platform/template* directory also provides  template files for
> > > > > implementing support for a new platform. The *objects.mk*, @@
> > > > > -54,3 +58,4 @@ comments to facilitate the implementation.
> > > > >  [spike.md]: spike.md
> > > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > > 0000000..a900cc7
> > > > > --- /dev/null
> > > > > +++ b/docs/platform/renesas-rzfive.md
> > > > > @@ -0,0 +1,145 @@
> > > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > > +=========================================
> > > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > > +(Andes
> > > > > +AX45MP)
> > > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> include:
> > > > > +- Gigabit Ethernet 2ch
> > > > > +- CAN interface (CAN-FD) 2ch
> > > > > +- USB 2.0 interface 2ch
> > > > > +- SD interface 2ch
> > > > > +- AD converter 2ch
> > > > > +making it ideal for applications such as entry-class social
> > > > > +infrastructure gateway control and industrial gateway control.
> > > > > +
> > > > > +To build platform specific library and firmwares, provide the
> > > > > +*PLATFORM=generic* parameter to the top level make command.
> > > > > +
> > > > > +Platform Options
> > > > > +----------------
> > > > > +
> > > > > +The Renesas RZ/Five platform does not have any
> > > > > +platform-specific
> > > > > options.
> > > > > +
> > > > > +Building Renesas RZ/Five Platform
> > > > > +---------------------------------
> > > > > +
> > > > > +```
> > > > > +make PLATFORM=generic
> > > > > +```
> > > > > +
> > > > > +DTS Example: (RZ/Five AX45MP)
> > > > > +-----------------------------
> > > > > +
> > > > > +```
> > > > > +     compatible = "renesas,r9a07g043";
> > > > > +
> > > > > +     cpus {
> > > > > +             #address-cells = <1>;
> > > > > +             #size-cells = <0>;
> > > > > +             timebase-frequency = <12000000>;
> > > > > +
> > > > > +             cpu0: cpu at 0 {
> > > > > +                     compatible = "andestech,ax45mp", "riscv";
> > > > > +                     device_type = "cpu";
> > > > > +                     reg = <0x0>;
> > > > > +                     status = "okay";
> > > > > +                     riscv,isa = "rv64imafdc";
> > > > > +                     mmu-type = "riscv,sv39";
> > > > > +                     i-cache-size = <0x8000>;
> > > > > +                     i-cache-line-size = <0x40>;
> > > > > +                     d-cache-size = <0x8000>;
> > > > > +                     d-cache-line-size = <0x40>;
> > > > > +                     clocks = <&cpg CPG_CORE
> > > R9A07G043_AX45MP_CORE0_CLK>,
> > > > > +                              <&cpg CPG_CORE
> > > > > + R9A07G043_AX45MP_ACLK>;
> > > >
> > > > Missing clock names.
> > > >
> > > > > +                     cpu0_intc: interrupt-controller {
> > > > > +                             #interrupt-cells = <1>;
> > > > > +                             compatible = "riscv,cpu-intc";
> > > > > +                             interrupt-controller;
> > > > > +                     };
> > > > > +             };
> > > > > +     };
> > > > > +
> > > > > +     soc {
> > > > > +             compatible = "simple-bus";
> > > > > +             #address-cells = <1>;
> > > > > +             #size-cells = <0>;
> > > > > +             ranges;
> > > > > +
> > > > > +             scif0: serial at 1004b800 {
> > > > > +                     compatible = "renesas,scif-r9a07g043",
> > > > > +                                  "renesas,scif-r9a07g044";
> > > > > +                     reg = <0 0x1004b800 0 0x400>;
> > > > > +                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <414 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <415 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <413 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>,
> > > > > +                                  <416 IRQ_TYPE_LEVEL_HIGH>;
> > > > > +                     interrupt-names = "eri", "rxi", "txi",
> > > > > +                                       "bri", "dri", "tei";
> > > > > +                     clocks = <&cpg CPG_MOD
> > > R9A07G043_SCIF0_CLK_PCK>;
> > > > > +                     clock-names = "fck";
> > > > > +                     power-domains = <&cpg>;
> > > > > +                     resets = <&cpg
> R9A07G043_SCIF0_RST_SYSTEM_N>;
> > > > > +                     status = "disabled";
> > > > > +             };
> > > > > +
> > > > > +             cpg: clock-controller at 11010000 {
> > > > > +                     compatible = "renesas,r9a07g043-cpg";
> > > > > +                     reg = <0 0x11010000 0 0x10000>;
> > > > > +                     clocks = <&extal_clk>;
> > > > > +                     clock-names = "extal";
> > > > > +                     #clock-cells = <2>;
> > > > > +                     #reset-cells = <1>;
> > > > > +                     #power-domain-cells = <0>;
> > > > > +             };
> > > > > +
> > > > > +             sysc: system-controller at 11020000 {
> > > > > +                     compatible = "renesas,r9a07g043-sysc";
> > > > > +                     reg = <0 0x11020000 0 0x10000>;
> > > > > +                     status = "disabled";
> > > > > +             };
> > > > > +
> > > > > +             pinctrl: pinctrl at 11030000 {
> > > > > +                     compatible = "renesas,r9a07g043-pinctrl";
> > > > > +                     reg = <0 0x11030000 0 0x10000>;
> > > > > +                     gpio-controller;
> > > > > +                     #gpio-cells = <2>;
> > > > > +                     #interrupt-cells = <2>;
> > > > > +                     interrupt-controller;
> > > > > +                     gpio-ranges = <&pinctrl 0 0 152>;
> > > > > +                     clocks = <&cpg CPG_MOD
> R9A07G043_GPIO_HCLK>;
> > > > > +                     power-domains = <&cpg>;
> > > > > +                     resets = <&cpg R9A07G043_GPIO_RSTN>,
> > > > > +                              <&cpg
> R9A07G043_GPIO_PORT_RESETN>,
> > > > > +                              <&cpg
> > > > > + R9A07G043_GPIO_SPARE_RESETN>;
> > > > Missing reset names.
> > > >
> > > Binding doesn't have reset names.
> >
> > Maybe add here and upstream the same patch to Linux.
> >
> OK, I'll only add here once it's accepted in upstream Linux (as what if
> it's not accepted there I dont want to misguide).

OK for me.

Cheers,
Biju

From biju.das.jz at bp.renesas.com  Thu Dec  1 01:38:34 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 09:38:34 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <CA+V-a8tBtMfRJVs9m9Zhjv3ew9nFwPBLNq+=xvG=L0Cp3PywEw@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <OS0PR01MB592250B3E8AA94226E1DE36B86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8tBtMfRJVs9m9Zhjv3ew9nFwPBLNq+=xvG=L0Cp3PywEw@mail.gmail.com>
Message-ID: <OS0PR01MB5922D1C0E260B213BE28F6EB86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>



> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> Sent: 01 December 2022 09:12
> To: Biju Das <biju.das.jz at bp.renesas.com>
> Cc: Anup Patel <anup at brainfault.org>; Atish Patra
> <atishp at atishpatra.org>; opensbi at lists.infradead.org; Yu Chien Peter Lin
> <peterlin at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; Andrew Jones
> <ajones at ventanamicro.com>; Chris Paterson <Chris.Paterson2 at renesas.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> Renesas RZ/Five SoC
> 
> Hi Biju,
> 
> On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz at bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > > Renesas RZ/Five SoC
> > >
> > > Hi Prabhakar,
> > >
> > > Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > >
> > > > This patch adds documentation to build Renesas RZ/Five
> > > > (R9A07G043F)
> > > SoC.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > ---
> > > > v2->v3
> > > > * Updated doc with new build command
> > > >
> > > > RFC->v2
> > > > * Updated doc
> > > > ---
> > > >  docs/platform/platform.md       |   5 ++
> > > >  docs/platform/renesas-rzfive.md | 145
> > > > ++++++++++++++++++++++++++++++++
> > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > docs/platform/renesas-rzfive.md
> > > >
> > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > index
> > > > f291931..4504d87 100644
> > > > --- a/docs/platform/platform.md
> > > > +++ b/docs/platform/platform.md
> > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > virtual and hardware platforms:
> > > >    processor based SOCs. More details on this platform can be
> > > > found in the
> > > >    file *[shakti_cclass.md]*.
> > > >
> > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > +(R9A07G043F) SoC
> > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > +this platform can
> > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > +
> > > >  The code for these supported platforms can be used as example to
> > > > implement  support for other platforms. The *platform/template*
> > > > directory also provides  template files for implementing support
> > > > for a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments
> > > > to facilitate the implementation.
> > > >  [spike.md]: spike.md
> > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > 0000000..a900cc7
> > > > --- /dev/null
> > > > +++ b/docs/platform/renesas-rzfive.md
> > > > @@ -0,0 +1,145 @@
> > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > +=========================================
> > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > +(Andes
> > > > +AX45MP)
> > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> include:
> > > > +- Gigabit Ethernet 2ch
> > > > +- CAN interface (CAN-FD) 2ch
> > > > +- USB 2.0 interface 2ch
> > > > +- SD interface 2ch
> > > > +- AD converter 2ch
> >
> > Only few interfaces. Maybe better add remaining one to avoid updating
> > this document every time.
> >
> The above list is from the Renesas website [0] (Features tab)
> 
> Can you please list out which all you want me to add?
> 

Maybe you add all 

? Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits,
? USB2.0 host / function interface,
? Gigabit Ethernet interface,
? SD card host interface,
? CAN interface,
? Sound interface
- SPI Multi I/O Bus Controller
- Multi-function Timer Pulse Unit 3(MTU3a)
- Port Output Enable 3(POE3)
- Watchdog Timer(WDT)
- General Timer(GTM)
- I2C Bus Interface (I2C)
- Serial Communication Interface with FIFO (SCIFA)
- Serial Communication Interface(SCI)
- Renesas Serial Peripheral Interface (RSPI)

or subset What is going to be supported in open SBI
like

1)CPU
2)Memory
3)IRQ
4)SCIF
5)SPI Multi I/O Bus Controller ( for QSPI boot)
6)SDHI(for eMMC boot)
7)GTM for Secure OS
8)WDT

Cheers,
Biju


From biju.das.jz at bp.renesas.com  Thu Dec  1 02:40:34 2022
From: biju.das.jz at bp.renesas.com (Biju Das)
Date: Thu, 1 Dec 2022 10:40:34 +0000
Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <OS0PR01MB5922BEAA3000624365C8B7E486149@OS0PR01MB5922.jpnprd01.prod.outlook.com>



> -----Original Message-----
> From: Prabhakar <prabhakar.csengg at gmail.com>
> Sent: 30 November 2022 22:08
> To: Anup Patel <anup at brainfault.org>; Atish Patra
> <atishp at atishpatra.org>; opensbi at lists.infradead.org
> Cc: Yu Chien Peter Lin <peterlin at andestech.com>; Bin Meng
> <bmeng.cn at gmail.com>; Andrew Jones <ajones at ventanamicro.com>; Prabhakar
> <prabhakar.csengg at gmail.com>; Biju Das <biju.das.jz at bp.renesas.com>;
> Chris Paterson <Chris.Paterson2 at renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add Renesas SCIF driver.
> 
> Based on a patch in the BSP by Takeki Hamada
> <takeki.hamada.ak at bp.renesas.com>
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v2->v3
> * Fixed review comments pointed by Bin
> 
> RFC->v2
> * Fixed comments pointed by Xiang W
> ---
>  include/sbi_utils/serial/renesas-scif.h |  11 +++
>  lib/utils/serial/Kconfig                |   4 +
>  lib/utils/serial/objects.mk             |   1 +
>  lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
>  4 files changed, 132 insertions(+)
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/renesas_scif.c
> 
> diff --git a/include/sbi_utils/serial/renesas-scif.h
> b/include/sbi_utils/serial/renesas-scif.h
> new file mode 100644
> index 0000000..0002a1a
> --- /dev/null
> +++ b/include/sbi_utils/serial/renesas-scif.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation  */
> +
> +#ifndef __SERIAL_RENESAS_SCIF_H__
> +#define __SERIAL_RENESAS_SCIF_H__
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> +
> +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig index
> da549a7..f6ed803 100644
> --- a/lib/utils/serial/Kconfig
> +++ b/lib/utils/serial/Kconfig
> @@ -59,6 +59,10 @@ config SERIAL_GAISLER
>  	bool "Gaisler UART support"
>  	default n
> 
> +config SERIAL_RENESAS_SCIF
> +	bool "Renesas SCIF support"
> +	default n
> +
>  config SERIAL_SHAKTI
>  	bool "Shakti UART support"
>  	default n
> diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> index 98f3f9a..6520424 100644
> --- a/lib/utils/serial/objects.mk
> +++ b/lib/utils/serial/objects.mk
> @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE)
> += serial/fdt_serial_xlnx_
> 
>  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o diff --
> git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> new file mode 100644 index 0000000..cf6b53c
> --- /dev/null
> +++ b/lib/utils/serial/renesas_scif.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation  */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_timer.h>
> +#include <sbi_utils/serial/renesas-scif.h>
> +
> +/* clang-format off */
> +
> +#define SCIF_REG_SMR		0x0
> +#define SCIF_REG_BRR		0x2
> +#define SCIF_REG_SCR		0x4
> +#define SCIF_REG_FTDR		0x6
> +#define SCIF_REG_FSR		0x8
> +#define SCIF_REG_FCR		0xc
> +#define SCIF_REG_LSR		0x12
> +#define SCIF_REG_SEMR		0x14
> +
> +#define SCIF_FCR_RFRST		0x2 /* Reset assert receive-FIFO (bit[1])
> */
> +#define SCIF_FCR_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2])
> */
> +
> +#define SCIF_FCR_RST_ASSRT_RFTF	(SCIF_FCR_RFRST | SCIF_FCR_TFRST) /*
> Reset assert tx-FIFO & rx-FIFO */
> +#define SCIF_FCR_RST_NGATE_RFTF	0x0 /* Reset negate tx-FIFO & rx-FIFO
> */
> +
> +#define SCIF_SCR_RE		0x10 /* Enable receive (bit[4]) */
> +#define SCIF_SCR_TE		0x20 /* Enable transmit(bit[5]) */
> +#define SCIF_SCR_RCV_TRN_EN	(SCIF_SCR_RE | SCIF_SCR_TE) /* Enable
> receive & transmit */
> +#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
> +
> +#define SCIF_FSR_ER		0x80 /* Receive error flag */
> +#define SCIF_FSR_TEND		0x40 /* Transmit End Flag */
> +#define SCIF_FSR_TDFE		0x20 /* Transmit FIFO Data Empty Flag */
> +#define SCIF_FSR_BRK		0x10 /* Detect break flag */
> +#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
> +
> +#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
> +
> +#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
> +
> +#define SCIF_REG_8BIT(reg)	((reg == SCIF_REG_BRR) || \
> +				 (reg == SCIF_REG_FTDR) || \
> +				 (reg == SCIF_REG_SEMR))
> +
> +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> +
> +/* clang-format on */
> +
> +static volatile char *scif_base;
> +
> +static u32 get_reg(u32 offset)
> +{
> +	if (SCIF_REG_8BIT(offset))
> +		return readb(scif_base + offset);
> +
> +	return readw(scif_base + offset);
> +}
> +
> +static void set_reg(u32 offset, u32 val) {
> +	if (SCIF_REG_8BIT(offset))
> +		return writeb(val, scif_base + offset);
> +
> +	return writew(val, scif_base + offset); }
> +
> +static void renesas_scif_putc(char ch)
> +{
> +	uint16_t reg;
> +
> +	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> +		;
> +
> +	set_reg(SCIF_REG_FTDR, ch);
> +	reg = get_reg(SCIF_REG_FSR);
> +	reg &= ~SCIF_FSR_TXD_CHK;
> +	set_reg(SCIF_REG_FSR, reg);
> +}
> +
> +static struct sbi_console_device renesas_scif_console = {
> +	.name		= "renesas_scif",
> +	.console_putc	= renesas_scif_putc,
> +};
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate) {
> +	volatile uint16_t data16;

Why volatile??


> +
> +	scif_base = (volatile char *)base;
> +
> +	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
> +	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
> +
> +	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> +	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> +
> +	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> +	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> +
> +	set_reg(SCIF_REG_SCR, 0x0);
> +
> +	set_reg(SCIF_REG_SMR, 0x0);
> +
> +	data16 = get_reg(SCIF_REG_SEMR);
> +	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
> +	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> +
> +	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
> +	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
> +
> +	sbi_console_set_device(&renesas_scif_console);
> +
> +	return 0;
> +}
> --
> 2.17.1



From prabhakar.csengg at gmail.com  Thu Dec  1 02:47:47 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 10:47:47 +0000
Subject: [PATCH v3 1/6] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <OS0PR01MB5922BEAA3000624365C8B7E486149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <OS0PR01MB5922BEAA3000624365C8B7E486149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8ua5sUsNUrcdt=4XdJ+ZXVfKYnzp_T3RytgYeaXnGk-_w@mail.gmail.com>

On Thu, Dec 1, 2022 at 10:40 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
>
<snip>
> > +
> > +     set_reg(SCIF_REG_FTDR, ch);
> > +     reg = get_reg(SCIF_REG_FSR);
> > +     reg &= ~SCIF_FSR_TXD_CHK;
> > +     set_reg(SCIF_REG_FSR, reg);
> > +}
> > +
> > +static struct sbi_console_device renesas_scif_console = {
> > +     .name           = "renesas_scif",
> > +     .console_putc   = renesas_scif_putc,
> > +};
> > +
> > +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate) {
> > +     volatile uint16_t data16;
>
> Why volatile??
>
Yep not needed. I will drop it.

Cheers,
Prabhakar


From prabhakar.csengg at gmail.com  Thu Dec  1 02:48:48 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 1 Dec 2022 10:48:48 +0000
Subject: [PATCH v3 5/6] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <OS0PR01MB5922D1C0E260B213BE28F6EB86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221130220825.193693-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <OS0PR01MB592290E34578FBD6E6222B3686149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <OS0PR01MB592250B3E8AA94226E1DE36B86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CA+V-a8tBtMfRJVs9m9Zhjv3ew9nFwPBLNq+=xvG=L0Cp3PywEw@mail.gmail.com> <OS0PR01MB5922D1C0E260B213BE28F6EB86149@OS0PR01MB5922.jpnprd01.prod.outlook.com>
Message-ID: <CA+V-a8t9DrqkakvDts0YuM35GFUrBByaXeLnLE=yDcG1DTCwxQ@mail.gmail.com>

On Thu, Dec 1, 2022 at 9:38 AM Biju Das <biju.das.jz at bp.renesas.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg at gmail.com>
> > Sent: 01 December 2022 09:12
> > To: Biju Das <biju.das.jz at bp.renesas.com>
> > Cc: Anup Patel <anup at brainfault.org>; Atish Patra
> > <atishp at atishpatra.org>; opensbi at lists.infradead.org; Yu Chien Peter Lin
> > <peterlin at andestech.com>; Bin Meng <bmeng.cn at gmail.com>; Andrew Jones
> > <ajones at ventanamicro.com>; Chris Paterson <Chris.Paterson2 at renesas.com>;
> > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > Subject: Re: [PATCH v3 5/6] docs: platform: Add documentation for
> > Renesas RZ/Five SoC
> >
> > Hi Biju,
> >
> > On Thu, Dec 1, 2022 at 8:41 AM Biju Das <biju.das.jz at bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > Subject: RE: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > Renesas RZ/Five SoC
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > Prabhakar Mahadev Lad
> > > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > > Subject: [PATCH v3 5/6] docs: platform: Add documentation for
> > > > > Renesas RZ/Five SoC
> > > > >
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > >
> > > > > This patch adds documentation to build Renesas RZ/Five
> > > > > (R9A07G043F)
> > > > SoC.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > > > ---
> > > > > v2->v3
> > > > > * Updated doc with new build command
> > > > >
> > > > > RFC->v2
> > > > > * Updated doc
> > > > > ---
> > > > >  docs/platform/platform.md       |   5 ++
> > > > >  docs/platform/renesas-rzfive.md | 145
> > > > > ++++++++++++++++++++++++++++++++
> > > > >  2 files changed, 150 insertions(+)  create mode 100644
> > > > > docs/platform/renesas-rzfive.md
> > > > >
> > > > > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > > > > index
> > > > > f291931..4504d87 100644
> > > > > --- a/docs/platform/platform.md
> > > > > +++ b/docs/platform/platform.md
> > > > > @@ -39,6 +39,10 @@ OpenSBI currently supports the following
> > > > > virtual and hardware platforms:
> > > > >    processor based SOCs. More details on this platform can be
> > > > > found in the
> > > > >    file *[shakti_cclass.md]*.
> > > > >
> > > > > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five
> > > > > +(R9A07G043F) SoC
> > > > > +  used on the Renesas RZ/Five SMARC EVK board. More details on
> > > > > +this platform can
> > > > > +  be found in the file *[renesas-rzfive.md]*.
> > > > > +
> > > > >  The code for these supported platforms can be used as example to
> > > > > implement  support for other platforms. The *platform/template*
> > > > > directory also provides  template files for implementing support
> > > > > for a new platform. The *objects.mk*, @@ -54,3 +58,4 @@ comments
> > > > > to facilitate the implementation.
> > > > >  [spike.md]: spike.md
> > > > >  [fpga-openpiton.md]: fpga-openpiton.md
> > > > >  [shakti_cclass.md]: shakti_cclass.md
> > > > > +[renesas-rzfive.md]: renesas-rzfive.md
> > > > > diff --git a/docs/platform/renesas-rzfive.md
> > > > > b/docs/platform/renesas- rzfive.md new file mode 100644 index
> > > > > 0000000..a900cc7
> > > > > --- /dev/null
> > > > > +++ b/docs/platform/renesas-rzfive.md
> > > > > @@ -0,0 +1,145 @@
> > > > > +Renesas RZ/Five SoC (R9A07G043F) Platform
> > > > > +=========================================
> > > > > +The RZ/Five microprocessor includes a single RISC-V CPU Core
> > > > > +(Andes
> > > > > +AX45MP)
> > > > > +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces
> > include:
> > > > > +- Gigabit Ethernet 2ch
> > > > > +- CAN interface (CAN-FD) 2ch
> > > > > +- USB 2.0 interface 2ch
> > > > > +- SD interface 2ch
> > > > > +- AD converter 2ch
> > >
> > > Only few interfaces. Maybe better add remaining one to avoid updating
> > > this document every time.
> > >
> > The above list is from the Renesas website [0] (Features tab)
> >
> > Can you please list out which all you want me to add?
> >
>
> Maybe you add all
>
> ? Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits,
> ? USB2.0 host / function interface,
> ? Gigabit Ethernet interface,
> ? SD card host interface,
> ? CAN interface,
> ? Sound interface
> - SPI Multi I/O Bus Controller
> - Multi-function Timer Pulse Unit 3(MTU3a)
> - Port Output Enable 3(POE3)
> - Watchdog Timer(WDT)
> - General Timer(GTM)
> - I2C Bus Interface (I2C)
> - Serial Communication Interface with FIFO (SCIFA)
> - Serial Communication Interface(SCI)
> - Renesas Serial Peripheral Interface (RSPI)
>
OK I will add the above.

Cheers,
Prabhakar


From weiliang.lim at starfivetech.com  Thu Dec  1 22:38:45 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 2 Dec 2022 14:38:45 +0800
Subject: [PATCH v2] lib: sbi: Add option to select boot hart
Message-ID: <20221202063845.14938-1-weiliang.lim@starfivetech.com>

In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the preferred boot hart.

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 firmware/objects.mk | 4 ++++
 lib/sbi/sbi_init.c  | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/firmware/objects.mk b/firmware/objects.mk
index a1704c4..2b41718 100644
--- a/firmware/objects.mk
+++ b/firmware/objects.mk
@@ -28,6 +28,10 @@ ifdef FW_TEXT_START
 firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
 endif
 
+ifdef FW_BOOT_HART_ID
+firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
+endif
+
 ifdef FW_FDT_PATH
 firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
 ifdef FW_FDT_PADDING
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..28698f1 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -447,7 +447,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 			     scratch->next_mode, FALSE);
 }
 
+#ifndef FW_BOOT_HART_ID
 static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
+#endif
 
 /**
  * Initialize OpenSBI library for current HART and jump to next
@@ -498,7 +500,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
+#ifdef FW_BOOT_HART_ID
+	if (next_mode_supported && hartid == FW_BOOT_HART_ID)
+#else
 	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
+#endif
 		coldboot = TRUE;
 
 	/*
-- 
2.25.1



From apatel at ventanamicro.com  Thu Dec  1 23:51:12 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Fri, 2 Dec 2022 13:21:12 +0530
Subject: [PATCH v2] lib: sbi: Add option to select boot hart
In-Reply-To: <20221202063845.14938-1-weiliang.lim@starfivetech.com>
References: <20221202063845.14938-1-weiliang.lim@starfivetech.com>
Message-ID: <CAK9=C2UuN85+3HP5DJ6Xw=K5i5vaDZjdXWvY0dFE0ir8E4_bsw@mail.gmail.com>

On Fri, Dec 2, 2022 at 12:10 PM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the preferred boot hart.
>
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
>  firmware/objects.mk | 4 ++++
>  lib/sbi/sbi_init.c  | 6 ++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/firmware/objects.mk b/firmware/objects.mk
> index a1704c4..2b41718 100644
> --- a/firmware/objects.mk
> +++ b/firmware/objects.mk
> @@ -28,6 +28,10 @@ ifdef FW_TEXT_START
>  firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
>  endif
>
> +ifdef FW_BOOT_HART_ID
> +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> +endif
> +
>  ifdef FW_FDT_PATH
>  firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
>  ifdef FW_FDT_PADDING
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..28698f1 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -447,7 +447,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
>                              scratch->next_mode, FALSE);
>  }
>
> +#ifndef FW_BOOT_HART_ID
>  static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> +#endif
>
>  /**
>   * Initialize OpenSBI library for current HART and jump to next
> @@ -498,7 +500,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
>          * HARTs which satisfy above condition.
>          */
>
> +#ifdef FW_BOOT_HART_ID
> +       if (next_mode_supported && hartid == FW_BOOT_HART_ID)
> +#else

This breaks the CPU hotplug for boot HART.

In other words, the boot HART will now always take coldboot path when
it is stopped (sbi_hsm_hart_stop()) and started (sbi_hsm_hart_start())
at runtime.

>         if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> +#endif
>                 coldboot = TRUE;
>
>         /*
> --
> 2.25.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Regards,
Anup


From apatel at ventanamicro.com  Fri Dec  2 03:35:47 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Fri, 2 Dec 2022 17:05:47 +0530
Subject: [PATCH v2] lib: sbi: Add option to select boot hart
In-Reply-To: <CAK9=C2UuN85+3HP5DJ6Xw=K5i5vaDZjdXWvY0dFE0ir8E4_bsw@mail.gmail.com>
References: <20221202063845.14938-1-weiliang.lim@starfivetech.com> <CAK9=C2UuN85+3HP5DJ6Xw=K5i5vaDZjdXWvY0dFE0ir8E4_bsw@mail.gmail.com>
Message-ID: <CAK9=C2WE83nuvkanpW_o_fRr39zg7VLuXsvurTttUEgHNdRJ5Q@mail.gmail.com>

On Fri, Dec 2, 2022 at 1:21 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> On Fri, Dec 2, 2022 at 12:10 PM Wei Liang Lim
> <weiliang.lim at starfivetech.com> wrote:
> >
> > In certain scenario, user needs to select a particular hart ID as the boot hart. This option provide the flexibility for user to select the preferred boot hart.
> >
> > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > ---
> >  firmware/objects.mk | 4 ++++
> >  lib/sbi/sbi_init.c  | 6 ++++++
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/firmware/objects.mk b/firmware/objects.mk
> > index a1704c4..2b41718 100644
> > --- a/firmware/objects.mk
> > +++ b/firmware/objects.mk
> > @@ -28,6 +28,10 @@ ifdef FW_TEXT_START
> >  firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
> >  endif
> >
> > +ifdef FW_BOOT_HART_ID
> > +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> > +endif
> > +
> >  ifdef FW_FDT_PATH
> >  firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> >  ifdef FW_FDT_PADDING
> > diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> > index a8500e5..28698f1 100644
> > --- a/lib/sbi/sbi_init.c
> > +++ b/lib/sbi/sbi_init.c
> > @@ -447,7 +447,9 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
> >                              scratch->next_mode, FALSE);
> >  }
> >
> > +#ifndef FW_BOOT_HART_ID
> >  static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> > +#endif
> >
> >  /**
> >   * Initialize OpenSBI library for current HART and jump to next
> > @@ -498,7 +500,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> >          * HARTs which satisfy above condition.
> >          */
> >
> > +#ifdef FW_BOOT_HART_ID
> > +       if (next_mode_supported && hartid == FW_BOOT_HART_ID)
> > +#else
>
> This breaks the CPU hotplug for boot HART.
>
> In other words, the boot HART will now always take coldboot path when
> it is stopped (sbi_hsm_hart_stop()) and started (sbi_hsm_hart_start())
> at runtime.

Can you try the two experimental patches from preferred_cold_boot_hart_v1
branch at: https://github.com/avpatel/opensbi.git ?

You will need to implement your platform specific override on top of these
patches to decide which HARTs are allowed to do cold boot. If it works
for you then include these patches in your v3 patches.

Regards,
Anup

>
> >         if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> > +#endif
> >                 coldboot = TRUE;
> >
> >         /*
> > --
> > 2.25.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
> Regards,
> Anup


From anup at brainfault.org  Fri Dec  2 03:47:50 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 2 Dec 2022 17:17:50 +0530
Subject: [PATCH] lib: sbi: Add option to select boot hart
In-Reply-To: <CAEUhbmUF0V=jKkwPyQXe4VOtyL=x6fyGOh1U14Tk49ATG1rVhw@mail.gmail.com>
References: <20221129052119.379830-1-weiliang.lim@starfivetech.com>
 <CFE42EEB-E5DC-4D16-B895-0D9C14661494@jrtc27.com> <89f182fb3eac45bda58e75a6d3a64a46@EXMBX163.cuchost.com>
 <CAEUhbmUF0V=jKkwPyQXe4VOtyL=x6fyGOh1U14Tk49ATG1rVhw@mail.gmail.com>
Message-ID: <CAAhSdy00esijuPZCMt=pQBn=pMxgY5wcJqxsL20-UAc+KPThxA@mail.gmail.com>

On Wed, Nov 30, 2022 at 9:18 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Wed, Nov 30, 2022 at 11:35 AM WeiLiang Lim
> <weiliang.lim at starfivetech.com> wrote:
> >
> > > -----Original Message-----
> > > From: Jessica Clarke <jrtc27 at jrtc27.com>
> > > Sent: Wednesday, November 30, 2022 12:18 AM
> > > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > > <junliang.tan at starfivetech.com>
> > > Subject: Re: [PATCH] lib: sbi: Add option to select boot hart
> > >
> > > On 29 Nov 2022, at 05:21, Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > wrote:
> > > >
> > > > In certain scenario, user needs to select a particular hart ID as the boot hart.
> > > This option provide the flexibility for user to select the preferred boot hart.
> > >
> > > Why? What?s wrong with the others?
> > >
> > > Jess
> > >
> > We need this patch for 2 scenarios below:
> > 1) On our architecture, there are some harts supporting MMU sv39/sv48 and some harts only supporting sv39. When those harts with sv48 support is picked as boot hart, the OS automatically assumes all the other non-boot harts support sv48 as well. Therefore, we need to select the harts with sv39 supports only as the boot hart to avoid the incorrect page table issues in non-boot harts.
>
> For such a case, you probably need to add a CONFIG option in the Linux
> kernel to force an MMU type instead of auto probing the highest MMU
> type on the boot hart.

Another option is to add a RISC-V specific kernel parameter and parse this
parameter very early in setup_vm().

Regards,
Anup

>
> >
> > 2) We have use case which requires the same boot hart to save OS context before going into 'hibernation' mode and to restore the OS context after resuming from 'hibernation' mode.
> >
> > > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > > ---
> > > > firmware/objects.mk | 4 ++++
> > > > lib/sbi/sbi_init.c  | 9 ++++++++-
> > > > 2 files changed, 12 insertions(+), 1 deletion(-)
> > > >
>
> Regards,
> Bin
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From prabhakar.csengg at gmail.com  Fri Dec  2 03:59:47 2022
From: prabhakar.csengg at gmail.com (Prabhakar)
Date: Fri,  2 Dec 2022 11:59:47 +0000
Subject: [PATCH] lib: utils: Add fdt_fixup_node() helper function
Message-ID: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Add a helper function fdt_fixup_node() based on the compatible string.
This will avoid code duplication for every new node fixup being added.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
 lib/utils/fdt/fdt_fixup.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index d1050bb..ef06c6b 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -74,22 +74,22 @@ static void fdt_domain_based_fixup_one(void *fdt, int nodeoff)
 	}
 }
 
-void fdt_aplic_fixup(void *fdt)
+static void fdt_fixup_node(void *fdt, const char *compatible)
 {
 	int noff = 0;
 
-	while ((noff = fdt_node_offset_by_compatible(fdt, noff,
-						     "riscv,aplic")) >= 0)
+	while ((noff = fdt_node_offset_by_compatible(fdt, noff, compatible)) >= 0)
 		fdt_domain_based_fixup_one(fdt, noff);
 }
 
-void fdt_imsic_fixup(void *fdt)
+void fdt_aplic_fixup(void *fdt)
 {
-	int noff = 0;
+	fdt_fixup_node(fdt, "riscv,aplic");
+}
 
-	while ((noff = fdt_node_offset_by_compatible(fdt, noff,
-						     "riscv,imsics")) >= 0)
-		fdt_domain_based_fixup_one(fdt, noff);
+void fdt_imsic_fixup(void *fdt)
+{
+	fdt_fixup_node(fdt, "riscv,imsics");
 }
 
 void fdt_plic_fixup(void *fdt)
-- 
2.17.1



From cheehong.ang at starfivetech.com  Fri Dec  2 04:47:40 2022
From: cheehong.ang at starfivetech.com (Cheehong Ang)
Date: Fri, 2 Dec 2022 12:47:40 +0000
Subject: [PATCH v2] lib: sbi: Add option to select boot hart
In-Reply-To: <CAK9=C2WE83nuvkanpW_o_fRr39zg7VLuXsvurTttUEgHNdRJ5Q@mail.gmail.com>
References: <20221202063845.14938-1-weiliang.lim@starfivetech.com>
 <CAK9=C2UuN85+3HP5DJ6Xw=K5i5vaDZjdXWvY0dFE0ir8E4_bsw@mail.gmail.com>
 <CAK9=C2WE83nuvkanpW_o_fRr39zg7VLuXsvurTttUEgHNdRJ5Q@mail.gmail.com>
Message-ID: <3d8419adb7ac4254a6034c4e62492d7b@EXMBX068.cuchost.com>

> -----Original Message-----
> From: Anup Patel <apatel at ventanamicro.com>
> Sent: Friday, December 2, 2022 7:36 PM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi at lists.infradead.org; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v2] lib: sbi: Add option to select boot hart
> 
> On Fri, Dec 2, 2022 at 1:21 PM Anup Patel <apatel at ventanamicro.com> wrote:
> >
> > On Fri, Dec 2, 2022 at 12:10 PM Wei Liang Lim
> > <weiliang.lim at starfivetech.com> wrote:
> > >
> > > In certain scenario, user needs to select a particular hart ID as the boot hart.
> This option provide the flexibility for user to select the preferred boot hart.
> > >
> > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > ---
> > >  firmware/objects.mk | 4 ++++
> > >  lib/sbi/sbi_init.c  | 6 ++++++
> > >  2 files changed, 10 insertions(+)
> > >
> > > diff --git a/firmware/objects.mk b/firmware/objects.mk index
> > > a1704c4..2b41718 100644
> > > --- a/firmware/objects.mk
> > > +++ b/firmware/objects.mk
> > > @@ -28,6 +28,10 @@ ifdef FW_TEXT_START  firmware-genflags-y +=
> > > -DFW_TEXT_START=$(FW_TEXT_START)  endif
> > >
> > > +ifdef FW_BOOT_HART_ID
> > > +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> > > +endif
> > > +
> > >  ifdef FW_FDT_PATH
> > >  firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> > >  ifdef FW_FDT_PADDING
> > > diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> > > a8500e5..28698f1 100644
> > > --- a/lib/sbi/sbi_init.c
> > > +++ b/lib/sbi/sbi_init.c
> > > @@ -447,7 +447,9 @@ static void __noreturn init_warmboot(struct
> sbi_scratch *scratch, u32 hartid)
> > >                              scratch->next_mode, FALSE);  }
> > >
> > > +#ifndef FW_BOOT_HART_ID
> > >  static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> > > +#endif
> > >
> > >  /**
> > >   * Initialize OpenSBI library for current HART and jump to next @@
> > > -498,7 +500,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> > >          * HARTs which satisfy above condition.
> > >          */
> > >
> > > +#ifdef FW_BOOT_HART_ID
> > > +       if (next_mode_supported && hartid == FW_BOOT_HART_ID) #else
> >
> > This breaks the CPU hotplug for boot HART.
> >
> > In other words, the boot HART will now always take coldboot path when
> > it is stopped (sbi_hsm_hart_stop()) and started (sbi_hsm_hart_start())
> > at runtime.
> 
> Can you try the two experimental patches from preferred_cold_boot_hart_v1
> branch at: https://github.com/avpatel/opensbi.git ?
> 
> You will need to implement your platform specific override on top of these
> patches to decide which HARTs are allowed to do cold boot. If it works for you
> then include these patches in your v3 patches.
> 
> Regards,
> Anup
Great! Thanks! This is exactly what we are looking for. This is so much better as we can
override the preferred cold boot hart behaviour in platform specific code.
We will integrate these 2 patches and test with our platform code.
BTW, our platform specific code is not quite ready to be upstreamed with these 2 patches for now yet.
Can we get back to you with the test result and you can just merge these 2 patches into mainline ?
Or you expect us to include these 2 patches as well when we upstream our platform code later ?
> 
> >
> > >         if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1)
> > > == 0)
> > > +#endif
> > >                 coldboot = TRUE;
> > >
> > >         /*
> > > --
> > > 2.25.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
> >
> > Regards,
> > Anup

From bmeng.cn at gmail.com  Fri Dec  2 07:43:34 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:43:34 +0800
Subject: [PATCH] lib: utils: Add fdt_fixup_node() helper function
In-Reply-To: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAEUhbmX7VPBOh11UiRHTMWCavSt7C_ZUMssKvqa5tVHLOoiORw@mail.gmail.com>

On Fri, Dec 2, 2022 at 8:00 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add a helper function fdt_fixup_node() based on the compatible string.
> This will avoid code duplication for every new node fixup being added.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
>  lib/utils/fdt/fdt_fixup.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index d1050bb..ef06c6b 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -74,22 +74,22 @@ static void fdt_domain_based_fixup_one(void *fdt, int nodeoff)
>         }
>  }
>
> -void fdt_aplic_fixup(void *fdt)
> +static void fdt_fixup_node(void *fdt, const char *compatible)
>  {
>         int noff = 0;
>
> -       while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -                                                    "riscv,aplic")) >= 0)
> +       while ((noff = fdt_node_offset_by_compatible(fdt, noff, compatible)) >= 0)

nits: 80 characters per line limit?

>                 fdt_domain_based_fixup_one(fdt, noff);
>  }
>
> -void fdt_imsic_fixup(void *fdt)
> +void fdt_aplic_fixup(void *fdt)
>  {
> -       int noff = 0;
> +       fdt_fixup_node(fdt, "riscv,aplic");
> +}
>
> -       while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -                                                    "riscv,imsics")) >= 0)
> -               fdt_domain_based_fixup_one(fdt, noff);
> +void fdt_imsic_fixup(void *fdt)
> +{
> +       fdt_fixup_node(fdt, "riscv,imsics");
>  }
>
>  void fdt_plic_fixup(void *fdt)
> --

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:14 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:14 +0800
Subject: [PATCH v2 1/6] lib: simplify fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-2-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-2-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmUkf3HG5vmgTgdeGcJHf=_oRg7iDMW_cKLuS9Xi9XZpww@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:16 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> We should not check !plmt_base || !plmt_size twice.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> Reviewed-by: Xiang W <wxjstz at 126.com>
> Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
> v2:
>         Reviewed-by added
> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:19 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:19 +0800
Subject: [PATCH v2 2/6] lib: simplify fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-3-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-3-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmV6sgB-W9XhNN9TShYcvzsaU2Mqgk+1P2hsx1dRKL3ymw@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:15 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> We should not check !plicsw_base || !size twice.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> Reviewed-by: Xiang W <wxjstz at 126.com>
> Reviewed-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
> v2:
>         Reviewed-by added
> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:22 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:22 +0800
Subject: [PATCH v2 3/6] lib: fix fdt_parse_plmt_node()
In-Reply-To: <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-4-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmVi2WB4W6F12f2iSH7y5k8VYeWjQPjdh7fntwcar=czNg@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:16 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> cpu_offset, cpu_intc_offset must be int to discover failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
>
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> v2:
>         check correct variable
> ---
>  lib/utils/fdt/fdt_helper.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:25 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:25 +0800
Subject: [PATCH v2 4/6] lib: fix fdt_parse_plicsw_node()
In-Reply-To: <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-5-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmUptF8GjoijS4j5fiRY1+L=4z3RP8FGR0pZ7_NTBzvd-g@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:16 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> cpu_offset and cpu_intc_offset must be int to detect failed invocations of
> fdt_node_offset_by_phandle() or fdt_parent_offset().
>
> After determining cpu_offset we have to check this value and not
> cpu_intc_offset.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> v2:
>         check correct variable
> ---
>  lib/utils/fdt/fdt_helper.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:28 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:28 +0800
Subject: [PATCH v2 5/6] lib: simplify fdt_translate_address()
In-Reply-To: <20221128091420.30391-6-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-6-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmVjGbRSRANTFjhD0CMkf7iW=aSab2s72CQ1Ts5aJipE5Q@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:15 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> Don't assign a value to offset which is never used.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
>         Reviewed-by added
> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 07:55:31 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Fri, 2 Dec 2022 23:55:31 +0800
Subject: [PATCH v2 6/6] lib: fix fdt_parse_aclint_node()
In-Reply-To: <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com> <20221128091420.30391-7-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmWmiZHLPRke3ntbwbNut4LH8VaZx5duyAy+FtDGrB1rXQ@mail.gmail.com>

On Mon, Nov 28, 2022 at 5:15 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> After determining cpu_offset we have to check this variable and not
> cpu_intc_offset.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> v2:
>         new patch
> ---
>  lib/utils/fdt/fdt_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 08:10:05 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 3 Dec 2022 00:10:05 +0800
Subject: [PATCH 1/4] platform: generic/andes: Enable generic platform
 support for AE350
In-Reply-To: <20221128083046.6799-2-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-2-peterlin@andestech.com>
Message-ID: <CAEUhbmVTmY1w_zOC8FgPJ8oDbm5hJmOZe6HYkAm-LJboHHGqoQ@mail.gmail.com>

On Mon, Nov 28, 2022 at 4:33 PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> We move andes directory to platform/generic since the necessary fdt
> drivers are available, the users can enable the console, timer, ipi,
> irqchip and reset devices by adding device tree nodes stated in the
> docs/platform/andes-ae350.md.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
> Although generic/platform.c has been able to boot the system
> on AE350, we will add HSM device for it soon so let's keep
> ae350.c as a placeholder.
> ---
>  platform/andes/ae350/Kconfig           |  34 -----
>  platform/andes/ae350/cache.c           |  89 -------------
>  platform/andes/ae350/cache.h           |  17 ---
>  platform/andes/ae350/configs/defconfig |   0
>  platform/andes/ae350/objects.mk        |  40 ------
>  platform/andes/ae350/platform.c        | 169 -------------------------
>  platform/andes/ae350/platform.h        | 109 ----------------
>  platform/generic/Kconfig               |   4 +
>  platform/generic/andes/ae350.c         |  21 +++
>  platform/generic/andes/objects.mk      |   6 +
>  platform/generic/configs/defconfig     |   4 +
>  11 files changed, 35 insertions(+), 458 deletions(-)
>  delete mode 100644 platform/andes/ae350/Kconfig
>  delete mode 100644 platform/andes/ae350/cache.c
>  delete mode 100644 platform/andes/ae350/cache.h
>  delete mode 100644 platform/andes/ae350/configs/defconfig
>  delete mode 100644 platform/andes/ae350/objects.mk
>  delete mode 100644 platform/andes/ae350/platform.c
>  delete mode 100644 platform/andes/ae350/platform.h
>  create mode 100644 platform/generic/andes/ae350.c
>  create mode 100644 platform/generic/andes/objects.mk
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 08:10:08 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 3 Dec 2022 00:10:08 +0800
Subject: [PATCH 2/4] docs: platform: Update AE350 and generic platform documentation
In-Reply-To: <20221128083046.6799-3-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-3-peterlin@andestech.com>
Message-ID: <CAEUhbmW8y4tQixXSw-kLsjsGTf89wMfEYAW_dnmAsruN581dWQ@mail.gmail.com>

On Mon, Nov 28, 2022 at 4:33 PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> Update compile option and platform compatible string for AE350 and
> add it to the generic platform list.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
>  docs/platform/andes-ae350.md | 5 +++--
>  docs/platform/generic.md     | 2 ++
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
> index ec241ec..4739951 100644
> --- a/docs/platform/andes-ae350.md
> +++ b/docs/platform/andes-ae350.md
> @@ -8,7 +8,7 @@ AHB/APB IPs suites a majority embedded systems, and the verified platform serves
>  as a starting point to jump start SoC designs.
>
>  To build platform specific library and firmwares, provide the
> -*PLATFORM=andes/ae350* parameter to the top level make command.
> +*PLATFORM=generic* parameter to the top level `make` command.
>
>  Platform Options
>  ----------------
> @@ -23,13 +23,14 @@ AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5
>  **Linux Kernel Payload**
>
>  ```
> -make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
> +make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
>  ```
>
>  DTS Example: (Quad-core AX45MP)
>  -------------------------------
>
>  ```
> +       compatible = "andestech,ae350";
>         cpus {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> diff --git a/docs/platform/generic.md b/docs/platform/generic.md
> index 73a8afa..bd3c8ab 100644
> --- a/docs/platform/generic.md
> +++ b/docs/platform/generic.md
> @@ -50,9 +50,11 @@ RISC-V Platforms Using Generic Platform
>  * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
>  * **Spike** (*[spike.md]*)
>  * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
> +* **Andes AE350 Platform** (*[andes-ae350.md]*)

nits: please insert this by following alphabetical order

>
>  [qemu_virt.md]: qemu_virt.md
>  [shakti_cclass.md]: shakti_cclass.md
>  [sifive_fu540.md]: sifive_fu540.md
>  [spike.md]: spike.md
>  [thead-c9xx.md]: thead-c9xx.md
> +[andes-ae350.md]: andse-ae350.md
> --

nits: please insert this by following alphabetical order

Otherwise,
Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 08:10:12 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 3 Dec 2022 00:10:12 +0800
Subject: [PATCH 3/4] docs: andes-ae350.md: fix watchdog nodename in dts example
In-Reply-To: <20221128083046.6799-4-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-4-peterlin@andestech.com>
Message-ID: <CAEUhbmU6YUrLF8Yk8t2kY0qU8AtC5iOG+NTjLWM6xPBt2GHaTA@mail.gmail.com>

On Mon, Nov 28, 2022 at 4:33 PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> The example should use watchdog as nodename instead of wdt.
> This is defined in watchdog common schemas:
> https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
>  docs/platform/andes-ae350.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Fri Dec  2 08:10:15 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 3 Dec 2022 00:10:15 +0800
Subject: [PATCH 4/4] scripts/create-binary-archive.sh: remove andes/ae350
 build directory
In-Reply-To: <20221128083046.6799-5-peterlin@andestech.com>
References: <20221128083046.6799-1-peterlin@andestech.com> <20221128083046.6799-5-peterlin@andestech.com>
Message-ID: <CAEUhbmUciAkZnkzBf-gedTgzB3f_j5F9xucSdcBBdx72RfZWXQ@mail.gmail.com>

On Mon, Nov 28, 2022 at 4:34 PM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> The andes-specific files have been moved to generic platform so we
> can drop this line.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> ---
>  scripts/create-binary-archive.sh | 1 -
>  1 file changed, 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From anup at brainfault.org  Fri Dec  2 08:35:33 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 2 Dec 2022 22:05:33 +0530
Subject: [PATCH v2] lib: sbi: Add option to select boot hart
In-Reply-To: <3d8419adb7ac4254a6034c4e62492d7b@EXMBX068.cuchost.com>
References: <20221202063845.14938-1-weiliang.lim@starfivetech.com>
 <CAK9=C2UuN85+3HP5DJ6Xw=K5i5vaDZjdXWvY0dFE0ir8E4_bsw@mail.gmail.com>
 <CAK9=C2WE83nuvkanpW_o_fRr39zg7VLuXsvurTttUEgHNdRJ5Q@mail.gmail.com> <3d8419adb7ac4254a6034c4e62492d7b@EXMBX068.cuchost.com>
Message-ID: <CAAhSdy2baLQb44PDwZ3qHxc__5XOjGqjc57dB1kGPT=CF6W7gA@mail.gmail.com>

On Fri, Dec 2, 2022 at 6:18 PM Cheehong Ang
<cheehong.ang at starfivetech.com> wrote:
>
> > -----Original Message-----
> > From: Anup Patel <apatel at ventanamicro.com>
> > Sent: Friday, December 2, 2022 7:36 PM
> > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > <junliang.tan at starfivetech.com>
> > Subject: Re: [PATCH v2] lib: sbi: Add option to select boot hart
> >
> > On Fri, Dec 2, 2022 at 1:21 PM Anup Patel <apatel at ventanamicro.com> wrote:
> > >
> > > On Fri, Dec 2, 2022 at 12:10 PM Wei Liang Lim
> > > <weiliang.lim at starfivetech.com> wrote:
> > > >
> > > > In certain scenario, user needs to select a particular hart ID as the boot hart.
> > This option provide the flexibility for user to select the preferred boot hart.
> > > >
> > > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > > ---
> > > >  firmware/objects.mk | 4 ++++
> > > >  lib/sbi/sbi_init.c  | 6 ++++++
> > > >  2 files changed, 10 insertions(+)
> > > >
> > > > diff --git a/firmware/objects.mk b/firmware/objects.mk index
> > > > a1704c4..2b41718 100644
> > > > --- a/firmware/objects.mk
> > > > +++ b/firmware/objects.mk
> > > > @@ -28,6 +28,10 @@ ifdef FW_TEXT_START  firmware-genflags-y +=
> > > > -DFW_TEXT_START=$(FW_TEXT_START)  endif
> > > >
> > > > +ifdef FW_BOOT_HART_ID
> > > > +firmware-genflags-y += -DFW_BOOT_HART_ID=$(FW_BOOT_HART_ID)
> > > > +endif
> > > > +
> > > >  ifdef FW_FDT_PATH
> > > >  firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
> > > >  ifdef FW_FDT_PADDING
> > > > diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> > > > a8500e5..28698f1 100644
> > > > --- a/lib/sbi/sbi_init.c
> > > > +++ b/lib/sbi/sbi_init.c
> > > > @@ -447,7 +447,9 @@ static void __noreturn init_warmboot(struct
> > sbi_scratch *scratch, u32 hartid)
> > > >                              scratch->next_mode, FALSE);  }
> > > >
> > > > +#ifndef FW_BOOT_HART_ID
> > > >  static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
> > > > +#endif
> > > >
> > > >  /**
> > > >   * Initialize OpenSBI library for current HART and jump to next @@
> > > > -498,7 +500,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> > > >          * HARTs which satisfy above condition.
> > > >          */
> > > >
> > > > +#ifdef FW_BOOT_HART_ID
> > > > +       if (next_mode_supported && hartid == FW_BOOT_HART_ID) #else
> > >
> > > This breaks the CPU hotplug for boot HART.
> > >
> > > In other words, the boot HART will now always take coldboot path when
> > > it is stopped (sbi_hsm_hart_stop()) and started (sbi_hsm_hart_start())
> > > at runtime.
> >
> > Can you try the two experimental patches from preferred_cold_boot_hart_v1
> > branch at: https://github.com/avpatel/opensbi.git ?
> >
> > You will need to implement your platform specific override on top of these
> > patches to decide which HARTs are allowed to do cold boot. If it works for you
> > then include these patches in your v3 patches.
> >
> > Regards,
> > Anup
> Great! Thanks! This is exactly what we are looking for. This is so much better as we can
> override the preferred cold boot hart behaviour in platform specific code.
> We will integrate these 2 patches and test with our platform code.
> BTW, our platform specific code is not quite ready to be upstreamed with these 2 patches for now yet.
> Can we get back to you with the test result and you can just merge these 2 patches into mainline ?
> Or you expect us to include these 2 patches as well when we upstream our platform code later ?

I am glad that these patches are useful.
I suggest you send these patches along with your platform support
whenever you upstream it.

Regards,
Anup

> >
> > >
> > > >         if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1)
> > > > == 0)
> > > > +#endif
> > > >                 coldboot = TRUE;
> > > >
> > > >         /*
> > > > --
> > > > 2.25.1
> > > >
> > > >
> > > > --
> > > > opensbi mailing list
> > > > opensbi at lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/opensbi
> > >
> > > Regards,
> > > Anup
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From wxjstz at 126.com  Sat Dec  3 05:07:28 2022
From: wxjstz at 126.com (Xiang W)
Date: Sat, 03 Dec 2022 21:07:28 +0800
Subject: [PATCH] lib: utils: Add fdt_fixup_node() helper function
In-Reply-To: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <3704d546969f17032c5de15bf332d324cb6c1823.camel@126.com>

? 2022-12-02???? 11:59 +0000?Prabhakar???
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add a helper function fdt_fixup_node() based on the compatible string.
> This will avoid code duplication for every new node fixup being added.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Look good to me

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/fdt/fdt_fixup.c | 16 ++++++++--------
> ?1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index d1050bb..ef06c6b 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -74,22 +74,22 @@ static void fdt_domain_based_fixup_one(void *fdt, int nodeoff)
> ????????}
> ?}
> ?
> -void fdt_aplic_fixup(void *fdt)
> +static void fdt_fixup_node(void *fdt, const char *compatible)
> ?{
> ????????int noff = 0;
> ?
> -???????while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -??????????????????????????????????????????????????? "riscv,aplic")) >= 0)
> +???????while ((noff = fdt_node_offset_by_compatible(fdt, noff, compatible)) >= 0)
> ????????????????fdt_domain_based_fixup_one(fdt, noff);
> ?}
> ?
> -void fdt_imsic_fixup(void *fdt)
> +void fdt_aplic_fixup(void *fdt)
> ?{
> -???????int noff = 0;
> +???????fdt_fixup_node(fdt, "riscv,aplic");
> +}
> ?
> -???????while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -??????????????????????????????????????????????????? "riscv,imsics")) >= 0)
> -???????????????fdt_domain_based_fixup_one(fdt, noff);
> +void fdt_imsic_fixup(void *fdt)
> +{
> +???????fdt_fixup_node(fdt, "riscv,imsics");
> ?}
> ?
> ?void fdt_plic_fixup(void *fdt)
> -- 
> 2.17.1
> 
> 




From geomatsi at gmail.com  Sat Dec  3 13:04:15 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sun,  4 Dec 2022 00:04:15 +0300
Subject: [PATCH 1/1] gitignore: add vim swap files
Message-ID: <20221203210415.113835-1-geomatsi@gmail.com>

From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>

Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 95692bb..c11afd3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,3 +10,4 @@ install/
 # Development friendly files
 tags
 cscope*
+*.swp
-- 
2.38.1



From geomatsi at gmail.com  Sat Dec  3 13:39:28 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sun,  4 Dec 2022 00:39:28 +0300
Subject: [PATCH RFC v2 1/2] include: sbi: endianness conversion macros
In-Reply-To: <20221203213929.206429-1-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
Message-ID: <20221203213929.206429-2-geomatsi@gmail.com>

From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>

Add basic endinness conversion macros based on compiler builtins.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
---
 include/sbi/riscv_endian.h | 48 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 include/sbi/riscv_endian.h

diff --git a/include/sbi/riscv_endian.h b/include/sbi/riscv_endian.h
new file mode 100644
index 0000000..fe51b4d
--- /dev/null
+++ b/include/sbi/riscv_endian.h
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#ifndef __RISCV_ENDIAN_H__
+#define __RISCV_ENDIAN_H__
+
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		__builtin_bswap16(x)
+# define cpu_to_be32(x)		__builtin_bswap32(x)
+# define cpu_to_be64(x)		__builtin_bswap64(x)
+# define be16_to_cpu(x)		__builtin_bswap16(x)
+# define be32_to_cpu(x)		__builtin_bswap32(x)
+# define be64_to_cpu(x)		__builtin_bswap64(x)
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+# define cpu_to_le16(x)		__builtin_bswap16(x)
+# define cpu_to_le32(x)		__builtin_bswap32(x)
+# define cpu_to_le64(x)		__builtin_bswap64(x)
+# define le16_to_cpu(x)		__builtin_bswap16(x)
+# define le32_to_cpu(x)		__builtin_bswap32(x)
+# define le64_to_cpu(x)		__builtin_bswap64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#else
+#error "Unexpected endianness"
+#endif
+
+#if __riscv_xlen == 64
+#define cpu_to_lle cpu_to_le64
+#define lle_to_cpu le64_to_cpu
+#elif __riscv_xlen == 32
+#define cpu_to_lle cpu_to_le32
+#define lle_to_cpu le32_to_cpu
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#endif
-- 
2.38.1



From geomatsi at gmail.com  Sat Dec  3 13:39:27 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sun,  4 Dec 2022 00:39:27 +0300
Subject: [PATCH RFC v2 0/2] lib: sbi: add support for debug triggers
Message-ID: <20221203213929.206429-1-geomatsi@gmail.com>

This is the second revision of the patches implementing SBI Debug
Trigger extension proposal posted at riscv tech-debug list:
https://lists.riscv.org/g/tech-debug/topic/92375492

The major changes include support for mcounter trigger type and
updates according to some of the review comments. 

As a part of endianness fixes, this revision includes a separate
patch for a header with endianness conversion macros. Depending
on the feedback, later on it can be reposted separately.

Regards,
Sergey

Changes v1 -> v2:
- add header with endianness conversion macros
- fix endinanness: keep possible big-endian support in mind
- do not mark shared structures as packed
- add support for type 2 (mcounter) triggers


Sergey Matyukevich (2):
  include: sbi: endianness conversion macros
  lib: sbi: add support for debug triggers

 include/sbi/riscv_dbtr.h          | 179 +++++++++++
 include/sbi/riscv_encoding.h      |   1 +
 include/sbi/riscv_endian.h        |  48 +++
 include/sbi/sbi_dbtr.h            |  80 +++++
 include/sbi/sbi_ecall_interface.h |  10 +
 lib/sbi/Kconfig                   |   4 +
 lib/sbi/objects.mk                |   4 +
 lib/sbi/sbi_dbtr.c                | 481 ++++++++++++++++++++++++++++++
 lib/sbi/sbi_ecall_dbtr.c          |  68 +++++
 lib/sbi/sbi_init.c                |   9 +
 10 files changed, 884 insertions(+)
 create mode 100644 include/sbi/riscv_dbtr.h
 create mode 100644 include/sbi/riscv_endian.h
 create mode 100644 include/sbi/sbi_dbtr.h
 create mode 100644 lib/sbi/sbi_dbtr.c
 create mode 100644 lib/sbi/sbi_ecall_dbtr.c

-- 
2.38.1



From geomatsi at gmail.com  Sat Dec  3 13:39:29 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sun,  4 Dec 2022 00:39:29 +0300
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221203213929.206429-1-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
Message-ID: <20221203213929.206429-3-geomatsi@gmail.com>

From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>

RISC-V Debug specification includes Sdtrig ISA extension.
This extension describes Trigger Module. Triggers can cause
a breakpoint exception, entry into Debug Mode, or a trace
action without having to execute a special instruction. For
native debugging triggers can be used to implement hardware
breakpoints and watchpoints.

Software support for triggers consists of the following
major components:
- U-mode: gdb
- S-mode: hardware breakpoints framework in Linux kernel
- M-mode: SBI firmware code to handle triggers

SBI Debug Trigger extension proposal has been posted by
Anup Patel to lists.riscv.org tech-debug mailing list:
https://lists.riscv.org/g/tech-debug/topic/92375492

This patch provides initial implementation of SBI Debug
Trigger Extension in OpenSBI library based on the
suggested extension proposal.

Initial implementation has the following limitations:
- supported triggers: mcontrol, mcontrol6
- no support for chained triggers
- only build test for RV32

---
 include/sbi/riscv_dbtr.h          | 179 +++++++++++
 include/sbi/riscv_encoding.h      |   1 +
 include/sbi/sbi_dbtr.h            |  80 +++++
 include/sbi/sbi_ecall_interface.h |  10 +
 lib/sbi/Kconfig                   |   4 +
 lib/sbi/objects.mk                |   4 +
 lib/sbi/sbi_dbtr.c                | 481 ++++++++++++++++++++++++++++++
 lib/sbi/sbi_ecall_dbtr.c          |  68 +++++
 lib/sbi/sbi_init.c                |   9 +
 9 files changed, 836 insertions(+)
 create mode 100644 include/sbi/riscv_dbtr.h
 create mode 100644 include/sbi/sbi_dbtr.h
 create mode 100644 lib/sbi/sbi_dbtr.c
 create mode 100644 lib/sbi/sbi_ecall_dbtr.c

diff --git a/include/sbi/riscv_dbtr.h b/include/sbi/riscv_dbtr.h
new file mode 100644
index 0000000..9944547
--- /dev/null
+++ b/include/sbi/riscv_dbtr.h
@@ -0,0 +1,179 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Syntacore
+ *
+ * Authors:
+ *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
+ *
+ */
+
+#ifndef __RISCV_DBTR_H__
+#define __RISCV_DBTR_H__
+
+#define RV_MAX_TRIGGERS	32
+
+enum {
+	RISCV_DBTR_TRIG_NONE = 0,
+	RISCV_DBTR_TRIG_LEGACY,
+	RISCV_DBTR_TRIG_MCONTROL,
+	RISCV_DBTR_TRIG_ICOUNT,
+	RISCV_DBTR_TRIG_ITRIGGER,
+	RISCV_DBTR_TRIG_ETRIGGER,
+	RISCV_DBTR_TRIG_MCONTROL6,
+};
+
+union riscv_dbtr_tdata1 {
+	unsigned long value;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		unsigned long type:4;
+		unsigned long dmode:1;
+#if __riscv_xlen == 64
+		unsigned long data:59;
+#elif __riscv_xlen == 32
+		unsigned long data:27;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#if __riscv_xlen == 64
+		unsigned long data:59;
+#elif __riscv_xlen == 32
+		unsigned long data:27;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+		unsigned long dmode:1;
+		unsigned long type:4;
+#else
+#error "Unexpected endianness"
+#endif
+	};
+};
+
+union riscv_dbtr_tdata1_mcontrol {
+	unsigned long value;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		unsigned long type:4;
+		unsigned long dmode:1;
+		unsigned long maskmax:6;
+#if __riscv_xlen >= 64
+		unsigned long _res1:30;
+		unsigned long sizehi:2;
+#endif
+		unsigned long hit:1;
+		unsigned long select:1;
+		unsigned long timing:1;
+		unsigned long sizelo:2;
+		unsigned long action:4;
+		unsigned long chain:1;
+		unsigned long match:4;
+		unsigned long m:1;
+		unsigned long _res2:1;
+		unsigned long s:1;
+		unsigned long u:1;
+		unsigned long execute:1;
+		unsigned long store:1;
+		unsigned long load:1;
+#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+		unsigned long load:1;
+		unsigned long store:1;
+		unsigned long execute:1;
+		unsigned long u:1;
+		unsigned long s:1;
+		unsigned long _res2:1;
+		unsigned long m:1;
+		unsigned long match:4;
+		unsigned long chain:1;
+		unsigned long action:4;
+		unsigned long sizelo:2;
+		unsigned long timing:1;
+		unsigned long select:1;
+		unsigned long hit:1;
+#if __riscv_xlen >= 64
+		unsigned long sizehi:2;
+		unsigned long _res1:30;
+#endif
+		unsigned long maskmax:6;
+		unsigned long dmode:1;
+		unsigned long type:4;
+#else
+#error "Unexpected endianness"
+#endif
+	};
+};
+
+#define MCONTROL_U_OFFSET	3
+#define MCONTROL_S_OFFSET	4
+#define MCONTROL_M_OFFSET	6
+
+union riscv_dbtr_tdata1_mcontrol6 {
+	unsigned long value;
+	struct {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		unsigned long type:4;
+		unsigned long dmode:1;
+#if __riscv_xlen == 64
+		unsigned long _res1:34;
+#elif __riscv_xlen == 32
+		unsigned long _res1:2;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+		unsigned long vs:1;
+		unsigned long vu:1;
+		unsigned long hit:1;
+		unsigned long select:1;
+		unsigned long timing:1;
+		unsigned long size:4;
+		unsigned long action:4;
+		unsigned long chain:1;
+		unsigned long match:4;
+		unsigned long m:1;
+		unsigned long _res2:1;
+		unsigned long s:1;
+		unsigned long u:1;
+		unsigned long execute:1;
+		unsigned long store:1;
+		unsigned long load:1;
+#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+		unsigned long load:1;
+		unsigned long store:1;
+		unsigned long execute:1;
+		unsigned long u:1;
+		unsigned long s:1;
+		unsigned long _res2:1;
+		unsigned long m:1;
+		unsigned long match:4;
+		unsigned long chain:1;
+		unsigned long action:4;
+		unsigned long size:4;
+		unsigned long timing:1;
+		unsigned long select:1;
+		unsigned long hit:1;
+		unsigned long vu:1;
+		unsigned long vs:1;
+#if __riscv_xlen == 64
+		unsigned long _res1:34;
+#elif __riscv_xlen == 32
+		unsigned long _res1:2;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+		unsigned long dmode:1;
+		unsigned long type:4;
+#else
+#error "Unexpected endianness"
+#endif
+	};
+};
+
+#define MCONTROL6_U_OFFSET	3
+#define MCONTROL6_S_OFFSET	4
+#define MCONTROL6_M_OFFSET	6
+#define MCONTROL6_VU_OFFSET	23
+#define MCONTROL6_VS_OFFSET	24
+
+#endif /* __RISCV_DBTR_H__ */
diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index b0f08c8..2041ab7 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -671,6 +671,7 @@
 #define CSR_TDATA1			0x7a1
 #define CSR_TDATA2			0x7a2
 #define CSR_TDATA3			0x7a3
+#define CSR_TINFO			0x7a4
 
 /* Debug Mode Registers */
 #define CSR_DCSR			0x7b0
diff --git a/include/sbi/sbi_dbtr.h b/include/sbi/sbi_dbtr.h
new file mode 100644
index 0000000..5ef6166
--- /dev/null
+++ b/include/sbi/sbi_dbtr.h
@@ -0,0 +1,80 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Syntacore
+ *
+ * Authors:
+ *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
+ *
+ */
+
+#ifndef __SBI_DBTR_H__
+#define __SBI_DBTR_H__
+
+#include <sbi/riscv_endian.h>
+#include <sbi/riscv_dbtr.h>
+
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_types.h>
+
+/** Representation of trigger state */
+union sbi_dbtr_trig_state {
+	unsigned long value;
+	struct {
+		unsigned long mapped:1;
+		unsigned long u:1;
+		unsigned long s:1;
+		unsigned long vu:1;
+		unsigned long vs:1;
+#if __riscv_xlen == 64
+		unsigned long reserved:59;
+#elif __riscv_xlen == 32
+		unsigned long reserved:27;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+	};
+};
+
+struct sbi_dbtr_trig_info {
+	unsigned long type_mask;
+	union sbi_dbtr_trig_state state;
+	unsigned long tdata1;
+	unsigned long tdata2;
+	unsigned long tdata3;
+};
+
+/** SBI shared mem messages layout */
+struct sbi_dbtr_data_msg {
+	unsigned long tstate;
+	unsigned long tdata1;
+	unsigned long tdata2;
+	unsigned long tdata3;
+};
+
+struct sbi_dbtr_id_msg {
+	unsigned long idx;
+};
+
+/** Initialize PMU */
+int sbi_dbtr_init(struct sbi_scratch *scratch);
+
+/** SBI DBTR extension functions */
+int sbi_dbtr_probe(unsigned long *out);
+int sbi_dbtr_num_trig(unsigned long trig_tdata1, unsigned long *out);
+int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_idx_base, unsigned long trig_count,
+		unsigned long out_addr_div_by_16);
+int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_count, unsigned long in_addr_div_by_16,
+		unsigned long out_addr_div_by_16, unsigned long *out);
+int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
+int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
+int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_count, unsigned long in_addr_div_by_16,
+		unsigned long out_addr_div_by_16);
+int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
+
+#endif
diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index a3f2bf4..3c1b1ea 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -29,6 +29,7 @@
 #define SBI_EXT_HSM				0x48534D
 #define SBI_EXT_SRST				0x53525354
 #define SBI_EXT_PMU				0x504D55
+#define SBI_EXT_DBTR				0x44425452
 
 /* SBI function IDs for BASE extension*/
 #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
@@ -100,6 +101,15 @@
 #define SBI_EXT_PMU_COUNTER_STOP	0x4
 #define SBI_EXT_PMU_COUNTER_FW_READ	0x5
 
+/* SBI function IDs for DBTR extension */
+#define SBI_EXT_DBTR_NUM_TRIGGERS	0x0
+#define SBI_EXT_DBTR_TRIGGER_READ	0x1
+#define SBI_EXT_DBTR_TRIGGER_INSTALL	0x2
+#define SBI_EXT_DBTR_TRIGGER_UNINSTALL	0x3
+#define SBI_EXT_DBTR_TRIGGER_ENABLE	0x4
+#define SBI_EXT_DBTR_TRIGGER_UPDATE	0x5
+#define SBI_EXT_DBTR_TRIGGER_DISABLE	0x6
+
 /** General pmu event codes specified in SBI PMU extension */
 enum sbi_pmu_hw_generic_events_t {
 	SBI_PMU_HW_NO_EVENT			= 0,
diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
index df74bba..e3a7955 100644
--- a/lib/sbi/Kconfig
+++ b/lib/sbi/Kconfig
@@ -34,4 +34,8 @@ config SBI_ECALL_VENDOR
 	bool "Platform-defined vendor extensions"
 	default y
 
+config SBI_ECALL_DBTR
+	bool "Debug Trigger Extension"
+	default y
+
 endmenu
diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
index c774ebb..36276e8 100644
--- a/lib/sbi/objects.mk
+++ b/lib/sbi/objects.mk
@@ -43,6 +43,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
 carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
 libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
 
+carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBTR) += ecall_dbtr
+libsbi-objs-$(CONFIG_SBI_ECALL_DBTR) += sbi_ecall_dbtr.o
+
 libsbi-objs-y += sbi_bitmap.o
 libsbi-objs-y += sbi_bitops.o
 libsbi-objs-y += sbi_console.o
@@ -60,6 +63,7 @@ libsbi-objs-y += sbi_irqchip.o
 libsbi-objs-y += sbi_misaligned_ldst.o
 libsbi-objs-y += sbi_platform.o
 libsbi-objs-y += sbi_pmu.o
+libsbi-objs-y += sbi_dbtr.o
 libsbi-objs-y += sbi_scratch.o
 libsbi-objs-y += sbi_string.o
 libsbi-objs-y += sbi_system.o
diff --git a/lib/sbi/sbi_dbtr.c b/lib/sbi/sbi_dbtr.c
new file mode 100644
index 0000000..bbad0cf
--- /dev/null
+++ b/lib/sbi/sbi_dbtr.c
@@ -0,0 +1,481 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Syntacore
+ *
+ * Authors:
+ *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
+ *
+ */
+
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_csr_detect.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_dbtr.h>
+
+#include <sbi/riscv_encoding.h>
+#include <sbi/riscv_asm.h>
+
+static struct sbi_dbtr_trig_info triggers[SBI_HARTMASK_MAX_BITS][RV_MAX_TRIGGERS] = {0};
+static uint32_t total_trigs;
+
+static void sbi_triggers_table_init(u32 hartid, int idx, unsigned long type_mask)
+{
+	triggers[hartid][idx].type_mask = type_mask;
+	triggers[hartid][idx].state.value = 0;
+	triggers[hartid][idx].tdata1 = 0;
+	triggers[hartid][idx].tdata2 = 0;
+	triggers[hartid][idx].tdata3 = 0;
+}
+
+int sbi_dbtr_init(struct sbi_scratch *scratch)
+{
+	struct sbi_trap_info trap = {0};
+	u32 hartid = current_hartid();
+	union riscv_dbtr_tdata1 tdata1;
+	unsigned long val;
+	int i;
+
+	total_trigs = 0;
+
+	for (i = 0; i < RV_MAX_TRIGGERS; i++) {
+		csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
+		if (trap.cause)
+			break;
+
+		val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
+		if (trap.cause)
+			break;
+
+		/* Read back tselect and check that it contains the written value */
+		if (val != i)
+			break;
+
+		val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
+		if (trap.cause) {
+			/**
+			 * If reading tinfo caused an exception, the debugger
+			 * must read tdata1 to discover the type.
+			 */
+			tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
+			if (trap.cause)
+				break;
+
+			if (tdata1.type == 0)
+				break;
+
+
+			sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
+			total_trigs++;
+		} else {
+			if (val == 1)
+				break;
+
+			sbi_triggers_table_init(hartid, i, val);
+			total_trigs++;
+		}
+	}
+
+	return 0;
+}
+
+int sbi_dbtr_probe(unsigned long *out)
+{
+	*out  = total_trigs;
+
+	return 0;
+}
+
+
+static void dbtr_trigger_init(unsigned int hartid, unsigned int idx,
+			      struct sbi_dbtr_data_msg *recv)
+{
+	union riscv_dbtr_tdata1 tdata1;
+
+	triggers[hartid][idx].tdata1 = lle_to_cpu(recv->tdata1);
+	triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
+	triggers[hartid][idx].tdata3 = lle_to_cpu(recv->tdata3);
+	triggers[hartid][idx].state.mapped = 1;
+
+	tdata1.value = lle_to_cpu(recv->tdata1);
+
+	switch (tdata1.type) {
+	case RISCV_DBTR_TRIG_MCONTROL:
+		triggers[hartid][idx].state.u = __test_bit(MCONTROL_U_OFFSET, &tdata1.value);
+		triggers[hartid][idx].state.s = __test_bit(MCONTROL_S_OFFSET, &tdata1.value);
+		triggers[hartid][idx].state.vu = 0;
+		triggers[hartid][idx].state.vs = 0;
+		break;
+	case RISCV_DBTR_TRIG_MCONTROL6:
+		triggers[hartid][idx].state.u = __test_bit(MCONTROL6_U_OFFSET, &tdata1.value);
+		triggers[hartid][idx].state.s = __test_bit(MCONTROL6_S_OFFSET, &tdata1.value);
+		triggers[hartid][idx].state.vu = __test_bit(MCONTROL6_VU_OFFSET, &tdata1.value);
+		triggers[hartid][idx].state.vs = __test_bit(MCONTROL6_VS_OFFSET, &tdata1.value);
+		break;
+	default:
+		break;
+	}
+}
+
+static inline void update_bit(unsigned long new, int nr, volatile unsigned long *addr)
+{
+	if (new)
+		__set_bit(nr, addr);
+	else
+		__clear_bit(nr, addr);
+}
+
+static void dbtr_trigger_enable(unsigned int hartid, unsigned int idx)
+{
+	union sbi_dbtr_trig_state state;
+	union riscv_dbtr_tdata1 tdata1;
+
+	if (!triggers[hartid][idx].state.mapped)
+		return;
+
+	state.value = triggers[hartid][idx].state.value;
+	tdata1.value = triggers[hartid][idx].tdata1;
+
+	switch (tdata1.type) {
+	case RISCV_DBTR_TRIG_MCONTROL:
+		update_bit(state.u, MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
+		update_bit(state.s, MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
+		break;
+	case RISCV_DBTR_TRIG_MCONTROL6:
+		update_bit(state.vu, MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
+		update_bit(state.vs, MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
+		update_bit(state.u, MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
+		update_bit(state.s, MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
+		break;
+	default:
+		break;
+	}
+
+	/*
+	 * RISC-V Debug Support v1.0.0 section 5.5:
+	 * Debugger cannot simply set a trigger by writing tdata1, then tdata2, etc. The current
+	 * value of tdata2 might not be legal with the new value of tdata1. To help with this
+	 * situation, it is guaranteed that writing 0 to tdata1 disables the trigger, and
+	 * leaves it in a state where tdata2 and tdata3 can be written with any value
+	 * that makes sense for any trigger type supported by this trigger.
+	 */
+	csr_write(CSR_TSELECT, idx);
+	csr_write(CSR_TDATA1, 0x0);
+	csr_write(CSR_TDATA2, triggers[hartid][idx].tdata2);
+	csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
+}
+
+static void dbtr_trigger_disable(unsigned int hartid, unsigned int idx)
+{
+	union riscv_dbtr_tdata1 tdata1;
+
+	if (!triggers[hartid][idx].state.mapped)
+		return;
+
+	tdata1.value = triggers[hartid][idx].tdata1;
+
+	switch (tdata1.type) {
+	case RISCV_DBTR_TRIG_MCONTROL:
+		__clear_bit(MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
+		__clear_bit(MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
+		break;
+	case RISCV_DBTR_TRIG_MCONTROL6:
+		__clear_bit(MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
+		__clear_bit(MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
+		__clear_bit(MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
+		__clear_bit(MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
+		break;
+	default:
+		break;
+	}
+
+	csr_write(CSR_TSELECT, idx);
+	csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
+}
+
+static void dbtr_trigger_clear(unsigned int hartid, unsigned int idx)
+{
+	if (!triggers[hartid][idx].state.mapped)
+		return;
+
+	csr_write(CSR_TSELECT, idx);
+	csr_write(CSR_TDATA1, 0x0);
+	csr_write(CSR_TDATA2, 0x0);
+}
+
+static int dbtr_trigger_supported(unsigned long type)
+{
+	switch (type) {
+	case RISCV_DBTR_TRIG_MCONTROL:
+	case RISCV_DBTR_TRIG_MCONTROL6:
+		return 1;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int dbtr_trigger_valid(unsigned long type, unsigned long tdata)
+{
+	union riscv_dbtr_tdata1_mcontrol6 control6;
+	union riscv_dbtr_tdata1_mcontrol control;
+
+	switch (type) {
+	case RISCV_DBTR_TRIG_MCONTROL:
+		control.value = tdata;
+		if (!control.action && !control.dmode && !control.m)
+			return 1;
+		break;
+	case RISCV_DBTR_TRIG_MCONTROL6:
+		control6.value = tdata;
+		if (!control6.action && !control6.dmode && !control6.m)
+			return 1;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int sbi_dbtr_num_trig(unsigned long data, unsigned long *out)
+{
+	unsigned long type = ((union riscv_dbtr_tdata1)data).type;
+	u32 hartid = current_hartid();
+	unsigned long total = 0;
+	int i;
+
+
+	if (data == 0) {
+		sbi_dprintf("%s: hart%d: total triggers: %u\n",
+			    __func__, hartid, total_trigs);
+		*out = total_trigs;
+		return SBI_SUCCESS;
+	}
+
+	for (i = 0; i < total_trigs; i++) {
+		if (__test_bit(type, &triggers[hartid][i].type_mask))
+			total++;
+	}
+
+
+	sbi_dprintf("%s: hart%d: total triggers of type %lu: %lu\n",
+		    __func__, hartid, type, total);
+
+	*out = total;
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_idx_base, unsigned long trig_count,
+		unsigned long out_addr_div_by_16)
+{
+	unsigned long out_addr = (out_addr_div_by_16 << 4);
+	struct sbi_dbtr_data_msg *xmit;
+	u32 hartid = current_hartid();
+	int i;
+
+	if (smode != PRV_S)
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
+		return SBI_ERR_INVALID_ADDRESS;
+
+	if (trig_idx_base >= total_trigs || trig_idx_base + trig_count >= total_trigs) {
+		sbi_dprintf("%s: hart%d: invalid trigger index\n", __func__, hartid);
+		return SBI_ERR_INVALID_PARAM;
+	}
+
+	for (i = 0; i < trig_count; i++) {
+		xmit = (struct sbi_dbtr_data_msg *)(out_addr + i * sizeof(*xmit));
+
+		sbi_dprintf("%s: hart%d: read trigger %d\n", __func__, hartid, i);
+
+		xmit->tstate = cpu_to_lle(triggers[hartid][i + trig_idx_base].state.value);
+		xmit->tdata1 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata1);
+		xmit->tdata2 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata2);
+		xmit->tdata3 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata3);
+	}
+
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_count, unsigned long in_addr_div_by_16,
+		unsigned long out_addr_div_by_16, unsigned long *out)
+{
+	unsigned long out_addr = (out_addr_div_by_16 << 4);
+	unsigned long in_addr = (in_addr_div_by_16 << 4);
+	u32 hartid = current_hartid();
+	struct sbi_dbtr_data_msg *recv;
+	struct sbi_dbtr_id_msg *xmit;
+	union riscv_dbtr_tdata1 ctrl;
+	int i, k;
+
+	if (smode != PRV_S)
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
+		return SBI_ERR_INVALID_ADDRESS;
+	if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
+		return SBI_ERR_INVALID_ADDRESS;
+
+	/* TODO: check chained triggers configurations */
+
+	/* Check requested triggers configuration */
+	for (k = 0; k < trig_count; k++) {
+		recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
+		ctrl = (union riscv_dbtr_tdata1)recv->tdata1;
+
+		if (!dbtr_trigger_supported(ctrl.type)) {
+			sbi_dprintf("%s: invalid type of trigger %d\n", __func__, k);
+			*out = k;
+			return SBI_ERR_FAILED;
+		}
+
+		if (!dbtr_trigger_valid(ctrl.type, ctrl.value)) {
+			sbi_dprintf("%s: invalid configuration of trigger %d\n", __func__, k);
+			*out = k;
+			return SBI_ERR_FAILED;
+		}
+	}
+
+	/* Check if we have enough spare triggers */
+	for (i = 0, k = 0; i < total_trigs; i++) {
+		if (!triggers[hartid][i].state.mapped)
+			k++;
+	}
+
+	if (k < trig_count) {
+		sbi_dprintf("%s: hartid%d: not enough spare triggers\n", __func__, hartid);
+		*out = k;
+		return SBI_ERR_FAILED;
+	}
+
+	/* Install triggers */
+	for (i = 0, k = 0; i < total_trigs; i++) {
+		if (triggers[hartid][i].state.mapped)
+			continue;
+
+		recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
+		xmit = (struct sbi_dbtr_id_msg *)(out_addr + k * sizeof(*xmit));
+
+		sbi_dprintf("%s: hart%d: idx[%d] tdata1[0x%lx] tdata2[0x%lx]\n",
+			    __func__, hartid, i, recv->tdata1, recv->tdata2);
+
+		dbtr_trigger_init(hartid, i,  recv);
+		dbtr_trigger_enable(hartid, i);
+		xmit->idx = cpu_to_lle(i);
+
+		if (++k >= trig_count)
+			break;
+	}
+
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
+{
+	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
+	unsigned long idx = trig_idx_base;
+	u32 hartid = current_hartid();
+
+	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
+		    __func__, hartid, trig_mask);
+
+	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
+		if (!triggers[hartid][idx].state.mapped) {
+			sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
+			return SBI_ERR_INVALID_PARAM;
+		}
+
+		sbi_dprintf("%s: clear trigger %lu\n", __func__, idx);
+		dbtr_trigger_clear(hartid, idx);
+
+		triggers[hartid][idx].state.value = 0;
+		triggers[hartid][idx].tdata1 = 0;
+		triggers[hartid][idx].tdata2 = 0;
+		triggers[hartid][idx].tdata3 = 0;
+	}
+
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
+{
+	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
+	unsigned long idx = trig_idx_base;
+	u32 hartid = current_hartid();
+
+	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
+		    __func__, hartid, trig_mask);
+
+	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
+		sbi_dprintf("%s: enable trigger %lu\n", __func__, idx);
+		dbtr_trigger_enable(hartid, idx);
+	}
+
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
+		unsigned long trig_idx_base, unsigned long trig_idx_mask,
+		unsigned long in_addr_div_by_16)
+{
+	unsigned long in_addr = (in_addr_div_by_16 << 4);
+	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
+	unsigned long idx = trig_idx_base;
+	u32 hartid = current_hartid();
+	struct sbi_dbtr_data_msg *recv;
+	unsigned long uidx = 0;
+
+	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
+		    __func__, hartid, trig_mask);
+
+	if (smode != PRV_S)
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
+		return SBI_ERR_DENIED;
+	if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
+		return SBI_ERR_INVALID_ADDRESS;
+
+	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
+		if (!triggers[hartid][idx].state.mapped) {
+			sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
+			return SBI_ERR_INVALID_PARAM;
+		}
+
+		recv = (struct sbi_dbtr_data_msg *)(in_addr + uidx * sizeof(*recv));
+
+		sbi_dprintf("%s: update trigger %lu: newaddr 0x%lx\n",
+			    __func__, idx, recv->tdata2);
+
+		triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
+		dbtr_trigger_enable(hartid, idx);
+		uidx++;
+	}
+
+	return SBI_SUCCESS;
+}
+
+int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
+{
+	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
+	unsigned long idx = trig_idx_base;
+	u32 hartid = current_hartid();
+
+	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
+		    __func__, hartid, trig_mask);
+
+	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
+		sbi_dprintf("%s: disable trigger %lu\n", __func__, idx);
+		dbtr_trigger_disable(hartid, idx);
+	}
+
+	return SBI_SUCCESS;
+}
diff --git a/lib/sbi/sbi_ecall_dbtr.c b/lib/sbi/sbi_ecall_dbtr.c
new file mode 100644
index 0000000..d013b3e
--- /dev/null
+++ b/lib/sbi/sbi_ecall_dbtr.c
@@ -0,0 +1,68 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Syntacore
+ *
+ * Authors:
+ *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
+ *
+ */
+
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_ecall.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_trap.h>
+#include <sbi/sbi_version.h>
+#include <sbi/sbi_dbtr.h>
+
+static int sbi_ecall_dbtr_handler(unsigned long extid, unsigned long funcid,
+				  const struct sbi_trap_regs *regs,
+				  unsigned long *out_val,
+				  struct sbi_trap_info *out_trap)
+{
+	unsigned long smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
+			MSTATUS_MPP_SHIFT;
+	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
+	int ret = 0;
+
+	switch (funcid) {
+	case SBI_EXT_DBTR_NUM_TRIGGERS:
+		ret = sbi_dbtr_num_trig(regs->a0, out_val);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_READ:
+		ret = sbi_dbtr_read_trig(dom, smode, regs->a0, regs->a1, regs->a2);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_INSTALL:
+		ret = sbi_dbtr_install_trig(dom, smode, regs->a0, regs->a1, regs->a2, out_val);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_UNINSTALL:
+		ret = sbi_dbtr_uninstall_trig(regs->a0, regs->a1);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_ENABLE:
+		ret = sbi_dbtr_enable_trig(regs->a0, regs->a1);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_UPDATE:
+		ret = sbi_dbtr_update_trig(dom, smode, regs->a0, regs->a1, regs->a2);
+		break;
+	case SBI_EXT_DBTR_TRIGGER_DISABLE:
+		ret = sbi_dbtr_disable_trig(regs->a0, regs->a1);
+		break;
+	default:
+		ret = SBI_ENOTSUPP;
+	};
+
+	return ret;
+}
+
+static int sbi_ecall_dbtr_probe(unsigned long extid, unsigned long *out_val)
+{
+	return sbi_dbtr_probe(out_val);
+}
+
+struct sbi_ecall_extension ecall_dbtr = {
+	.extid_start = SBI_EXT_DBTR,
+	.extid_end = SBI_EXT_DBTR,
+	.handle = sbi_ecall_dbtr_handler,
+	.probe = sbi_ecall_dbtr_probe,
+};
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..956afae 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -21,6 +21,7 @@
 #include <sbi/sbi_irqchip.h>
 #include <sbi/sbi_platform.h>
 #include <sbi/sbi_pmu.h>
+#include <sbi/sbi_dbtr.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_timer.h>
@@ -275,6 +276,10 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
+	rc = sbi_dbtr_init(scratch);
+	if (rc)
+		sbi_hart_hang();
+
 	sbi_boot_print_banner(scratch);
 
 	rc = sbi_irqchip_init(scratch, TRUE);
@@ -380,6 +385,10 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
+	rc = sbi_dbtr_init(scratch);
+	if (rc)
+		sbi_hart_hang();
+
 	rc = sbi_irqchip_init(scratch, FALSE);
 	if (rc)
 		sbi_hart_hang();
-- 
2.38.1



From geomatsi at gmail.com  Sat Dec  3 13:59:08 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sun, 4 Dec 2022 00:59:08 +0300
Subject: [PATCH RFC v2 0/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221203213929.206429-1-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
Message-ID: <Y4vGrLxywGPpCJ//@curiosity>

> This is the second revision of the patches implementing SBI Debug
> Trigger extension proposal posted at riscv tech-debug list:
> https://lists.riscv.org/g/tech-debug/topic/92375492
> 
> The major changes include support for mcounter trigger type and
> updates according to some of the review comments. 
> 
> As a part of endianness fixes, this revision includes a separate
> patch for a header with endianness conversion macros. Depending
> on the feedback, later on it can be reposted separately.
> 
> Regards,
> Sergey
> 
> Changes v1 -> v2:
> - add header with endianness conversion macros
> - fix endinanness: keep possible big-endian support in mind
> - do not mark shared structures as packed
> - add support for type 2 (mcounter) triggers
 
The accompanying patches for Linux and GDB has also been posted:
- https://patchwork.sourceware.org/project/gdb/patch/20221130182605.1905317-1-yuly.tarasov at syntacore.com/
- https://lore.kernel.org/linux-riscv/20221203215535.208948-1-geomatsi at gmail.com/T/#t

Regards,
Sergey


From bmeng at tinylab.org  Sat Dec  3 21:14:59 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:14:59 +0800
Subject: [PATCH v2 1/5] lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers
Message-ID: <20221204051503.439727-1-bmeng@tinylab.org>

Interrupt source 0 is reserved. Hence the irq should start from 1.

Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

(no changes since v1)

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 73d7788..4df9020 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 
 void plic_priority_save(const struct plic_data *plic, u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:15:01 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:15:01 +0800
Subject: [PATCH v2 3/5] lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
In-Reply-To: <20221204051503.439727-1-bmeng@tinylab.org>
References: <20221204051503.439727-1-bmeng@tinylab.org>
Message-ID: <20221204051503.439727-3-bmeng@tinylab.org>

The number of interrupt enable register in words was once correct,
but was wrongly changed to have an off-by-one error since
commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").

Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

 lib/utils/irqchip/plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index c5c1879..5b87d3b 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -121,7 +121,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
 	if (!plic || context_id < 0)
 		return SBI_EINVAL;
 
-	ie_words = (plic->num_src + 31) / 32;
+	ie_words = plic->num_src / 32 + 1;
 	ie_value = enable ? 0xffffffffU : 0U;
 
 	for (u32 i = 0; i < ie_words; i++)
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:15:00 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:15:00 +0800
Subject: [PATCH v2 2/5] libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
In-Reply-To: <20221204051503.439727-1-bmeng@tinylab.org>
References: <20221204051503.439727-1-bmeng@tinylab.org>
Message-ID: <20221204051503.439727-2-bmeng@tinylab.org>

Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h |  4 ++--
 include/sbi_utils/irqchip/plic.h             |  5 +++--
 lib/utils/irqchip/fdt_irqchip_plic.c         | 12 ++++++++----
 lib/utils/irqchip/plic.c                     |  9 +++++----
 platform/generic/allwinner/sun20i-d1.c       |  4 ++--
 5 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index 98d4de5..5f3f54d 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -9,9 +9,9 @@
 
 #include <sbi/sbi_types.h>
 
-void fdt_plic_priority_save(u8 *priority);
+void fdt_plic_priority_save(u8 *priority, u32 num);
 
-void fdt_plic_priority_restore(const u8 *priority);
+void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 48c24f0..38704a1 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -18,9 +18,10 @@ struct plic_data {
 };
 
 /* So far, priorities on all consumers of these functions fit in 8 bits. */
-void plic_priority_save(const struct plic_data *plic, u8 *priority);
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..87fb9bd 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -24,18 +24,22 @@ static struct plic_data plic[PLIC_MAX_NR];
 static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
 static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
 
-void fdt_plic_priority_save(u8 *priority)
+void fdt_plic_priority_save(u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_save(plic, priority);
+	if (num > plic->num_src + 1)
+		num = plic->num_src + 1;
+	plic_priority_save(plic, priority, num);
 }
 
-void fdt_plic_priority_restore(const u8 *priority)
+void fdt_plic_priority_restore(const u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_restore(plic, priority);
+	if (num > plic->num_src + 1)
+		num = plic->num_src + 1;
+	plic_priority_restore(plic, priority, num);
 }
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 4df9020..c5c1879 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -36,15 +36,16 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 	writel(val, plic_priority);
 }
 
-void plic_priority_save(const struct plic_data *plic, u8 *priority)
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	for (u32 i = 1; i <= num; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	for (u32 i = 1; i <= num; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 707313b..46d336f 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -79,13 +79,13 @@ static u32 plic_threshold;
 static void sun20i_d1_plic_save(void)
 {
 	fdt_plic_context_save(true, plic_sie, &plic_threshold);
-	fdt_plic_priority_save(plic_priority);
+	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
 static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
-	fdt_plic_priority_restore(plic_priority);
+	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
 	fdt_plic_context_restore(true, plic_sie, plic_threshold);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:15:02 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:15:02 +0800
Subject: [PATCH v2 4/5] lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
In-Reply-To: <20221204051503.439727-1-bmeng@tinylab.org>
References: <20221204051503.439727-1-bmeng@tinylab.org>
Message-ID: <20221204051503.439727-4-bmeng@tinylab.org>

plic->num_src holds the number of interrupt sources without interrupt
source 0 but the interrupt enable register includes a bit for the
interrupt source 0 in the first word.

Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 5b87d3b..0a1596c 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -94,7 +94,7 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
@@ -105,7 +105,7 @@ void plic_context_save(const struct plic_data *plic, int context_id,
 void plic_context_restore(const struct plic_data *plic, int context_id,
 			  const u32 *enable, u32 threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:15:03 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:15:03 +0800
Subject: [PATCH v2 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
In-Reply-To: <20221204051503.439727-1-bmeng@tinylab.org>
References: <20221204051503.439727-1-bmeng@tinylab.org>
Message-ID: <20221204051503.439727-5-bmeng@tinylab.org>

Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
 include/sbi_utils/irqchip/plic.h             |  4 ++--
 lib/utils/irqchip/fdt_irqchip_plic.c         | 21 ++++++++++++++------
 lib/utils/irqchip/plic.c                     | 12 ++++-------
 platform/generic/allwinner/sun20i-d1.c       |  5 +++--
 5 files changed, 27 insertions(+), 20 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index 5f3f54d..f855454 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -13,9 +13,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
 
 void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num);
 
 void thead_plic_restore(void);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 38704a1..112a714 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
 			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold);
+		       u32 *enable, u32 *threshold, u32 num);
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold);
+			  const u32 *enable, u32 threshold, u32 num);
 
 int plic_context_init(const struct plic_data *plic, int context_id,
 		      bool enable, u32 threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index 87fb9bd..e975415 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -42,22 +42,31 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
 	plic_priority_restore(plic, priority, num);
 }
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
 {
 	u32 hartid = current_hartid();
+	struct plic_data *plic = plic_hartid2data[hartid];
+	u32 ie_words = plic->num_src / 32 + 1;
 
-	plic_context_save(plic_hartid2data[hartid],
+	if (num > ie_words)
+		num = ie_words;
+	plic_context_save(plic,
 			  plic_hartid2context[hartid][smode],
-			  enable, threshold);
+			  enable, threshold, num);
 }
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num)
 {
 	u32 hartid = current_hartid();
+	struct plic_data *plic = plic_hartid2data[hartid];
+	u32 ie_words = plic->num_src / 32 + 1;
 
-	plic_context_restore(plic_hartid2data[hartid],
+	if (num > ie_words)
+		num = ie_words;
+	plic_context_restore(plic,
 			     plic_hartid2context[hartid][smode],
-			     enable, threshold);
+			     enable, threshold, num);
 }
 
 static int irqchip_plic_warm_init(void)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 0a1596c..5922c75 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -92,22 +92,18 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 }
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold)
+		       u32 *enable, u32 *threshold, u32 num)
 {
-	u32 ie_words = plic->num_src / 32 + 1;
-
-	for (u32 i = 0; i < ie_words; i++)
+	for (u32 i = 0; i < num; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
 
 	*threshold = plic_get_thresh(plic, context_id);
 }
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold)
+			  const u32 *enable, u32 threshold, u32 num)
 {
-	u32 ie_words = plic->num_src / 32 + 1;
-
-	for (u32 i = 0; i < ie_words; i++)
+	for (u32 i = 0; i < num; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
 
 	plic_set_thresh(plic, context_id, threshold);
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 46d336f..f6f7df1 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -78,7 +78,7 @@ static u32 plic_threshold;
 
 static void sun20i_d1_plic_save(void)
 {
-	fdt_plic_context_save(true, plic_sie, &plic_threshold);
+	fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
 	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
@@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
 	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
-	fdt_plic_context_restore(true, plic_sie, plic_threshold);
+	fdt_plic_context_restore(true, plic_sie, plic_threshold,
+				 PLIC_IE_WORDS);
 }
 
 /*
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:17:37 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:17:37 +0800
Subject: [RESEND PATCH v2 1/5] lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers
Message-ID: <20221204051741.440008-1-bmeng@tinylab.org>

Interrupt source 0 is reserved. Hence the irq should start from 1.

Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

(no changes since v1)

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 73d7788..4df9020 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 
 void plic_priority_save(const struct plic_data *plic, u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:17:38 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:17:38 +0800
Subject: [RESEND PATCH v2 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
In-Reply-To: <20221204051741.440008-1-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org>
Message-ID: <20221204051741.440008-2-bmeng@tinylab.org>

Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2 RESEND:
- %s/libs/lib in the commit title

Changes in v2:
- new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h |  4 ++--
 include/sbi_utils/irqchip/plic.h             |  5 +++--
 lib/utils/irqchip/fdt_irqchip_plic.c         | 12 ++++++++----
 lib/utils/irqchip/plic.c                     |  9 +++++----
 platform/generic/allwinner/sun20i-d1.c       |  4 ++--
 5 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index 98d4de5..5f3f54d 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -9,9 +9,9 @@
 
 #include <sbi/sbi_types.h>
 
-void fdt_plic_priority_save(u8 *priority);
+void fdt_plic_priority_save(u8 *priority, u32 num);
 
-void fdt_plic_priority_restore(const u8 *priority);
+void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 48c24f0..38704a1 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -18,9 +18,10 @@ struct plic_data {
 };
 
 /* So far, priorities on all consumers of these functions fit in 8 bits. */
-void plic_priority_save(const struct plic_data *plic, u8 *priority);
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..87fb9bd 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -24,18 +24,22 @@ static struct plic_data plic[PLIC_MAX_NR];
 static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
 static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
 
-void fdt_plic_priority_save(u8 *priority)
+void fdt_plic_priority_save(u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_save(plic, priority);
+	if (num > plic->num_src + 1)
+		num = plic->num_src + 1;
+	plic_priority_save(plic, priority, num);
 }
 
-void fdt_plic_priority_restore(const u8 *priority)
+void fdt_plic_priority_restore(const u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_restore(plic, priority);
+	if (num > plic->num_src + 1)
+		num = plic->num_src + 1;
+	plic_priority_restore(plic, priority, num);
 }
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 4df9020..c5c1879 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -36,15 +36,16 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 	writel(val, plic_priority);
 }
 
-void plic_priority_save(const struct plic_data *plic, u8 *priority)
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	for (u32 i = 1; i <= num; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	for (u32 i = 1; i <= num; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 707313b..46d336f 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -79,13 +79,13 @@ static u32 plic_threshold;
 static void sun20i_d1_plic_save(void)
 {
 	fdt_plic_context_save(true, plic_sie, &plic_threshold);
-	fdt_plic_priority_save(plic_priority);
+	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
 static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
-	fdt_plic_priority_restore(plic_priority);
+	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
 	fdt_plic_context_restore(true, plic_sie, plic_threshold);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:17:39 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:17:39 +0800
Subject: [RESEND PATCH v2 3/5] lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
In-Reply-To: <20221204051741.440008-1-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org>
Message-ID: <20221204051741.440008-3-bmeng@tinylab.org>

The number of interrupt enable register in words was once correct,
but was wrongly changed to have an off-by-one error since
commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").

Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

 lib/utils/irqchip/plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index c5c1879..5b87d3b 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -121,7 +121,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
 	if (!plic || context_id < 0)
 		return SBI_EINVAL;
 
-	ie_words = (plic->num_src + 31) / 32;
+	ie_words = plic->num_src / 32 + 1;
 	ie_value = enable ? 0xffffffffU : 0U;
 
 	for (u32 i = 0; i < ie_words; i++)
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:17:40 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:17:40 +0800
Subject: [RESEND PATCH v2 4/5] lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
In-Reply-To: <20221204051741.440008-1-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org>
Message-ID: <20221204051741.440008-4-bmeng@tinylab.org>

plic->num_src holds the number of interrupt sources without interrupt
source 0 but the interrupt enable register includes a bit for the
interrupt source 0 in the first word.

Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 5b87d3b..0a1596c 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -94,7 +94,7 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
@@ -105,7 +105,7 @@ void plic_context_save(const struct plic_data *plic, int context_id,
 void plic_context_restore(const struct plic_data *plic, int context_id,
 			  const u32 *enable, u32 threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec  3 21:17:41 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun,  4 Dec 2022 13:17:41 +0800
Subject: [RESEND PATCH v2 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
In-Reply-To: <20221204051741.440008-1-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org>
Message-ID: <20221204051741.440008-5-bmeng@tinylab.org>

Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v2:
- new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
 include/sbi_utils/irqchip/plic.h             |  4 ++--
 lib/utils/irqchip/fdt_irqchip_plic.c         | 21 ++++++++++++++------
 lib/utils/irqchip/plic.c                     | 12 ++++-------
 platform/generic/allwinner/sun20i-d1.c       |  5 +++--
 5 files changed, 27 insertions(+), 20 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index 5f3f54d..f855454 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -13,9 +13,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
 
 void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num);
 
 void thead_plic_restore(void);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 38704a1..112a714 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
 			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold);
+		       u32 *enable, u32 *threshold, u32 num);
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold);
+			  const u32 *enable, u32 threshold, u32 num);
 
 int plic_context_init(const struct plic_data *plic, int context_id,
 		      bool enable, u32 threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index 87fb9bd..e975415 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -42,22 +42,31 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
 	plic_priority_restore(plic, priority, num);
 }
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
 {
 	u32 hartid = current_hartid();
+	struct plic_data *plic = plic_hartid2data[hartid];
+	u32 ie_words = plic->num_src / 32 + 1;
 
-	plic_context_save(plic_hartid2data[hartid],
+	if (num > ie_words)
+		num = ie_words;
+	plic_context_save(plic,
 			  plic_hartid2context[hartid][smode],
-			  enable, threshold);
+			  enable, threshold, num);
 }
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num)
 {
 	u32 hartid = current_hartid();
+	struct plic_data *plic = plic_hartid2data[hartid];
+	u32 ie_words = plic->num_src / 32 + 1;
 
-	plic_context_restore(plic_hartid2data[hartid],
+	if (num > ie_words)
+		num = ie_words;
+	plic_context_restore(plic,
 			     plic_hartid2context[hartid][smode],
-			     enable, threshold);
+			     enable, threshold, num);
 }
 
 static int irqchip_plic_warm_init(void)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 0a1596c..5922c75 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -92,22 +92,18 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 }
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold)
+		       u32 *enable, u32 *threshold, u32 num)
 {
-	u32 ie_words = plic->num_src / 32 + 1;
-
-	for (u32 i = 0; i < ie_words; i++)
+	for (u32 i = 0; i < num; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
 
 	*threshold = plic_get_thresh(plic, context_id);
 }
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold)
+			  const u32 *enable, u32 threshold, u32 num)
 {
-	u32 ie_words = plic->num_src / 32 + 1;
-
-	for (u32 i = 0; i < ie_words; i++)
+	for (u32 i = 0; i < num; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
 
 	plic_set_thresh(plic, context_id, threshold);
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 46d336f..f6f7df1 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -78,7 +78,7 @@ static u32 plic_threshold;
 
 static void sun20i_d1_plic_save(void)
 {
-	fdt_plic_context_save(true, plic_sie, &plic_threshold);
+	fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
 	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
@@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
 	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
-	fdt_plic_context_restore(true, plic_sie, plic_threshold);
+	fdt_plic_context_restore(true, plic_sie, plic_threshold,
+				 PLIC_IE_WORDS);
 }
 
 /*
-- 
2.34.1



From bmeng.cn at gmail.com  Sat Dec  3 21:25:57 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sun, 4 Dec 2022 13:25:57 +0800
Subject: [PATCH 1/1] gitignore: add vim swap files
In-Reply-To: <20221203210415.113835-1-geomatsi@gmail.com>
References: <20221203210415.113835-1-geomatsi@gmail.com>
Message-ID: <CAEUhbmWq26tZDkXGC2c3dK+nMjY5WHZiAXzgBnQGq88XBq7k6g@mail.gmail.com>

On Sun, Dec 4, 2022 at 5:06 AM Sergey Matyukevich <geomatsi at gmail.com> wrote:
>
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
>
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> ---
>  .gitignore | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From wxjstz at 126.com  Sun Dec  4 03:56:16 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 04 Dec 2022 19:56:16 +0800
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221203213929.206429-3-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
	 <20221203213929.206429-3-geomatsi@gmail.com>
Message-ID: <57086abe77447357d6f33cc92f713e2c08860c0b.camel@126.com>

? 2022-12-04???? 00:39 +0300?Sergey Matyukevich???
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> 
> RISC-V Debug specification includes Sdtrig ISA extension.
> This extension describes Trigger Module. Triggers can cause
> a breakpoint exception, entry into Debug Mode, or a trace
> action without having to execute a special instruction. For
> native debugging triggers can be used to implement hardware
> breakpoints and watchpoints.
> 
> Software support for triggers consists of the following
> major components:
> - U-mode: gdb
> - S-mode: hardware breakpoints framework in Linux kernel
> - M-mode: SBI firmware code to handle triggers
> 
> SBI Debug Trigger extension proposal has been posted by
> Anup Patel to lists.riscv.org tech-debug mailing list:
> https://lists.riscv.org/g/tech-debug/topic/92375492
> 
> This patch provides initial implementation of SBI Debug
> Trigger Extension in OpenSBI library based on the
> suggested extension proposal.
> 
> Initial implementation has the following limitations:
> - supported triggers: mcontrol, mcontrol6
> - no support for chained triggers
> - only build test for RV32
> 
Missing Signed-off-by

Compilation preprocessing too much. It is recommended to process register
fields by defining some masks, and via INSERT_FIELD and EXTRACT_FIELD.

Regards,
Xiang W
> ---
> ?include/sbi/riscv_dbtr.h????????? | 179 +++++++++++
> ?include/sbi/riscv_encoding.h????? |?? 1 +
> ?include/sbi/sbi_dbtr.h??????????? |? 80 +++++
> ?include/sbi/sbi_ecall_interface.h |? 10 +
> ?lib/sbi/Kconfig?????????????????? |?? 4 +
> ?lib/sbi/objects.mk??????????????? |?? 4 +
> ?lib/sbi/sbi_dbtr.c??????????????? | 481 ++++++++++++++++++++++++++++++
> ?lib/sbi/sbi_ecall_dbtr.c????????? |? 68 +++++
> ?lib/sbi/sbi_init.c??????????????? |?? 9 +
> ?9 files changed, 836 insertions(+)
> ?create mode 100644 include/sbi/riscv_dbtr.h
> ?create mode 100644 include/sbi/sbi_dbtr.h
> ?create mode 100644 lib/sbi/sbi_dbtr.c
> ?create mode 100644 lib/sbi/sbi_ecall_dbtr.c
> 
> diff --git a/include/sbi/riscv_dbtr.h b/include/sbi/riscv_dbtr.h
> new file mode 100644
> index 0000000..9944547
> --- /dev/null
> +++ b/include/sbi/riscv_dbtr.h
> @@ -0,0 +1,179 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __RISCV_DBTR_H__
> +#define __RISCV_DBTR_H__
> +
> +#define RV_MAX_TRIGGERS????????32
> +
> +enum {
> +???????RISCV_DBTR_TRIG_NONE = 0,
> +???????RISCV_DBTR_TRIG_LEGACY,
> +???????RISCV_DBTR_TRIG_MCONTROL,
> +???????RISCV_DBTR_TRIG_ICOUNT,
> +???????RISCV_DBTR_TRIG_ITRIGGER,
> +???????RISCV_DBTR_TRIG_ETRIGGER,
> +???????RISCV_DBTR_TRIG_MCONTROL6,
> +};
> +
> +union riscv_dbtr_tdata1 {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long data:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +#if __riscv_xlen == 64
> +???????????????unsigned long data:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +union riscv_dbtr_tdata1_mcontrol {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long maskmax:6;
> +#if __riscv_xlen >= 64
> +???????????????unsigned long _res1:30;
> +???????????????unsigned long sizehi:2;
> +#endif
> +???????????????unsigned long hit:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long sizelo:2;
> +???????????????unsigned long action:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long m:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +???????????????unsigned long load:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long m:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long action:4;
> +???????????????unsigned long sizelo:2;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long hit:1;
> +#if __riscv_xlen >= 64
> +???????????????unsigned long sizehi:2;
> +???????????????unsigned long _res1:30;
> +#endif
> +???????????????unsigned long maskmax:6;
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +#define MCONTROL_U_OFFSET??????3
> +#define MCONTROL_S_OFFSET??????4
> +#define MCONTROL_M_OFFSET??????6
> +
> +union riscv_dbtr_tdata1_mcontrol6 {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long vs:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long hit:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long size:4;
> +???????????????unsigned long action:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long m:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +???????????????unsigned long load:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long m:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long action:4;
> +???????????????unsigned long size:4;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long hit:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long vs:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +#define MCONTROL6_U_OFFSET?????3
> +#define MCONTROL6_S_OFFSET?????4
> +#define MCONTROL6_M_OFFSET?????6
> +#define MCONTROL6_VU_OFFSET????23
> +#define MCONTROL6_VS_OFFSET????24
> +
> +#endif /* __RISCV_DBTR_H__ */
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index b0f08c8..2041ab7 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -671,6 +671,7 @@
> ?#define CSR_TDATA1?????????????????????0x7a1
> ?#define CSR_TDATA2?????????????????????0x7a2
> ?#define CSR_TDATA3?????????????????????0x7a3
> +#define CSR_TINFO??????????????????????0x7a4
> ?
> ?/* Debug Mode Registers */
> ?#define CSR_DCSR???????????????????????0x7b0
> diff --git a/include/sbi/sbi_dbtr.h b/include/sbi/sbi_dbtr.h
> new file mode 100644
> index 0000000..5ef6166
> --- /dev/null
> +++ b/include/sbi/sbi_dbtr.h
> @@ -0,0 +1,80 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __SBI_DBTR_H__
> +#define __SBI_DBTR_H__
> +
> +#include <sbi/riscv_endian.h>
> +#include <sbi/riscv_dbtr.h>
> +
> +#include <sbi/sbi_hartmask.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_types.h>
> +
> +/** Representation of trigger state */
> +union sbi_dbtr_trig_state {
> +???????unsigned long value;
> +???????struct {
> +???????????????unsigned long mapped:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long vs:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long reserved:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long reserved:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????};
> +};
> +
> +struct sbi_dbtr_trig_info {
> +???????unsigned long type_mask;
> +???????union sbi_dbtr_trig_state state;
> +???????unsigned long tdata1;
> +???????unsigned long tdata2;
> +???????unsigned long tdata3;
> +};
> +
> +/** SBI shared mem messages layout */
> +struct sbi_dbtr_data_msg {
> +???????unsigned long tstate;
> +???????unsigned long tdata1;
> +???????unsigned long tdata2;
> +???????unsigned long tdata3;
> +};
> +
> +struct sbi_dbtr_id_msg {
> +???????unsigned long idx;
> +};
> +
> +/** Initialize PMU */
> +int sbi_dbtr_init(struct sbi_scratch *scratch);
> +
> +/** SBI DBTR extension functions */
> +int sbi_dbtr_probe(unsigned long *out);
> +int sbi_dbtr_num_trig(unsigned long trig_tdata1, unsigned long *out);
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_count,
> +???????????????unsigned long out_addr_div_by_16);
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16, unsigned long *out);
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16);
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +
> +#endif
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index a3f2bf4..3c1b1ea 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -29,6 +29,7 @@
> ?#define SBI_EXT_HSM????????????????????????????0x48534D
> ?#define SBI_EXT_SRST???????????????????????????0x53525354
> ?#define SBI_EXT_PMU????????????????????????????0x504D55
> +#define SBI_EXT_DBTR???????????????????????????0x44425452
> ?
> ?/* SBI function IDs for BASE extension*/
> ?#define SBI_EXT_BASE_GET_SPEC_VERSION??????????0x0
> @@ -100,6 +101,15 @@
> ?#define SBI_EXT_PMU_COUNTER_STOP???????0x4
> ?#define SBI_EXT_PMU_COUNTER_FW_READ????0x5
> ?
> +/* SBI function IDs for DBTR extension */
> +#define SBI_EXT_DBTR_NUM_TRIGGERS??????0x0
> +#define SBI_EXT_DBTR_TRIGGER_READ??????0x1
> +#define SBI_EXT_DBTR_TRIGGER_INSTALL???0x2
> +#define SBI_EXT_DBTR_TRIGGER_UNINSTALL?0x3
> +#define SBI_EXT_DBTR_TRIGGER_ENABLE????0x4
> +#define SBI_EXT_DBTR_TRIGGER_UPDATE????0x5
> +#define SBI_EXT_DBTR_TRIGGER_DISABLE???0x6
> +
> ?/** General pmu event codes specified in SBI PMU extension */
> ?enum sbi_pmu_hw_generic_events_t {
> ????????SBI_PMU_HW_NO_EVENT?????????????????????= 0,
> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> index df74bba..e3a7955 100644
> --- a/lib/sbi/Kconfig
> +++ b/lib/sbi/Kconfig
> @@ -34,4 +34,8 @@ config SBI_ECALL_VENDOR
> ????????bool "Platform-defined vendor extensions"
> ????????default y
> ?
> +config SBI_ECALL_DBTR
> +???????bool "Debug Trigger Extension"
> +???????default y
> +
> ?endmenu
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index c774ebb..36276e8 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -43,6 +43,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
> ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
> ?libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
> ?
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBTR) += ecall_dbtr
> +libsbi-objs-$(CONFIG_SBI_ECALL_DBTR) += sbi_ecall_dbtr.o
> +
> ?libsbi-objs-y += sbi_bitmap.o
> ?libsbi-objs-y += sbi_bitops.o
> ?libsbi-objs-y += sbi_console.o
> @@ -60,6 +63,7 @@ libsbi-objs-y += sbi_irqchip.o
> ?libsbi-objs-y += sbi_misaligned_ldst.o
> ?libsbi-objs-y += sbi_platform.o
> ?libsbi-objs-y += sbi_pmu.o
> +libsbi-objs-y += sbi_dbtr.o
> ?libsbi-objs-y += sbi_scratch.o
> ?libsbi-objs-y += sbi_string.o
> ?libsbi-objs-y += sbi_system.o
> diff --git a/lib/sbi/sbi_dbtr.c b/lib/sbi/sbi_dbtr.c
> new file mode 100644
> index 0000000..bbad0cf
> --- /dev/null
> +++ b/lib/sbi/sbi_dbtr.c
> @@ -0,0 +1,481 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_csr_detect.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/riscv_asm.h>
> +
> +static struct sbi_dbtr_trig_info triggers[SBI_HARTMASK_MAX_BITS][RV_MAX_TRIGGERS] = {0};
> +static uint32_t total_trigs;
> +
> +static void sbi_triggers_table_init(u32 hartid, int idx, unsigned long type_mask)
> +{
> +???????triggers[hartid][idx].type_mask = type_mask;
> +???????triggers[hartid][idx].state.value = 0;
> +???????triggers[hartid][idx].tdata1 = 0;
> +???????triggers[hartid][idx].tdata2 = 0;
> +???????triggers[hartid][idx].tdata3 = 0;
> +}
> +
> +int sbi_dbtr_init(struct sbi_scratch *scratch)
> +{
> +???????struct sbi_trap_info trap = {0};
> +???????u32 hartid = current_hartid();
> +???????union riscv_dbtr_tdata1 tdata1;
> +???????unsigned long val;
> +???????int i;
> +
> +???????total_trigs = 0;
> +
> +???????for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> +???????????????csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
> +???????????????if (trap.cause)
> +???????????????????????break;
> +
> +???????????????val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
> +???????????????if (trap.cause)
> +???????????????????????break;
> +
> +???????????????/* Read back tselect and check that it contains the written value */
> +???????????????if (val != i)
> +???????????????????????break;
> +
> +???????????????val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
> +???????????????if (trap.cause) {
> +???????????????????????/**
> +??????????????????????? * If reading tinfo caused an exception, the debugger
> +??????????????????????? * must read tdata1 to discover the type.
> +??????????????????????? */
> +???????????????????????tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
> +???????????????????????if (trap.cause)
> +???????????????????????????????break;
> +
> +???????????????????????if (tdata1.type == 0)
> +???????????????????????????????break;
> +
> +
> +???????????????????????sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
> +???????????????????????total_trigs++;
> +???????????????} else {
> +???????????????????????if (val == 1)
> +???????????????????????????????break;
> +
> +???????????????????????sbi_triggers_table_init(hartid, i, val);
> +???????????????????????total_trigs++;
> +???????????????}
> +???????}
> +
> +???????return 0;
> +}
> +
> +int sbi_dbtr_probe(unsigned long *out)
> +{
> +???????*out? = total_trigs;
> +
> +???????return 0;
> +}
> +
> +
> +static void dbtr_trigger_init(unsigned int hartid, unsigned int idx,
> +???????????????????????????? struct sbi_dbtr_data_msg *recv)
> +{
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????triggers[hartid][idx].tdata1 = lle_to_cpu(recv->tdata1);
> +???????triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +???????triggers[hartid][idx].tdata3 = lle_to_cpu(recv->tdata3);
> +???????triggers[hartid][idx].state.mapped = 1;
> +
> +???????tdata1.value = lle_to_cpu(recv->tdata1);
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????triggers[hartid][idx].state.u = __test_bit(MCONTROL_U_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.s = __test_bit(MCONTROL_S_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vu = 0;
> +???????????????triggers[hartid][idx].state.vs = 0;
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????triggers[hartid][idx].state.u = __test_bit(MCONTROL6_U_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.s = __test_bit(MCONTROL6_S_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vu = __test_bit(MCONTROL6_VU_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vs = __test_bit(MCONTROL6_VS_OFFSET, &tdata1.value);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +}
> +
> +static inline void update_bit(unsigned long new, int nr, volatile unsigned long *addr)
> +{
> +???????if (new)
> +???????????????__set_bit(nr, addr);
> +???????else
> +???????????????__clear_bit(nr, addr);
> +}
> +
> +static void dbtr_trigger_enable(unsigned int hartid, unsigned int idx)
> +{
> +???????union sbi_dbtr_trig_state state;
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????state.value = triggers[hartid][idx].state.value;
> +???????tdata1.value = triggers[hartid][idx].tdata1;
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????update_bit(state.u, MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.s, MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????update_bit(state.vu, MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.vs, MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.u, MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.s, MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????/*
> +??????? * RISC-V Debug Support v1.0.0 section 5.5:
> +??????? * Debugger cannot simply set a trigger by writing tdata1, then tdata2, etc. The current
> +??????? * value of tdata2 might not be legal with the new value of tdata1. To help with this
> +??????? * situation, it is guaranteed that writing 0 to tdata1 disables the trigger, and
> +??????? * leaves it in a state where tdata2 and tdata3 can be written with any value
> +??????? * that makes sense for any trigger type supported by this trigger.
> +??????? */
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, 0x0);
> +???????csr_write(CSR_TDATA2, triggers[hartid][idx].tdata2);
> +???????csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_disable(unsigned int hartid, unsigned int idx)
> +{
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????tdata1.value = triggers[hartid][idx].tdata1;
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????__clear_bit(MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????__clear_bit(MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_clear(unsigned int hartid, unsigned int idx)
> +{
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, 0x0);
> +???????csr_write(CSR_TDATA2, 0x0);
> +}
> +
> +static int dbtr_trigger_supported(unsigned long type)
> +{
> +???????switch (type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????return 1;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????return 0;
> +}
> +
> +static int dbtr_trigger_valid(unsigned long type, unsigned long tdata)
> +{
> +???????union riscv_dbtr_tdata1_mcontrol6 control6;
> +???????union riscv_dbtr_tdata1_mcontrol control;
> +
> +???????switch (type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????control.value = tdata;
> +???????????????if (!control.action && !control.dmode && !control.m)
> +???????????????????????return 1;
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????control6.value = tdata;
> +???????????????if (!control6.action && !control6.dmode && !control6.m)
> +???????????????????????return 1;
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????return 0;
> +}
> +
> +int sbi_dbtr_num_trig(unsigned long data, unsigned long *out)
> +{
> +???????unsigned long type = ((union riscv_dbtr_tdata1)data).type;
> +???????u32 hartid = current_hartid();
> +???????unsigned long total = 0;
> +???????int i;
> +
> +
> +???????if (data == 0) {
> +???????????????sbi_dprintf("%s: hart%d: total triggers: %u\n",
> +?????????????????????????? __func__, hartid, total_trigs);
> +???????????????*out = total_trigs;
> +???????????????return SBI_SUCCESS;
> +???????}
> +
> +???????for (i = 0; i < total_trigs; i++) {
> +???????????????if (__test_bit(type, &triggers[hartid][i].type_mask))
> +???????????????????????total++;
> +???????}
> +
> +
> +???????sbi_dprintf("%s: hart%d: total triggers of type %lu: %lu\n",
> +?????????????????? __func__, hartid, type, total);
> +
> +???????*out = total;
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_count,
> +???????????????unsigned long out_addr_div_by_16)
> +{
> +???????unsigned long out_addr = (out_addr_div_by_16 << 4);
> +???????struct sbi_dbtr_data_msg *xmit;
> +???????u32 hartid = current_hartid();
> +???????int i;
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????if (trig_idx_base >= total_trigs || trig_idx_base + trig_count >= total_trigs) {
> +???????????????sbi_dprintf("%s: hart%d: invalid trigger index\n", __func__, hartid);
> +???????????????return SBI_ERR_INVALID_PARAM;
> +???????}
> +
> +???????for (i = 0; i < trig_count; i++) {
> +???????????????xmit = (struct sbi_dbtr_data_msg *)(out_addr + i * sizeof(*xmit));
> +
> +???????????????sbi_dprintf("%s: hart%d: read trigger %d\n", __func__, hartid, i);
> +
> +???????????????xmit->tstate = cpu_to_lle(triggers[hartid][i + trig_idx_base].state.value);
> +???????????????xmit->tdata1 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata1);
> +???????????????xmit->tdata2 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata2);
> +???????????????xmit->tdata3 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata3);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16, unsigned long *out)
> +{
> +???????unsigned long out_addr = (out_addr_div_by_16 << 4);
> +???????unsigned long in_addr = (in_addr_div_by_16 << 4);
> +???????u32 hartid = current_hartid();
> +???????struct sbi_dbtr_data_msg *recv;
> +???????struct sbi_dbtr_id_msg *xmit;
> +???????union riscv_dbtr_tdata1 ctrl;
> +???????int i, k;
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +???????if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????/* TODO: check chained triggers configurations */
> +
> +???????/* Check requested triggers configuration */
> +???????for (k = 0; k < trig_count; k++) {
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +???????????????ctrl = (union riscv_dbtr_tdata1)recv->tdata1;
> +
> +???????????????if (!dbtr_trigger_supported(ctrl.type)) {
> +???????????????????????sbi_dprintf("%s: invalid type of trigger %d\n", __func__, k);
> +???????????????????????*out = k;
> +???????????????????????return SBI_ERR_FAILED;
> +???????????????}
> +
> +???????????????if (!dbtr_trigger_valid(ctrl.type, ctrl.value)) {
> +???????????????????????sbi_dprintf("%s: invalid configuration of trigger %d\n", __func__, k);
> +???????????????????????*out = k;
> +???????????????????????return SBI_ERR_FAILED;
> +???????????????}
> +???????}
> +
> +???????/* Check if we have enough spare triggers */
> +???????for (i = 0, k = 0; i < total_trigs; i++) {
> +???????????????if (!triggers[hartid][i].state.mapped)
> +???????????????????????k++;
> +???????}
> +
> +???????if (k < trig_count) {
> +???????????????sbi_dprintf("%s: hartid%d: not enough spare triggers\n", __func__, hartid);
> +???????????????*out = k;
> +???????????????return SBI_ERR_FAILED;
> +???????}
> +
> +???????/* Install triggers */
> +???????for (i = 0, k = 0; i < total_trigs; i++) {
> +???????????????if (triggers[hartid][i].state.mapped)
> +???????????????????????continue;
> +
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +???????????????xmit = (struct sbi_dbtr_id_msg *)(out_addr + k * sizeof(*xmit));
> +
> +???????????????sbi_dprintf("%s: hart%d: idx[%d] tdata1[0x%lx] tdata2[0x%lx]\n",
> +?????????????????????????? __func__, hartid, i, recv->tdata1, recv->tdata2);
> +
> +???????????????dbtr_trigger_init(hartid, i,? recv);
> +???????????????dbtr_trigger_enable(hartid, i);
> +???????????????xmit->idx = cpu_to_lle(i);
> +
> +???????????????if (++k >= trig_count)
> +???????????????????????break;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????if (!triggers[hartid][idx].state.mapped) {
> +???????????????????????sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +???????????????????????return SBI_ERR_INVALID_PARAM;
> +???????????????}
> +
> +???????????????sbi_dprintf("%s: clear trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_clear(hartid, idx);
> +
> +???????????????triggers[hartid][idx].state.value = 0;
> +???????????????triggers[hartid][idx].tdata1 = 0;
> +???????????????triggers[hartid][idx].tdata2 = 0;
> +???????????????triggers[hartid][idx].tdata3 = 0;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????sbi_dprintf("%s: enable trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_enable(hartid, idx);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_idx_mask,
> +???????????????unsigned long in_addr_div_by_16)
> +{
> +???????unsigned long in_addr = (in_addr_div_by_16 << 4);
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +???????struct sbi_dbtr_data_msg *recv;
> +???????unsigned long uidx = 0;
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????if (!triggers[hartid][idx].state.mapped) {
> +???????????????????????sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +???????????????????????return SBI_ERR_INVALID_PARAM;
> +???????????????}
> +
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + uidx * sizeof(*recv));
> +
> +???????????????sbi_dprintf("%s: update trigger %lu: newaddr 0x%lx\n",
> +?????????????????????????? __func__, idx, recv->tdata2);
> +
> +???????????????triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +???????????????dbtr_trigger_enable(hartid, idx);
> +???????????????uidx++;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????sbi_dprintf("%s: disable trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_disable(hartid, idx);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> diff --git a/lib/sbi/sbi_ecall_dbtr.c b/lib/sbi/sbi_ecall_dbtr.c
> new file mode 100644
> index 0000000..d013b3e
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_dbtr.c
> @@ -0,0 +1,68 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_version.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +static int sbi_ecall_dbtr_handler(unsigned long extid, unsigned long funcid,
> +???????????????????????????????? const struct sbi_trap_regs *regs,
> +???????????????????????????????? unsigned long *out_val,
> +???????????????????????????????? struct sbi_trap_info *out_trap)
> +{
> +???????unsigned long smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
> +???????????????????????MSTATUS_MPP_SHIFT;
> +???????const struct sbi_domain *dom = sbi_domain_thishart_ptr();
> +???????int ret = 0;
> +
> +???????switch (funcid) {
> +???????case SBI_EXT_DBTR_NUM_TRIGGERS:
> +???????????????ret = sbi_dbtr_num_trig(regs->a0, out_val);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_READ:
> +???????????????ret = sbi_dbtr_read_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_INSTALL:
> +???????????????ret = sbi_dbtr_install_trig(dom, smode, regs->a0, regs->a1, regs->a2, out_val);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_UNINSTALL:
> +???????????????ret = sbi_dbtr_uninstall_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_ENABLE:
> +???????????????ret = sbi_dbtr_enable_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_UPDATE:
> +???????????????ret = sbi_dbtr_update_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_DISABLE:
> +???????????????ret = sbi_dbtr_disable_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????default:
> +???????????????ret = SBI_ENOTSUPP;
> +???????};
> +
> +???????return ret;
> +}
> +
> +static int sbi_ecall_dbtr_probe(unsigned long extid, unsigned long *out_val)
> +{
> +???????return sbi_dbtr_probe(out_val);
> +}
> +
> +struct sbi_ecall_extension ecall_dbtr = {
> +???????.extid_start = SBI_EXT_DBTR,
> +???????.extid_end = SBI_EXT_DBTR,
> +???????.handle = sbi_ecall_dbtr_handler,
> +???????.probe = sbi_ecall_dbtr_probe,
> +};
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..956afae 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -21,6 +21,7 @@
> ?#include <sbi/sbi_irqchip.h>
> ?#include <sbi/sbi_platform.h>
> ?#include <sbi/sbi_pmu.h>
> +#include <sbi/sbi_dbtr.h>
> ?#include <sbi/sbi_system.h>
> ?#include <sbi/sbi_string.h>
> ?#include <sbi/sbi_timer.h>
> @@ -275,6 +276,10 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
> ????????if (rc)
> ????????????????sbi_hart_hang();
> ?
> +???????rc = sbi_dbtr_init(scratch);
> +???????if (rc)
> +???????????????sbi_hart_hang();
> +
> ????????sbi_boot_print_banner(scratch);
> ?
> ????????rc = sbi_irqchip_init(scratch, TRUE);
> @@ -380,6 +385,10 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
> ????????if (rc)
> ????????????????sbi_hart_hang();
> ?
> +???????rc = sbi_dbtr_init(scratch);
> +???????if (rc)
> +???????????????sbi_hart_hang();
> +
> ????????rc = sbi_irqchip_init(scratch, FALSE);
> ????????if (rc)
> ????????????????sbi_hart_hang();
> -- 
> 2.38.1
> 
> 




From wxjstz at 126.com  Sun Dec  4 03:57:57 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 04 Dec 2022 19:57:57 +0800
Subject: [PATCH 1/1] gitignore: add vim swap files
In-Reply-To: <20221203210415.113835-1-geomatsi@gmail.com>
References: <20221203210415.113835-1-geomatsi@gmail.com>
Message-ID: <d3e17bf0634eaf67facc346480c3ad50fb813f0c.camel@126.com>

? 2022-12-04???? 00:04 +0300?Sergey Matyukevich???
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> 
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?.gitignore | 1 +
> ?1 file changed, 1 insertion(+)
> 
> diff --git a/.gitignore b/.gitignore
> index 95692bb..c11afd3 100644
> --- a/.gitignore
> +++ b/.gitignore
> @@ -10,3 +10,4 @@ install/
> ?# Development friendly files
> ?tags
> ?cscope*
> +*.swp
> -- 
> 2.38.1
> 
> 




From anup at brainfault.org  Sun Dec  4 07:05:47 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 20:35:47 +0530
Subject: [PATCH] platform: generic/allwinner: Remove ghostly type cast
In-Reply-To: <20221119085507.156418-1-wxjstz@126.com>
References: <20221119085507.156418-1-wxjstz@126.com>
Message-ID: <CAAhSdy1Ny+QOzQOiEqSF-Ke7Jv=v9LH4n0Qmv=PM8hpSzByCQA@mail.gmail.com>

On Sat, Nov 19, 2022 at 2:25 PM Xiang W <wxjstz at 126.com> wrote:
>
> Corrected the same parameter of writel_relaxed in sun20i_d1_riscv_cfg_init
> to be u32 for a while and u64 for a while.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  platform/generic/allwinner/sun20i-d1.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 6a502e5..18fcf56 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -146,14 +146,14 @@ static void sun20i_d1_riscv_cfg_restore(void)
>
>  static void sun20i_d1_riscv_cfg_init(void)
>  {
> -       unsigned long entry = sbi_hartid_to_scratch(0)->warmboot_addr;
> +       u64 entry = sbi_hartid_to_scratch(0)->warmboot_addr;
>
>         /* Enable MMIO access. */
>         writel_relaxed(CCU_BGR_ENABLE, SUN20I_D1_CCU_BASE + RISCV_CFG_BGR_REG);
>
>         /* Program the reset entry address. */
> -       writel_relaxed((u32)entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
> -       writel_relaxed((u64)entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
> +       writel_relaxed(entry, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_LO_REG);
> +       writel_relaxed(entry >> 32, SUN20I_D1_RISCV_CFG_BASE + RESET_ENTRY_HI_REG);
>  }
>
>  static int sun20i_d1_hart_suspend(u32 suspend_type)
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec  4 07:18:18 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 20:48:18 +0530
Subject: [PATCH] Makefile: replace `echo` with `printf` for compatibility
In-Reply-To: <20221121155905.48577-1-kalle.wachsmuth@gmail.com>
References: <20221121155905.48577-1-kalle.wachsmuth@gmail.com>
Message-ID: <CAAhSdy2Lw+2_o0wgCBdT+6Wj=HKJvo7FNkCLyFWDw0XMLJHn1g@mail.gmail.com>

On Mon, Nov 21, 2022 at 9:29 PM KaDiWa <kalle.wachsmuth at gmail.com> wrote:
>
> I don't know why but `echo -n` didn't work for me. macOS supports the `-n` option but it doesn't work in the makefile. What it does instead is it literally writes `-n` to the file and then also
> leaves a newline at the end.

Please try to wrap your commit description text within 80 characters.

>
> I'm using GNU Make 4.4 (`gmake` from Homebrew).
>
> Signed-off-by: KaDiWa <kalle.wachsmuth at gmail.com>
> ---
>  Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Makefile b/Makefile
> index 8db6eab..98e42fc 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -224,7 +224,7 @@ $(KCONFIG_CONFIG): $(platform_src_dir)/configs/$(PLATFORM_DEFCONFIG) $(platform_
>
>  $(KCONFIG_AUTOCMD): $(KCONFIG_CONFIG)
>         $(CMD_PREFIX)mkdir -p $(KCONFIG_DIR)
> -       $(CMD_PREFIX)echo -n "$(KCONFIG_CONFIG): " > $(KCONFIG_AUTOCMD)
> +       $(CMD_PREFIX)printf "%s: " $(KCONFIG_CONFIG) > $(KCONFIG_AUTOCMD)
>         $(CMD_PREFIX)cat $(KCONFIG_AUTOLIST) | tr '\n' ' ' >> $(KCONFIG_AUTOCMD)
>
>  include $(KCONFIG_CONFIG)
> --
> 2.37.1 (Apple Git-137.1)
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Apart from the above comment, this looks good to me. I have
taken care of the above comment at the time of merging this patch.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


From anup at brainfault.org  Sun Dec  4 07:32:24 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 21:02:24 +0530
Subject: [PATCH] Makefile: bugfix for handling platform paths
In-Reply-To: <904be39c57862760477bc0663527c55ab6db6ad2.camel@126.com>
References: <20221122102825.88440-1-aldaya@gmail.com> <904be39c57862760477bc0663527c55ab6db6ad2.camel@126.com>
Message-ID: <CAAhSdy3OKUZ-v0N5QR7T6ySPVSf5gJqfhShYUg5oMKE5EOVbgQ@mail.gmail.com>

On Tue, Nov 22, 2022 at 7:12 PM Xiang W <wxjstz at 126.com> wrote:
>
> ? 2022-11-22???? 12:28 +0200?Alejandro Cabrera Aldaya???
> > If the path where this repo is located contains the platform name on it,
> > the original Makefile replaced its occurrences from the path making it an invalid path.
> > This commit prevents this behavior replacing only the last part of the path as intended.
> >
> > Signed-off-by: Alejandro Cabrera Aldaya <aldaya at gmail.com>
> > ---
> >  Makefile | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Makefile b/Makefile
> > index 8db6eab..32d4c48 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -47,7 +47,7 @@ ifdef PLATFORM_DIR
> >      platform_parent_dir=$(platform_dir_path)
> >    else
> >      PLATFORM=$(shell basename $(platform_dir_path))
> > -    platform_parent_dir=$(subst $(PLATFORM),,$(platform_dir_path))
> > +    platform_parent_dir=$(shell dirname $(shell realpath $(platform_dir_path)))
> >
>
> Looks good, could simplify it a bit.
>         platform_parent_dir=$(shell realpath ${platform_dir_path}/..)
>
> Reviewed-by: Xiang W <wxjstz at 126.com>

I have considered the simplified version at the time of merging
this patch.

Reviewed-by: Anup Patel <anup at brainfaul.torg>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> >    endif
> >  else
> >   platform_parent_dir=$(src_dir)/platform
> > --
> > 2.34.1
> >
> >
>
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec  4 08:29:24 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 21:59:24 +0530
Subject: [PATCH v2 1/3] lib: sbi: Simplified mmio match checking
In-Reply-To: <20221124031605.216192-2-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com> <20221124031605.216192-2-wxjstz@126.com>
Message-ID: <CAAhSdy1q327TWgEGSx9-+rJyZxEzxrstB-nNEMzTN7XbE-EtgA@mail.gmail.com>

On Thu, Nov 24, 2022 at 8:46 AM Xiang W <wxjstz at 126.com> wrote:
>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
>  lib/sbi/sbi_domain.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index f24a8e5..fec9074 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -105,7 +105,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
>                            unsigned long addr, unsigned long mode,
>                            unsigned long access_flags)
>  {
> -       bool mmio = FALSE;
> +       bool rmmio, mmio = FALSE;
>         struct sbi_domain_memregion *reg;
>         unsigned long rstart, rend, rflags, rwx = 0;
>
> @@ -130,8 +130,8 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
>                 rend = (reg->order < __riscv_xlen) ?
>                         rstart + ((1UL << reg->order) - 1) : -1UL;
>                 if (rstart <= addr && addr <= rend) {
> -                       if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
> -                           (!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
> +                       rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
> +                       if (mmio != rmmio)
>                                 return FALSE;
>                         return ((rflags & rwx) == rwx) ? TRUE : FALSE;
>                 }
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Please try to have at least one sentence in the commit description.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Regards,
Anup


From anup at brainfault.org  Sun Dec  4 08:31:09 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 22:01:09 +0530
Subject: [PATCH v2 2/3] lib: sbi: add in_region
In-Reply-To: <20221124031605.216192-3-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com> <20221124031605.216192-3-wxjstz@126.com>
Message-ID: <CAAhSdy3gEKXGzSshQvo7VA6xCggbLeaor2GXyVgv71R2JWXDQQ@mail.gmail.com>

On Thu, Nov 24, 2022 at 8:46 AM Xiang W <wxjstz at 126.com> wrote:
>
> It is a common operation to judge whether an address is in a
> certain region, and add an inline function. and simplify
> sbi_domain_memregion_init and is_region_subset.
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

I don't see the point behind this optimization since compiler will
anyway inline in_region().

Regards,
Anup

> ---
>  lib/sbi/sbi_domain.c | 52 +++++++++++++++++++-------------------------
>  1 file changed, 22 insertions(+), 30 deletions(-)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index fec9074..3365e74 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -36,6 +36,14 @@ struct sbi_domain root = {
>         .system_reset_allowed = TRUE,
>  };
>
> +static inline bool in_region(unsigned long addr, const struct sbi_domain_memregion *reg)
> +{
> +       unsigned long s, e;
> +       s= reg->base;
> +       e = reg->order < __riscv_xlen ? reg->base + (BIT(reg->order) - 1) : -1;
> +       return (s <= addr) && (addr <= e);
> +}
> +
>  bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
>  {
>         if (dom)
> @@ -77,27 +85,18 @@ void sbi_domain_memregion_init(unsigned long addr,
>                                 unsigned long flags,
>                                 struct sbi_domain_memregion *reg)
>  {
> -       unsigned long base = 0, order;
> +       unsigned long order;
> +
> +       if (reg == NULL)
> +               return;
>
>         for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
> -               if (order < __riscv_xlen) {
> -                       base = addr & ~((1UL << order) - 1UL);
> -                       if ((base <= addr) &&
> -                           (addr < (base + (1UL << order))) &&
> -                           (base <= (addr + size - 1UL)) &&
> -                           ((addr + size - 1UL) < (base + (1UL << order))))
> -                               break;
> -               } else {
> -                       base = 0;
> +               reg->base = order < __riscv_xlen ? addr & ~((1UL << order) - 1UL) : 0;
> +               reg->order = order;
> +               if (in_region(addr,reg) && in_region(addr + size - 1, reg)) {
> +                       reg->flags = flags;
>                         break;
>                 }
> -
> -       }
> -
> -       if (reg) {
> -               reg->base = base;
> -               reg->order = order;
> -               reg->flags = flags;
>         }
>  }
>
> @@ -126,10 +125,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
>                 if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
>                         continue;
>
> -               rstart = reg->base;
> -               rend = (reg->order < __riscv_xlen) ?
> -                       rstart + ((1UL << reg->order) - 1) : -1UL;
> -               if (rstart <= addr && addr <= rend) {
> +               if (in_region(addr, reg)) {
>                         rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
>                         if (mmio != rmmio)
>                                 return FALSE;
> @@ -156,15 +152,11 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
>  static bool is_region_subset(const struct sbi_domain_memregion *regA,
>                              const struct sbi_domain_memregion *regB)
>  {
> -       ulong regA_start = regA->base;
> -       ulong regA_end = regA->base + (BIT(regA->order) - 1);
> -       ulong regB_start = regB->base;
> -       ulong regB_end = regB->base + (BIT(regB->order) - 1);
> -
> -       if ((regB_start <= regA_start) &&
> -           (regA_start < regB_end) &&
> -           (regB_start < regA_end) &&
> -           (regA_end <= regB_end))
> +       unsigned long start, end;
> +       start = regA->base;
> +       end = regA->order < __riscv_xlen ? regA->base + (BIT(regA->order) - 1) : -1;
> +
> +       if (in_region(start, regB) && in_region(end, regB))
>                 return TRUE;
>
>         return FALSE;
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec  4 08:31:55 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 4 Dec 2022 22:01:55 +0530
Subject: [PATCH v2 3/3] lib: sbi: fix is_region_valid
In-Reply-To: <20221124031605.216192-4-wxjstz@126.com>
References: <20221124031605.216192-1-wxjstz@126.com> <20221124031605.216192-4-wxjstz@126.com>
Message-ID: <CAAhSdy3CEUUrsqdvwnQi3b2WgWbBAxKpf9+z-9nN-iXCRhqW5g@mail.gmail.com>

On Thu, Nov 24, 2022 at 8:46 AM Xiang W <wxjstz at 126.com> wrote:
>
> When order is equal to __riscv_xlen, the shift operation will not
> perform any operation, which will cause
> reg->base & (BIT(reg->order) - 1) to always be 0, and the condition
> has not been established. This patch fixes this bug
>
> Signed-off-by: Xiang W <wxjstz at 126.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_domain.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3365e74..65fae89 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -142,6 +142,9 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
>         if (reg->order < 3 || __riscv_xlen < reg->order)
>                 return FALSE;
>
> +       if (reg->order == __riscv_xlen && reg->base != 0)
> +               return FALSE;
> +
>         if (reg->base & (BIT(reg->order) - 1))
>                 return FALSE;
>
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From wxjstz at 126.com  Sun Dec  4 16:25:04 2022
From: wxjstz at 126.com (Xiang W)
Date: Mon, 05 Dec 2022 08:25:04 +0800
Subject: [PATCH v2 2/3] lib: sbi: add in_region
In-Reply-To: <CAAhSdy3gEKXGzSshQvo7VA6xCggbLeaor2GXyVgv71R2JWXDQQ@mail.gmail.com>
References: <20221124031605.216192-1-wxjstz@126.com>
	 <20221124031605.216192-3-wxjstz@126.com>
	 <CAAhSdy3gEKXGzSshQvo7VA6xCggbLeaor2GXyVgv71R2JWXDQQ@mail.gmail.com>
Message-ID: <4a6b961f99380e9c12426806a14f48fe1ea26eb9.camel@126.com>

? 2022-12-04???? 22:01 +0530?Anup Patel???
> On Thu, Nov 24, 2022 at 8:46 AM Xiang W <wxjstz at 126.com> wrote:
> > 
> > It is a common operation to judge whether an address is in a
> > certain region, and add an inline function. and simplify
> > sbi_domain_memregion_init and is_region_subset.
> > 
> > Signed-off-by: Xiang W <wxjstz at 126.com>
> 
> I don't see the point behind this optimization since compiler will
> anyway inline in_region().
This patch can make the code concise and easy to understand. inline is to
improve operating efficiency, not to reduce code size. inline can be
removed if needed

Regards,
Xiang W
> 
> Regards,
> Anup
> 
> > ---
> > ?lib/sbi/sbi_domain.c | 52 +++++++++++++++++++-------------------------
> > ?1 file changed, 22 insertions(+), 30 deletions(-)
> > 
> > diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> > index fec9074..3365e74 100644
> > --- a/lib/sbi/sbi_domain.c
> > +++ b/lib/sbi/sbi_domain.c
> > @@ -36,6 +36,14 @@ struct sbi_domain root = {
> > ??????? .system_reset_allowed = TRUE,
> > ?};
> > 
> > +static inline bool in_region(unsigned long addr, const struct sbi_domain_memregion *reg)
> > +{
> > +?????? unsigned long s, e;
> > +?????? s= reg->base;
> > +?????? e = reg->order < __riscv_xlen ? reg->base + (BIT(reg->order) - 1) : -1;
> > +?????? return (s <= addr) && (addr <= e);
> > +}
> > +
> > ?bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
> > ?{
> > ??????? if (dom)
> > @@ -77,27 +85,18 @@ void sbi_domain_memregion_init(unsigned long addr,
> > ??????????????????????????????? unsigned long flags,
> > ??????????????????????????????? struct sbi_domain_memregion *reg)
> > ?{
> > -?????? unsigned long base = 0, order;
> > +?????? unsigned long order;
> > +
> > +?????? if (reg == NULL)
> > +?????????????? return;
> > 
> > ??????? for (order = log2roundup(size) ; order <= __riscv_xlen; order++) {
> > -?????????????? if (order < __riscv_xlen) {
> > -?????????????????????? base = addr & ~((1UL << order) - 1UL);
> > -?????????????????????? if ((base <= addr) &&
> > -?????????????????????????? (addr < (base + (1UL << order))) &&
> > -?????????????????????????? (base <= (addr + size - 1UL)) &&
> > -?????????????????????????? ((addr + size - 1UL) < (base + (1UL << order))))
> > -?????????????????????????????? break;
> > -?????????????? } else {
> > -?????????????????????? base = 0;
> > +?????????????? reg->base = order < __riscv_xlen ? addr & ~((1UL << order) - 1UL) : 0;
> > +?????????????? reg->order = order;
> > +?????????????? if (in_region(addr,reg) && in_region(addr + size - 1, reg)) {
> > +?????????????????????? reg->flags = flags;
> > ??????????????????????? break;
> > ??????????????? }
> > -
> > -?????? }
> > -
> > -?????? if (reg) {
> > -?????????????? reg->base = base;
> > -?????????????? reg->order = order;
> > -?????????????? reg->flags = flags;
> > ??????? }
> > ?}
> > 
> > @@ -126,10 +125,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> > ??????????????? if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
> > ??????????????????????? continue;
> > 
> > -?????????????? rstart = reg->base;
> > -?????????????? rend = (reg->order < __riscv_xlen) ?
> > -?????????????????????? rstart + ((1UL << reg->order) - 1) : -1UL;
> > -?????????????? if (rstart <= addr && addr <= rend) {
> > +?????????????? if (in_region(addr, reg)) {
> > ??????????????????????? rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
> > ??????????????????????? if (mmio != rmmio)
> > ??????????????????????????????? return FALSE;
> > @@ -156,15 +152,11 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
> > ?static bool is_region_subset(const struct sbi_domain_memregion *regA,
> > ???????????????????????????? const struct sbi_domain_memregion *regB)
> > ?{
> > -?????? ulong regA_start = regA->base;
> > -?????? ulong regA_end = regA->base + (BIT(regA->order) - 1);
> > -?????? ulong regB_start = regB->base;
> > -?????? ulong regB_end = regB->base + (BIT(regB->order) - 1);
> > -
> > -?????? if ((regB_start <= regA_start) &&
> > -?????????? (regA_start < regB_end) &&
> > -?????????? (regB_start < regA_end) &&
> > -?????????? (regA_end <= regB_end))
> > +?????? unsigned long start, end;
> > +?????? start = regA->base;
> > +?????? end = regA->order < __riscv_xlen ? regA->base + (BIT(regA->order) - 1) : -1;
> > +
> > +?????? if (in_region(start, regB) && in_region(end, regB))
> > ??????????????? return TRUE;
> > 
> > ??????? return FALSE;
> > --
> > 2.30.2
> > 
> > 
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi




From peterlin at andestech.com  Mon Dec  5 01:38:23 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Mon, 5 Dec 2022 09:38:23 +0000
Subject: [PATCH 2/4] docs: platform: Update AE350 and generic platform
 documentation
In-Reply-To: <CAEUhbmW8y4tQixXSw-kLsjsGTf89wMfEYAW_dnmAsruN581dWQ@mail.gmail.com>
References: <20221128083046.6799-1-peterlin@andestech.com>
 <20221128083046.6799-3-peterlin@andestech.com>
 <CAEUhbmW8y4tQixXSw-kLsjsGTf89wMfEYAW_dnmAsruN581dWQ@mail.gmail.com>
Message-ID: <Y428D1JYLNd8/s1R@APC323>

On Sat, Dec 03, 2022 at 12:10:08AM +0800, Bin Meng wrote:
> On Mon, Nov 28, 2022 at 4:33 PM Yu Chien Peter Lin
> <peterlin at andestech.com> wrote:
> >
> > Update compile option and platform compatible string for AE350 and
> > add it to the generic platform list.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> > ---
> >  docs/platform/andes-ae350.md | 5 +++--
> >  docs/platform/generic.md     | 2 ++
> >  2 files changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
> > index ec241ec..4739951 100644
> > --- a/docs/platform/andes-ae350.md
> > +++ b/docs/platform/andes-ae350.md
> > @@ -8,7 +8,7 @@ AHB/APB IPs suites a majority embedded systems, and the verified platform serves
> >  as a starting point to jump start SoC designs.
> >
> >  To build platform specific library and firmwares, provide the
> > -*PLATFORM=andes/ae350* parameter to the top level make command.
> > +*PLATFORM=generic* parameter to the top level `make` command.
> >
> >  Platform Options
> >  ----------------
> > @@ -23,13 +23,14 @@ AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5
> >  **Linux Kernel Payload**
> >
> >  ```
> > -make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
> > +make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
> >  ```
> >
> >  DTS Example: (Quad-core AX45MP)
> >  -------------------------------
> >
> >  ```
> > +       compatible = "andestech,ae350";
> >         cpus {
> >                 #address-cells = <1>;
> >                 #size-cells = <0>;
> > diff --git a/docs/platform/generic.md b/docs/platform/generic.md
> > index 73a8afa..bd3c8ab 100644
> > --- a/docs/platform/generic.md
> > +++ b/docs/platform/generic.md
> > @@ -50,9 +50,11 @@ RISC-V Platforms Using Generic Platform
> >  * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
> >  * **Spike** (*[spike.md]*)
> >  * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
> > +* **Andes AE350 Platform** (*[andes-ae350.md]*)
> 
> nits: please insert this by following alphabetical order
> 
> >
> >  [qemu_virt.md]: qemu_virt.md
> >  [shakti_cclass.md]: shakti_cclass.md
> >  [sifive_fu540.md]: sifive_fu540.md
> >  [spike.md]: spike.md
> >  [thead-c9xx.md]: thead-c9xx.md
> > +[andes-ae350.md]: andse-ae350.md
> > --
> 
> nits: please insert this by following alphabetical order
> 
> Otherwise,
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

Hi Bin,

Thanks for your review,
I'll reorder the list.

Best regards,
Peter Lin


From peterlin at andestech.com  Sun Dec  4 18:03:56 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 5 Dec 2022 10:03:56 +0800
Subject: [PATCH v2 0/4] Enable generic platform support for AE350
Message-ID: <20221205020400.28712-1-peterlin@andestech.com>

The fdt drivers used by AE350 are provided, we can use generic
platform sharing with other vendors and remove the duplicate code.
We also update the documentation of AE350 accordingly.

Yu Chien Peter Lin (4):
  platform: generic/andes: Enable generic platform support for AE350
  docs: platform: Update AE350 and generic platform documentation
  docs: andes-ae350.md: fix watchdog nodename in dts example
  scripts/create-binary-archive.sh: remove andes/ae350 build directory

 docs/platform/andes-ae350.md           |   7 +-
 docs/platform/generic.md               |   2 +
 platform/andes/ae350/Kconfig           |  34 -----
 platform/andes/ae350/cache.c           |  89 -------------
 platform/andes/ae350/cache.h           |  17 ---
 platform/andes/ae350/configs/defconfig |   0
 platform/andes/ae350/objects.mk        |  40 ------
 platform/andes/ae350/platform.c        | 169 -------------------------
 platform/andes/ae350/platform.h        | 109 ----------------
 platform/generic/Kconfig               |   4 +
 platform/generic/andes/ae350.c         |  21 +++
 platform/generic/andes/objects.mk      |   6 +
 platform/generic/configs/defconfig     |   4 +
 scripts/create-binary-archive.sh       |   1 -
 14 files changed, 41 insertions(+), 462 deletions(-)
 delete mode 100644 platform/andes/ae350/Kconfig
 delete mode 100644 platform/andes/ae350/cache.c
 delete mode 100644 platform/andes/ae350/cache.h
 delete mode 100644 platform/andes/ae350/configs/defconfig
 delete mode 100644 platform/andes/ae350/objects.mk
 delete mode 100644 platform/andes/ae350/platform.c
 delete mode 100644 platform/andes/ae350/platform.h
 create mode 100644 platform/generic/andes/ae350.c
 create mode 100644 platform/generic/andes/objects.mk

-- 
2.34.1



From peterlin at andestech.com  Sun Dec  4 18:03:57 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 5 Dec 2022 10:03:57 +0800
Subject: [PATCH v2 1/4] platform: generic/andes: Enable generic platform support for AE350
In-Reply-To: <20221205020400.28712-1-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com>
Message-ID: <20221205020400.28712-2-peterlin@andestech.com>

We move andes directory to platform/generic as the necessary fdt
drivers are available, the users can enable the console, timer, ipi,
irqchip and reset devices by adding device tree nodes stated in the
docs/platform/andes-ae350.md.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
Changes v1 -> v2
- Add Bin Meng's review tag
---
 platform/andes/ae350/Kconfig           |  34 -----
 platform/andes/ae350/cache.c           |  89 -------------
 platform/andes/ae350/cache.h           |  17 ---
 platform/andes/ae350/configs/defconfig |   0
 platform/andes/ae350/objects.mk        |  40 ------
 platform/andes/ae350/platform.c        | 169 -------------------------
 platform/andes/ae350/platform.h        | 109 ----------------
 platform/generic/Kconfig               |   4 +
 platform/generic/andes/ae350.c         |  21 +++
 platform/generic/andes/objects.mk      |   6 +
 platform/generic/configs/defconfig     |   4 +
 11 files changed, 35 insertions(+), 458 deletions(-)
 delete mode 100644 platform/andes/ae350/Kconfig
 delete mode 100644 platform/andes/ae350/cache.c
 delete mode 100644 platform/andes/ae350/cache.h
 delete mode 100644 platform/andes/ae350/configs/defconfig
 delete mode 100644 platform/andes/ae350/objects.mk
 delete mode 100644 platform/andes/ae350/platform.c
 delete mode 100644 platform/andes/ae350/platform.h
 create mode 100644 platform/generic/andes/ae350.c
 create mode 100644 platform/generic/andes/objects.mk

diff --git a/platform/andes/ae350/Kconfig b/platform/andes/ae350/Kconfig
deleted file mode 100644
index 38e4001..0000000
--- a/platform/andes/ae350/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: BSD-2-Clause
-
-config PLATFORM_ANDES_AE350
-	bool
-	select FDT
-	select FDT_SERIAL
-	select FDT_SERIAL_UART8250
-	select FDT_TIMER
-	select FDT_TIMER_PLMT
-	select FDT_RESET
-	select FDT_RESET_ATCWDT200
-	select FDT_IRQCHIP
-	select FDT_IRQCHIP_PLIC
-	select FDT_IPI
-	select FDT_IPI_PLICSW
-	default y
-
-if PLATFORM_ANDES_AE350
-
-config PLATFORM_ANDES_AE350_NAME
-	string "Platform default name"
-	default "Andes AE350"
-
-config PLATFORM_ANDES_AE350_MAJOR_VER
-	int "Platform major version"
-	range 0 65535
-	default 0
-
-config PLATFORM_ANDES_AE350_MINOR_VER
-	int "Platform minor version"
-	range 0 65535
-	default 1
-
-endif
diff --git a/platform/andes/ae350/cache.c b/platform/andes/ae350/cache.c
deleted file mode 100644
index af724c5..0000000
--- a/platform/andes/ae350/cache.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Andes Technology Corporation
- *
- * Authors:
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_io.h>
-#include <sbi/sbi_types.h>
-#include "platform.h"
-
-uintptr_t mcall_set_mcache_ctl(unsigned long input)
-{
-	csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
-	csr_write(CSR_MCACHECTL, input);
-	return 0;
-}
-
-uintptr_t mcall_set_mmisc_ctl(unsigned long input)
-{
-	csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
-	csr_write(CSR_MMISCCTL, input);
-	return 0;
-}
-
-uintptr_t mcall_icache_op(unsigned int enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
-		asm volatile("fence.i\n\t");
-	}
-	return 0;
-}
-
-uintptr_t mcall_dcache_op(unsigned int enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
-		csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
-	}
-	return 0;
-}
-
-uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_non_blocking_load_store(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
-	}
-	return 0;
-}
-
-uintptr_t mcall_write_around(unsigned long enable)
-{
-	if (enable) {
-		csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
-	} else {
-		csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
-	}
-	return 0;
-}
diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
deleted file mode 100644
index e1c1826..0000000
--- a/platform/andes/ae350/cache.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Andes Technology Corporation
- *
- * Authors:
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-uintptr_t mcall_set_mcache_ctl(unsigned long input);
-uintptr_t mcall_set_mmisc_ctl(unsigned long input);
-uintptr_t mcall_icache_op(unsigned int enable);
-uintptr_t mcall_dcache_op(unsigned int enable);
-uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
-uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
-uintptr_t mcall_non_blocking_load_store(unsigned long enable);
-uintptr_t mcall_write_around(unsigned long enable);
diff --git a/platform/andes/ae350/configs/defconfig b/platform/andes/ae350/configs/defconfig
deleted file mode 100644
index e69de29..0000000
diff --git a/platform/andes/ae350/objects.mk b/platform/andes/ae350/objects.mk
deleted file mode 100644
index a4a2332..0000000
--- a/platform/andes/ae350/objects.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# SPDX-License-Identifier: BSD-2-Clause
-#
-# Copyright (c) 2019 Andes Technology Corporation
-#
-# Authors:
-#   Zong Li <zong at andestech.com>
-#   Nylon Chen <nylon7 at andestech.com>
-#
-
-# Compiler flags
-platform-cppflags-y =
-platform-cflags-y =
-platform-asflags-y =
-platform-ldflags-y =
-
-# Objects to build
-platform-objs-y += cache.o platform.o
-
-# Blobs to build
-FW_TEXT_START=0x00000000
-
-FW_DYNAMIC=y
-
-FW_JUMP=y
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
-  FW_JUMP_ADDR=0x400000
-else
-  FW_JUMP_ADDR=0x200000
-endif
-FW_JUMP_FDT_ADDR=0x2000000
-
-FW_PAYLOAD=y
-ifeq ($(PLATFORM_RISCV_XLEN), 32)
-  FW_PAYLOAD_OFFSET=0x400000
-else
-  FW_PAYLOAD_OFFSET=0x200000
-endif
-
-FW_PAYLOAD_FDT_ADDR=0x2000000
diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c
deleted file mode 100644
index d36d11e..0000000
--- a/platform/andes/ae350/platform.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong at andestech.com>
- *   Nylon Chen <nylon7 at andestech.com>
- *   Yu Chien Peter Lin <peterlin at andestech.com>
- */
-
-#include <libfdt.h>
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_console.h>
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_hartmask.h>
-#include <sbi/sbi_ipi.h>
-#include <sbi/sbi_platform.h>
-#include <sbi/sbi_string.h>
-#include <sbi/sbi_trap.h>
-#include <sbi_utils/fdt/fdt_domain.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/ipi/fdt_ipi.h>
-#include <sbi_utils/irqchip/fdt_irqchip.h>
-#include <sbi_utils/reset/fdt_reset.h>
-#include <sbi_utils/serial/fdt_serial.h>
-#include <sbi_utils/timer/fdt_timer.h>
-#include "platform.h"
-#include "cache.h"
-
-struct sbi_platform platform;
-unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
-				unsigned long arg2, unsigned long arg3,
-				unsigned long arg4)
-{
-	const char *model;
-	void *fdt = (void *)arg1;
-	u32 hartid, hart_count = 0;
-	int rc, root_offset, cpus_offset, cpu_offset, len;
-
-	root_offset = fdt_path_offset(fdt, "/");
-	if (root_offset < 0)
-		goto fail;
-
-	model = fdt_getprop(fdt, root_offset, "model", &len);
-	if (model)
-		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
-
-	cpus_offset = fdt_path_offset(fdt, "/cpus");
-	if (cpus_offset < 0)
-		goto fail;
-
-	fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
-		rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-		if (rc)
-			continue;
-
-		if (SBI_HARTMASK_MAX_BITS <= hartid)
-			continue;
-
-		hart_count++;
-	}
-
-	platform.hart_count = hart_count;
-
-	/* Return original FDT pointer */
-	return arg1;
-
-fail:
-	while (1)
-		wfi();
-}
-
-/* Platform final initialization. */
-static int ae350_final_init(bool cold_boot)
-{
-	void *fdt;
-
-	if (!cold_boot)
-		return 0;
-
-	fdt_reset_init();
-
-	fdt = fdt_get_address();
-	fdt_fixups(fdt);
-	fdt_domain_fixup(fdt);
-
-	return 0;
-}
-
-/* Vendor-Specific SBI handler */
-static int ae350_vendor_ext_provider(long extid, long funcid,
-	const struct sbi_trap_regs *regs, unsigned long *out_value,
-	struct sbi_trap_info *out_trap)
-{
-	int ret = 0;
-	switch (funcid) {
-	case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
-		*out_value = csr_read(CSR_MCACHECTL);
-		break;
-	case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
-		*out_value = csr_read(CSR_MMISCCTL);
-		break;
-	case SBI_EXT_ANDES_SET_MCACHE_CTL:
-		ret = mcall_set_mcache_ctl(regs->a0);
-		break;
-	case SBI_EXT_ANDES_SET_MMISC_CTL:
-		ret = mcall_set_mmisc_ctl(regs->a0);
-		break;
-	case SBI_EXT_ANDES_ICACHE_OP:
-		ret = mcall_icache_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_DCACHE_OP:
-		ret = mcall_dcache_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
-		ret = mcall_l1_cache_i_prefetch_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
-		ret = mcall_l1_cache_d_prefetch_op(regs->a0);
-		break;
-	case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
-		ret = mcall_non_blocking_load_store(regs->a0);
-		break;
-	case SBI_EXT_ANDES_WRITE_AROUND:
-		ret = mcall_write_around(regs->a0);
-		break;
-	default:
-		sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
-		asm volatile("ebreak");
-	}
-	return ret;
-}
-
-static int ae350_domains_init(void)
-{
-	return fdt_domains_populate(fdt_get_address());
-}
-
-/* Platform descriptor. */
-const struct sbi_platform_operations platform_ops = {
-	.final_init = ae350_final_init,
-
-	.domains_init = ae350_domains_init,
-
-	.console_init = fdt_serial_init,
-
-	.irqchip_init = fdt_irqchip_init,
-
-	.ipi_init     = fdt_ipi_init,
-
-	.timer_init	   = fdt_timer_init,
-
-	.vendor_ext_provider = ae350_vendor_ext_provider
-};
-
-struct sbi_platform platform = {
-	.opensbi_version = OPENSBI_VERSION,
-	.platform_version =
-		SBI_PLATFORM_VERSION(CONFIG_PLATFORM_ANDES_AE350_MAJOR_VER,
-				     CONFIG_PLATFORM_ANDES_AE350_MINOR_VER),
-	.name = CONFIG_PLATFORM_ANDES_AE350_NAME,
-	.features = SBI_PLATFORM_DEFAULT_FEATURES,
-	.hart_count = SBI_HARTMASK_MAX_BITS,
-	.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
-	.platform_ops_addr = (unsigned long)&platform_ops
-};
diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h
deleted file mode 100644
index 903bef0..0000000
--- a/platform/andes/ae350/platform.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Andes Technology Corporation
- *
- * Authors:
- *   Zong Li <zong at andestech.com>
- *   Nylon Chen <nylon7 at andestech.com>
- */
-
-#ifndef _AE350_PLATFORM_H_
-#define _AE350_PLATFORM_H_
-
-#define AE350_L2C_ADDR			0xe0500000
-
-/*Memory and Miscellaneous Registers*/
-#define CSR_MILMB		0x7c0
-#define CSR_MDLMB		0x7c1
-#define CSR_MECC_CDOE		0x7c2
-#define CSR_MNVEC		0x7c3
-#define CSR_MPFTCTL		0x7c5
-#define CSR_MCACHECTL		0x7ca
-#define CSR_MCCTLBEGINADDR	0x7cb
-#define CSR_MCCTLCOMMAND	0x7cc
-#define CSR_MCCTLDATA		0x7cc
-#define CSR_SCCTLDATA		0x9cd
-#define CSR_UCCTLBEGINADDR	0x80c
-#define CSR_MMISCCTL		0x7d0
-
-enum sbi_ext_andes_fid {
-	SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
-	SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
-	SBI_EXT_ANDES_SET_MCACHE_CTL,
-	SBI_EXT_ANDES_SET_MMISC_CTL,
-	SBI_EXT_ANDES_ICACHE_OP,
-	SBI_EXT_ANDES_DCACHE_OP,
-	SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
-	SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
-	SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
-	SBI_EXT_ANDES_WRITE_AROUND,
-};
-
-/* nds v5 mmisc_ctl register*/
-#define V5_MMISC_CTL_VEC_PLIC_OFFSET            1
-#define V5_MMISC_CTL_RVCOMPM_OFFSET             2
-#define V5_MMISC_CTL_BRPE_OFFSET                3
-#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET          6
-#define V5_MMISC_CTL_NON_BLOCKING_OFFSET        8
-#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET       9
-#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET       10
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1       13
-#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2       14
-
-#define V5_MMISC_CTL_VEC_PLIC_EN        (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
-#define V5_MMISC_CTL_RVCOMPM_EN         (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
-#define V5_MMISC_CTL_BRPE_EN            (1UL << V5_MMISC_CTL_BRPE_OFFSET)
-#define V5_MMISC_CTL_MSA_OR_UNA_EN      (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
-#define V5_MMISC_CTL_NON_BLOCKING_EN    (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
-#define V5_MCACHE_CTL_L1I_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_L1D_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
-#define V5_MCACHE_CTL_DC_WAROUND_1_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
-#define V5_MCACHE_CTL_DC_WAROUND_2_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
-
-#define V5_MMISC_CTL_MASK  (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
-	| V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
-
-/* nds mcache_ctl register*/
-#define V5_MCACHE_CTL_IC_EN_OFFSET      0
-#define V5_MCACHE_CTL_DC_EN_OFFSET      1
-#define V5_MCACHE_CTL_IC_ECCEN_OFFSET   2
-#define V5_MCACHE_CTL_DC_ECCEN_OFFSET   4
-#define V5_MCACHE_CTL_IC_RWECC_OFFSET   6
-#define V5_MCACHE_CTL_DC_RWECC_OFFSET   7
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET  8
-
-/*nds cctl command*/
-#define V5_UCCTL_L1D_WBINVAL_ALL 6
-#define V5_UCCTL_L1D_WB_ALL 7
-
-#define V5_MCACHE_CTL_IC_EN     (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN     (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_IC_RWECC  (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_DC_RWECC  (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-
-#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
-	| V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
-	| V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
-	| V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
-	| V5_MCACHE_CTL_DC_WAROUND_2_EN)
-
-#define V5_L2C_CTL_OFFSET           0x8
-#define V5_L2C_CTL_ENABLE_OFFSET    0
-#define V5_L2C_CTL_IPFDPT_OFFSET    3
-#define V5_L2C_CTL_DPFDPT_OFFSET    5
-#define V5_L2C_CTL_TRAMOCTL_OFFSET  8
-#define V5_L2C_CTL_TRAMICTL_OFFSET  10
-#define V5_L2C_CTL_DRAMOCTL_OFFSET  11
-#define V5_L2C_CTL_DRAMICTL_OFFSET  13
-
-#define V5_L2C_CTL_ENABLE_MASK      (1UL << V5_L2C_CTL_ENABLE_OFFSET)
-#define V5_L2C_CTL_IPFDPT_MASK      (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
-#define V5_L2C_CTL_DPFDPT_MASK      (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
-#define V5_L2C_CTL_TRAMOCTL_MASK    (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
-#define V5_L2C_CTL_TRAMICTL_MASK    (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
-#define V5_L2C_CTL_DRAMOCTL_MASK    (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
-#define V5_L2C_CTL_DRAMICTL_MASK    (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
-
-#endif /* _AE350_PLATFORM_H_ */
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 63d1be4..4b5d2cd 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -28,6 +28,10 @@ config PLATFORM_ALLWINNER_D1
 	depends on FDT_IRQCHIP_PLIC
 	default n
 
+config PLATFORM_ANDES_AE350
+	bool "Andes AE350 support"
+	default n
+
 config PLATFORM_SIFIVE_FU540
 	bool "SiFive FU540 support"
 	default n
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
new file mode 100644
index 0000000..cf7f6f2
--- /dev/null
+++ b/platform/generic/andes/ae350.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Andes Technology Corporation
+ *
+ * Authors:
+ *   Yu Chien Peter Lin <peterlin at andestech.com>
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static const struct fdt_match andes_ae350_match[] = {
+	{ .compatible = "andestech,ae350" },
+	{ },
+};
+
+const struct platform_override andes_ae350 = {
+	.match_table = andes_ae350_match,
+};
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
new file mode 100644
index 0000000..dd6408d
--- /dev/null
+++ b/platform/generic/andes/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_ANDES_AE350) += andes_ae350
+platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index c95b7fa..2eaeeb7 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -1,4 +1,5 @@
 CONFIG_PLATFORM_ALLWINNER_D1=y
+CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
 CONFIG_FDT_GPIO=y
@@ -7,11 +8,13 @@ CONFIG_FDT_I2C=y
 CONFIG_FDT_I2C_SIFIVE=y
 CONFIG_FDT_IPI=y
 CONFIG_FDT_IPI_MSWI=y
+CONFIG_FDT_IPI_PLICSW=y
 CONFIG_FDT_IRQCHIP=y
 CONFIG_FDT_IRQCHIP_APLIC=y
 CONFIG_FDT_IRQCHIP_IMSIC=y
 CONFIG_FDT_IRQCHIP_PLIC=y
 CONFIG_FDT_RESET=y
+CONFIG_FDT_RESET_ATCWDT200=y
 CONFIG_FDT_RESET_GPIO=y
 CONFIG_FDT_RESET_HTIF=y
 CONFIG_FDT_RESET_SIFIVE_TEST=y
@@ -28,4 +31,5 @@ CONFIG_FDT_SERIAL_UART8250=y
 CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
 CONFIG_FDT_TIMER=y
 CONFIG_FDT_TIMER_MTIMER=y
+CONFIG_FDT_TIMER_PLMT=y
 CONFIG_SERIAL_SEMIHOSTING=y
-- 
2.34.1



From peterlin at andestech.com  Sun Dec  4 18:03:58 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 5 Dec 2022 10:03:58 +0800
Subject: [PATCH v2 2/4] docs: platform: Update AE350 and generic platform documentation
In-Reply-To: <20221205020400.28712-1-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com>
Message-ID: <20221205020400.28712-3-peterlin@andestech.com>

Update compile option and platform compatible string for AE350 and
add it to the generic platform list.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
Changes v1 -> v2
- Add Bin Meng's review tag
- Insert AE350 platform in alphabetical order
---
 docs/platform/andes-ae350.md | 5 +++--
 docs/platform/generic.md     | 2 ++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
index ec241ec..4739951 100644
--- a/docs/platform/andes-ae350.md
+++ b/docs/platform/andes-ae350.md
@@ -8,7 +8,7 @@ AHB/APB IPs suites a majority embedded systems, and the verified platform serves
 as a starting point to jump start SoC designs.
 
 To build platform specific library and firmwares, provide the
-*PLATFORM=andes/ae350* parameter to the top level make command.
+*PLATFORM=generic* parameter to the top level `make` command.
 
 Platform Options
 ----------------
@@ -23,13 +23,14 @@ AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5
 **Linux Kernel Payload**
 
 ```
-make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
+make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
 ```
 
 DTS Example: (Quad-core AX45MP)
 -------------------------------
 
 ```
+	compatible = "andestech,ae350";
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index 73a8afa..e8a3296 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -45,12 +45,14 @@ The *Generic* platform does not have any platform-specific options.
 RISC-V Platforms Using Generic Platform
 ---------------------------------------
 
+* **Andes AE350 Platform** (*[andes-ae350.md]*)
 * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
 * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
 * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
 * **Spike** (*[spike.md]*)
 * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
 
+[andes-ae350.md]: andse-ae350.md
 [qemu_virt.md]: qemu_virt.md
 [shakti_cclass.md]: shakti_cclass.md
 [sifive_fu540.md]: sifive_fu540.md
-- 
2.34.1



From peterlin at andestech.com  Sun Dec  4 18:03:59 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 5 Dec 2022 10:03:59 +0800
Subject: [PATCH v2 3/4] docs: andes-ae350.md: fix watchdog nodename in dts example
In-Reply-To: <20221205020400.28712-1-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com>
Message-ID: <20221205020400.28712-4-peterlin@andestech.com>

The example should use watchdog as nodename instead of wdt.
This is defined in watchdog common schemas:
https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
Changes v1 -> v2
- Add Bin Meng's review tag
---
 docs/platform/andes-ae350.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
index 4739951..8fc8ec6 100644
--- a/docs/platform/andes-ae350.md
+++ b/docs/platform/andes-ae350.md
@@ -178,7 +178,7 @@ DTS Example: (Quad-core AX45MP)
 			                        &CPU3_intc 7 >;
 		};
 
-		wdt: wdt at f0500000 {
+		wdt: watchdog at f0500000 {
 			compatible = "andestech,atcwdt200";
 			reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
 			interrupts = <3 4>;
-- 
2.34.1



From peterlin at andestech.com  Sun Dec  4 18:04:00 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Mon, 5 Dec 2022 10:04:00 +0800
Subject: [PATCH v2 4/4] scripts/create-binary-archive.sh: remove andes/ae350 build directory
In-Reply-To: <20221205020400.28712-1-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com>
Message-ID: <20221205020400.28712-5-peterlin@andestech.com>

The andes-specific files have been moved to generic platform so we
can drop this line.

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
Changes v1 -> v2
- Add Bin Meng's review tag
---
 scripts/create-binary-archive.sh | 1 -
 1 file changed, 1 deletion(-)

diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index 261a45a..4dda7b4 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -103,7 +103,6 @@ build_opensbi() {
 		BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
 		BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
 		BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
-		BUILD_PLATFORM_SUBDIR+=("andes/ae350")
 		BUILD_PLATFORM_SUBDIR+=("generic")
 		;;
 	*)
-- 
2.34.1



From eric.lin at sifive.com  Sun Dec  4 18:31:29 2022
From: eric.lin at sifive.com (Eric Lin)
Date: Mon, 5 Dec 2022 10:31:29 +0800
Subject: [PATCH] lib: sbi: Bypass CY and IR bit setting in mcountinhibit
In-Reply-To: <CAOnJCUKi8NSqNgDyKaT9u7w-bPFeMbCM=K6DYTzW+e+3srYfnA@mail.gmail.com>
References: <20221116101826.10465-1-eric.lin@sifive.com> <E95DA6B1-DCB9-45D9-BB30-8EC53F2D1596@jrtc27.com>
 <CAOnJCUKi8NSqNgDyKaT9u7w-bPFeMbCM=K6DYTzW+e+3srYfnA@mail.gmail.com>
Message-ID: <CAPqJEFoe0R1aY=P8NEwaAipg=jSYaAJ4Prz=VJ7txp3vqqG-PQ@mail.gmail.com>

(Resend to OpenSBI mailing list)

Hi Aitsh,

On Fri, Nov 18, 2022 at 7:00 AM Atish Patra <atishp at atishpatra.org> wrote:
>
> On Wed, Nov 16, 2022 at 6:57 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
> >
> > On 16 Nov 2022, at 10:18, Eric Lin <eric.lin at sifive.com> wrote:
> > >
> > > CYCLE and INSTRET counters are part of uABI and they were
> > > re-enable for userspace in Linux riscv pmu driver.
> > >
> > > To make these counters increase normally in userspace, we bypass
> > > CY and IR bit checking when setting mcountinhibit register.
> > >
> > > LINK:https://lore.kernel.org/all/20220928131807.30386-1-palmer at rivosinc.com/
> > > Signed-off-by: Eric Lin <eric.lin at sifive.com>
> >
> > If Linux is making SBI calls it doesn?t want then it should stop making
> > those calls. S-mode requesting CY and IR inhibit bits be set is totally
> > legitimate in some circumstances, it?s not up to firmware to enforce a
> > specific S-mode OS policy.
> >
>
> Yes. Start/sop is required when the user is doing perf stat or record
> for these counters.
>
> To increase the CYCLE and INSTRET,
> pmu_sbi_starting_cpu( in drivers/perf/riscv_pmu_sbi.c)
> should be modified to stop only the programmable counters. Not all.
>
Since CYCLE and INSTRET counters are re-enabled in userspace, user
applications will use rdcycle and rdinstert pseudoinstruction for
performance monitoring.

IMO, when a user uses rdcycle and rdinstert pseudoinstruction to get
cycle and instructions count, they would assume that CYCLE and INSTRET
counters are strictly increasing and no need to initialize in Linux.
Is the assumption right?

However, if another user uses the perf tool to get cycle and
instruction count, the perf framework will start and stop counters
when events are scheduled in and out.
This will make the CYCLE and INSTRET counters not strictly increase
and the rdcycle and rdinstert results are not what the user expects.

Therefore, I think two places need to modify in Linux riscv pmu driver.

The first one is that when booting, we should only stop programmable
counters in pmu_sbi_stop_all().
The patch is as below:
 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
 {
+       unsigned long cmask = 0;
        /*
-        * No need to check the error because we are disabling all the counters
+        * No need to check the error because we are disabling
programmable counters
         * which may include counters that are not enabled yet.
         */
+       cmask = pmu->cmask & (~(BIT(0) | BIT(2)));
        sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
-                 0, pmu->cmask, 0, 0, 0, 0);
+                 0, cmask, 0, 0, 0, 0);

The second one is that when the user uses the perf stat -e
cycles/instructions command, it will stop counters when the event
stop.
We should skip stopping CYCLE and INSTRET counters in pmu_sbi_ctr_stop().
The patch is as below:
@@ -446,6 +446,10 @@ static void pmu_sbi_ctr_stop(struct perf_event
*event, unsigned long flag)
        struct sbiret ret;
        struct hw_perf_event *hwc = &event->hw;

+       /* Skip to stop CYCLE and INSTRET counters */
+       if (hwc->idx == 0 || hwc->idx == 2)
+               return;
+
        ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
hwc->idx, 1, flag, 0, 0, 0);
        if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
                flag != SBI_PMU_STOP_FLAG_RESET)

Is this the right way to fix rdcycle and rdinstert increase issue in
userspace? Or is there something that I miss?
Thanks.

Regards,
Eric Lin


> > Jess
> >
> > > ---
> > > lib/sbi/sbi_pmu.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> > > index 91d9ccc..28107e5 100644
> > > --- a/lib/sbi/sbi_pmu.c
> > > +++ b/lib/sbi/sbi_pmu.c
> > > @@ -318,7 +318,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
> > >       if (cidx >= num_hw_ctrs || cidx == 1)
> > >               return SBI_EINVAL;
> > >
> > > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> > > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> > >               goto skip_inhibit_update;
> > >
> > >       /*
> > > @@ -413,7 +413,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
> > >       struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> > >       unsigned long mctr_inhbt;
> > >
> > > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
> > > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
> > >               return 0;
> > >
> > >       mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
> > > --
> > > 2.36.1
> > >
> > >
> > > --
> > > opensbi mailing list
> > > opensbi at lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/opensbi
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
>
>
> --
> Regards,
> Atish


From anup at brainfault.org  Sun Dec  4 20:36:28 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 10:06:28 +0530
Subject: [PATCH 1/3] lib: sbi: Optionally use ".insn" instead of ".word"
In-Reply-To: <d0ab3f9e2b778ce834a81ec56c3cfd9d0fe255d2.1669452733.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com> <d0ab3f9e2b778ce834a81ec56c3cfd9d0fe255d2.1669452733.git.research_trasio@irq.a4lg.com>
Message-ID: <CAAhSdy0+e9_oiVJS9GSzb69t5OV5PMU2Ggf379j=LDOOABWjBg@mail.gmail.com>

On Sat, Nov 26, 2022 at 2:24 PM Tsukasa OI <research_trasio at irq.a4lg.com> wrote:
>
> From: Tsukasa OI <research_trasio at irq.a4lg.com>
>
> ".word" is used to emit a data word (32-bits) and recent GNU assembler
> adds mapping symbol "$d" before ".word" to make sure that this is a data
> word.  However, in lib/sbi/sbi_hfence.S, we use this to emit hfence.*
> instructions (for assemblers that do not support hfence.*).  The mapping
> symbol "$d" prevents these instructions being disassembled as code.
>
> Instead, ".insn" is available to emit raw instructions but not all
> assemblers with ".insn" support raw values.
>
> This commit tests support of ".insn" with raw value in the Makefile
> (AS_SUPPORT_INSN_RAW_DIRECTIVE) and optionally replaces ".word" with ".insn"
> when ".insn" with raw value is supported.
>
> Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
> ---
>  Makefile             |  8 ++++++++
>  lib/sbi/sbi_hfence.S | 16 ++++++++--------
>  2 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 8db6eabe9fda..e942dfdc00bc 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
>  # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
>  CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
>
> +# Check whether the ".insn" directive on the assembler (with raw value) is supported
> +AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
> +
>  # Build Info:
>  # OPENSBI_BUILD_TIME_STAMP -- the compilation time stamp
>  # OPENSBI_BUILD_COMPILER_VERSION -- the compiler version info
> @@ -323,6 +326,11 @@ ifeq ($(BUILD_INFO),y)
>  GENFLAGS       +=      -DOPENSBI_BUILD_TIME_STAMP="\"$(OPENSBI_BUILD_TIME_STAMP)\""
>  GENFLAGS       +=      -DOPENSBI_BUILD_COMPILER_VERSION="\"$(OPENSBI_BUILD_COMPILER_VERSION)\""
>  endif
> +ifeq ($(AS_SUPPORT_INSN_RAW_DIRECTIVE),y)
> +GENFLAGS    +=  -DRAW_INSN=".insn"
> +else
> +GENFLAGS    +=  -DRAW_INSN=".word"
> +endif

OpenSBI specific defines have "OPENSBI_" prefix so
better use that OPENSBI_RAW_INSN as define name.

>  ifdef PLATFORM
>  GENFLAGS       +=      -include $(KCONFIG_AUTOHEADER)
>  endif
> diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
> index e11e6505383d..40882e036932 100644
> --- a/lib/sbi/sbi_hfence.S
> +++ b/lib/sbi/sbi_hfence.S
> @@ -32,7 +32,7 @@ __sbi_hfence_gvma_vmid_gpa:
>          * HFENCE.GVMA a0, a1
>          * 0110001 01011 01010 000 00000 1110011
>          */
> -       .word 0x62b50073
> +       RAW_INSN 0x62b50073

This will fail to compile for people using OpenSBI as a library.

We need some kind of macro to fallback to ".word" when
OPENSBI_RAW_INSN is not defined.

It's better to do something like
<linux_source>/arch/riscv/include/asm/insn-def.h
which is flexible and scalable.

Regards,
Anup

>         ret
>
>         .align 3
> @@ -44,7 +44,7 @@ __sbi_hfence_gvma_vmid:
>          * HFENCE.GVMA zero, a0
>          * 0110001 01010 00000 000 00000 1110011
>          */
> -       .word 0x62a00073
> +       RAW_INSN 0x62a00073
>         ret
>
>         .align 3
> @@ -56,7 +56,7 @@ __sbi_hfence_gvma_gpa:
>          * HFENCE.GVMA a0
>          * 0110001 00000 01010 000 00000 1110011
>          */
> -       .word 0x62050073
> +       RAW_INSN 0x62050073
>         ret
>
>         .align 3
> @@ -68,7 +68,7 @@ __sbi_hfence_gvma_all:
>          * HFENCE.GVMA
>          * 0110001 00000 00000 000 00000 1110011
>          */
> -       .word 0x62000073
> +       RAW_INSN 0x62000073
>         ret
>
>         /*
> @@ -95,7 +95,7 @@ __sbi_hfence_vvma_asid_va:
>          * HFENCE.VVMA a0, a1
>          * 0010001 01011 01010 000 00000 1110011
>          */
> -       .word 0x22b50073
> +       RAW_INSN 0x22b50073
>         ret
>
>         .align 3
> @@ -107,7 +107,7 @@ __sbi_hfence_vvma_asid:
>          * HFENCE.VVMA zero, a0
>          * 0010001 01010 00000 000 00000 1110011
>          */
> -       .word 0x22a00073
> +       RAW_INSN 0x22a00073
>         ret
>
>         .align 3
> @@ -119,7 +119,7 @@ __sbi_hfence_vvma_va:
>          * HFENCE.VVMA zero, a0
>          * 0010001 00000 01010 000 00000 1110011
>          */
> -       .word 0x22050073
> +       RAW_INSN 0x22050073
>         ret
>
>         .align 3
> @@ -131,5 +131,5 @@ __sbi_hfence_vvma_all:
>          * HFENCE.VVMA
>          * 0010001 00000 00000 000 00000 1110011
>          */
> -       .word 0x22000073
> +       RAW_INSN 0x22000073
>         ret
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec  4 20:38:14 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 10:08:14 +0530
Subject: [PATCH v2 2/3] lib: sbi: Optionally use ".option arch,+h"
In-Reply-To: <688110cfcf63a3b70562d58daa095fcbb6a7820b.1669518264.git.research_trasio@irq.a4lg.com>
References: <cover.1669452733.git.research_trasio@irq.a4lg.com>
 <cover.1669518264.git.research_trasio@irq.a4lg.com> <688110cfcf63a3b70562d58daa095fcbb6a7820b.1669518264.git.research_trasio@irq.a4lg.com>
Message-ID: <CAAhSdy2kNehxoEPQit25PyVvKqBUv5r6=JPKtn5HTSYHAXykYg@mail.gmail.com>

On Sun, Nov 27, 2022 at 8:35 AM Tsukasa OI <research_trasio at irq.a4lg.com> wrote:
>
> From: Tsukasa OI <research_trasio at irq.a4lg.com>
>
> On the debugger / disassembler, disassembling hfence.* as hfence.* requires
> indication of the 'H'-extension use.
>
> ".option arch,+[EXT_NAME]" is one of the such ways and this commit
> optionally inserts this assembler directive when supported.
>
> It enables disassembling on the software which supports "$x[arch]" (mapping
> symbols with ISA string) - latest GNU Binutils (will be released as 2.40).
> Note that this commit alone won't make disassembler behavior correct on
> GNU Binutils 2.39 because of a linker issue.
>
> Signed-off-by: Tsukasa OI <research_trasio at irq.a4lg.com>
> ---
>  Makefile             | 6 ++++++
>  lib/sbi/sbi_hfence.S | 4 ++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/Makefile b/Makefile
> index e942dfdc00bc..d8b85f0497aa 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -173,6 +173,9 @@ CC_SUPPORT_SAVE_RESTORE := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib
>  # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
>  CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep "zicsr\|zifencei" > /dev/null && echo n || echo y)
>
> +# Check whether the assembler support the H extension with .option arch,+h
> +AS_SUPPORT_H_EXT_BY_OPTION_ARCH := $(shell echo ".option arch,+h" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null 2>&1 | grep -i "warning:.*option" > /dev/null && echo n || echo y)
> +

Currently, its H-extension and in-future there will be some other
extension adding new instructions.

Please look at <linux>/arch/riscv/include/asm/insn-def.h, we should
go this route for OpenSBI as well.

Regards,
Anup

>  # Check whether the ".insn" directive on the assembler (with raw value) is supported
>  AS_SUPPORT_INSN_RAW_DIRECTIVE := $(shell echo ".insn 0x1000000f" | $(AS) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -x assembler-with-cpp -c - -o /dev/null >/dev/null 2>&1 && echo y || echo n)
>
> @@ -331,6 +334,9 @@ GENFLAGS    +=  -DRAW_INSN=".insn"
>  else
>  GENFLAGS    +=  -DRAW_INSN=".word"
>  endif
> +ifeq ($(AS_SUPPORT_H_EXT_BY_OPTION_ARCH),y)
> +GENFLAGS    +=  -DOPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
> +endif
>  ifdef PLATFORM
>  GENFLAGS       +=      -include $(KCONFIG_AUTOHEADER)
>  endif
> diff --git a/lib/sbi/sbi_hfence.S b/lib/sbi/sbi_hfence.S
> index 40882e036932..146a41959a67 100644
> --- a/lib/sbi/sbi_hfence.S
> +++ b/lib/sbi/sbi_hfence.S
> @@ -8,6 +8,10 @@
>   *   Atish Patra <anup.patel at wdc.com>
>   */
>
> +#ifdef OPENSBI_H_EXT_BY_OPTION_ARCH_SUPPORTED
> +       .option arch,+h
> +#endif
> +
>         /*
>          * HFENCE.GVMA rs1, rs2
>          * HFENCE.GVMA zero, rs2
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec  4 21:15:04 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 10:45:04 +0530
Subject: [PATCH v2 0/6] lib: fixes for fdt functions
In-Reply-To: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
References: <20221128091420.30391-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy1GnbBA6831b07d5Ak0hLKp-LmC-dNFKmFnM6EravdWTQ@mail.gmail.com>

Hi Heinrich,

On Mon, Nov 28, 2022 at 2:44 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> * Use correct type for variables used in error checks
> * Check correct variables
> * Avoid duplicates checks
> * Don't assign values that are never used.
>
> v2:
>         check correct variables
>         fix fdt_parse_aclint_node() too
>
> Heinrich Schuchardt (6):
>   lib: simplify fdt_parse_plmt_node()
>   lib: simplify fdt_parse_plicsw_node()
>   lib: fix fdt_parse_plmt_node()
>   lib: fix fdt_parse_plicsw_node()
>   lib: simplify fdt_translate_address()
>   lib: fix fdt_parse_aclint_node()

Thanks for catching and fixing all these issues.

Applied this series to the riscv/opensbi repo.

Regards,
Anup

>
>  lib/utils/fdt/fdt_helper.c | 20 ++++++++++++--------
>  1 file changed, 12 insertions(+), 8 deletions(-)
>
> --
> 2.37.2
>


From anup at brainfault.org  Sun Dec  4 21:23:54 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 10:53:54 +0530
Subject: [PATCH 1/1] firmware: Minor optimization for relocate
In-Reply-To: <20221129035407.28946-2-zhangdongdong@eswincomputing.com>
References: <20221129035407.28946-1-zhangdongdong@eswincomputing.com> <20221129035407.28946-2-zhangdongdong@eswincomputing.com>
Message-ID: <CAAhSdy0-a9PtRj18dMmv3fe-EU6t0O0TNHFDhu0GP9uhKnNPKg@mail.gmail.com>

On Tue, Nov 29, 2022 at 9:26 AM Dongdong Zhang
<zhangdongdong at eswincomputing.com> wrote:
>
> The t3 register stores the address of _load_end. If relocation is not required, it is unnecessary to calculate the address of _load_end.
>
> This can reduce the operation time of two instructions.
>
> Signed-off-by: Dongdong Zhang <zhangdongdong at eswincomputing.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

I have taken care of Bin's comment at the time of merging this patch.

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  firmware/fw_base.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index 07be4c4..3f622b3 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -128,9 +128,9 @@ _relocate:
>         REG_L   t1, 0(t1)
>         lla     t2, _load_start
>         REG_L   t2, 0(t2)
> +       beq     t0, t2, _relocate_done
>         sub     t3, t1, t0
>         add     t3, t3, t2
> -       beq     t0, t2, _relocate_done
>         lla     t4, _relocate_done
>         sub     t4, t4, t2
>         add     t4, t4, t0
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:09:35 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 17:39:35 +0530
Subject: [PATCH v2 1/4] platform: generic/andes: Enable generic platform
 support for AE350
In-Reply-To: <20221205020400.28712-2-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com> <20221205020400.28712-2-peterlin@andestech.com>
Message-ID: <CAAhSdy0wiGYaPs2dkHknU-3rBD77hRUih9Yizfvz65OcAHdM9A@mail.gmail.com>

On Mon, Dec 5, 2022 at 7:34 AM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> We move andes directory to platform/generic as the necessary fdt
> drivers are available, the users can enable the console, timer, ipi,
> irqchip and reset devices by adding device tree nodes stated in the
> docs/platform/andes-ae350.md.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> Changes v1 -> v2
> - Add Bin Meng's review tag
> ---
>  platform/andes/ae350/Kconfig           |  34 -----
>  platform/andes/ae350/cache.c           |  89 -------------
>  platform/andes/ae350/cache.h           |  17 ---
>  platform/andes/ae350/configs/defconfig |   0
>  platform/andes/ae350/objects.mk        |  40 ------
>  platform/andes/ae350/platform.c        | 169 -------------------------
>  platform/andes/ae350/platform.h        | 109 ----------------
>  platform/generic/Kconfig               |   4 +
>  platform/generic/andes/ae350.c         |  21 +++
>  platform/generic/andes/objects.mk      |   6 +
>  platform/generic/configs/defconfig     |   4 +
>  11 files changed, 35 insertions(+), 458 deletions(-)
>  delete mode 100644 platform/andes/ae350/Kconfig
>  delete mode 100644 platform/andes/ae350/cache.c
>  delete mode 100644 platform/andes/ae350/cache.h
>  delete mode 100644 platform/andes/ae350/configs/defconfig
>  delete mode 100644 platform/andes/ae350/objects.mk
>  delete mode 100644 platform/andes/ae350/platform.c
>  delete mode 100644 platform/andes/ae350/platform.h
>  create mode 100644 platform/generic/andes/ae350.c
>  create mode 100644 platform/generic/andes/objects.mk
>
> diff --git a/platform/andes/ae350/Kconfig b/platform/andes/ae350/Kconfig
> deleted file mode 100644
> index 38e4001..0000000
> --- a/platform/andes/ae350/Kconfig
> +++ /dev/null
> @@ -1,34 +0,0 @@
> -# SPDX-License-Identifier: BSD-2-Clause
> -
> -config PLATFORM_ANDES_AE350
> -       bool
> -       select FDT
> -       select FDT_SERIAL
> -       select FDT_SERIAL_UART8250
> -       select FDT_TIMER
> -       select FDT_TIMER_PLMT
> -       select FDT_RESET
> -       select FDT_RESET_ATCWDT200
> -       select FDT_IRQCHIP
> -       select FDT_IRQCHIP_PLIC
> -       select FDT_IPI
> -       select FDT_IPI_PLICSW
> -       default y
> -
> -if PLATFORM_ANDES_AE350
> -
> -config PLATFORM_ANDES_AE350_NAME
> -       string "Platform default name"
> -       default "Andes AE350"
> -
> -config PLATFORM_ANDES_AE350_MAJOR_VER
> -       int "Platform major version"
> -       range 0 65535
> -       default 0
> -
> -config PLATFORM_ANDES_AE350_MINOR_VER
> -       int "Platform minor version"
> -       range 0 65535
> -       default 1
> -
> -endif
> diff --git a/platform/andes/ae350/cache.c b/platform/andes/ae350/cache.c
> deleted file mode 100644
> index af724c5..0000000
> --- a/platform/andes/ae350/cache.c
> +++ /dev/null
> @@ -1,89 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - *
> - * Copyright (c) 2020 Andes Technology Corporation
> - *
> - * Authors:
> - *   Nylon Chen <nylon7 at andestech.com>
> - */
> -
> -#include <sbi/riscv_asm.h>
> -#include <sbi/riscv_io.h>
> -#include <sbi/sbi_types.h>
> -#include "platform.h"
> -
> -uintptr_t mcall_set_mcache_ctl(unsigned long input)
> -{
> -       csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
> -       csr_write(CSR_MCACHECTL, input);
> -       return 0;
> -}
> -
> -uintptr_t mcall_set_mmisc_ctl(unsigned long input)
> -{
> -       csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
> -       csr_write(CSR_MMISCCTL, input);
> -       return 0;
> -}
> -
> -uintptr_t mcall_icache_op(unsigned int enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
> -               asm volatile("fence.i\n\t");
> -       }
> -       return 0;
> -}
> -
> -uintptr_t mcall_dcache_op(unsigned int enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
> -               csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
> -       }
> -       return 0;
> -}
> -
> -uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
> -       }
> -       return 0;
> -}
> -
> -uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
> -       }
> -       return 0;
> -}
> -
> -uintptr_t mcall_non_blocking_load_store(unsigned long enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
> -       }
> -       return 0;
> -}
> -
> -uintptr_t mcall_write_around(unsigned long enable)
> -{
> -       if (enable) {
> -               csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
> -       } else {
> -               csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
> -       }
> -       return 0;
> -}
> diff --git a/platform/andes/ae350/cache.h b/platform/andes/ae350/cache.h
> deleted file mode 100644
> index e1c1826..0000000
> --- a/platform/andes/ae350/cache.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - *
> - * Copyright (c) 2020 Andes Technology Corporation
> - *
> - * Authors:
> - *   Nylon Chen <nylon7 at andestech.com>
> - */
> -
> -uintptr_t mcall_set_mcache_ctl(unsigned long input);
> -uintptr_t mcall_set_mmisc_ctl(unsigned long input);
> -uintptr_t mcall_icache_op(unsigned int enable);
> -uintptr_t mcall_dcache_op(unsigned int enable);
> -uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable);
> -uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable);
> -uintptr_t mcall_non_blocking_load_store(unsigned long enable);
> -uintptr_t mcall_write_around(unsigned long enable);
> diff --git a/platform/andes/ae350/configs/defconfig b/platform/andes/ae350/configs/defconfig
> deleted file mode 100644
> index e69de29..0000000
> diff --git a/platform/andes/ae350/objects.mk b/platform/andes/ae350/objects.mk
> deleted file mode 100644
> index a4a2332..0000000
> --- a/platform/andes/ae350/objects.mk
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -#
> -# SPDX-License-Identifier: BSD-2-Clause
> -#
> -# Copyright (c) 2019 Andes Technology Corporation
> -#
> -# Authors:
> -#   Zong Li <zong at andestech.com>
> -#   Nylon Chen <nylon7 at andestech.com>
> -#
> -
> -# Compiler flags
> -platform-cppflags-y =
> -platform-cflags-y =
> -platform-asflags-y =
> -platform-ldflags-y =
> -
> -# Objects to build
> -platform-objs-y += cache.o platform.o
> -
> -# Blobs to build
> -FW_TEXT_START=0x00000000
> -
> -FW_DYNAMIC=y
> -
> -FW_JUMP=y
> -ifeq ($(PLATFORM_RISCV_XLEN), 32)
> -  FW_JUMP_ADDR=0x400000
> -else
> -  FW_JUMP_ADDR=0x200000
> -endif
> -FW_JUMP_FDT_ADDR=0x2000000
> -
> -FW_PAYLOAD=y
> -ifeq ($(PLATFORM_RISCV_XLEN), 32)
> -  FW_PAYLOAD_OFFSET=0x400000
> -else
> -  FW_PAYLOAD_OFFSET=0x200000
> -endif
> -
> -FW_PAYLOAD_FDT_ADDR=0x2000000
> diff --git a/platform/andes/ae350/platform.c b/platform/andes/ae350/platform.c
> deleted file mode 100644
> index d36d11e..0000000
> --- a/platform/andes/ae350/platform.c
> +++ /dev/null
> @@ -1,169 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - *
> - * Copyright (c) 2019 Andes Technology Corporation
> - *
> - * Authors:
> - *   Zong Li <zong at andestech.com>
> - *   Nylon Chen <nylon7 at andestech.com>
> - *   Yu Chien Peter Lin <peterlin at andestech.com>
> - */
> -
> -#include <libfdt.h>
> -#include <sbi/riscv_asm.h>
> -#include <sbi/riscv_encoding.h>
> -#include <sbi/sbi_console.h>
> -#include <sbi/sbi_const.h>
> -#include <sbi/sbi_hartmask.h>
> -#include <sbi/sbi_ipi.h>
> -#include <sbi/sbi_platform.h>
> -#include <sbi/sbi_string.h>
> -#include <sbi/sbi_trap.h>
> -#include <sbi_utils/fdt/fdt_domain.h>
> -#include <sbi_utils/fdt/fdt_fixup.h>
> -#include <sbi_utils/fdt/fdt_helper.h>
> -#include <sbi_utils/ipi/fdt_ipi.h>
> -#include <sbi_utils/irqchip/fdt_irqchip.h>
> -#include <sbi_utils/reset/fdt_reset.h>
> -#include <sbi_utils/serial/fdt_serial.h>
> -#include <sbi_utils/timer/fdt_timer.h>
> -#include "platform.h"
> -#include "cache.h"
> -
> -struct sbi_platform platform;
> -unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
> -                               unsigned long arg2, unsigned long arg3,
> -                               unsigned long arg4)
> -{
> -       const char *model;
> -       void *fdt = (void *)arg1;
> -       u32 hartid, hart_count = 0;
> -       int rc, root_offset, cpus_offset, cpu_offset, len;
> -
> -       root_offset = fdt_path_offset(fdt, "/");
> -       if (root_offset < 0)
> -               goto fail;
> -
> -       model = fdt_getprop(fdt, root_offset, "model", &len);
> -       if (model)
> -               sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
> -
> -       cpus_offset = fdt_path_offset(fdt, "/cpus");
> -       if (cpus_offset < 0)
> -               goto fail;
> -
> -       fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
> -               rc = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> -               if (rc)
> -                       continue;
> -
> -               if (SBI_HARTMASK_MAX_BITS <= hartid)
> -                       continue;
> -
> -               hart_count++;
> -       }
> -
> -       platform.hart_count = hart_count;
> -
> -       /* Return original FDT pointer */
> -       return arg1;
> -
> -fail:
> -       while (1)
> -               wfi();
> -}
> -
> -/* Platform final initialization. */
> -static int ae350_final_init(bool cold_boot)
> -{
> -       void *fdt;
> -
> -       if (!cold_boot)
> -               return 0;
> -
> -       fdt_reset_init();
> -
> -       fdt = fdt_get_address();
> -       fdt_fixups(fdt);
> -       fdt_domain_fixup(fdt);
> -
> -       return 0;
> -}
> -
> -/* Vendor-Specific SBI handler */
> -static int ae350_vendor_ext_provider(long extid, long funcid,
> -       const struct sbi_trap_regs *regs, unsigned long *out_value,
> -       struct sbi_trap_info *out_trap)
> -{
> -       int ret = 0;
> -       switch (funcid) {
> -       case SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS:
> -               *out_value = csr_read(CSR_MCACHECTL);
> -               break;
> -       case SBI_EXT_ANDES_GET_MMISC_CTL_STATUS:
> -               *out_value = csr_read(CSR_MMISCCTL);
> -               break;
> -       case SBI_EXT_ANDES_SET_MCACHE_CTL:
> -               ret = mcall_set_mcache_ctl(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_SET_MMISC_CTL:
> -               ret = mcall_set_mmisc_ctl(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_ICACHE_OP:
> -               ret = mcall_icache_op(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_DCACHE_OP:
> -               ret = mcall_dcache_op(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_L1CACHE_I_PREFETCH:
> -               ret = mcall_l1_cache_i_prefetch_op(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_L1CACHE_D_PREFETCH:
> -               ret = mcall_l1_cache_d_prefetch_op(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE:
> -               ret = mcall_non_blocking_load_store(regs->a0);
> -               break;
> -       case SBI_EXT_ANDES_WRITE_AROUND:
> -               ret = mcall_write_around(regs->a0);
> -               break;
> -       default:
> -               sbi_printf("Unsupported vendor sbi call : %ld\n", funcid);
> -               asm volatile("ebreak");
> -       }
> -       return ret;
> -}
> -
> -static int ae350_domains_init(void)
> -{
> -       return fdt_domains_populate(fdt_get_address());
> -}
> -
> -/* Platform descriptor. */
> -const struct sbi_platform_operations platform_ops = {
> -       .final_init = ae350_final_init,
> -
> -       .domains_init = ae350_domains_init,
> -
> -       .console_init = fdt_serial_init,
> -
> -       .irqchip_init = fdt_irqchip_init,
> -
> -       .ipi_init     = fdt_ipi_init,
> -
> -       .timer_init        = fdt_timer_init,
> -
> -       .vendor_ext_provider = ae350_vendor_ext_provider
> -};
> -
> -struct sbi_platform platform = {
> -       .opensbi_version = OPENSBI_VERSION,
> -       .platform_version =
> -               SBI_PLATFORM_VERSION(CONFIG_PLATFORM_ANDES_AE350_MAJOR_VER,
> -                                    CONFIG_PLATFORM_ANDES_AE350_MINOR_VER),
> -       .name = CONFIG_PLATFORM_ANDES_AE350_NAME,
> -       .features = SBI_PLATFORM_DEFAULT_FEATURES,
> -       .hart_count = SBI_HARTMASK_MAX_BITS,
> -       .hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
> -       .platform_ops_addr = (unsigned long)&platform_ops
> -};
> diff --git a/platform/andes/ae350/platform.h b/platform/andes/ae350/platform.h
> deleted file mode 100644
> index 903bef0..0000000
> --- a/platform/andes/ae350/platform.h
> +++ /dev/null
> @@ -1,109 +0,0 @@
> -/*
> - * SPDX-License-Identifier: BSD-2-Clause
> - *
> - * Copyright (c) 2019 Andes Technology Corporation
> - *
> - * Authors:
> - *   Zong Li <zong at andestech.com>
> - *   Nylon Chen <nylon7 at andestech.com>
> - */
> -
> -#ifndef _AE350_PLATFORM_H_
> -#define _AE350_PLATFORM_H_
> -
> -#define AE350_L2C_ADDR                 0xe0500000
> -
> -/*Memory and Miscellaneous Registers*/
> -#define CSR_MILMB              0x7c0
> -#define CSR_MDLMB              0x7c1
> -#define CSR_MECC_CDOE          0x7c2
> -#define CSR_MNVEC              0x7c3
> -#define CSR_MPFTCTL            0x7c5
> -#define CSR_MCACHECTL          0x7ca
> -#define CSR_MCCTLBEGINADDR     0x7cb
> -#define CSR_MCCTLCOMMAND       0x7cc
> -#define CSR_MCCTLDATA          0x7cc
> -#define CSR_SCCTLDATA          0x9cd
> -#define CSR_UCCTLBEGINADDR     0x80c
> -#define CSR_MMISCCTL           0x7d0
> -
> -enum sbi_ext_andes_fid {
> -       SBI_EXT_ANDES_GET_MCACHE_CTL_STATUS = 0,
> -       SBI_EXT_ANDES_GET_MMISC_CTL_STATUS,
> -       SBI_EXT_ANDES_SET_MCACHE_CTL,
> -       SBI_EXT_ANDES_SET_MMISC_CTL,
> -       SBI_EXT_ANDES_ICACHE_OP,
> -       SBI_EXT_ANDES_DCACHE_OP,
> -       SBI_EXT_ANDES_L1CACHE_I_PREFETCH,
> -       SBI_EXT_ANDES_L1CACHE_D_PREFETCH,
> -       SBI_EXT_ANDES_NON_BLOCKING_LOAD_STORE,
> -       SBI_EXT_ANDES_WRITE_AROUND,
> -};
> -
> -/* nds v5 mmisc_ctl register*/
> -#define V5_MMISC_CTL_VEC_PLIC_OFFSET            1
> -#define V5_MMISC_CTL_RVCOMPM_OFFSET             2
> -#define V5_MMISC_CTL_BRPE_OFFSET                3
> -#define V5_MMISC_CTL_MSA_OR_UNA_OFFSET          6
> -#define V5_MMISC_CTL_NON_BLOCKING_OFFSET        8
> -#define V5_MCACHE_CTL_L1I_PREFETCH_OFFSET       9
> -#define V5_MCACHE_CTL_L1D_PREFETCH_OFFSET       10
> -#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_1       13
> -#define V5_MCACHE_CTL_DC_WAROUND_OFFSET_2       14
> -
> -#define V5_MMISC_CTL_VEC_PLIC_EN        (1UL << V5_MMISC_CTL_VEC_PLIC_OFFSET)
> -#define V5_MMISC_CTL_RVCOMPM_EN         (1UL << V5_MMISC_CTL_RVCOMPM_OFFSET)
> -#define V5_MMISC_CTL_BRPE_EN            (1UL << V5_MMISC_CTL_BRPE_OFFSET)
> -#define V5_MMISC_CTL_MSA_OR_UNA_EN      (1UL << V5_MMISC_CTL_MSA_OR_UNA_OFFSET)
> -#define V5_MMISC_CTL_NON_BLOCKING_EN    (1UL << V5_MMISC_CTL_NON_BLOCKING_OFFSET)
> -#define V5_MCACHE_CTL_L1I_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1I_PREFETCH_OFFSET)
> -#define V5_MCACHE_CTL_L1D_PREFETCH_EN   (1UL << V5_MCACHE_CTL_L1D_PREFETCH_OFFSET)
> -#define V5_MCACHE_CTL_DC_WAROUND_1_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_1)
> -#define V5_MCACHE_CTL_DC_WAROUND_2_EN   (1UL << V5_MCACHE_CTL_DC_WAROUND_OFFSET_2)
> -
> -#define V5_MMISC_CTL_MASK  (V5_MMISC_CTL_VEC_PLIC_EN | V5_MMISC_CTL_RVCOMPM_EN \
> -       | V5_MMISC_CTL_BRPE_EN | V5_MMISC_CTL_MSA_OR_UNA_EN | V5_MMISC_CTL_NON_BLOCKING_EN)
> -
> -/* nds mcache_ctl register*/
> -#define V5_MCACHE_CTL_IC_EN_OFFSET      0
> -#define V5_MCACHE_CTL_DC_EN_OFFSET      1
> -#define V5_MCACHE_CTL_IC_ECCEN_OFFSET   2
> -#define V5_MCACHE_CTL_DC_ECCEN_OFFSET   4
> -#define V5_MCACHE_CTL_IC_RWECC_OFFSET   6
> -#define V5_MCACHE_CTL_DC_RWECC_OFFSET   7
> -#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET  8
> -
> -/*nds cctl command*/
> -#define V5_UCCTL_L1D_WBINVAL_ALL 6
> -#define V5_UCCTL_L1D_WB_ALL 7
> -
> -#define V5_MCACHE_CTL_IC_EN     (1UL << V5_MCACHE_CTL_IC_EN_OFFSET)
> -#define V5_MCACHE_CTL_DC_EN     (1UL << V5_MCACHE_CTL_DC_EN_OFFSET)
> -#define V5_MCACHE_CTL_IC_RWECC  (1UL << V5_MCACHE_CTL_IC_RWECC_OFFSET)
> -#define V5_MCACHE_CTL_DC_RWECC  (1UL << V5_MCACHE_CTL_DC_RWECC_OFFSET)
> -#define V5_MCACHE_CTL_CCTL_SUEN (1UL << V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
> -
> -#define V5_MCACHE_CTL_MASK (V5_MCACHE_CTL_IC_EN | V5_MCACHE_CTL_DC_EN \
> -       | V5_MCACHE_CTL_IC_RWECC | V5_MCACHE_CTL_DC_RWECC \
> -       | V5_MCACHE_CTL_CCTL_SUEN | V5_MCACHE_CTL_L1I_PREFETCH_EN \
> -       | V5_MCACHE_CTL_L1D_PREFETCH_EN | V5_MCACHE_CTL_DC_WAROUND_1_EN \
> -       | V5_MCACHE_CTL_DC_WAROUND_2_EN)
> -
> -#define V5_L2C_CTL_OFFSET           0x8
> -#define V5_L2C_CTL_ENABLE_OFFSET    0
> -#define V5_L2C_CTL_IPFDPT_OFFSET    3
> -#define V5_L2C_CTL_DPFDPT_OFFSET    5
> -#define V5_L2C_CTL_TRAMOCTL_OFFSET  8
> -#define V5_L2C_CTL_TRAMICTL_OFFSET  10
> -#define V5_L2C_CTL_DRAMOCTL_OFFSET  11
> -#define V5_L2C_CTL_DRAMICTL_OFFSET  13
> -
> -#define V5_L2C_CTL_ENABLE_MASK      (1UL << V5_L2C_CTL_ENABLE_OFFSET)
> -#define V5_L2C_CTL_IPFDPT_MASK      (3UL << V5_L2C_CTL_IPFDPT_OFFSET)
> -#define V5_L2C_CTL_DPFDPT_MASK      (3UL << V5_L2C_CTL_DPFDPT_OFFSET)
> -#define V5_L2C_CTL_TRAMOCTL_MASK    (3UL << V5_L2C_CTL_TRAMOCTL_OFFSET)
> -#define V5_L2C_CTL_TRAMICTL_MASK    (1UL << V5_L2C_CTL_TRAMICTL_OFFSET)
> -#define V5_L2C_CTL_DRAMOCTL_MASK    (3UL << V5_L2C_CTL_DRAMOCTL_OFFSET)
> -#define V5_L2C_CTL_DRAMICTL_MASK    (1UL << V5_L2C_CTL_DRAMICTL_OFFSET)
> -
> -#endif /* _AE350_PLATFORM_H_ */
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 63d1be4..4b5d2cd 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -28,6 +28,10 @@ config PLATFORM_ALLWINNER_D1
>         depends on FDT_IRQCHIP_PLIC
>         default n
>
> +config PLATFORM_ANDES_AE350
> +       bool "Andes AE350 support"
> +       default n
> +
>  config PLATFORM_SIFIVE_FU540
>         bool "SiFive FU540 support"
>         default n
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> new file mode 100644
> index 0000000..cf7f6f2
> --- /dev/null
> +++ b/platform/generic/andes/ae350.c
> @@ -0,0 +1,21 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Andes Technology Corporation
> + *
> + * Authors:
> + *   Yu Chien Peter Lin <peterlin at andestech.com>
> + */
> +
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/fdt/fdt_fixup.h>
> +
> +static const struct fdt_match andes_ae350_match[] = {
> +       { .compatible = "andestech,ae350" },
> +       { },
> +};
> +
> +const struct platform_override andes_ae350 = {
> +       .match_table = andes_ae350_match,
> +};
> diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> new file mode 100644
> index 0000000..dd6408d
> --- /dev/null
> +++ b/platform/generic/andes/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_ANDES_AE350) += andes_ae350
> +platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index c95b7fa..2eaeeb7 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -1,4 +1,5 @@
>  CONFIG_PLATFORM_ALLWINNER_D1=y
> +CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
>  CONFIG_FDT_GPIO=y
> @@ -7,11 +8,13 @@ CONFIG_FDT_I2C=y
>  CONFIG_FDT_I2C_SIFIVE=y
>  CONFIG_FDT_IPI=y
>  CONFIG_FDT_IPI_MSWI=y
> +CONFIG_FDT_IPI_PLICSW=y
>  CONFIG_FDT_IRQCHIP=y
>  CONFIG_FDT_IRQCHIP_APLIC=y
>  CONFIG_FDT_IRQCHIP_IMSIC=y
>  CONFIG_FDT_IRQCHIP_PLIC=y
>  CONFIG_FDT_RESET=y
> +CONFIG_FDT_RESET_ATCWDT200=y
>  CONFIG_FDT_RESET_GPIO=y
>  CONFIG_FDT_RESET_HTIF=y
>  CONFIG_FDT_RESET_SIFIVE_TEST=y
> @@ -28,4 +31,5 @@ CONFIG_FDT_SERIAL_UART8250=y
>  CONFIG_FDT_SERIAL_XILINX_UARTLITE=y
>  CONFIG_FDT_TIMER=y
>  CONFIG_FDT_TIMER_MTIMER=y
> +CONFIG_FDT_TIMER_PLMT=y
>  CONFIG_SERIAL_SEMIHOSTING=y
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:10:18 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 17:40:18 +0530
Subject: [PATCH v2 2/4] docs: platform: Update AE350 and generic platform documentation
In-Reply-To: <20221205020400.28712-3-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com> <20221205020400.28712-3-peterlin@andestech.com>
Message-ID: <CAAhSdy1XJik0cy_L1hjuXGNphig2vsnEJWQjOFWT4XQXS9ahVA@mail.gmail.com>

On Mon, Dec 5, 2022 at 7:35 AM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> Update compile option and platform compatible string for AE350 and
> add it to the generic platform list.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> Changes v1 -> v2
> - Add Bin Meng's review tag
> - Insert AE350 platform in alphabetical order
> ---
>  docs/platform/andes-ae350.md | 5 +++--
>  docs/platform/generic.md     | 2 ++
>  2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
> index ec241ec..4739951 100644
> --- a/docs/platform/andes-ae350.md
> +++ b/docs/platform/andes-ae350.md
> @@ -8,7 +8,7 @@ AHB/APB IPs suites a majority embedded systems, and the verified platform serves
>  as a starting point to jump start SoC designs.
>
>  To build platform specific library and firmwares, provide the
> -*PLATFORM=andes/ae350* parameter to the top level make command.
> +*PLATFORM=generic* parameter to the top level `make` command.
>
>  Platform Options
>  ----------------
> @@ -23,13 +23,14 @@ AE350's dts is included in https://github.com/andestech/linux/tree/RISCV-Linux-5
>  **Linux Kernel Payload**
>
>  ```
> -make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
> +make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
>  ```
>
>  DTS Example: (Quad-core AX45MP)
>  -------------------------------
>
>  ```
> +       compatible = "andestech,ae350";
>         cpus {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> diff --git a/docs/platform/generic.md b/docs/platform/generic.md
> index 73a8afa..e8a3296 100644
> --- a/docs/platform/generic.md
> +++ b/docs/platform/generic.md
> @@ -45,12 +45,14 @@ The *Generic* platform does not have any platform-specific options.
>  RISC-V Platforms Using Generic Platform
>  ---------------------------------------
>
> +* **Andes AE350 Platform** (*[andes-ae350.md]*)
>  * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
>  * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
>  * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
>  * **Spike** (*[spike.md]*)
>  * **T-HEAD C9xx series Processors** (*[thead-c9xx.md]*)
>
> +[andes-ae350.md]: andse-ae350.md
>  [qemu_virt.md]: qemu_virt.md
>  [shakti_cclass.md]: shakti_cclass.md
>  [sifive_fu540.md]: sifive_fu540.md
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:10:34 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 17:40:34 +0530
Subject: [PATCH v2 3/4] docs: andes-ae350.md: fix watchdog nodename in dts example
In-Reply-To: <20221205020400.28712-4-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com> <20221205020400.28712-4-peterlin@andestech.com>
Message-ID: <CAAhSdy3JbTZT9Xu6CzhiCLVRyazj5-X=Sm1vDaMECB6pxXtDpQ@mail.gmail.com>

On Mon, Dec 5, 2022 at 7:35 AM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> The example should use watchdog as nodename instead of wdt.
> This is defined in watchdog common schemas:
> https://github.com/torvalds/linux/blob/v6.0/Documentation/devicetree/bindings/watchdog/watchdog.yaml#L19
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> Changes v1 -> v2
> - Add Bin Meng's review tag
> ---
>  docs/platform/andes-ae350.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/platform/andes-ae350.md b/docs/platform/andes-ae350.md
> index 4739951..8fc8ec6 100644
> --- a/docs/platform/andes-ae350.md
> +++ b/docs/platform/andes-ae350.md
> @@ -178,7 +178,7 @@ DTS Example: (Quad-core AX45MP)
>                                                 &CPU3_intc 7 >;
>                 };
>
> -               wdt: wdt at f0500000 {
> +               wdt: watchdog at f0500000 {
>                         compatible = "andestech,atcwdt200";
>                         reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
>                         interrupts = <3 4>;
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:11:13 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 17:41:13 +0530
Subject: [PATCH v2 4/4] scripts/create-binary-archive.sh: remove
 andes/ae350 build directory
In-Reply-To: <20221205020400.28712-5-peterlin@andestech.com>
References: <20221205020400.28712-1-peterlin@andestech.com> <20221205020400.28712-5-peterlin@andestech.com>
Message-ID: <CAAhSdy0ZrYNMtK4xgCareA=z+jD9w-iuyRuFo-q_XrP9-+d+cQ@mail.gmail.com>

On Mon, Dec 5, 2022 at 7:35 AM Yu Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> The andes-specific files have been moved to generic platform so we
> can drop this line.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
> Reviewed-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> Changes v1 -> v2
> - Add Bin Meng's review tag
> ---
>  scripts/create-binary-archive.sh | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
> index 261a45a..4dda7b4 100755
> --- a/scripts/create-binary-archive.sh
> +++ b/scripts/create-binary-archive.sh
> @@ -103,7 +103,6 @@ build_opensbi() {
>                 BUILD_PLATFORM_SUBDIR+=("kendryte/k210")
>                 BUILD_PLATFORM_SUBDIR+=("fpga/ariane")
>                 BUILD_PLATFORM_SUBDIR+=("fpga/openpiton")
> -               BUILD_PLATFORM_SUBDIR+=("andes/ae350")
>                 BUILD_PLATFORM_SUBDIR+=("generic")
>                 ;;
>         *)
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:26:16 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 17:56:16 +0530
Subject: [PATCH] lib: utils: Add fdt_fixup_node() helper function
In-Reply-To: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221202115947.226472-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2G9XJ+z0X-A8-tDSr3kjBjDWebDF7LVbxzP1NL3BpU_g@mail.gmail.com>

On Fri, Dec 2, 2022 at 5:30 PM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add a helper function fdt_fixup_node() based on the compatible string.
> This will avoid code duplication for every new node fixup being added.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

I have taken care of Bin's comment at the time of merging this patch.
Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/utils/fdt/fdt_fixup.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index d1050bb..ef06c6b 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -74,22 +74,22 @@ static void fdt_domain_based_fixup_one(void *fdt, int nodeoff)
>         }
>  }
>
> -void fdt_aplic_fixup(void *fdt)
> +static void fdt_fixup_node(void *fdt, const char *compatible)
>  {
>         int noff = 0;
>
> -       while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -                                                    "riscv,aplic")) >= 0)
> +       while ((noff = fdt_node_offset_by_compatible(fdt, noff, compatible)) >= 0)
>                 fdt_domain_based_fixup_one(fdt, noff);
>  }
>
> -void fdt_imsic_fixup(void *fdt)
> +void fdt_aplic_fixup(void *fdt)
>  {
> -       int noff = 0;
> +       fdt_fixup_node(fdt, "riscv,aplic");
> +}
>
> -       while ((noff = fdt_node_offset_by_compatible(fdt, noff,
> -                                                    "riscv,imsics")) >= 0)
> -               fdt_domain_based_fixup_one(fdt, noff);
> +void fdt_imsic_fixup(void *fdt)
> +{
> +       fdt_fixup_node(fdt, "riscv,imsics");
>  }
>
>  void fdt_plic_fixup(void *fdt)
> --
> 2.17.1
>


From anup at brainfault.org  Mon Dec  5 04:31:37 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 18:01:37 +0530
Subject: [PATCH 1/1] gitignore: add vim swap files
In-Reply-To: <20221203210415.113835-1-geomatsi@gmail.com>
References: <20221203210415.113835-1-geomatsi@gmail.com>
Message-ID: <CAAhSdy182WMuGOqGAhPDS7POONyxMRLJca59PSuYu6Yk+aa7eA@mail.gmail.com>

On Sun, Dec 4, 2022 at 2:34 AM Sergey Matyukevich <geomatsi at gmail.com> wrote:
>
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>

Please don't leave the commit description empty.

>
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich at syntacore.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  .gitignore | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/.gitignore b/.gitignore
> index 95692bb..c11afd3 100644
> --- a/.gitignore
> +++ b/.gitignore
> @@ -10,3 +10,4 @@ install/
>  # Development friendly files
>  tags
>  cscope*
> +*.swp
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 04:37:58 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 18:07:58 +0530
Subject: [PATCH v3 2/6] lib: utils: serial: Add FDT driver for Renesas SCIF
In-Reply-To: <20221130220825.193693-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221130220825.193693-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2t7kj1dc-OZMaJ=g8JmosiE2rES1_D2eW=t4DhSaxo7Q@mail.gmail.com>

On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Add FDT driver for Renesas SCIF.
>
>     dts example:
>
>     soc: soc {
>           ....
>             scif0: serial at 1004b800 {
>                     compatible = "renesas,scif-r9a07g043",
>                                  "renesas,scif-r9a07g044";
>                     reg = <0 0x1004b800 0 0x400>;
>                     interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
>                                  <414 IRQ_TYPE_LEVEL_HIGH>,
>                                  <415 IRQ_TYPE_LEVEL_HIGH>,
>                                  <413 IRQ_TYPE_LEVEL_HIGH>,
>                                  <416 IRQ_TYPE_LEVEL_HIGH>,
>                                  <416 IRQ_TYPE_LEVEL_HIGH>;
>                     interrupt-names = "eri", "rxi", "txi",
>                                       "bri", "dri", "tei";
>                     clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
>                     clock-names = "fck";
>                     power-domains = <&cpg>;
>                     resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
>                     status = "disabled";
>             };
>           ....
>     };
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> v2->v3
> * No change
>
> RFC->v2
> * Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and
>   DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros.
>
> DT binding [0].
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80
> ---
>  include/sbi_utils/fdt/fdt_helper.h         |  3 +++
>  lib/utils/fdt/fdt_helper.c                 | 11 ++++++++
>  lib/utils/serial/Kconfig                   |  5 ++++
>  lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++
>  lib/utils/serial/objects.mk                |  3 +++
>  5 files changed, 53 insertions(+)
>  create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
>
> diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
> index c39f77a..09f3095 100644
> --- a/include/sbi_utils/fdt/fdt_helper.h
> +++ b/include/sbi_utils/fdt/fdt_helper.h
> @@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
>  int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>                                 struct platform_uart_data *uart);
>
> +int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
> +                               struct platform_uart_data *uart);
> +
>  int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart);
>
> diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> index d4b38dc..48bc2fe 100644
> --- a/lib/utils/fdt/fdt_helper.c
> +++ b/lib/utils/fdt/fdt_helper.c
> @@ -23,6 +23,9 @@
>  #define DEFAULT_UART_REG_IO_WIDTH      1
>  #define DEFAULT_UART_REG_OFFSET                0
>
> +#define DEFAULT_RENESAS_SCIF_FREQ              100000000
> +#define DEFAULT_RENESAS_SCIF_BAUD              115200
> +
>  #define DEFAULT_SIFIVE_UART_FREQ               0
>  #define DEFAULT_SIFIVE_UART_BAUD               115200
>
> @@ -355,6 +358,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
>                                         DEFAULT_UART_BAUD);
>  }
>
> +int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
> +                               struct platform_uart_data *uart)
> +{
> +       return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
> +                                         DEFAULT_RENESAS_SCIF_FREQ,
> +                                         DEFAULT_RENESAS_SCIF_BAUD);
> +}
> +
>  int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
>                                struct platform_uart_data *uart)
>  {
> diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> index f6ed803..e3589ca 100644
> --- a/lib/utils/serial/Kconfig
> +++ b/lib/utils/serial/Kconfig
> @@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF
>         select SYS_HTIF
>         default n
>
> +config FDT_SERIAL_RENESAS_SCIF
> +       bool "Renesas SCIF FDT driver"
> +       select SERIAL_RENESAS_SCIF
> +       default n
> +
>  config FDT_SERIAL_SHAKTI
>         bool "Shakti UART FDT driver"
>         select SERIAL_SHAKTI
> diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c
> new file mode 100644
> index 0000000..c331ca1
> --- /dev/null
> +++ b/lib/utils/serial/fdt_serial_renesas_scif.c
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#include <sbi_utils/fdt/fdt_helper.h>
> +#include <sbi_utils/serial/fdt_serial.h>
> +#include <sbi_utils/serial/renesas-scif.h>
> +
> +static int serial_renesas_scif_init(void *fdt, int nodeoff,
> +                                   const struct fdt_match *match)
> +{
> +       struct platform_uart_data uart = { 0 };
> +       int ret;
> +
> +       ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart);
> +       if (ret)
> +               return ret;
> +
> +       return renesas_scif_init(uart.addr, uart.freq, uart.baud);
> +}
> +
> +static const struct fdt_match serial_renesas_scif_match[] = {
> +       { .compatible = "renesas,scif-r9a07g043" },
> +       { /* sentinel */ }
> +};
> +
> +struct fdt_serial fdt_serial_renesas_scif = {
> +       .match_table = serial_renesas_scif_match,
> +       .init = serial_renesas_scif_init
> +};
> diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> index 6520424..1e6bd2e 100644
> --- a/lib/utils/serial/objects.mk
> +++ b/lib/utils/serial/objects.mk
> @@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o
>  carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif
>  libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o
>
> +carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif
> +libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o
> +
>  carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti
>  libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o
>
> --
> 2.17.1
>


From anup at brainfault.org  Mon Dec  5 04:38:48 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 18:08:48 +0530
Subject: [PATCH v3 4/6] platform: generic: Add Renesas RZ/Five initial support
In-Reply-To: <20221130220825.193693-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221130220825.193693-5-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2qCe0Vq9ujxT0SEU1RTo11X_V9Wb30SON6OPGtiWNa0A@mail.gmail.com>

On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> This commit provides basic support for the Renesas RZ/Five
> (R9A07G043F) SoC.
>
> The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> - Gigabit Ethernet 2ch
> - CAN interface (CAN-FD) 2ch
> - USB 2.0 interface 2ch
> - SD interface 2ch
> - AD converter 2ch
>
> Useful links:
> -------------
> Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> v2->v3
> * New patch
> ---
>  platform/generic/Kconfig                   |  4 ++++
>  platform/generic/configs/defconfig         |  2 ++
>  platform/generic/renesas/rzfive/objects.mk |  8 ++++++++
>  platform/generic/renesas/rzfive/rzfive.c   | 17 +++++++++++++++++
>  4 files changed, 31 insertions(+)
>  create mode 100644 platform/generic/renesas/rzfive/objects.mk
>  create mode 100644 platform/generic/renesas/rzfive/rzfive.c
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 4b5d2cd..62c7a2d 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -32,6 +32,10 @@ config PLATFORM_ANDES_AE350
>         bool "Andes AE350 support"
>         default n
>
> +config PLATFORM_RENESAS_RZFIVE
> +       bool "Renesas RZ/Five support"
> +       default n
> +
>  config PLATFORM_SIFIVE_FU540
>         bool "SiFive FU540 support"
>         default n
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 2eaeeb7..47fca95 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -1,5 +1,6 @@
>  CONFIG_PLATFORM_ALLWINNER_D1=y
>  CONFIG_PLATFORM_ANDES_AE350=y
> +CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
>  CONFIG_FDT_GPIO=y
> @@ -24,6 +25,7 @@ CONFIG_FDT_SERIAL=y
>  CONFIG_FDT_SERIAL_CADENCE=y
>  CONFIG_FDT_SERIAL_GAISLER=y
>  CONFIG_FDT_SERIAL_HTIF=y
> +CONFIG_FDT_SERIAL_RENESAS_SCIF=y
>  CONFIG_FDT_SERIAL_SHAKTI=y
>  CONFIG_FDT_SERIAL_SIFIVE=y
>  CONFIG_FDT_SERIAL_LITEX=y
> diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
> new file mode 100644
> index 0000000..2e7e37f
> --- /dev/null
> +++ b/platform/generic/renesas/rzfive/objects.mk
> @@ -0,0 +1,8 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +# Copyright (C) 2022 Renesas Electronics Corp.
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
> +platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> new file mode 100644
> index 0000000..2b82bc6
> --- /dev/null
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + */
> +
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static const struct fdt_match renesas_rzfive_match[] = {
> +       { .compatible = "renesas,r9a07g043" },
> +       { /* sentinel */ }
> +};
> +
> +const struct platform_override renesas_rzfive = {
> +       .match_table = renesas_rzfive_match,
> +};
> --
> 2.17.1
>


From anup at brainfault.org  Mon Dec  5 04:46:34 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 18:16:34 +0530
Subject: [PATCH v3 6/6] platform: generic: Drop root_offset parameter from fw_platform_lookup_special()
In-Reply-To: <20221130220825.193693-7-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221130220825.193693-7-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy0kZDPJd4jWQGU-18gOtuS3dzgSQsThAafbf1RpDQrgQw@mail.gmail.com>

On Thu, Dec 1, 2022 at 3:39 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> root_offset parameter isn't used in fw_platform_lookup_special() so
> just drop it.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v2->v3
> * New patch
> ---
>  platform/generic/platform.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 595b0fd..fb5f476 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -32,7 +32,7 @@ extern unsigned long platform_override_modules_size;
>  static const struct platform_override *generic_plat = NULL;
>  static const struct fdt_match *generic_plat_match = NULL;
>
> -static void fw_platform_lookup_special(void *fdt, int root_offset)
> +static void fw_platform_lookup_special(void *fdt)

Rather than dropping root_offset, please update this patch to
replace use of fdt_find_match() with fdt_match_node(). This is
because platform override should be detected only based on
root DT node matching.

Regards,
Anup

>  {
>         int pos, noff;
>         const struct platform_override *plat;
> @@ -83,7 +83,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
>         if (root_offset < 0)
>                 goto fail;
>
> -       fw_platform_lookup_special(fdt, root_offset);
> +       fw_platform_lookup_special(fdt);
>
>         model = fdt_getprop(fdt, root_offset, "model", &len);
>         if (model)
> --
> 2.17.1
>


From anup at brainfault.org  Mon Dec  5 04:53:40 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 18:23:40 +0530
Subject: [PATCH v3 0/6] Add support for Renesas RZ/Five SoC
In-Reply-To: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2R2t9QENdi7qn-hx1_3xQMFi5D=cnT9AyL_k485YafBw@mail.gmail.com>

On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
>
> Hi All,
>
> This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
> is equipped with AX45MP AndesCore). Platform supports DT based probing.
>
> Linux support is currently being upstreamed the latest patchset can be
> found at [0](currently in linux-next, DT bindings can be seen here)
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
>   and is used in a similar manner as compared Andes AE350 [1]
>   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
>
> Note:
> - The PMA implementation is still in discussion [1] once its decided
> corresponding patch to OpenSBI will be added to reserve the memory nodes
> and vendor specific SBI EXT.
> - U-boot from BSP release wont work with these patches, it requires additional
>   patches (happy to share the u-boot branch if anyone wants to test this patchset)
> - Patches apply on top of [2]
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> [2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/
>
> v2->v3
> * Switched to generic platform
> * Dropped all vendor specific SBI EXT
> * Fixed review comments pointed by Bin for SCIF driver
> * Updated doc
>
> RFC->v2
> * Fixed comments pointed by Xiang W
> * Included RB tag from Yu Chien Peter Lin for patch #3
>
> RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
> -----------------------------------------------------------
> U-Boot SPL 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
> Trying to boot from NOR
>
> OpenSBI v1.1-109-gfa85d48
>    ____                    _____ ____ _____
>   / __ \                  / ____|  _ \_   _|
>  | |  | |_ __   ___ _ __ | (___ | |_) || |
>  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
>  | |__| | |_) |  __/ | | |____) | |_) || |_
>   \____/| .__/ \___|_| |_|_____/|____/_____|
>         | |
>         |_|
>
> Platform Name             : Renesas SMARC EVK based on r9a07g043f01
> Platform Features         : medeleg
> Platform HART Count       : 1
> Platform IPI Device       : andes_plicsw
> Platform Timer Device     : andes_plmt @ 12000000Hz
> Platform Console Device   : renesas_scif
> Platform HSM Device       : ---
> Platform PMU Device       : ---
> Platform Reboot Device    : ---
> Platform Shutdown Device  : ---

Any plans for a system reboot/shutdown driver for OpenSBI ?

Regards,
Anup

> Firmware Base             : 0x44000000
> Firmware Size             : 212 KB
> Runtime SBI Version       : 1.0
>
> Domain0 Name              : root
> Domain0 Boot HART         : 0
> Domain0 HARTs             : 0*
> Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
> Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
> Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
> Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
> Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
> Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
> Domain0 Next Address      : 0x0000000050000000
> Domain0 Next Arg1         : 0x00000000500bdee0
> Domain0 Next Mode         : S-mode
> Domain0 SysReset          : yes
>
> Boot HART ID              : 0
> Boot HART Domain          : root
> Boot HART Priv Version    : v1.11
> Boot HART Base ISA        : rv64imafdcnx
> Boot HART ISA Extensions  : none
> Boot HART PMP Count       : 16
> Boot HART PMP Granularity : 8
> Boot HART PMP Address Bits: 36
> Boot HART MHPM Count      : 4
> Boot HART MIDELEG         : 0x0000000000000222
> Boot HART MEDELEG         : 0x000000000000b109
>
>
> U-Boot 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
>
> CPU:   rv64imafdc
> Model: Renesas SMARC EVK based on r9a07g043f01
> DRAM:  896 MiB
> SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
> MMC:   sd at 11c00000: 0, sd at 11c10000: 1
> Loading Environment from MMC... OK
> In:    serial at 1004b800
> Out:   serial at 1004b800
> Err:   serial at 1004b800
> Net:   eth0: ethernet at 11c30000
> Hit any key to stop autoboot:  0
> => run prafat;run pranfs;run bootimage
> 7153012 bytes read in 445 ms (15.3 MiB/s)
> 22510 bytes read in 3 ms (7.2 MiB/s)
> Uncompressed size: 19854848 = 0x12EF600
> Moving Image from 0x48080000 to 0x48200000, end=49569000
> ## Flattened Device Tree blob at 48000000
>    Booting using the fdt blob at 0x48000000
>    Loading Device Tree to 0000000077f00000, end 0000000077f087ed ... OK
>
> Starting kernel ...
>
> [    0.000000] Linux version 6.1.0-rc4-00292-ga3c6b529ec9f-dirty (prasmi at prasmi) (riscv64-unknown-linux-gnu-gcc (g2ee5e430018) 12.2.0, GNU ld (GNU Binutils) 2.39) #69 SMP Wed Nov 30 17:36:35 GMT 2022
> [    0.000000] OF: fdt: Ignoring memory range 0x48000000 - 0x48200000
> [    0.000000] Machine model: Renesas SMARC EVK based on r9a07g043f01
> [    0.000000] efi: UEFI not found.
> [    0.000000] Reserved memory: created DMA memory pool at 0x0000000058000000, size 128 MiB
> [    0.000000] OF: reserved mem: initialized node linux,cma at 58000000, compatible id shared-dma-pool
> [    0.000000] Zone ranges:
> [    0.000000]   DMA32    [mem 0x0000000048200000-0x000000007fffffff]
> [    0.000000]   Normal   empty
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000048200000-0x0000000057ffffff]
> [    0.000000]   node   0: [mem 0x0000000058000000-0x000000005fffffff]
> [    0.000000]   node   0: [mem 0x0000000060000000-0x000000007fffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000048200000-0x000000007fffffff]
> [    0.000000] SBI specification v1.0 detected
> [    0.000000] SBI implementation ID=0x1 Version=0x10001
> [    0.000000] SBI TIME extension detected
> [    0.000000] SBI IPI extension detected
> [    0.000000] SBI RFENCE extension detected
> [    0.000000] SBI HSM extension detected
> [    0.000000] riscv: base ISA extensions acdfim
> [    0.000000] riscv: ELF capabilities acdfim
> [    0.000000] percpu: Embedded 18 pages/cpu s34744 r8192 d30792 u73728
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 225288
> [    0.000000] Kernel command line: root=/dev/nfs rw rootwait ip=dhcp nfsroot=192.168.10.1:/mnt/rzfive,vers=4,tcp console=ttySC0,115200n8 earlycon=sbi debug loglevel=7 deferred_probe_timeout=5
> [    0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
> [    0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
> [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
> [    0.000000] Virtual kernel memory layout:
> [    0.000000]       fixmap : 0xffffffc6fee00000 - 0xffffffc6ff000000   (2048 kB)
> [    0.000000]       pci io : 0xffffffc6ff000000 - 0xffffffc700000000   (  16 MB)
> [    0.000000]      vmemmap : 0xffffffc700000000 - 0xffffffc800000000   (4096 MB)
> [    0.000000]      vmalloc : 0xffffffc800000000 - 0xffffffd800000000   (  64 GB)
> [    0.000000]      modules : 0xffffffff01369000 - 0xffffffff80000000   (2028 MB)
> [    0.000000]       lowmem : 0xffffffd800000000 - 0xffffffd837e00000   ( 894 MB)
> [    0.000000]       kernel : 0xffffffff80000000 - 0xffffffffffffffff   (2047 MB)
> [    0.000000] Memory: 747812K/915456K available (7394K kernel code, 3746K rwdata, 4096K rodata, 3355K init, 480K bss, 167644K reserved, 0K cma-reserved)
> [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> [    0.000000] rcu: Hierarchical RCU implementation.
> [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1.
> [    0.000000] rcu:     RCU debug extended QS entry/exit.
> [    0.000000]  Tracing variant of Tasks RCU enabled.
> [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
> [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
> [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> [    0.000000] riscv-intc: 64 local interrupts mapped
> [    0.000000] plic: interrupt-controller at 12c00000: mapped 511 interrupts with 1 handlers for 2 contexts.
> [    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
> [    0.000000] riscv-timer: riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
> [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x2c47f4ee7, max_idle_ns: 440795202497 ns
> [    0.000003] sched_clock: 64 bits at 12MHz, resolution 83ns, wraps every 4398046511096ns
> [    0.000242] Console: colour dummy device 80x25
> [    0.000345] Calibrating delay loop (skipped), value calculated using timer frequency.. 24.00 BogoMIPS (lpj=48000)
> [    0.000367] pid_max: default: 32768 minimum: 301
> [    0.000472] LSM: Security Framework initializing
> [    0.000684] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
> [    0.000712] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
> [    0.002601] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    0.003937] cblist_init_generic: Setting adjustable number of callback queues.
> [    0.003956] cblist_init_generic: Setting shift to 0 and lim to 1.
> [    0.004235] riscv: ELF compat mode unsupported
> [    0.004316] ASID allocator using 9 bits (512 entries)
> [    0.004576] rcu: Hierarchical SRCU implementation.
> [    0.004587] rcu:     Max phase no-delay instances is 1000.
> [    0.005204] Detected Renesas RZ/Five r9a07g043 Rev 0
> [    0.005221] EFI services will not be available.
> [    0.005728] smp: Bringing up secondary CPUs ...
> [    0.005740] smp: Brought up 1 node, 1 CPU
> [    0.006644] devtmpfs: initialized
> [    0.013628] DMA: default coherent area is set
> [    0.013648] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
> [    0.013678] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
> [    0.013951] pinctrl core: initialized pinctrl subsystem
> [    0.015869] NET: Registered PF_NETLINK/PF_ROUTE protocol family
> [    0.016359] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
> [    0.016413] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
> [    0.016526] audit: initializing netlink subsys (disabled)
> [    0.017387] thermal_sys: Registered thermal governor 'step_wise'
> [    0.017504] cpuidle: using governor menu
> [    0.033712] audit: type=2000 audit(0.020:1): state=initialized audit_enabled=0 res=1
> [    0.034608] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
> [    0.034623] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
> [    0.038322] SCSI subsystem initialized
> [    0.038641] usbcore: registered new interface driver usbfs
> [    0.038707] usbcore: registered new interface driver hub
> [    0.038766] usbcore: registered new device driver usb
> [    0.039808] Advanced Linux Sound Architecture Driver Initialized.
> [    0.041311] clocksource: Switched to clocksource riscv_clocksource
> [    0.054917] NET: Registered PF_INET protocol family
> [    0.055223] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
> [    0.057347] tcp_listen_portaddr_hash hash table entries: 512 (order: 2, 16384 bytes, linear)
> [    0.057402] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
> [    0.057430] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
> [    0.057523] TCP bind hash table entries: 8192 (order: 7, 524288 bytes, linear)
> [    0.058595] TCP: Hash tables configured (established 8192 bind 8192)
> [    0.058814] UDP hash table entries: 512 (order: 3, 49152 bytes, linear)
> [    0.058951] UDP-Lite hash table entries: 512 (order: 3, 49152 bytes, linear)
> [    0.059394] NET: Registered PF_UNIX/PF_LOCAL protocol family
> [    0.060323] RPC: Registered named UNIX socket transport module.
> [    0.060342] RPC: Registered udp transport module.
> [    0.060348] RPC: Registered tcp transport module.
> [    0.060354] RPC: Registered tcp NFSv4.1 backchannel transport module.
> [    0.069907] workingset: timestamp_bits=46 max_order=18 bucket_order=0
> [    0.094416] NFS: Registering the id_resolver key type
> [    0.094498] Key type id_resolver registered
> [    0.094507] Key type id_legacy registered
> [    0.094665] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
> [    0.094675] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
> [    0.095031] 9p: Installing v9fs 9p2000 file system support
> [    0.095642] NET: Registered PF_ALG protocol family
> [    0.095756] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248)
> [    0.095769] io scheduler mq-deadline registered
> [    0.095776] io scheduler kyber registered
> [    0.211112] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> [    0.213011] SuperH (H)SCI(F) driver initialized
> [    0.213764] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    0.223531] loop: module loaded
> [    0.227640] usbcore: registered new interface driver uas
> [    0.227742] usbcore: registered new interface driver usb-storage
> [    0.228103] mousedev: PS/2 mouse device common for all mice
> [    0.279088] sdhci: Secure Digital Host Controller Interface driver
> [    0.279104] sdhci: Copyright(c) Pierre Ossman
> [    0.279281] sdhci-pltfm: SDHCI platform and OF driver helper
> [    0.279596] usbcore: registered new interface driver usbhid
> [    0.279607] usbhid: USB HID core driver
> [    0.280169] riscv-pmu-sbi: SBI PMU extension is available
> [    0.280214] riscv-pmu-sbi: 16 firmware and 6 hardware counters
> [    0.280225] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available
> [    0.282558] NET: Registered PF_INET6 protocol family
> [    0.284457] Segment Routing with IPv6
> [    0.284537] In-situ OAM (IOAM) with IPv6
> [    0.284639] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
> [    0.285632] NET: Registered PF_PACKET protocol family
> [    0.285879] 9pnet: Installing 9P2000 support
> [    0.286004] Key type dns_resolver registered
> [    0.290080] debug_vm_pgtable: [debug_vm_pgtable         ]: Validating architecture page table helpers
> [    0.305477] gpio-378 (can0_stb): hogged as output/low
> [    0.305517] gpio-379 (can1_stb): hogged as output/low
> [    0.305549] gpio-363 (sd1_pwr_en): hogged as output/high
> [    0.306264] pinctrl-rzg2l 11030000.pinctrl: pinctrl-rzg2l support registered
> [    0.307379] 1004b800.serial: ttySC0 at MMIO 0x1004b800 (irq = 2, base_baud = 0) is a scif
> [    1.169958] printk: console [ttySC0] enabled
> [    1.176321] i2c-riic 10058000.i2c: registered with 100000Hz bus speed
> [    1.185005] i2c-riic 10058400.i2c: registered with 100000Hz bus speed
> [    1.193147] Trying to probe devices needed for running init ...
> [   13.481453] ALSA device list:
> [   13.484433]   No soundcards found.
> [   13.490459] Freeing unused kernel image (initmem) memory: 3352K
> [   13.496415] Run /init as init process
> This is for testing KEXEC!
> mount: mounting /dev/sda1 on /mnt/root failed: No such file or directory
> Dropping to a shell.
> sh: can't access tty; job control turned off
> / #
> / #
> -------------------------------------------------------------------------------
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (6):
>   lib: utils: serial: Add Renesas SCIF driver
>   lib: utils: serial: Add FDT driver for Renesas SCIF
>   lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
>   platform: generic: Add Renesas RZ/Five initial support
>   docs: platform: Add documentation for Renesas RZ/Five SoC
>   platform: generic: Drop root_offset parameter from
>     fw_platform_lookup_special()
>
>  docs/platform/platform.md                  |   5 +
>  docs/platform/renesas-rzfive.md            | 145 +++++++++++++++++++++
>  include/sbi_utils/fdt/fdt_helper.h         |   3 +
>  include/sbi_utils/serial/renesas-scif.h    |  11 ++
>  lib/utils/fdt/fdt_helper.c                 |  11 ++
>  lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
>  lib/utils/serial/Kconfig                   |   9 ++
>  lib/utils/serial/fdt_serial_renesas_scif.c |  31 +++++
>  lib/utils/serial/objects.mk                |   4 +
>  lib/utils/serial/renesas_scif.c            | 116 +++++++++++++++++
>  platform/generic/Kconfig                   |   4 +
>  platform/generic/configs/defconfig         |   2 +
>  platform/generic/platform.c                |   4 +-
>  platform/generic/renesas/rzfive/objects.mk |   8 ++
>  platform/generic/renesas/rzfive/rzfive.c   |  17 +++
>  15 files changed, 370 insertions(+), 3 deletions(-)
>  create mode 100644 docs/platform/renesas-rzfive.md
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
>  create mode 100644 lib/utils/serial/renesas_scif.c
>  create mode 100644 platform/generic/renesas/rzfive/objects.mk
>  create mode 100644 platform/generic/renesas/rzfive/rzfive.c
>
> --
> 2.17.1
>


From prabhakar.csengg at gmail.com  Mon Dec  5 05:10:07 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Mon, 5 Dec 2022 13:10:07 +0000
Subject: [PATCH v3 0/6] Add support for Renesas RZ/Five SoC
In-Reply-To: <CAAhSdy2R2t9QENdi7qn-hx1_3xQMFi5D=cnT9AyL_k485YafBw@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <CAAhSdy2R2t9QENdi7qn-hx1_3xQMFi5D=cnT9AyL_k485YafBw@mail.gmail.com>
Message-ID: <CA+V-a8uR8EuSUGdz773P_U2gzDmQRe458yDTdgU2n4fQkMwUrA@mail.gmail.com>

Hi Anup,

On Mon, Dec 5, 2022 at 12:53 PM Anup Patel <anup at brainfault.org> wrote:
>
> On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> >
> > Hi All,
> >
> > This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
> > is equipped with AX45MP AndesCore). Platform supports DT based probing.
> >
> > Linux support is currently being upstreamed the latest patchset can be
> > found at [0](currently in linux-next, DT bindings can be seen here)
> >
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> >
> > - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> > - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
> >   and is used in a similar manner as compared Andes AE350 [1]
> >   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> > - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
> >
> > Note:
> > - The PMA implementation is still in discussion [1] once its decided
> > corresponding patch to OpenSBI will be added to reserve the memory nodes
> > and vendor specific SBI EXT.
> > - U-boot from BSP release wont work with these patches, it requires additional
> >   patches (happy to share the u-boot branch if anyone wants to test this patchset)
> > - Patches apply on top of [2]
> >
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > [2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/
> >
> > v2->v3
> > * Switched to generic platform
> > * Dropped all vendor specific SBI EXT
> > * Fixed review comments pointed by Bin for SCIF driver
> > * Updated doc
> >
> > RFC->v2
> > * Fixed comments pointed by Xiang W
> > * Included RB tag from Yu Chien Peter Lin for patch #3
> >
> > RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> >
> > Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
> > -----------------------------------------------------------
> > U-Boot SPL 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
> > Trying to boot from NOR
> >
> > OpenSBI v1.1-109-gfa85d48
> >    ____                    _____ ____ _____
> >   / __ \                  / ____|  _ \_   _|
> >  | |  | |_ __   ___ _ __ | (___ | |_) || |
> >  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
> >  | |__| | |_) |  __/ | | |____) | |_) || |_
> >   \____/| .__/ \___|_| |_|_____/|____/_____|
> >         | |
> >         |_|
> >
> > Platform Name             : Renesas SMARC EVK based on r9a07g043f01
> > Platform Features         : medeleg
> > Platform HART Count       : 1
> > Platform IPI Device       : andes_plicsw
> > Platform Timer Device     : andes_plmt @ 12000000Hz
> > Platform Console Device   : renesas_scif
> > Platform HSM Device       : ---
> > Platform PMU Device       : ---
> > Platform Reboot Device    : ---
> > Platform Shutdown Device  : ---
>
> Any plans for a system reboot/shutdown driver for OpenSBI ?
>
Not with the current patchest, but going forward we will.

I need to investigate this (can you please point me to an example for this).

BTW when do you plan to plan for the next OpenSBI release (I'll plan
accordingly to send a v4 for this series).

Cheers,
Prabhakar


From apatel at ventanamicro.com  Mon Dec  5 05:25:44 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Mon, 5 Dec 2022 18:55:44 +0530
Subject: [PATCH v3 0/6] Add support for Renesas RZ/Five SoC
In-Reply-To: <CA+V-a8uR8EuSUGdz773P_U2gzDmQRe458yDTdgU2n4fQkMwUrA@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAAhSdy2R2t9QENdi7qn-hx1_3xQMFi5D=cnT9AyL_k485YafBw@mail.gmail.com> <CA+V-a8uR8EuSUGdz773P_U2gzDmQRe458yDTdgU2n4fQkMwUrA@mail.gmail.com>
Message-ID: <CAK9=C2UFNLemX-k3d_=u8gn_oTfNfPx4b-EgMrV743AV=vqiPw@mail.gmail.com>

On Mon, Dec 5, 2022 at 6:40 PM Lad, Prabhakar
<prabhakar.csengg at gmail.com> wrote:
>
> Hi Anup,
>
> On Mon, Dec 5, 2022 at 12:53 PM Anup Patel <anup at brainfault.org> wrote:
> >
> > On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > Hi All,
> > >
> > > This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
> > > is equipped with AX45MP AndesCore). Platform supports DT based probing.
> > >
> > > Linux support is currently being upstreamed the latest patchset can be
> > > found at [0](currently in linux-next, DT bindings can be seen here)
> > >
> > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> > > - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
> > >   and is used in a similar manner as compared Andes AE350 [1]
> > >   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> > > - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
> > >
> > > Note:
> > > - The PMA implementation is still in discussion [1] once its decided
> > > corresponding patch to OpenSBI will be added to reserve the memory nodes
> > > and vendor specific SBI EXT.
> > > - U-boot from BSP release wont work with these patches, it requires additional
> > >   patches (happy to share the u-boot branch if anyone wants to test this patchset)
> > > - Patches apply on top of [2]
> > >
> > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > > [2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/
> > >
> > > v2->v3
> > > * Switched to generic platform
> > > * Dropped all vendor specific SBI EXT
> > > * Fixed review comments pointed by Bin for SCIF driver
> > > * Updated doc
> > >
> > > RFC->v2
> > > * Fixed comments pointed by Xiang W
> > > * Included RB tag from Yu Chien Peter Lin for patch #3
> > >
> > > RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
> > > -----------------------------------------------------------
> > > U-Boot SPL 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
> > > Trying to boot from NOR
> > >
> > > OpenSBI v1.1-109-gfa85d48
> > >    ____                    _____ ____ _____
> > >   / __ \                  / ____|  _ \_   _|
> > >  | |  | |_ __   ___ _ __ | (___ | |_) || |
> > >  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
> > >  | |__| | |_) |  __/ | | |____) | |_) || |_
> > >   \____/| .__/ \___|_| |_|_____/|____/_____|
> > >         | |
> > >         |_|
> > >
> > > Platform Name             : Renesas SMARC EVK based on r9a07g043f01
> > > Platform Features         : medeleg
> > > Platform HART Count       : 1
> > > Platform IPI Device       : andes_plicsw
> > > Platform Timer Device     : andes_plmt @ 12000000Hz
> > > Platform Console Device   : renesas_scif
> > > Platform HSM Device       : ---
> > > Platform PMU Device       : ---
> > > Platform Reboot Device    : ---
> > > Platform Shutdown Device  : ---
> >
> > Any plans for a system reboot/shutdown driver for OpenSBI ?
> >
> Not with the current patchest, but going forward we will.
>
> I need to investigate this (can you please point me to an example for this).
>
> BTW when do you plan to plan for the next OpenSBI release (I'll plan
> accordingly to send a v4 for this series).

It would be nice if we can conclude this series before the end of next week.

Regards,
Anup

>
> Cheers,
> Prabhakar
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec  5 05:47:31 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 5 Dec 2022 19:17:31 +0530
Subject: [PATCH v3 0/6] Add support for Renesas RZ/Five SoC
In-Reply-To: <CA+V-a8uR8EuSUGdz773P_U2gzDmQRe458yDTdgU2n4fQkMwUrA@mail.gmail.com>
References: <20221130220825.193693-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAAhSdy2R2t9QENdi7qn-hx1_3xQMFi5D=cnT9AyL_k485YafBw@mail.gmail.com> <CA+V-a8uR8EuSUGdz773P_U2gzDmQRe458yDTdgU2n4fQkMwUrA@mail.gmail.com>
Message-ID: <CAAhSdy1Vtt5nArE=Qp2cpW=uBPVpxZqq2qAwR-y8oBYyC2ZnjA@mail.gmail.com>

On Mon, Dec 5, 2022 at 6:40 PM Lad, Prabhakar
<prabhakar.csengg at gmail.com> wrote:
>
> Hi Anup,
>
> On Mon, Dec 5, 2022 at 12:53 PM Anup Patel <anup at brainfault.org> wrote:
> >
> > On Thu, Dec 1, 2022 at 3:38 AM Prabhakar <prabhakar.csengg at gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > >
> > > Hi All,
> > >
> > > This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
> > > is equipped with AX45MP AndesCore). Platform supports DT based probing.
> > >
> > > Linux support is currently being upstreamed the latest patchset can be
> > > found at [0](currently in linux-next, DT bindings can be seen here)
> > >
> > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> > > - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
> > >   and is used in a similar manner as compared Andes AE350 [1]
> > >   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> > > - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
> > >
> > > Note:
> > > - The PMA implementation is still in discussion [1] once its decided
> > > corresponding patch to OpenSBI will be added to reserve the memory nodes
> > > and vendor specific SBI EXT.
> > > - U-boot from BSP release wont work with these patches, it requires additional
> > >   patches (happy to share the u-boot branch if anyone wants to test this patchset)
> > > - Patches apply on top of [2]
> > >
> > > [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > > [2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/
> > >
> > > v2->v3
> > > * Switched to generic platform
> > > * Dropped all vendor specific SBI EXT
> > > * Fixed review comments pointed by Bin for SCIF driver
> > > * Updated doc
> > >
> > > RFC->v2
> > > * Fixed comments pointed by Xiang W
> > > * Included RB tag from Yu Chien Peter Lin for patch #3
> > >
> > > RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
> > > -----------------------------------------------------------
> > > U-Boot SPL 2022.10-00194-g8fe71ee1da (Nov 30 2022 - 17:32:32 +0000)
> > > Trying to boot from NOR
> > >
> > > OpenSBI v1.1-109-gfa85d48
> > >    ____                    _____ ____ _____
> > >   / __ \                  / ____|  _ \_   _|
> > >  | |  | |_ __   ___ _ __ | (___ | |_) || |
> > >  | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
> > >  | |__| | |_) |  __/ | | |____) | |_) || |_
> > >   \____/| .__/ \___|_| |_|_____/|____/_____|
> > >         | |
> > >         |_|
> > >
> > > Platform Name             : Renesas SMARC EVK based on r9a07g043f01
> > > Platform Features         : medeleg
> > > Platform HART Count       : 1
> > > Platform IPI Device       : andes_plicsw
> > > Platform Timer Device     : andes_plmt @ 12000000Hz
> > > Platform Console Device   : renesas_scif
> > > Platform HSM Device       : ---
> > > Platform PMU Device       : ---
> > > Platform Reboot Device    : ---
> > > Platform Shutdown Device  : ---
> >
> > Any plans for a system reboot/shutdown driver for OpenSBI ?
> >
> Not with the current patchest, but going forward we will.
>
> I need to investigate this (can you please point me to an example for this).

You can look at <opensbi>/lib/utils/reset.
This has quite a few drivers.

If you still have questions then email me separately about how
system reboot/shutdown works on your SoC.

Regards,
Anup

>
> BTW when do you plan to plan for the next OpenSBI release (I'll plan
> accordingly to send a v4 for this series).
>
> Cheers,
> Prabhakar


From hchauhan at ventanamicro.com  Mon Dec  5 08:42:31 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Mon,  5 Dec 2022 22:12:31 +0530
Subject: [PATCH] lib: sbi: Synchronize PMP settings with virtual memory system
Message-ID: <20221205164231.170617-1-hchauhan@ventanamicro.com>

As per section 3.7.2 of RISC-V Privileged Specification,
PMP settings must be synchronized with the virtual memory
system after PMP settings have been written.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index dacab1a..5447c52 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -22,6 +22,7 @@
 #include <sbi/sbi_pmu.h>
 #include <sbi/sbi_string.h>
 #include <sbi/sbi_trap.h>
+#include <sbi/sbi_hfence.h>
 
 extern void __sbi_expected_trap(void);
 extern void __sbi_expected_trap_hext(void);
@@ -321,6 +322,27 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 		}
 	}
 
+	/*
+	 * As per section 3.7.2 of privileged specification v1.12,
+	 * virtual address translations can be speculatively performed
+	 * (even before actual access). These, along with PMP traslations,
+	 * can be cached. This can pose a problem with CPU hotplug
+	 * and non-retentive suspend scenario because PMP states are
+	 * not preserved.
+	 * It is advisable to flush the caching structures under such
+	 * conditions.
+	 */
+	if (misa_extension('S')) {
+		__asm__ __volatile__("sfence.vma");
+
+		/*
+		 * If hypervisor mode is supported, flush caching
+		 * structures in guest mode too.
+		 */
+		if (misa_extension('H'))
+			__sbi_hfence_gvma_all();
+	}
+
 	return 0;
 }
 
-- 
2.38.1



From geomatsi at gmail.com  Mon Dec  5 12:34:37 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Mon, 5 Dec 2022 23:34:37 +0300
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <57086abe77447357d6f33cc92f713e2c08860c0b.camel@126.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
 <20221203213929.206429-3-geomatsi@gmail.com>
 <57086abe77447357d6f33cc92f713e2c08860c0b.camel@126.com>
Message-ID: <Y45V3fAIOc9jNGaG@curiosity>

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> > 
> > Software support for triggers consists of the following
> > major components:
> > - U-mode: gdb
> > - S-mode: hardware breakpoints framework in Linux kernel
> > - M-mode: SBI firmware code to handle triggers
> > 
> > SBI Debug Trigger extension proposal has been posted by
> > Anup Patel to lists.riscv.org tech-debug mailing list:
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> > 
> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> > 
> > Initial implementation has the following limitations:
> > - supported triggers: mcontrol, mcontrol6
> > - no support for chained triggers
> > - only build test for RV32
> > 
> Missing Signed-off-by

Thanks for catching, will fix.
 
> Compilation preprocessing too much. It is recommended to process register
> fields by defining some masks, and via INSERT_FIELD and EXTRACT_FIELD.

Indeed, current bitfield/union code looks awkward. I'll try to make it
more comprehensible in the next revision. BTW thanks for mentioning
INSERT/EXTRACT  - I missed them when looking for something suitable
bitops header.

Regards,
Sergey


From atishp at atishpatra.org  Wed Dec  7 01:35:37 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Wed, 7 Dec 2022 01:35:37 -0800
Subject: [PATCH] lib: sbi: Bypass CY and IR bit setting in mcountinhibit
In-Reply-To: <CAPqJEFq-Pm5FUdckyqgqb==Pi88zcdNRcRpKjK89SD6b2+ziFg@mail.gmail.com>
References: <20221116101826.10465-1-eric.lin@sifive.com> <E95DA6B1-DCB9-45D9-BB30-8EC53F2D1596@jrtc27.com>
 <CAOnJCUKi8NSqNgDyKaT9u7w-bPFeMbCM=K6DYTzW+e+3srYfnA@mail.gmail.com> <CAPqJEFq-Pm5FUdckyqgqb==Pi88zcdNRcRpKjK89SD6b2+ziFg@mail.gmail.com>
Message-ID: <CAOnJCUJnUC9uxt3jk2KMyEQ38brMz+K1g8AaPoWMRn_qXnVpuw@mail.gmail.com>

On Thu, Dec 1, 2022 at 11:15 PM Eric Lin <eric.lin at sifive.com> wrote:
>
>
> Hi Atish,
>
> On Fri, Nov 18, 2022 at 7:00 AM Atish Patra <atishp at atishpatra.org> wrote:
>>
>> On Wed, Nov 16, 2022 at 6:57 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>> >
>> > On 16 Nov 2022, at 10:18, Eric Lin <eric.lin at sifive.com> wrote:
>> > >
>> > > CYCLE and INSTRET counters are part of uABI and they were
>> > > re-enable for userspace in Linux riscv pmu driver.
>> > >
>> > > To make these counters increase normally in userspace, we bypass
>> > > CY and IR bit checking when setting mcountinhibit register.
>> > >
>> > > LINK:https://lore.kernel.org/all/20220928131807.30386-1-palmer at rivosinc.com/
>> > > Signed-off-by: Eric Lin <eric.lin at sifive.com>
>> >
>> > If Linux is making SBI calls it doesn?t want then it should stop making
>> > those calls. S-mode requesting CY and IR inhibit bits be set is totally
>> > legitimate in some circumstances, it?s not up to firmware to enforce a
>> > specific S-mode OS policy.
>> >
>>
>> Yes. Start/sop is required when the user is doing perf stat or record
>> for these counters.
>>
>> To increase the CYCLE and INSTRET,
>> pmu_sbi_starting_cpu( in drivers/perf/riscv_pmu_sbi.c)
>> should be modified to stop only the programmable counters. Not all.
>>
> Since CYCLE and INSTRET counters are re-enabled in userspace, user applications will use rdcycle and rdinstert
> pseudoinstruction for performance monitoring.
>
> IMO, when a user uses rdcycle and rdinstert pseudoinstruction to get cycle and instructions count, they would assume
> that CYCLE and INSTRET counters are strictly increasing and no need to initialize in Linux. Is the assumption right?
>

CYCLE & INSTRET is guaranteed to be strictly increasing. The
underlying shadow mcycle/minstret CSR are writable.
In addition to that, mcountinhibit allows these counters to stop.
These are fixed counters but not always running.

> However, if another user uses the perf tool to get cycle and instruction count, the perf framework will start and stop counters
> when events are scheduled in and out. This will make the CYCLE and INSTRET counters not strictly increase and the rdcycle
> and rdinstert results are not what the user expects.
>
> Therefore, I think two places need to modify in Linux riscv pmu driver.
>
> The first one is that when booting, we should only stop programmable counters in pmu_sbi_stop_all().
> The patch is as below:
>  static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
>  {
> +       unsigned long cmask = 0;
>         /*
> -        * No need to check the error because we are disabling all the counters
> +        * No need to check the error because we are disabling programmable counters
>          * which may include counters that are not enabled yet.
>          */
> +       cmask = pmu->cmask & (~(BIT(0) | BIT(2)));
>         sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
> -                 0, pmu->cmask, 0, 0, 0, 0);
> +                 0, cmask, 0, 0, 0, 0);
>
> The second one is that when the user uses the perf stat -e cycles/instructions command, it will stop counters when the event stop.
> We should skip stopping CYCLE and INSTRET counters in pmu_sbi_ctr_stop().
> The patch is as below:
> @@ -446,6 +446,10 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag)
>         struct sbiret ret;
>         struct hw_perf_event *hwc = &event->hw;
>
> +       /* Skip to stop CYCLE and INSTRET counters */
> +       if (hwc->idx == 0 || hwc->idx == 2)
> +               return;
> +

This is wrong as it will break for users who are using perf to monitor
cycle and instret events.

>         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0);
>         if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) &&
>                 flag != SBI_PMU_STOP_FLAG_RESET)
>
> Is this the right way to fix rdcycle and rdinstert increase issue in userspace? Or is there something that I miss?
> Thanks.
>

There are multiple issues when user space tries to read rdcycle and
rdinstret directly.

1. Currently, there is no privilege mode filtering support for
cycle/instret. Thus, counters also report the number of instructions
retired while in S or M mode.
2. The kernel does not take care of context switching. Without context
switch support, an application will most likely read values that are
completely garbage because of the context switch.
3. While a user is reading these counters directly, some other user
may use perf to read these counters as well. In that case, the user
may even see smaller value as perf interface writes to cycle/instret.

Thus, the values read by any user will most likely contain some noise
depending on the number of context switches happening during two
counter reads.
We need more ISA extension support to allow privilege mode filtering
for these counters, counter delegation to S-mode. Some of the topics
were discussed recently during the perf analysis SIG.
Hopefully, we can come up with a coherent solution to address these issues.



> Regards,
> Eric Lin
>
>
>
>>
>> > Jess
>> >
>> > > ---
>> > > lib/sbi/sbi_pmu.c | 4 ++--
>> > > 1 file changed, 2 insertions(+), 2 deletions(-)
>> > >
>> > > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
>> > > index 91d9ccc..28107e5 100644
>> > > --- a/lib/sbi/sbi_pmu.c
>> > > +++ b/lib/sbi/sbi_pmu.c
>> > > @@ -318,7 +318,7 @@ static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update)
>> > >       if (cidx >= num_hw_ctrs || cidx == 1)
>> > >               return SBI_EINVAL;
>> > >
>> > > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
>> > > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
>> > >               goto skip_inhibit_update;
>> > >
>> > >       /*
>> > > @@ -413,7 +413,7 @@ static int pmu_ctr_stop_hw(uint32_t cidx)
>> > >       struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
>> > >       unsigned long mctr_inhbt;
>> > >
>> > > -     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11)
>> > > +     if (sbi_hart_priv_version(scratch) < SBI_HART_PRIV_VER_1_11 || cidx == 0 || cidx == 2)
>> > >               return 0;
>> > >
>> > >       mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT);
>> > > --
>> > > 2.36.1
>> > >
>> > >
>> > > --
>> > > opensbi mailing list
>> > > opensbi at lists.infradead.org
>> > > http://lists.infradead.org/mailman/listinfo/opensbi
>> >
>> >
>> > --
>> > opensbi mailing list
>> > opensbi at lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/opensbi
>>
>>
>>
>> --
>> Regards,
>> Atish



--
Regards,
Atish


From heinrich.schuchardt at canonical.com  Wed Dec  7 06:07:49 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Wed,  7 Dec 2022 15:07:49 +0100
Subject: [PATCH 1/3] lib: fix is_region_valid()
In-Reply-To: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221207140751.9135-2-heinrich.schuchardt@canonical.com>

For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.

Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/sbi/sbi_domain.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3302213..52ae1a1 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -146,11 +146,12 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 	if (reg->order < 3 || __riscv_xlen < reg->order)
 		return FALSE;
 
-	if (reg->order == __riscv_xlen && reg->base != 0)
-		return FALSE;
-
-	if (reg->base & (BIT(reg->order) - 1))
+	if (reg->order == __riscv_xlen) {
+		if (reg->base != 0)
+			return FALSE;
+	} else if (reg->base & (BIT(reg->order) - 1)) {
 		return FALSE;
+	}
 
 	return TRUE;
 }
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 06:07:50 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Wed,  7 Dec 2022 15:07:50 +0100
Subject: [PATCH 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221207140751.9135-3-heinrich.schuchardt@canonical.com>

If fdt_getprop() returns NULL, this indicates an error. In this case lenp
is set to an error code. But even if lenp = 0 we should not continue.

If fdt_getprop() returns a wider value than we expect this is a separate
error condition.

In both cases the device-tree is invalid.

Addresses-Coverity-ID: 1529703 ("Dereference after null check")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/fdt/fdt_domain.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index bd0eec3..6051025 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 
 	/* Read "base" DT property */
 	val = fdt_getprop(fdt, region_offset, "base", &len);
-	if (!val && len >= 8)
+	if (!val || len >= 8)
 		return SBI_EINVAL;
 	val64 = fdt32_to_cpu(val[0]);
 	val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
@@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 
 	/* Read "order" DT property */
 	val = fdt_getprop(fdt, region_offset, "order", &len);
-	if (!val && len >= 4)
+	if (!val || len >= 4)
 		return SBI_EINVAL;
 	val32 = fdt32_to_cpu(*val);
 	if (val32 < 3 || __riscv_xlen < val32)
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 06:07:51 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Wed,  7 Dec 2022 15:07:51 +0100
Subject: [PATCH 3/3] lib: fix irqchip_plic_update_hartid_table
In-Reply-To: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221207140751.9135-4-heinrich.schuchardt@canonical.com>

After determining cpu_offset we have to check this value.

Addresses-Coverity-ID: 1529706 ("Logically dead code")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..fe08836 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -86,7 +86,7 @@ static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
 			continue;
 
 		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
-		if (cpu_intc_offset < 0)
+		if (cpu_offset < 0)
 			continue;
 
 		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 06:07:48 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Wed,  7 Dec 2022 15:07:48 +0100
Subject: [PATCH 0/3] lib: fix fdt functions
Message-ID: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>

Fix library device-tree library functions.

The problems were indicated by Coverity. Details can be seen at
https://scan.coverity.com/projects/opensbi/view_defects

Heinrich Schuchardt (3):
  lib: fix is_region_valid()
  lib: fix __fdt_parse_region()
  lib: fix irqchip_plic_update_hartid_table

 lib/sbi/sbi_domain.c                 | 9 +++++----
 lib/utils/fdt/fdt_domain.c           | 4 ++--
 lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

-- 
2.37.2



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:14:19 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:14:19 +0000
Subject: [PATCH] platform: generic: Make use of fdt_match_node()
Message-ID: <20221207161419.10259-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

It makes sense to use fdt_match_node() instead of fdt_find_match()
in fw_platform_lookup_special() as we already have the start offset
to search from.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
Based on the feedback provided by Anup [0].

[0] https://patchwork.ozlabs.org/project/opensbi/patch/20221130220825.193693-7-prabhakar.mahadev-lad.rj at bp.renesas.com/#3015759
---
 platform/generic/platform.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 595b0fd..bfe15f0 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -34,17 +34,17 @@ static const struct fdt_match *generic_plat_match = NULL;
 
 static void fw_platform_lookup_special(void *fdt, int root_offset)
 {
-	int pos, noff;
 	const struct platform_override *plat;
 	const struct fdt_match *match;
+	int pos;
 
 	for (pos = 0; pos < platform_override_modules_size; pos++) {
 		plat = platform_override_modules[pos];
 		if (!plat->match_table)
 			continue;
 
-		noff = fdt_find_match(fdt, -1, plat->match_table, &match);
-		if (noff < 0)
+		match = fdt_match_node(fdt, root_offset, plat->match_table);
+		if (!match)
 			continue;
 
 		generic_plat = plat;
-- 
2.17.1



From atishp at atishpatra.org  Wed Dec  7 08:31:11 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Wed, 7 Dec 2022 08:31:11 -0800
Subject: [PATCH 3/3] lib: fix irqchip_plic_update_hartid_table
In-Reply-To: <20221207140751.9135-4-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com> <20221207140751.9135-4-heinrich.schuchardt@canonical.com>
Message-ID: <CAOnJCUL2AHfUb3L52=VTtwK6H2e+XWt5adHShMPQ6C0RsTNSGg@mail.gmail.com>

On Wed, Dec 7, 2022 at 6:08 AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> After determining cpu_offset we have to check this value.
>
> Addresses-Coverity-ID: 1529706 ("Logically dead code")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
>  lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..fe08836 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -86,7 +86,7 @@ static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
>                         continue;
>
>                 cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -               if (cpu_intc_offset < 0)
> +               if (cpu_offset < 0)
>                         continue;
>
>                 err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> --
> 2.37.2
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:28 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:28 +0000
Subject: [PATCH v4 0/5]  Add support for Renesas RZ/Five SoC
Message-ID: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
is equipped with AX45MP AndesCore). Platform supports DT based probing.

Linux support is currently being upstreamed the latest patchset can be
found at [0](currently in linux-next, DT bindings can be seen here)

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

- PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
- PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
  and is used in a similar manner as compared Andes AE350 [1]
  [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
- SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79

Note:
- The PMA implementation is still in discussion [1] once its decided
corresponding patch to OpenSBI will be added to reserve the memory nodes
and vendor specific SBI EXT.
- U-boot from BSP release wont work with these patches, it requires additional
  patches (happy to share the u-boot branch if anyone wants to test this patchset)
- Patches apply on top of [2]

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
[2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/

v3->v4
* Included RB tags
* Updated doc
* Sorted compatible string list
* Fixed minor issues related to scif driver

v2->v3
* Switched to generic platform
* Dropped all vendor specific SBI EXT
* Fixed review comments pointed by Bin for SCIF driver
* Updated doc

RFC->v2
* Fixed comments pointed by Xiang W
* Included RB tag from Yu Chien Peter Lin for patch #3

RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

Below are the logs for U-Boot (2022.10), OpenSBI and Linux:
-----------------------------------------------------------
U-Boot SPL 2022.10-00195-g1403538afc (Dec 07 2022 - 10:00:01 +0000)
Trying to boot from NOR

OpenSBI v1.1-112-g5066f28
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : Renesas SMARC EVK based on r9a07g043f01
Platform Features         : medeleg
Platform HART Count       : 1
Platform IPI Device       : andes_plicsw
Platform Timer Device     : andes_plmt @ 12000000Hz
Platform Console Device   : renesas_scif
Platform HSM Device       : ---
Platform PMU Device       : ---
Platform Reboot Device    : ---
Platform Shutdown Device  : ---
Firmware Base             : 0x44000000
Firmware Size             : 212 KB
Runtime SBI Version       : 1.0

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x00000000110c0000-0x00000000110fffff (I,R)
Domain0 Region01          : 0x0000000011180000-0x00000000111bffff (I,R)
Domain0 Region02          : 0x0000000044000000-0x000000004403ffff ()
Domain0 Region03          : 0x0000000011100000-0x000000001117ffff (I,R)
Domain0 Region04          : 0x0000000013000000-0x00000000133fffff (I)
Domain0 Region05          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000050000000
Domain0 Next Arg1         : 0x00000000500be0c0
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART Priv Version    : v1.11
Boot HART Base ISA        : rv64imafdcnx
Boot HART ISA Extensions  : none
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 8
Boot HART PMP Address Bits: 36
Boot HART MHPM Count      : 4
Boot HART MIDELEG         : 0x0000000000000222
Boot HART MEDELEG         : 0x000000000000b109


U-Boot 2022.10-00195-g1403538afc (Dec 07 2022 - 10:00:01 +0000)

CPU:   rv64imafdc
Model: Renesas SMARC EVK based on r9a07g043f01
DRAM:  896 MiB
SW_ET0_EN: OFFCore:  30 devices, 18 uclasses, devicetree: separate
MMC:   sd at 11c00000: 0, sd at 11c10000: 1
Loading Environment from MMC... OK
In:    serial at 1004b800
Out:   serial at 1004b800
Err:   serial at 1004b800
Net:   eth0: ethernet at 11c30000
Hit any key to stop autoboot:  0
=>
-----------------------------------------------------------------------------------

Cheers,
Prabhakar

Lad Prabhakar (5):
  lib: utils: serial: Add Renesas SCIF driver
  lib: utils: serial: Add FDT driver for Renesas SCIF
  lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
  platform: generic: Add Renesas RZ/Five initial support
  docs: platform: Add documentation for Renesas RZ/Five SoC

 docs/platform/platform.md                  |   5 +
 docs/platform/renesas-rzfive.md            | 160 +++++++++++++++++++++
 include/sbi_utils/fdt/fdt_helper.h         |   3 +
 include/sbi_utils/serial/renesas-scif.h    |  11 ++
 lib/utils/fdt/fdt_helper.c                 |  11 ++
 lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
 lib/utils/serial/Kconfig                   |   9 ++
 lib/utils/serial/fdt_serial_renesas_scif.c |  31 ++++
 lib/utils/serial/objects.mk                |   4 +
 lib/utils/serial/renesas_scif.c            | 116 +++++++++++++++
 platform/generic/Kconfig                   |   4 +
 platform/generic/configs/defconfig         |   2 +
 platform/generic/renesas/rzfive/objects.mk |   8 ++
 platform/generic/renesas/rzfive/rzfive.c   |  17 +++
 14 files changed, 383 insertions(+), 1 deletion(-)
 create mode 100644 docs/platform/renesas-rzfive.md
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
 create mode 100644 lib/utils/serial/renesas_scif.c
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:29 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:29 +0000
Subject: [PATCH v4 1/5] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221207163233.10656-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
<takeki.hamada.ak at bp.renesas.com>
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v3->v4
* Dropped returning from void func
* Dropped unnecessary volatile variable

v2->v3
* Fixed review comments pointed by Bin

RFC->v2
* Fixed comments pointed by Xiang W
---
 include/sbi_utils/serial/renesas-scif.h |  11 +++
 lib/utils/serial/Kconfig                |   4 +
 lib/utils/serial/objects.mk             |   1 +
 lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
 4 files changed, 132 insertions(+)
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/renesas_scif.c

diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
new file mode 100644
index 0000000..0002a1a
--- /dev/null
+++ b/include/sbi_utils/serial/renesas-scif.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#ifndef __SERIAL_RENESAS_SCIF_H__
+#define __SERIAL_RENESAS_SCIF_H__
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif /* __SERIAL_RENESAS_SCIF_H__ */
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index da549a7..f6ed803 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -59,6 +59,10 @@ config SERIAL_GAISLER
 	bool "Gaisler UART support"
 	default n
 
+config SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF support"
+	default n
+
 config SERIAL_SHAKTI
 	bool "Shakti UART support"
 	default n
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 98f3f9a..6520424 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
 
 libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
+libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
 libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
new file mode 100644
index 0000000..cbe9db4
--- /dev/null
+++ b/lib/utils/serial/renesas_scif.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_timer.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+/* clang-format off */
+
+#define SCIF_REG_SMR		0x0
+#define SCIF_REG_BRR		0x2
+#define SCIF_REG_SCR		0x4
+#define SCIF_REG_FTDR		0x6
+#define SCIF_REG_FSR		0x8
+#define SCIF_REG_FCR		0xc
+#define SCIF_REG_LSR		0x12
+#define SCIF_REG_SEMR		0x14
+
+#define SCIF_FCR_RFRST		0x2 /* Reset assert receive-FIFO (bit[1]) */
+#define SCIF_FCR_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2]) */
+
+#define SCIF_FCR_RST_ASSRT_RFTF	(SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
+#define SCIF_FCR_RST_NGATE_RFTF	0x0 /* Reset negate tx-FIFO & rx-FIFO */
+
+#define SCIF_SCR_RE		0x10 /* Enable receive (bit[4]) */
+#define SCIF_SCR_TE		0x20 /* Enable transmit(bit[5]) */
+#define SCIF_SCR_RCV_TRN_EN	(SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
+#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
+
+#define SCIF_FSR_ER		0x80 /* Receive error flag */
+#define SCIF_FSR_TEND		0x40 /* Transmit End Flag */
+#define SCIF_FSR_TDFE		0x20 /* Transmit FIFO Data Empty Flag */
+#define SCIF_FSR_BRK		0x10 /* Detect break flag */
+#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
+
+#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
+
+#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
+
+#define SCIF_REG_8BIT(reg)	((reg == SCIF_REG_BRR) || \
+				 (reg == SCIF_REG_FTDR) || \
+				 (reg == SCIF_REG_SEMR))
+
+#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
+
+/* clang-format on */
+
+static volatile char *scif_base;
+
+static u32 get_reg(u32 offset)
+{
+	if (SCIF_REG_8BIT(offset))
+		return readb(scif_base + offset);
+
+	return readw(scif_base + offset);
+}
+
+static void set_reg(u32 offset, u32 val)
+{
+	if (SCIF_REG_8BIT(offset))
+		writeb(val, scif_base + offset);
+	else
+		writew(val, scif_base + offset);
+}
+
+static void renesas_scif_putc(char ch)
+{
+	uint16_t reg;
+
+	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
+		;
+
+	set_reg(SCIF_REG_FTDR, ch);
+	reg = get_reg(SCIF_REG_FSR);
+	reg &= ~SCIF_FSR_TXD_CHK;
+	set_reg(SCIF_REG_FSR, reg);
+}
+
+static struct sbi_console_device renesas_scif_console = {
+	.name		= "renesas_scif",
+	.console_putc	= renesas_scif_putc,
+};
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
+{
+	uint16_t data16;
+
+	scif_base = (volatile char *)base;
+
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
+
+	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
+	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
+
+	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
+	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
+
+	set_reg(SCIF_REG_SCR, 0x0);
+
+	set_reg(SCIF_REG_SMR, 0x0);
+
+	data16 = get_reg(SCIF_REG_SEMR);
+	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
+	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
+
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
+
+	sbi_console_set_device(&renesas_scif_console);
+
+	return 0;
+}
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:30 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:30 +0000
Subject: [PATCH v4 2/5] lib: utils: serial: Add FDT driver for Renesas SCIF
In-Reply-To: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221207163233.10656-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial at 1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = <0 0x1004b800 0 0x400>;
                    interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
                                 <414 IRQ_TYPE_LEVEL_HIGH>,
                                 <415 IRQ_TYPE_LEVEL_HIGH>,
                                 <413 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
                    clock-names = "fck";
                    power-domains = <&cpg>;
                    resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
v3->v4
* Included RB tag

v2->v3
* No change

RFC->v2
* Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and
  DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros.

DT binding [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80
---
 include/sbi_utils/fdt/fdt_helper.h         |  3 +++
 lib/utils/fdt/fdt_helper.c                 | 11 ++++++++
 lib/utils/serial/Kconfig                   |  5 ++++
 lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++
 lib/utils/serial/objects.mk                |  3 +++
 5 files changed, 53 insertions(+)
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c

diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
index c39f77a..09f3095 100644
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
 int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 				struct platform_uart_data *uart);
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart);
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);
 
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index d4b38dc..48bc2fe 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -23,6 +23,9 @@
 #define DEFAULT_UART_REG_IO_WIDTH	1
 #define DEFAULT_UART_REG_OFFSET		0
 
+#define DEFAULT_RENESAS_SCIF_FREQ		100000000
+#define DEFAULT_RENESAS_SCIF_BAUD		115200
+
 #define DEFAULT_SIFIVE_UART_FREQ		0
 #define DEFAULT_SIFIVE_UART_BAUD		115200
 
@@ -355,6 +358,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 					DEFAULT_UART_BAUD);
 }
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart)
+{
+	return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
+					  DEFAULT_RENESAS_SCIF_FREQ,
+					  DEFAULT_RENESAS_SCIF_BAUD);
+}
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart)
 {
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index f6ed803..e3589ca 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF
 	select SYS_HTIF
 	default n
 
+config FDT_SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF FDT driver"
+	select SERIAL_RENESAS_SCIF
+	default n
+
 config FDT_SERIAL_SHAKTI
 	bool "Shakti UART FDT driver"
 	select SERIAL_SHAKTI
diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c
new file mode 100644
index 0000000..c331ca1
--- /dev/null
+++ b/lib/utils/serial/fdt_serial_renesas_scif.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+static int serial_renesas_scif_init(void *fdt, int nodeoff,
+				    const struct fdt_match *match)
+{
+	struct platform_uart_data uart = { 0 };
+	int ret;
+
+	ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart);
+	if (ret)
+		return ret;
+
+	return renesas_scif_init(uart.addr, uart.freq, uart.baud);
+}
+
+static const struct fdt_match serial_renesas_scif_match[] = {
+	{ .compatible = "renesas,scif-r9a07g043" },
+	{ /* sentinel */ }
+};
+
+struct fdt_serial fdt_serial_renesas_scif = {
+	.match_table = serial_renesas_scif_match,
+	.init = serial_renesas_scif_init
+};
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 6520424..1e6bd2e 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o
 
+carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif
+libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o
+
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o
 
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:31 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:31 +0000
Subject: [PATCH v4 3/5] lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
In-Reply-To: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221207163233.10656-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.

While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.

dts example (Single-core AX45MP):

    soc: soc {
          ....
          plic: interrupt-controller at 12c00000 {
              compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
              #interrupt-cells = <2>;
              #address-cells = <0>;
              riscv,ndev = <511>;
              interrupt-controller;
              reg = <0x0 0x12c00000 0 0x400000>;
              clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
              power-domains = <&cpg>;
              resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
              interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
          };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
v3->v4
* Sorted compatible string list

v2->v3
* Included RB tags

RFC->v2
* No change

DT binding [0]
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..c0242ac 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -159,11 +159,12 @@ void thead_plic_restore(void)
 }
 
 static const struct fdt_match irqchip_plic_match[] = {
+	{ .compatible = "andestech,nceplic100" },
 	{ .compatible = "riscv,plic0" },
 	{ .compatible = "sifive,plic-1.0.0" },
 	{ .compatible = "thead,c900-plic",
 	  .data = thead_plic_plat_init },
-	{ },
+	{ /* sentinel */ }
 };
 
 struct fdt_irqchip fdt_irqchip_plic = {
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:32 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:32 +0000
Subject: [PATCH v4 4/5] platform: generic: Add Renesas RZ/Five initial support
In-Reply-To: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221207163233.10656-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
v3->v4
* Replaced "renesas,r9a07g043" -> "renesas,r9a07g043f01"
* Included RB tag

v2->v3
* New patch
---
 platform/generic/Kconfig                   |  4 ++++
 platform/generic/configs/defconfig         |  2 ++
 platform/generic/renesas/rzfive/objects.mk |  8 ++++++++
 platform/generic/renesas/rzfive/rzfive.c   | 17 +++++++++++++++++
 4 files changed, 31 insertions(+)
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 4b5d2cd..62c7a2d 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -32,6 +32,10 @@ config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
 	default n
 
+config PLATFORM_RENESAS_RZFIVE
+	bool "Renesas RZ/Five support"
+	default n
+
 config PLATFORM_SIFIVE_FU540
 	bool "SiFive FU540 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 2eaeeb7..47fca95 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -1,5 +1,6 @@
 CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
+CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
 CONFIG_FDT_GPIO=y
@@ -24,6 +25,7 @@ CONFIG_FDT_SERIAL=y
 CONFIG_FDT_SERIAL_CADENCE=y
 CONFIG_FDT_SERIAL_GAISLER=y
 CONFIG_FDT_SERIAL_HTIF=y
+CONFIG_FDT_SERIAL_RENESAS_SCIF=y
 CONFIG_FDT_SERIAL_SHAKTI=y
 CONFIG_FDT_SERIAL_SIFIVE=y
 CONFIG_FDT_SERIAL_LITEX=y
diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
new file mode 100644
index 0000000..2e7e37f
--- /dev/null
+++ b/platform/generic/renesas/rzfive/objects.mk
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2022 Renesas Electronics Corp.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
+platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
new file mode 100644
index 0000000..ca182e3
--- /dev/null
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static const struct fdt_match renesas_rzfive_match[] = {
+	{ .compatible = "renesas,r9a07g043f01" },
+	{ /* sentinel */ }
+};
+
+const struct platform_override renesas_rzfive = {
+	.match_table = renesas_rzfive_match,
+};
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Wed Dec  7 08:32:33 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Wed,  7 Dec 2022 16:32:33 +0000
Subject: [PATCH v4 5/5] docs: platform: Add documentation for Renesas RZ/Five SoC
In-Reply-To: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221207163233.10656-6-prabhakar.mahadev-lad.rj@bp.renesas.com>

This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v3->v4
* Added complete list of IP blocks

v2->v3
* Updated doc with new build command

RFC->v2
* Updated doc
---
 docs/platform/platform.md       |   5 +
 docs/platform/renesas-rzfive.md | 160 ++++++++++++++++++++++++++++++++
 2 files changed, 165 insertions(+)
 create mode 100644 docs/platform/renesas-rzfive.md

diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index f291931..4504d87 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
 
+* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
+  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
+  be found in the file *[renesas-rzfive.md]*.
+
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *objects.mk*,
@@ -54,3 +58,4 @@ comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
+[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
new file mode 100644
index 0000000..41edf36
--- /dev/null
+++ b/docs/platform/renesas-rzfive.md
@@ -0,0 +1,160 @@
+Renesas RZ/Five SoC (R9A07G043F) Platform
+=========================================
+The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
+1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
+- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits
+- System RAM (RAM of 128 Kbytes (ECC))
+- SPI Multi I/O Bus Controller 1ch
+- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch
+- Serial Sound Interface (SSI) 4ch
+- Sampling Rate Converter (SRC) 1ch
+- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only)
+- Gigabit Ethernet Interface (GbE) 2ch
+- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant)
+- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits ? 8 channels, 32 bits ? 1 channel)
+- Port Output Enable 3 (POE3)
+- Watchdog Timer (WDT) 1ch
+- General Timer (GTM) 3ch (32bits)
+- I2C Bus Interface (I2C) 4ch
+- Serial Communication Interface with FIFO (SCIFA) 5ch
+- Serial Communication Interface (SCI) 2ch
+- Renesas Serial Peripheral Interface (RSPI) 3ch
+- A/D Converter (ADC) 2ch
+making it ideal for applications such as entry-class social infrastructure
+gateway control and industrial gateway control. More details can be found at
+below link [0].
+
+[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=generic* parameter to the top level make command.
+
+Platform Options
+----------------
+
+The Renesas RZ/Five platform does not have any platform-specific options.
+
+Building Renesas RZ/Five Platform
+---------------------------------
+
+```
+make PLATFORM=generic
+```
+
+DTS Example: (RZ/Five AX45MP)
+-----------------------------
+
+```
+	compatible = "renesas,r9a07g043";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <12000000>;
+
+		cpu0: cpu at 0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ranges;
+
+		scif0: serial at 1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller at 11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller at 11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl at 11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plmt0: plmt0 at 110c0000 {
+			compatible = "andestech,plmt0", "riscv,plmt0";
+			reg = <0x0 0x110c0000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller at 12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <511>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0x0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+
+		plicsw: interrupt-controller at 13000000 {
+			compatible = "andestech,plicsw";
+			reg = <0x0 0x13000000 0x0 0x400000>;
+			interrupts-extended = <&cpu0_intc 3>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+		};
+	};
+```
-- 
2.17.1



From wxjstz at 126.com  Wed Dec  7 08:45:41 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 00:45:41 +0800
Subject: [PATCH 1/3] lib: fix is_region_valid()
In-Reply-To: <20221207140751.9135-2-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
	 <20221207140751.9135-2-heinrich.schuchardt@canonical.com>
Message-ID: <872b8692141f26a7cb02eeed034dfa55b091b451.camel@126.com>

? 2022-12-07???? 15:07 +0100?Heinrich Schuchardt???
> For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.
> 
> Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> ?lib/sbi/sbi_domain.c | 9 +++++----
> ?1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3302213..52ae1a1 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -146,11 +146,12 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
> ????????if (reg->order < 3 || __riscv_xlen < reg->order)
> ????????????????return FALSE;
> ?
> -???????if (reg->order == __riscv_xlen && reg->base != 0)
> -???????????????return FALSE;
> -
> -???????if (reg->base & (BIT(reg->order) - 1))
> +???????if (reg->order == __riscv_xlen) {
> +???????????????if (reg->base != 0)
> +???????????????????????return FALSE;
> +???????} else if (reg->base & (BIT(reg->order) - 1)) {
> ????????????????return FALSE;
> +???????}
> ?
> ????????return TRUE;
> ?}
> -- 
> 2.37.2
> 
> 
suggestion?

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3302213..3205595 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -149,7 +149,7 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
        if (reg->order == __riscv_xlen && reg->base != 0)
                return FALSE;
 
-       if (reg->base & (BIT(reg->order) - 1))
+       if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
                return FALSE;
 
        return TRUE;

Regards,
Xiang W



From atishp at atishpatra.org  Wed Dec  7 08:50:11 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Wed, 7 Dec 2022 08:50:11 -0800
Subject: [PATCH 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221207140751.9135-3-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com> <20221207140751.9135-3-heinrich.schuchardt@canonical.com>
Message-ID: <CAOnJCUJRs04aDKXFYO6PrwYoQoeZqB=S7Aa-J3qrcgQ-0_PpUw@mail.gmail.com>

On Wed, Dec 7, 2022 at 6:08 AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> If fdt_getprop() returns NULL, this indicates an error. In this case lenp
> is set to an error code. But even if lenp = 0 we should not continue.
>
> If fdt_getprop() returns a wider value than we expect this is a separate
> error condition.
>
> In both cases the device-tree is invalid.
>
> Addresses-Coverity-ID: 1529703 ("Dereference after null check")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
>  lib/utils/fdt/fdt_domain.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
> index bd0eec3..6051025 100644
> --- a/lib/utils/fdt/fdt_domain.c
> +++ b/lib/utils/fdt/fdt_domain.c
> @@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>
>         /* Read "base" DT property */
>         val = fdt_getprop(fdt, region_offset, "base", &len);
> -       if (!val && len >= 8)
> +       if (!val || len >= 8)
>                 return SBI_EINVAL;
>         val64 = fdt32_to_cpu(val[0]);
>         val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
> @@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>
>         /* Read "order" DT property */
>         val = fdt_getprop(fdt, region_offset, "order", &len);
> -       if (!val && len >= 4)
> +       if (!val || len >= 4)
>                 return SBI_EINVAL;
>         val32 = fdt32_to_cpu(*val);
>         if (val32 < 3 || __riscv_xlen < val32)
> --
> 2.37.2
>

Reviewed-by: Atish Patra <atishp at rivosinc.com>

-- 
Regards,
Atish


From wxjstz at 126.com  Wed Dec  7 09:01:03 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 01:01:03 +0800
Subject: [PATCH 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221207140751.9135-3-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
	 <20221207140751.9135-3-heinrich.schuchardt@canonical.com>
Message-ID: <b83632a64b539d45328e392999a8b58d99f2e642.camel@126.com>

? 2022-12-07???? 15:07 +0100?Heinrich Schuchardt???
> If fdt_getprop() returns NULL, this indicates an error. In this case lenp
> is set to an error code. But even if lenp = 0 we should not continue.
> 
> If fdt_getprop() returns a wider value than we expect this is a separate
> error condition.
> 
> In both cases the device-tree is invalid.
> 
> Addresses-Coverity-ID: 1529703 ("Dereference after null check")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
> ?lib/utils/fdt/fdt_domain.c | 4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
> index bd0eec3..6051025 100644
> --- a/lib/utils/fdt/fdt_domain.c
> +++ b/lib/utils/fdt/fdt_domain.c
> @@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
> ?
> ????????/* Read "base" DT property */
> ????????val = fdt_getprop(fdt, region_offset, "base", &len);
> -???????if (!val && len >= 8)
> +???????if (!val || len >= 8)
When len is less than 8, the complete val64 cannot be read, and it can
only be equal to 8 here, so it should be modified as follows
          if (!val || len != 8)
> ????????????????return SBI_EINVAL;
> ????????val64 = fdt32_to_cpu(val[0]);
> ????????val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
> @@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
> ?
> ????????/* Read "order" DT property */
> ????????val = fdt_getprop(fdt, region_offset, "order", &len);
> -???????if (!val && len >= 4)
> +???????if (!val || len >= 4)
When len is less than 4, the complete val32 cannot be read, and it can
only be equal to 4 here, so it should be modified as follows
           if (!val || len != 4)
> ????????????????return SBI_EINVAL;
> ????????val32 = fdt32_to_cpu(*val);
> ????????if (val32 < 3 || __riscv_xlen < val32)
> -- 
> 2.37.2
> 
> 
Regards,
Xiang W



From wxjstz at 126.com  Wed Dec  7 09:02:02 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 01:02:02 +0800
Subject: [PATCH 3/3] lib: fix irqchip_plic_update_hartid_table
In-Reply-To: <20221207140751.9135-4-heinrich.schuchardt@canonical.com>
References: <20221207140751.9135-1-heinrich.schuchardt@canonical.com>
	 <20221207140751.9135-4-heinrich.schuchardt@canonical.com>
Message-ID: <ac369b610b6b2d385ee31efb84b2a5dc087a7beb.camel@126.com>

? 2022-12-07???? 15:07 +0100?Heinrich Schuchardt???
> After determining cpu_offset we have to check this value.
> 
> Addresses-Coverity-ID: 1529706 ("Logically dead code")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..fe08836 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -86,7 +86,7 @@ static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
> ????????????????????????continue;
> ?
> ????????????????cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -???????????????if (cpu_intc_offset < 0)
> +???????????????if (cpu_offset < 0)
> ????????????????????????continue;
> ?
> ????????????????err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> -- 
> 2.37.2
> 
> 




From wxjstz at 126.com  Wed Dec  7 09:12:49 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu,  8 Dec 2022 01:12:49 +0800
Subject: [PATCH] lib: utils/fdt: Add full valid detection for __fdt_parse_region
Message-ID: <20221207171249.1097169-1-wxjstz@126.com>

The original code only detects region->order, and a certain relationship
needs to be satisfied between region->order and region->base. This patch
detects whether the region in fdt is valid through is_region_valid

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/utils/fdt/fdt_domain.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index bd0eec3..30a40dc 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -257,8 +257,6 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 	if (!val && len >= 4)
 		return SBI_EINVAL;
 	val32 = fdt32_to_cpu(*val);
-	if (val32 < 3 || __riscv_xlen < val32)
-		return SBI_EINVAL;
 	region->order = val32;
 
 	/* Read "mmio" DT property */
@@ -266,6 +264,9 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 	if (fdt_get_property(fdt, region_offset, "mmio", NULL))
 		region->flags |= SBI_DOMAIN_MEMREGION_MMIO;
 
+	if(!is_region_valid(region))
+		return SBI_EINVAL;
+
 	(*region_count)++;
 
 	return 0;
-- 
2.30.2



From wxjstz at 126.com  Wed Dec  7 09:36:44 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu,  8 Dec 2022 01:36:44 +0800
Subject: [PATCH v2] lib: utils/fdt: Add full valid detection for __fdt_parse_region
Message-ID: <20221207173644.1106040-1-wxjstz@126.com>

The original code only detects region->order, and a certain relationship
needs to be satisfied between region->order and region->base. This patch
detects whether the region in fdt is valid through sbi_is_region_valid

Signed-off-by: Xiang W <wxjstz at 126.com>
---
REF -> v2
* is_region_valid is local function, change it public and rename
  sbi_is_region_valid
---
 include/sbi/sbi_domain.h   | 7 +++++++
 lib/sbi/sbi_domain.c       | 4 ++--
 lib/utils/fdt/fdt_domain.c | 5 +++--
 3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..fdd73a9 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -109,6 +109,13 @@ extern struct sbi_domain *domidx_to_domain_table[];
 #define sbi_domain_for_each_memregion(__d, __r) \
 	for ((__r) = (__d)->regions; (__r)->order; (__r)++)
 
+/**
+ * Check if sbi_domain_memregion is valid
+ * @param reg pointrt to the sbi_domain_memregion that needs to be check
+ * @return True if reg is vaild sbi_domain_memregion
+*/
+bool sbi_is_region_valid(const struct sbi_domain_memregion *reg);
+
 /**
  * Check whether given HART is assigned to specified domain
  * @param dom pointer to domain
diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3302213..08f0ea6 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -141,7 +141,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 }
 
 /* Check if region complies with constraints */
-static bool is_region_valid(const struct sbi_domain_memregion *reg)
+bool sbi_is_region_valid(const struct sbi_domain_memregion *reg)
 {
 	if (reg->order < 3 || __riscv_xlen < reg->order)
 		return FALSE;
@@ -226,7 +226,7 @@ static int sanitize_domain(const struct sbi_platform *plat,
 		return SBI_EINVAL;
 	}
 	sbi_domain_for_each_memregion(dom, reg) {
-		if (!is_region_valid(reg)) {
+		if (!sbi_is_region_valid(reg)) {
 			sbi_printf("%s: %s has invalid region base=0x%lx "
 				   "order=%lu flags=0x%lx\n", __func__,
 				   dom->name, reg->base, reg->order,
diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index bd0eec3..49908f5 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -257,8 +257,6 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 	if (!val && len >= 4)
 		return SBI_EINVAL;
 	val32 = fdt32_to_cpu(*val);
-	if (val32 < 3 || __riscv_xlen < val32)
-		return SBI_EINVAL;
 	region->order = val32;
 
 	/* Read "mmio" DT property */
@@ -266,6 +264,9 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 	if (fdt_get_property(fdt, region_offset, "mmio", NULL))
 		region->flags |= SBI_DOMAIN_MEMREGION_MMIO;
 
+	if(!sbi_is_region_valid(region))
+		return SBI_EINVAL;
+
 	(*region_count)++;
 
 	return 0;
-- 
2.30.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 17:14:21 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Thu,  8 Dec 2022 02:14:21 +0100
Subject: [PATCH v2 3/3] lib: fix irqchip_plic_update_hartid_table
In-Reply-To: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221208011421.11624-4-heinrich.schuchardt@canonical.com>

After determining cpu_offset we have to check this value.

Addresses-Coverity-ID: 1529706 ("Logically dead code")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
Reviewed-by: Atish Patra <atishp at rivosinc.com>
---
v2:
	add reviewed-by lines
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index a6e185c..fe08836 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -86,7 +86,7 @@ static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
 			continue;
 
 		cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
-		if (cpu_intc_offset < 0)
+		if (cpu_offset < 0)
 			continue;
 
 		err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 17:14:18 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Thu,  8 Dec 2022 02:14:18 +0100
Subject: [PATCH v2 0/3] lib: fix fdt functions
Message-ID: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>

Fix library device-tree library functions.

The problems were indicated by Coverity. Details can be seen at
https://scan.coverity.com/projects/opensbi/view_defects

v2:
	change logical constraints

Heinrich Schuchardt (3):
  lib: fix is_region_valid()
  lib: fix __fdt_parse_region()
  lib: fix irqchip_plic_update_hartid_table

 lib/sbi/sbi_domain.c                 | 9 +++++----
 lib/utils/fdt/fdt_domain.c           | 4 ++--
 lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 17:14:19 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Thu,  8 Dec 2022 02:14:19 +0100
Subject: [PATCH v2 1/3] lib: fix is_region_valid()
In-Reply-To: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221208011421.11624-2-heinrich.schuchardt@canonical.com>

For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.

Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
v2:
	Make the logical constraint a bit easier to read.
---
 lib/sbi/sbi_domain.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3302213..3205595 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -149,7 +149,7 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
 	if (reg->order == __riscv_xlen && reg->base != 0)
 		return FALSE;
 
-	if (reg->base & (BIT(reg->order) - 1))
+	if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
 		return FALSE;
 
 	return TRUE;
-- 
2.37.2



From heinrich.schuchardt at canonical.com  Wed Dec  7 17:14:20 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Thu,  8 Dec 2022 02:14:20 +0100
Subject: [PATCH v2 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
Message-ID: <20221208011421.11624-3-heinrich.schuchardt@canonical.com>

If fdt_getprop() returns NULL, this indicates an error. In this case lenp
is set to an error code. But even if lenp = 0 we should not continue.

If fdt_getprop() returns a wider value than we expect this is a separate
error condition.

In both cases the device-tree is invalid.

Addresses-Coverity-ID: 1529703 ("Dereference after null check")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
v2:
	correct the len requirements
---
 lib/utils/fdt/fdt_domain.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index bd0eec3..0568603 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 
 	/* Read "base" DT property */
 	val = fdt_getprop(fdt, region_offset, "base", &len);
-	if (!val && len >= 8)
+	if (!val || len != 8)
 		return SBI_EINVAL;
 	val64 = fdt32_to_cpu(val[0]);
 	val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
@@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 
 	/* Read "order" DT property */
 	val = fdt_getprop(fdt, region_offset, "order", &len);
-	if (!val && len >= 4)
+	if (!val || len != 4)
 		return SBI_EINVAL;
 	val32 = fdt32_to_cpu(*val);
 	if (val32 < 3 || __riscv_xlen < val32)
-- 
2.37.2



From wxjstz at 126.com  Wed Dec  7 18:30:47 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 10:30:47 +0800
Subject: [PATCH v2 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221208011421.11624-3-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
	 <20221208011421.11624-3-heinrich.schuchardt@canonical.com>
Message-ID: <6e65c138578e566c60b04db0637bdd70499aa2b1.camel@126.com>

? 2022-12-08???? 02:14 +0100?Heinrich Schuchardt???
> If fdt_getprop() returns NULL, this indicates an error. In this case lenp
> is set to an error code. But even if lenp = 0 we should not continue.
> 
> If fdt_getprop() returns a wider value than we expect this is a separate
> error condition.
> 
> In both cases the device-tree is invalid.
> 
> Addresses-Coverity-ID: 1529703 ("Dereference after null check")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????correct the len requirements
> ---
> ?lib/utils/fdt/fdt_domain.c | 4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
> index bd0eec3..0568603 100644
> --- a/lib/utils/fdt/fdt_domain.c
> +++ b/lib/utils/fdt/fdt_domain.c
> @@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
> ?
> ????????/* Read "base" DT property */
> ????????val = fdt_getprop(fdt, region_offset, "base", &len);
> -???????if (!val && len >= 8)
> +???????if (!val || len != 8)
> ????????????????return SBI_EINVAL;
> ????????val64 = fdt32_to_cpu(val[0]);
> ????????val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
> @@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
> ?
> ????????/* Read "order" DT property */
> ????????val = fdt_getprop(fdt, region_offset, "order", &len);
> -???????if (!val && len >= 4)
> +???????if (!val || len != 4)
> ????????????????return SBI_EINVAL;
> ????????val32 = fdt32_to_cpu(*val);
> ????????if (val32 < 3 || __riscv_xlen < val32)




From wxjstz at 126.com  Wed Dec  7 18:30:21 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 10:30:21 +0800
Subject: [PATCH v2 1/3] lib: fix is_region_valid()
In-Reply-To: <20221208011421.11624-2-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com>
	 <20221208011421.11624-2-heinrich.schuchardt@canonical.com>
Message-ID: <e8724b906252ccb17dc0b8be6e14358d0704a4ee.camel@126.com>

? 2022-12-08???? 02:14 +0100?Heinrich Schuchardt???
> For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.
> 
> Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> v2:
> ????????Make the logical constraint a bit easier to read.
> ---
> ?lib/sbi/sbi_domain.c | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3302213..3205595 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -149,7 +149,7 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
> ????????if (reg->order == __riscv_xlen && reg->base != 0)
> ????????????????return FALSE;
> ?
> -???????if (reg->base & (BIT(reg->order) - 1))
> +???????if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
> ????????????????return FALSE;
> ?
> ????????return TRUE;




From hchauhan at ventanamicro.com  Thu Dec  8 04:49:04 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Thu, 8 Dec 2022 18:19:04 +0530
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221203213929.206429-3-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
 <20221203213929.206429-3-geomatsi@gmail.com>
Message-ID: <20221208124904.qi5n6b6k7tamt22t@archlinux>

On Sun, Dec 04, 2022 at 12:39:29AM +0300, Sergey Matyukevich wrote:
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> 
> RISC-V Debug specification includes Sdtrig ISA extension.
> This extension describes Trigger Module. Triggers can cause
> a breakpoint exception, entry into Debug Mode, or a trace
> action without having to execute a special instruction. For
> native debugging triggers can be used to implement hardware
> breakpoints and watchpoints.
> 
> Software support for triggers consists of the following
> major components:
> - U-mode: gdb
> - S-mode: hardware breakpoints framework in Linux kernel
> - M-mode: SBI firmware code to handle triggers
> 
> SBI Debug Trigger extension proposal has been posted by
> Anup Patel to lists.riscv.org tech-debug mailing list:
> https://lists.riscv.org/g/tech-debug/topic/92375492
> 
> This patch provides initial implementation of SBI Debug
> Trigger Extension in OpenSBI library based on the
> suggested extension proposal.
> 
> Initial implementation has the following limitations:
> - supported triggers: mcontrol, mcontrol6
> - no support for chained triggers
> - only build test for RV32
> 
> ---
>  include/sbi/riscv_dbtr.h          | 179 +++++++++++
>  include/sbi/riscv_encoding.h      |   1 +
>  include/sbi/sbi_dbtr.h            |  80 +++++
>  include/sbi/sbi_ecall_interface.h |  10 +
>  lib/sbi/Kconfig                   |   4 +
>  lib/sbi/objects.mk                |   4 +
>  lib/sbi/sbi_dbtr.c                | 481 ++++++++++++++++++++++++++++++
>  lib/sbi/sbi_ecall_dbtr.c          |  68 +++++
>  lib/sbi/sbi_init.c                |   9 +
>  9 files changed, 836 insertions(+)
>  create mode 100644 include/sbi/riscv_dbtr.h
>  create mode 100644 include/sbi/sbi_dbtr.h
>  create mode 100644 lib/sbi/sbi_dbtr.c
>  create mode 100644 lib/sbi/sbi_ecall_dbtr.c
> 
> diff --git a/include/sbi/riscv_dbtr.h b/include/sbi/riscv_dbtr.h
> new file mode 100644
> index 0000000..9944547
> --- /dev/null
> +++ b/include/sbi/riscv_dbtr.h
> @@ -0,0 +1,179 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __RISCV_DBTR_H__
> +#define __RISCV_DBTR_H__
> +
> +#define RV_MAX_TRIGGERS	32
> +
> +enum {
> +	RISCV_DBTR_TRIG_NONE = 0,
> +	RISCV_DBTR_TRIG_LEGACY,
> +	RISCV_DBTR_TRIG_MCONTROL,
> +	RISCV_DBTR_TRIG_ICOUNT,
> +	RISCV_DBTR_TRIG_ITRIGGER,
> +	RISCV_DBTR_TRIG_ETRIGGER,
> +	RISCV_DBTR_TRIG_MCONTROL6,
> +};
> +
> +union riscv_dbtr_tdata1 {
> +	unsigned long value;
> +	struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +		unsigned long type:4;
> +		unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +		unsigned long data:59;
> +#elif __riscv_xlen == 32
> +		unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +#if __riscv_xlen == 64
> +		unsigned long data:59;
> +#elif __riscv_xlen == 32
> +		unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +		unsigned long dmode:1;
> +		unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +	};
> +};

Since, RISC-V implementations can allow a combination of different endianness for
M-mode and S-mode software. I am wondering how would this be handled if S-mode
software is actually different endianess?

> +
> +union riscv_dbtr_tdata1_mcontrol {
> +	unsigned long value;
> +	struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +		unsigned long type:4;
> +		unsigned long dmode:1;
> +		unsigned long maskmax:6;
> +#if __riscv_xlen >= 64
> +		unsigned long _res1:30;
> +		unsigned long sizehi:2;
> +#endif
> +		unsigned long hit:1;
> +		unsigned long select:1;
> +		unsigned long timing:1;
> +		unsigned long sizelo:2;
> +		unsigned long action:4;
> +		unsigned long chain:1;
> +		unsigned long match:4;
> +		unsigned long m:1;
> +		unsigned long _res2:1;
> +		unsigned long s:1;
> +		unsigned long u:1;
> +		unsigned long execute:1;
> +		unsigned long store:1;
> +		unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +		unsigned long load:1;
> +		unsigned long store:1;
> +		unsigned long execute:1;
> +		unsigned long u:1;
> +		unsigned long s:1;
> +		unsigned long _res2:1;
> +		unsigned long m:1;
> +		unsigned long match:4;
> +		unsigned long chain:1;
> +		unsigned long action:4;
> +		unsigned long sizelo:2;
> +		unsigned long timing:1;
> +		unsigned long select:1;
> +		unsigned long hit:1;
> +#if __riscv_xlen >= 64
> +		unsigned long sizehi:2;
> +		unsigned long _res1:30;
> +#endif
> +		unsigned long maskmax:6;
> +		unsigned long dmode:1;
> +		unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +	};
> +};
> +
> +#define MCONTROL_U_OFFSET	3
> +#define MCONTROL_S_OFFSET	4
> +#define MCONTROL_M_OFFSET	6
> +
> +union riscv_dbtr_tdata1_mcontrol6 {
> +	unsigned long value;
> +	struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +		unsigned long type:4;
> +		unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +		unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +		unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +		unsigned long vs:1;
> +		unsigned long vu:1;
> +		unsigned long hit:1;
> +		unsigned long select:1;
> +		unsigned long timing:1;
> +		unsigned long size:4;
> +		unsigned long action:4;
> +		unsigned long chain:1;
> +		unsigned long match:4;
> +		unsigned long m:1;
> +		unsigned long _res2:1;
> +		unsigned long s:1;
> +		unsigned long u:1;
> +		unsigned long execute:1;
> +		unsigned long store:1;
> +		unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +		unsigned long load:1;
> +		unsigned long store:1;
> +		unsigned long execute:1;
> +		unsigned long u:1;
> +		unsigned long s:1;
> +		unsigned long _res2:1;
> +		unsigned long m:1;
> +		unsigned long match:4;
> +		unsigned long chain:1;
> +		unsigned long action:4;
> +		unsigned long size:4;
> +		unsigned long timing:1;
> +		unsigned long select:1;
> +		unsigned long hit:1;
> +		unsigned long vu:1;
> +		unsigned long vs:1;
> +#if __riscv_xlen == 64
> +		unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +		unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +		unsigned long dmode:1;
> +		unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +	};
> +};
Also, IMHO, these definitions defined under aren't maintenance friendly.


> +
> +#define MCONTROL6_U_OFFSET	3
> +#define MCONTROL6_S_OFFSET	4
> +#define MCONTROL6_M_OFFSET	6
> +#define MCONTROL6_VU_OFFSET	23
> +#define MCONTROL6_VS_OFFSET	24
> +
> +#endif /* __RISCV_DBTR_H__ */
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index b0f08c8..2041ab7 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -671,6 +671,7 @@
>  #define CSR_TDATA1			0x7a1
>  #define CSR_TDATA2			0x7a2
>  #define CSR_TDATA3			0x7a3
> +#define CSR_TINFO			0x7a4
>  
>  /* Debug Mode Registers */
>  #define CSR_DCSR			0x7b0
> diff --git a/include/sbi/sbi_dbtr.h b/include/sbi/sbi_dbtr.h
> new file mode 100644
> index 0000000..5ef6166
> --- /dev/null
> +++ b/include/sbi/sbi_dbtr.h
> @@ -0,0 +1,80 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __SBI_DBTR_H__
> +#define __SBI_DBTR_H__
> +
> +#include <sbi/riscv_endian.h>
> +#include <sbi/riscv_dbtr.h>
> +
> +#include <sbi/sbi_hartmask.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_types.h>
> +
> +/** Representation of trigger state */
> +union sbi_dbtr_trig_state {
> +	unsigned long value;
> +	struct {
> +		unsigned long mapped:1;
> +		unsigned long u:1;
> +		unsigned long s:1;
> +		unsigned long vu:1;
> +		unsigned long vs:1;
> +#if __riscv_xlen == 64
> +		unsigned long reserved:59;
> +#elif __riscv_xlen == 32
> +		unsigned long reserved:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +	};
> +};
> +
> +struct sbi_dbtr_trig_info {
> +	unsigned long type_mask;
> +	union sbi_dbtr_trig_state state;
> +	unsigned long tdata1;
> +	unsigned long tdata2;
> +	unsigned long tdata3;
> +};
> +
> +/** SBI shared mem messages layout */
> +struct sbi_dbtr_data_msg {
> +	unsigned long tstate;
> +	unsigned long tdata1;
> +	unsigned long tdata2;
> +	unsigned long tdata3;
> +};
> +
> +struct sbi_dbtr_id_msg {
> +	unsigned long idx;
> +};
> +
> +/** Initialize PMU */
> +int sbi_dbtr_init(struct sbi_scratch *scratch);
> +
> +/** SBI DBTR extension functions */
> +int sbi_dbtr_probe(unsigned long *out);
> +int sbi_dbtr_num_trig(unsigned long trig_tdata1, unsigned long *out);
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_idx_base, unsigned long trig_count,
> +		unsigned long out_addr_div_by_16);
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_count, unsigned long in_addr_div_by_16,
> +		unsigned long out_addr_div_by_16, unsigned long *out);
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_count, unsigned long in_addr_div_by_16,
> +		unsigned long out_addr_div_by_16);
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +
> +#endif
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index a3f2bf4..3c1b1ea 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -29,6 +29,7 @@
>  #define SBI_EXT_HSM				0x48534D
>  #define SBI_EXT_SRST				0x53525354
>  #define SBI_EXT_PMU				0x504D55
> +#define SBI_EXT_DBTR				0x44425452
>  
>  /* SBI function IDs for BASE extension*/
>  #define SBI_EXT_BASE_GET_SPEC_VERSION		0x0
> @@ -100,6 +101,15 @@
>  #define SBI_EXT_PMU_COUNTER_STOP	0x4
>  #define SBI_EXT_PMU_COUNTER_FW_READ	0x5
>  
> +/* SBI function IDs for DBTR extension */
> +#define SBI_EXT_DBTR_NUM_TRIGGERS	0x0
> +#define SBI_EXT_DBTR_TRIGGER_READ	0x1
> +#define SBI_EXT_DBTR_TRIGGER_INSTALL	0x2
> +#define SBI_EXT_DBTR_TRIGGER_UNINSTALL	0x3
> +#define SBI_EXT_DBTR_TRIGGER_ENABLE	0x4
> +#define SBI_EXT_DBTR_TRIGGER_UPDATE	0x5
> +#define SBI_EXT_DBTR_TRIGGER_DISABLE	0x6
> +
>  /** General pmu event codes specified in SBI PMU extension */
>  enum sbi_pmu_hw_generic_events_t {
>  	SBI_PMU_HW_NO_EVENT			= 0,
> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> index df74bba..e3a7955 100644
> --- a/lib/sbi/Kconfig
> +++ b/lib/sbi/Kconfig
> @@ -34,4 +34,8 @@ config SBI_ECALL_VENDOR
>  	bool "Platform-defined vendor extensions"
>  	default y
>  
> +config SBI_ECALL_DBTR
> +	bool "Debug Trigger Extension"
> +	default y
> +
>  endmenu
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index c774ebb..36276e8 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -43,6 +43,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
>  carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
>  libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
>  
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBTR) += ecall_dbtr
> +libsbi-objs-$(CONFIG_SBI_ECALL_DBTR) += sbi_ecall_dbtr.o
> +
>  libsbi-objs-y += sbi_bitmap.o
>  libsbi-objs-y += sbi_bitops.o
>  libsbi-objs-y += sbi_console.o
> @@ -60,6 +63,7 @@ libsbi-objs-y += sbi_irqchip.o
>  libsbi-objs-y += sbi_misaligned_ldst.o
>  libsbi-objs-y += sbi_platform.o
>  libsbi-objs-y += sbi_pmu.o
> +libsbi-objs-y += sbi_dbtr.o
>  libsbi-objs-y += sbi_scratch.o
>  libsbi-objs-y += sbi_string.o
>  libsbi-objs-y += sbi_system.o
> diff --git a/lib/sbi/sbi_dbtr.c b/lib/sbi/sbi_dbtr.c
> new file mode 100644
> index 0000000..bbad0cf
> --- /dev/null
> +++ b/lib/sbi/sbi_dbtr.c
> @@ -0,0 +1,481 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_csr_detect.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/riscv_asm.h>
> +
> +static struct sbi_dbtr_trig_info triggers[SBI_HARTMASK_MAX_BITS][RV_MAX_TRIGGERS] = {0};
> +static uint32_t total_trigs;
> +
> +static void sbi_triggers_table_init(u32 hartid, int idx, unsigned long type_mask)
> +{
> +	triggers[hartid][idx].type_mask = type_mask;
> +	triggers[hartid][idx].state.value = 0;
> +	triggers[hartid][idx].tdata1 = 0;
> +	triggers[hartid][idx].tdata2 = 0;
> +	triggers[hartid][idx].tdata3 = 0;
> +}
> +
> +int sbi_dbtr_init(struct sbi_scratch *scratch)
> +{
> +	struct sbi_trap_info trap = {0};
> +	u32 hartid = current_hartid();
> +	union riscv_dbtr_tdata1 tdata1;
> +	unsigned long val;
> +	int i;
> +
> +	total_trigs = 0;
> +
> +	for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> +		csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
> +		if (trap.cause)
> +			break;
> +
> +		val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
> +		if (trap.cause)
> +			break;
> +
> +		/* Read back tselect and check that it contains the written value */
> +		if (val != i)
> +			break;
> +
> +		val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
> +		if (trap.cause) {
> +			/**
> +			 * If reading tinfo caused an exception, the debugger
> +			 * must read tdata1 to discover the type.
> +			 */
> +			tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
> +			if (trap.cause)
> +				break;
> +
> +			if (tdata1.type == 0)
> +				break;
> +
> +
> +			sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
> +			total_trigs++;
> +		} else {
> +			if (val == 1)
> +				break;
> +
> +			sbi_triggers_table_init(hartid, i, val);
> +			total_trigs++;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int sbi_dbtr_probe(unsigned long *out)
> +{
> +	*out  = total_trigs;
> +
> +	return 0;
> +}
> +
> +
> +static void dbtr_trigger_init(unsigned int hartid, unsigned int idx,
> +			      struct sbi_dbtr_data_msg *recv)
> +{
> +	union riscv_dbtr_tdata1 tdata1;
> +
> +	triggers[hartid][idx].tdata1 = lle_to_cpu(recv->tdata1);
> +	triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +	triggers[hartid][idx].tdata3 = lle_to_cpu(recv->tdata3);
> +	triggers[hartid][idx].state.mapped = 1;
> +
> +	tdata1.value = lle_to_cpu(recv->tdata1);
> +
> +	switch (tdata1.type) {
> +	case RISCV_DBTR_TRIG_MCONTROL:
> +		triggers[hartid][idx].state.u = __test_bit(MCONTROL_U_OFFSET, &tdata1.value);
> +		triggers[hartid][idx].state.s = __test_bit(MCONTROL_S_OFFSET, &tdata1.value);
> +		triggers[hartid][idx].state.vu = 0;
> +		triggers[hartid][idx].state.vs = 0;
> +		break;
> +	case RISCV_DBTR_TRIG_MCONTROL6:
> +		triggers[hartid][idx].state.u = __test_bit(MCONTROL6_U_OFFSET, &tdata1.value);
> +		triggers[hartid][idx].state.s = __test_bit(MCONTROL6_S_OFFSET, &tdata1.value);
> +		triggers[hartid][idx].state.vu = __test_bit(MCONTROL6_VU_OFFSET, &tdata1.value);
> +		triggers[hartid][idx].state.vs = __test_bit(MCONTROL6_VS_OFFSET, &tdata1.value);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +static inline void update_bit(unsigned long new, int nr, volatile unsigned long *addr)
> +{
> +	if (new)
> +		__set_bit(nr, addr);
> +	else
> +		__clear_bit(nr, addr);
> +}
> +
> +static void dbtr_trigger_enable(unsigned int hartid, unsigned int idx)
> +{
> +	union sbi_dbtr_trig_state state;
> +	union riscv_dbtr_tdata1 tdata1;
> +
> +	if (!triggers[hartid][idx].state.mapped)
> +		return;
> +
> +	state.value = triggers[hartid][idx].state.value;
> +	tdata1.value = triggers[hartid][idx].tdata1;
> +
> +	switch (tdata1.type) {
> +	case RISCV_DBTR_TRIG_MCONTROL:
> +		update_bit(state.u, MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +		update_bit(state.s, MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +		break;
> +	case RISCV_DBTR_TRIG_MCONTROL6:
> +		update_bit(state.vu, MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +		update_bit(state.vs, MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +		update_bit(state.u, MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +		update_bit(state.s, MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	/*
> +	 * RISC-V Debug Support v1.0.0 section 5.5:
> +	 * Debugger cannot simply set a trigger by writing tdata1, then tdata2, etc. The current
> +	 * value of tdata2 might not be legal with the new value of tdata1. To help with this
> +	 * situation, it is guaranteed that writing 0 to tdata1 disables the trigger, and
> +	 * leaves it in a state where tdata2 and tdata3 can be written with any value
> +	 * that makes sense for any trigger type supported by this trigger.
> +	 */
> +	csr_write(CSR_TSELECT, idx);
> +	csr_write(CSR_TDATA1, 0x0);
> +	csr_write(CSR_TDATA2, triggers[hartid][idx].tdata2);
> +	csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_disable(unsigned int hartid, unsigned int idx)
> +{
> +	union riscv_dbtr_tdata1 tdata1;
> +
> +	if (!triggers[hartid][idx].state.mapped)
> +		return;
> +
> +	tdata1.value = triggers[hartid][idx].tdata1;
> +
> +	switch (tdata1.type) {
> +	case RISCV_DBTR_TRIG_MCONTROL:
> +		__clear_bit(MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +		__clear_bit(MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +		break;
> +	case RISCV_DBTR_TRIG_MCONTROL6:
> +		__clear_bit(MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +		__clear_bit(MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +		__clear_bit(MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +		__clear_bit(MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	csr_write(CSR_TSELECT, idx);
> +	csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_clear(unsigned int hartid, unsigned int idx)
> +{
> +	if (!triggers[hartid][idx].state.mapped)
> +		return;
> +
> +	csr_write(CSR_TSELECT, idx);
> +	csr_write(CSR_TDATA1, 0x0);
> +	csr_write(CSR_TDATA2, 0x0);
> +}
> +
> +static int dbtr_trigger_supported(unsigned long type)
> +{
> +	switch (type) {
> +	case RISCV_DBTR_TRIG_MCONTROL:
> +	case RISCV_DBTR_TRIG_MCONTROL6:
> +		return 1;
> +	default:
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +static int dbtr_trigger_valid(unsigned long type, unsigned long tdata)
> +{
> +	union riscv_dbtr_tdata1_mcontrol6 control6;
> +	union riscv_dbtr_tdata1_mcontrol control;
> +
> +	switch (type) {
> +	case RISCV_DBTR_TRIG_MCONTROL:
> +		control.value = tdata;
> +		if (!control.action && !control.dmode && !control.m)
> +			return 1;
> +		break;
> +	case RISCV_DBTR_TRIG_MCONTROL6:
> +		control6.value = tdata;
> +		if (!control6.action && !control6.dmode && !control6.m)
> +			return 1;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +int sbi_dbtr_num_trig(unsigned long data, unsigned long *out)
> +{
> +	unsigned long type = ((union riscv_dbtr_tdata1)data).type;
> +	u32 hartid = current_hartid();
> +	unsigned long total = 0;
> +	int i;
> +
> +
> +	if (data == 0) {
> +		sbi_dprintf("%s: hart%d: total triggers: %u\n",
> +			    __func__, hartid, total_trigs);
> +		*out = total_trigs;
> +		return SBI_SUCCESS;
> +	}
> +
> +	for (i = 0; i < total_trigs; i++) {
> +		if (__test_bit(type, &triggers[hartid][i].type_mask))
> +			total++;
> +	}
> +
> +
> +	sbi_dprintf("%s: hart%d: total triggers of type %lu: %lu\n",
> +		    __func__, hartid, type, total);
> +
> +	*out = total;
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_idx_base, unsigned long trig_count,
> +		unsigned long out_addr_div_by_16)
> +{
> +	unsigned long out_addr = (out_addr_div_by_16 << 4);
> +	struct sbi_dbtr_data_msg *xmit;
> +	u32 hartid = current_hartid();
> +	int i;
> +
> +	if (smode != PRV_S)
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +		return SBI_ERR_INVALID_ADDRESS;
> +
> +	if (trig_idx_base >= total_trigs || trig_idx_base + trig_count >= total_trigs) {
> +		sbi_dprintf("%s: hart%d: invalid trigger index\n", __func__, hartid);
> +		return SBI_ERR_INVALID_PARAM;
> +	}
> +
> +	for (i = 0; i < trig_count; i++) {
> +		xmit = (struct sbi_dbtr_data_msg *)(out_addr + i * sizeof(*xmit));
> +
> +		sbi_dprintf("%s: hart%d: read trigger %d\n", __func__, hartid, i);
> +
> +		xmit->tstate = cpu_to_lle(triggers[hartid][i + trig_idx_base].state.value);
> +		xmit->tdata1 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata1);
> +		xmit->tdata2 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata2);
> +		xmit->tdata3 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata3);
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_count, unsigned long in_addr_div_by_16,
> +		unsigned long out_addr_div_by_16, unsigned long *out)
> +{
> +	unsigned long out_addr = (out_addr_div_by_16 << 4);
> +	unsigned long in_addr = (in_addr_div_by_16 << 4);
> +	u32 hartid = current_hartid();
> +	struct sbi_dbtr_data_msg *recv;
> +	struct sbi_dbtr_id_msg *xmit;
> +	union riscv_dbtr_tdata1 ctrl;
> +	int i, k;
> +
> +	if (smode != PRV_S)
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +		return SBI_ERR_INVALID_ADDRESS;
> +	if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +		return SBI_ERR_INVALID_ADDRESS;
> +
> +	/* TODO: check chained triggers configurations */
> +
> +	/* Check requested triggers configuration */
> +	for (k = 0; k < trig_count; k++) {
> +		recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +		ctrl = (union riscv_dbtr_tdata1)recv->tdata1;
> +
> +		if (!dbtr_trigger_supported(ctrl.type)) {
> +			sbi_dprintf("%s: invalid type of trigger %d\n", __func__, k);
> +			*out = k;
> +			return SBI_ERR_FAILED;
> +		}
> +
> +		if (!dbtr_trigger_valid(ctrl.type, ctrl.value)) {
> +			sbi_dprintf("%s: invalid configuration of trigger %d\n", __func__, k);
> +			*out = k;
> +			return SBI_ERR_FAILED;
> +		}
> +	}
> +
> +	/* Check if we have enough spare triggers */
> +	for (i = 0, k = 0; i < total_trigs; i++) {
> +		if (!triggers[hartid][i].state.mapped)
> +			k++;
> +	}
> +
> +	if (k < trig_count) {
> +		sbi_dprintf("%s: hartid%d: not enough spare triggers\n", __func__, hartid);
> +		*out = k;
> +		return SBI_ERR_FAILED;
> +	}
> +
> +	/* Install triggers */
> +	for (i = 0, k = 0; i < total_trigs; i++) {
> +		if (triggers[hartid][i].state.mapped)
> +			continue;
> +
> +		recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +		xmit = (struct sbi_dbtr_id_msg *)(out_addr + k * sizeof(*xmit));
> +
> +		sbi_dprintf("%s: hart%d: idx[%d] tdata1[0x%lx] tdata2[0x%lx]\n",
> +			    __func__, hartid, i, recv->tdata1, recv->tdata2);
> +
> +		dbtr_trigger_init(hartid, i,  recv);
> +		dbtr_trigger_enable(hartid, i);
> +		xmit->idx = cpu_to_lle(i);
> +
> +		if (++k >= trig_count)
> +			break;
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +	unsigned long idx = trig_idx_base;
> +	u32 hartid = current_hartid();
> +
> +	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +		    __func__, hartid, trig_mask);
> +
> +	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +		if (!triggers[hartid][idx].state.mapped) {
> +			sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +			return SBI_ERR_INVALID_PARAM;
> +		}
> +
> +		sbi_dprintf("%s: clear trigger %lu\n", __func__, idx);
> +		dbtr_trigger_clear(hartid, idx);
> +
> +		triggers[hartid][idx].state.value = 0;
> +		triggers[hartid][idx].tdata1 = 0;
> +		triggers[hartid][idx].tdata2 = 0;
> +		triggers[hartid][idx].tdata3 = 0;
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +	unsigned long idx = trig_idx_base;
> +	u32 hartid = current_hartid();
> +
> +	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +		    __func__, hartid, trig_mask);
> +
> +	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +		sbi_dprintf("%s: enable trigger %lu\n", __func__, idx);
> +		dbtr_trigger_enable(hartid, idx);
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +		unsigned long trig_idx_base, unsigned long trig_idx_mask,
> +		unsigned long in_addr_div_by_16)
> +{
> +	unsigned long in_addr = (in_addr_div_by_16 << 4);
> +	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +	unsigned long idx = trig_idx_base;
> +	u32 hartid = current_hartid();
> +	struct sbi_dbtr_data_msg *recv;
> +	unsigned long uidx = 0;
> +
> +	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +		    __func__, hartid, trig_mask);
> +
> +	if (smode != PRV_S)
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +		return SBI_ERR_DENIED;
> +	if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +		return SBI_ERR_INVALID_ADDRESS;
> +
> +	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +		if (!triggers[hartid][idx].state.mapped) {
> +			sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +			return SBI_ERR_INVALID_PARAM;
> +		}
> +
> +		recv = (struct sbi_dbtr_data_msg *)(in_addr + uidx * sizeof(*recv));
> +
> +		sbi_dprintf("%s: update trigger %lu: newaddr 0x%lx\n",
> +			    __func__, idx, recv->tdata2);
> +
> +		triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +		dbtr_trigger_enable(hartid, idx);
> +		uidx++;
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +	unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +	unsigned long idx = trig_idx_base;
> +	u32 hartid = current_hartid();
> +
> +	sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +		    __func__, hartid, trig_mask);
> +
> +	for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +		sbi_dprintf("%s: disable trigger %lu\n", __func__, idx);
> +		dbtr_trigger_disable(hartid, idx);
> +	}
> +
> +	return SBI_SUCCESS;
> +}
> diff --git a/lib/sbi/sbi_ecall_dbtr.c b/lib/sbi/sbi_ecall_dbtr.c
> new file mode 100644
> index 0000000..d013b3e
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_dbtr.c
> @@ -0,0 +1,68 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *   Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_version.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +static int sbi_ecall_dbtr_handler(unsigned long extid, unsigned long funcid,
> +				  const struct sbi_trap_regs *regs,
> +				  unsigned long *out_val,
> +				  struct sbi_trap_info *out_trap)
> +{
> +	unsigned long smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
> +			MSTATUS_MPP_SHIFT;
> +	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
> +	int ret = 0;
> +
> +	switch (funcid) {
> +	case SBI_EXT_DBTR_NUM_TRIGGERS:
> +		ret = sbi_dbtr_num_trig(regs->a0, out_val);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_READ:
> +		ret = sbi_dbtr_read_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_INSTALL:
> +		ret = sbi_dbtr_install_trig(dom, smode, regs->a0, regs->a1, regs->a2, out_val);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_UNINSTALL:
> +		ret = sbi_dbtr_uninstall_trig(regs->a0, regs->a1);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_ENABLE:
> +		ret = sbi_dbtr_enable_trig(regs->a0, regs->a1);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_UPDATE:
> +		ret = sbi_dbtr_update_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +		break;
> +	case SBI_EXT_DBTR_TRIGGER_DISABLE:
> +		ret = sbi_dbtr_disable_trig(regs->a0, regs->a1);
> +		break;
> +	default:
> +		ret = SBI_ENOTSUPP;
> +	};
> +
> +	return ret;
> +}
> +
> +static int sbi_ecall_dbtr_probe(unsigned long extid, unsigned long *out_val)
> +{
> +	return sbi_dbtr_probe(out_val);
> +}
> +
> +struct sbi_ecall_extension ecall_dbtr = {
> +	.extid_start = SBI_EXT_DBTR,
> +	.extid_end = SBI_EXT_DBTR,
> +	.handle = sbi_ecall_dbtr_handler,
> +	.probe = sbi_ecall_dbtr_probe,
> +};
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..956afae 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -21,6 +21,7 @@
>  #include <sbi/sbi_irqchip.h>
>  #include <sbi/sbi_platform.h>
>  #include <sbi/sbi_pmu.h>
> +#include <sbi/sbi_dbtr.h>
>  #include <sbi/sbi_system.h>
>  #include <sbi/sbi_string.h>
>  #include <sbi/sbi_timer.h>
> @@ -275,6 +276,10 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
>  	if (rc)
>  		sbi_hart_hang();
>  
> +	rc = sbi_dbtr_init(scratch);
> +	if (rc)
> +		sbi_hart_hang();
> +
>  	sbi_boot_print_banner(scratch);
>  
>  	rc = sbi_irqchip_init(scratch, TRUE);
> @@ -380,6 +385,10 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
>  	if (rc)
>  		sbi_hart_hang();
>  
> +	rc = sbi_dbtr_init(scratch);
> +	if (rc)
> +		sbi_hart_hang();
> +
>  	rc = sbi_irqchip_init(scratch, FALSE);
>  	if (rc)
>  		sbi_hart_hang();
> -- 
> 2.38.1
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

-- 
Thanks & Regards
Himanshu


From hchauhan at ventanamicro.com  Thu Dec  8 05:38:20 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Thu,  8 Dec 2022 19:08:20 +0530
Subject: [PATCH] scripts: use env to invoke bash
Message-ID: <20221208133820.1082271-1-hchauhan@ventanamicro.com>

Not all systems have bash at a fixed location like /bin/bash.
FreeBSD, for example, would typically have it at /usr/local/bin/bash.
When building OpenSBI on freebsd system, the build breaks.

Its advisable to use: #!/usr/bin/env bash

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 scripts/carray.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/carray.sh b/scripts/carray.sh
index 0c52bd6..13f9d36 100755
--- a/scripts/carray.sh
+++ b/scripts/carray.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 function usage()
 {
-- 
2.38.1



From wxjstz at 126.com  Thu Dec  8 07:20:45 2022
From: wxjstz at 126.com (Xiang W)
Date: Thu, 08 Dec 2022 23:20:45 +0800
Subject: [PATCH] scripts: use env to invoke bash
In-Reply-To: <20221208133820.1082271-1-hchauhan@ventanamicro.com>
References: <20221208133820.1082271-1-hchauhan@ventanamicro.com>
Message-ID: <6860d8eee60b0a6a9ef4b9678517ed9e2d2f8515.camel@126.com>

? 2022-12-08???? 19:08 +0530?Himanshu Chauhan???
> Not all systems have bash at a fixed location like /bin/bash.
> FreeBSD, for example, would typically have it at /usr/local/bin/bash.
> When building OpenSBI on freebsd system, the build breaks.
> 
> Its advisable to use: #!/usr/bin/env bash
> 
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
scripts/d2c.sh and scripts/create-binary-archive.sh also need the
same modification.

Regards,
Xiang W
> ---
> ?scripts/carray.sh | 2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/scripts/carray.sh b/scripts/carray.sh
> index 0c52bd6..13f9d36 100755
> --- a/scripts/carray.sh
> +++ b/scripts/carray.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
> ?
> ?function usage()
> ?{
> -- 
> 2.38.1
> 
> 




From anup at brainfault.org  Thu Dec  8 21:10:04 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 10:40:04 +0530
Subject: [RESEND PATCH v2 2/5] lib: utils/irqchip: plic: Ensure no
 out-of-bound access in priority save/restore helpers
In-Reply-To: <20221204051741.440008-2-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org> <20221204051741.440008-2-bmeng@tinylab.org>
Message-ID: <CAAhSdy1ZhX=LueggHQhkfZ4AnRLBOQ5Q4fX++05De_4z-z1szA@mail.gmail.com>

On Sun, Dec 4, 2022 at 10:47 AM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the priority save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
> ---
>
> Changes in v2 RESEND:
> - %s/libs/lib in the commit title
>
> Changes in v2:
> - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  4 ++--
>  include/sbi_utils/irqchip/plic.h             |  5 +++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         | 12 ++++++++----
>  lib/utils/irqchip/plic.c                     |  9 +++++----
>  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
>  5 files changed, 20 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 98d4de5..5f3f54d 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -9,9 +9,9 @@
>
>  #include <sbi/sbi_types.h>
>
> -void fdt_plic_priority_save(u8 *priority);
> +void fdt_plic_priority_save(u8 *priority, u32 num);
>
> -void fdt_plic_priority_restore(const u8 *priority);
> +void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 48c24f0..38704a1 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -18,9 +18,10 @@ struct plic_data {
>  };
>
>  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
>                        u32 *enable, u32 *threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..87fb9bd 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -24,18 +24,22 @@ static struct plic_data plic[PLIC_MAX_NR];
>  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
>  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
>
> -void fdt_plic_priority_save(u8 *priority)
> +void fdt_plic_priority_save(u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_save(plic, priority);
> +       if (num > plic->num_src + 1)
> +               num = plic->num_src + 1;

This should be:
if (num > plic->num_src)
    num = plic->num_src;

> +       plic_priority_save(plic, priority, num);
>  }
>
> -void fdt_plic_priority_restore(const u8 *priority)
> +void fdt_plic_priority_restore(const u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_restore(plic, priority);
> +       if (num > plic->num_src + 1)
> +               num = plic->num_src + 1;

Same as above.

> +       plic_priority_restore(plic, priority, num);
>  }
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 4df9020..c5c1879 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -36,15 +36,16 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>         writel(val, plic_priority);
>  }
>
> -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       for (u32 i = 1; i <= num; i++)
>                 priority[i] = plic_get_priority(plic, i);
>  }
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       for (u32 i = 1; i <= num; i++)
>                 plic_set_priority(plic, i, priority[i]);
>  }
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 707313b..46d336f 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>  static void sun20i_d1_plic_save(void)
>  {
>         fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -       fdt_plic_priority_save(plic_priority);
> +       fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
>  static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
> -       fdt_plic_priority_restore(plic_priority);
> +       fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>         fdt_plic_context_restore(true, plic_sie, plic_threshold);
>  }
>
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Otherwise it looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup


From anup at brainfault.org  Thu Dec  8 21:10:36 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 10:40:36 +0530
Subject: [RESEND PATCH v2 1/5] lib: utils/irqchip: plic: Fix the
 off-by-one error in priority save/restore helpers
In-Reply-To: <20221204051741.440008-1-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org>
Message-ID: <CAAhSdy1=b4anTcRJajd1fHziQPsRFcu4PcCrOiUFUZStkwjztQ@mail.gmail.com>

On Sun, Dec 4, 2022 at 10:47 AM Bin Meng <bmeng at tinylab.org> wrote:
>
> Interrupt source 0 is reserved. Hence the irq should start from 1.
>
> Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>
> (no changes since v1)
>
>  lib/utils/irqchip/plic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 73d7788..4df9020 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>
>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>  {
> -       for (u32 i = 0; i < plic->num_src; i++)
> +       for (u32 i = 1; i <= plic->num_src; i++)
>                 priority[i] = plic_get_priority(plic, i);
>  }
>
>  void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
>  {
> -       for (u32 i = 0; i < plic->num_src; i++)
> +       for (u32 i = 1; i <= plic->num_src; i++)
>                 plic_set_priority(plic, i, priority[i]);
>  }
>
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Dec  8 21:21:35 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 10:51:35 +0530
Subject: [RESEND PATCH v2 3/5] lib: utils/irqchip: plic: Fix the
 off-by-one error in plic_context_init()
In-Reply-To: <20221204051741.440008-3-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org> <20221204051741.440008-3-bmeng@tinylab.org>
Message-ID: <CAAhSdy1UEFP3d_O0yy0TVFLmf8ws-pLZ1qXJTgbei3BW25qWXQ@mail.gmail.com>

On Sun, Dec 4, 2022 at 10:47 AM Bin Meng <bmeng at tinylab.org> wrote:
>
> The number of interrupt enable register in words was once correct,
> but was wrongly changed to have an off-by-one error since
> commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").
>
> Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

>
> ---
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
>
>  lib/utils/irqchip/plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index c5c1879..5b87d3b 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -121,7 +121,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
>         if (!plic || context_id < 0)
>                 return SBI_EINVAL;
>
> -       ie_words = (plic->num_src + 31) / 32;
> +       ie_words = plic->num_src / 32 + 1;
>         ie_value = enable ? 0xffffffffU : 0U;
>
>         for (u32 i = 0; i < ie_words; i++)
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Dec  8 21:22:02 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 10:52:02 +0530
Subject: [RESEND PATCH v2 4/5] lib: utils/irqchip: plic: Fix the
 off-by-one error in context save/restore helpers
In-Reply-To: <20221204051741.440008-4-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org> <20221204051741.440008-4-bmeng@tinylab.org>
Message-ID: <CAAhSdy3t91pZ6dVuFjxeHRYaj4v1o53=NjeQXfY_EAsKUAVH9Q@mail.gmail.com>

On Sun, Dec 4, 2022 at 10:47 AM Bin Meng <bmeng at tinylab.org> wrote:
>
> plic->num_src holds the number of interrupt sources without interrupt
> source 0 but the interrupt enable register includes a bit for the
> interrupt source 0 in the first word.
>
> Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

>
> ---
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
>
>  lib/utils/irqchip/plic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 5b87d3b..0a1596c 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -94,7 +94,7 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
>  void plic_context_save(const struct plic_data *plic, int context_id,
>                        u32 *enable, u32 *threshold)
>  {
> -       u32 ie_words = (plic->num_src + 31) / 32;
> +       u32 ie_words = plic->num_src / 32 + 1;
>
>         for (u32 i = 0; i < ie_words; i++)
>                 enable[i] = plic_get_ie(plic, context_id, i);
> @@ -105,7 +105,7 @@ void plic_context_save(const struct plic_data *plic, int context_id,
>  void plic_context_restore(const struct plic_data *plic, int context_id,
>                           const u32 *enable, u32 threshold)
>  {
> -       u32 ie_words = (plic->num_src + 31) / 32;
> +       u32 ie_words = plic->num_src / 32 + 1;
>
>         for (u32 i = 0; i < ie_words; i++)
>                 plic_set_ie(plic, context_id, i, enable[i]);
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Thu Dec  8 21:33:16 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 11:03:16 +0530
Subject: [RESEND PATCH v2 2/5] lib: utils/irqchip: plic: Ensure no
 out-of-bound access in priority save/restore helpers
In-Reply-To: <CAAhSdy1ZhX=LueggHQhkfZ4AnRLBOQ5Q4fX++05De_4z-z1szA@mail.gmail.com>
References: <20221204051741.440008-1-bmeng@tinylab.org> <20221204051741.440008-2-bmeng@tinylab.org>
 <CAAhSdy1ZhX=LueggHQhkfZ4AnRLBOQ5Q4fX++05De_4z-z1szA@mail.gmail.com>
Message-ID: <CAAhSdy0JzmuSyJ+LZsS3dsvPy_nYepYjpeGjPdroPbT=x4CzGA@mail.gmail.com>

On Fri, Dec 9, 2022 at 10:40 AM Anup Patel <anup at brainfault.org> wrote:
>
> On Sun, Dec 4, 2022 at 10:47 AM Bin Meng <bmeng at tinylab.org> wrote:
> >
> > Currently the priority save/restore helpers writes/reads the provided
> > array using an index whose maximum value is determined by PLIC, which
> > potentially may disagree with the caller to these helpers.
> >
> > Add a parameter to ask the caller to provide the size limit of the
> > array to ensure no out-of-bound access happens.
> >
> > Signed-off-by: Bin Meng <bmeng at tinylab.org>
> >
> > ---
> >
> > Changes in v2 RESEND:
> > - %s/libs/lib in the commit title
> >
> > Changes in v2:
> > - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
> >
> >  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  4 ++--
> >  include/sbi_utils/irqchip/plic.h             |  5 +++--
> >  lib/utils/irqchip/fdt_irqchip_plic.c         | 12 ++++++++----
> >  lib/utils/irqchip/plic.c                     |  9 +++++----
> >  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
> >  5 files changed, 20 insertions(+), 14 deletions(-)
> >
> > diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > index 98d4de5..5f3f54d 100644
> > --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > @@ -9,9 +9,9 @@
> >
> >  #include <sbi/sbi_types.h>
> >
> > -void fdt_plic_priority_save(u8 *priority);
> > +void fdt_plic_priority_save(u8 *priority, u32 num);
> >
> > -void fdt_plic_priority_restore(const u8 *priority);
> > +void fdt_plic_priority_restore(const u8 *priority, u32 num);
> >
> >  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
> >
> > diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> > index 48c24f0..38704a1 100644
> > --- a/include/sbi_utils/irqchip/plic.h
> > +++ b/include/sbi_utils/irqchip/plic.h
> > @@ -18,9 +18,10 @@ struct plic_data {
> >  };
> >
> >  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> > -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> > +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
> >
> > -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> > +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> > +                          u32 num);
> >
> >  void plic_context_save(const struct plic_data *plic, int context_id,
> >                        u32 *enable, u32 *threshold);
> > diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> > index a6e185c..87fb9bd 100644
> > --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> > +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> > @@ -24,18 +24,22 @@ static struct plic_data plic[PLIC_MAX_NR];
> >  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
> >  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
> >
> > -void fdt_plic_priority_save(u8 *priority)
> > +void fdt_plic_priority_save(u8 *priority, u32 num)
> >  {
> >         struct plic_data *plic = plic_hartid2data[current_hartid()];
> >
> > -       plic_priority_save(plic, priority);
> > +       if (num > plic->num_src + 1)
> > +               num = plic->num_src + 1;
>
> This should be:
> if (num > plic->num_src)
>     num = plic->num_src;

I think it is better to move this "if ()" block in plic_priority_save().

>
> > +       plic_priority_save(plic, priority, num);
> >  }
> >
> > -void fdt_plic_priority_restore(const u8 *priority)
> > +void fdt_plic_priority_restore(const u8 *priority, u32 num)
> >  {
> >         struct plic_data *plic = plic_hartid2data[current_hartid()];
> >
> > -       plic_priority_restore(plic, priority);
> > +       if (num > plic->num_src + 1)
> > +               num = plic->num_src + 1;
>
> Same as above.
>
> > +       plic_priority_restore(plic, priority, num);
> >  }
> >
> >  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> > diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> > index 4df9020..c5c1879 100644
> > --- a/lib/utils/irqchip/plic.c
> > +++ b/lib/utils/irqchip/plic.c
> > @@ -36,15 +36,16 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
> >         writel(val, plic_priority);
> >  }
> >
> > -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> > +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
> >  {
> > -       for (u32 i = 1; i <= plic->num_src; i++)
> > +       for (u32 i = 1; i <= num; i++)
> >                 priority[i] = plic_get_priority(plic, i);
> >  }
> >
> > -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> > +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> > +                          u32 num)
> >  {
> > -       for (u32 i = 1; i <= plic->num_src; i++)
> > +       for (u32 i = 1; i <= num; i++)
> >                 plic_set_priority(plic, i, priority[i]);
> >  }
> >
> > diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> > index 707313b..46d336f 100644
> > --- a/platform/generic/allwinner/sun20i-d1.c
> > +++ b/platform/generic/allwinner/sun20i-d1.c
> > @@ -79,13 +79,13 @@ static u32 plic_threshold;
> >  static void sun20i_d1_plic_save(void)
> >  {
> >         fdt_plic_context_save(true, plic_sie, &plic_threshold);
> > -       fdt_plic_priority_save(plic_priority);
> > +       fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
> >  }
> >
> >  static void sun20i_d1_plic_restore(void)
> >  {
> >         thead_plic_restore();
> > -       fdt_plic_priority_restore(plic_priority);
> > +       fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> >         fdt_plic_context_restore(true, plic_sie, plic_threshold);
> >  }
> >
> > --
> > 2.34.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>
> Otherwise it looks good to me.
>
> Reviewed-by: Anup Patel <anup at brainfault.org>
>
> Regards,
> Anup

Regards,
Anup


From anup at brainfault.org  Thu Dec  8 21:37:28 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 11:07:28 +0530
Subject: [RESEND PATCH v2 5/5] lib: utils/irqchip: plic: Ensure no
 out-of-bound access in context save/restore helpers
In-Reply-To: <20221204051741.440008-5-bmeng@tinylab.org>
References: <20221204051741.440008-1-bmeng@tinylab.org> <20221204051741.440008-5-bmeng@tinylab.org>
Message-ID: <CAAhSdy2SuG7E+b-5_SCvCsiRW=K7zbSMF8J3Diacy46Ee1tokA@mail.gmail.com>

On Sun, Dec 4, 2022 at 10:48 AM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the context save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
> ---
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
>  include/sbi_utils/irqchip/plic.h             |  4 ++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         | 21 ++++++++++++++------
>  lib/utils/irqchip/plic.c                     | 12 ++++-------
>  platform/generic/allwinner/sun20i-d1.c       |  5 +++--
>  5 files changed, 27 insertions(+), 20 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 5f3f54d..f855454 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -13,9 +13,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
>
>  void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num);
>
>  void thead_plic_restore(void);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 38704a1..112a714 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
>                            u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold);
> +                      u32 *enable, u32 *threshold, u32 num);
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold);
> +                         const u32 *enable, u32 threshold, u32 num);
>
>  int plic_context_init(const struct plic_data *plic, int context_id,
>                       bool enable, u32 threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index 87fb9bd..e975415 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -42,22 +42,31 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
>         plic_priority_restore(plic, priority, num);
>  }
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
>  {
>         u32 hartid = current_hartid();
> +       struct plic_data *plic = plic_hartid2data[hartid];
> +       u32 ie_words = plic->num_src / 32 + 1;
>
> -       plic_context_save(plic_hartid2data[hartid],
> +       if (num > ie_words)
> +               num = ie_words;

Move this "if ()" block to plic_context_save() function.

> +       plic_context_save(plic,
>                           plic_hartid2context[hartid][smode],
> -                         enable, threshold);
> +                         enable, threshold, num);
>  }
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num)
>  {
>         u32 hartid = current_hartid();
> +       struct plic_data *plic = plic_hartid2data[hartid];
> +       u32 ie_words = plic->num_src / 32 + 1;
>
> -       plic_context_restore(plic_hartid2data[hartid],
> +       if (num > ie_words)
> +               num = ie_words;

Same as above, move this "if ()" block to plic_context_restore() function.

> +       plic_context_restore(plic,
>                              plic_hartid2context[hartid][smode],
> -                            enable, threshold);
> +                            enable, threshold, num);
>  }
>
>  static int irqchip_plic_warm_init(void)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 0a1596c..5922c75 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -92,22 +92,18 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
>  }
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold)
> +                      u32 *enable, u32 *threshold, u32 num)
>  {
> -       u32 ie_words = plic->num_src / 32 + 1;
> -
> -       for (u32 i = 0; i < ie_words; i++)
> +       for (u32 i = 0; i < num; i++)
>                 enable[i] = plic_get_ie(plic, context_id, i);
>
>         *threshold = plic_get_thresh(plic, context_id);
>  }
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold)
> +                         const u32 *enable, u32 threshold, u32 num)
>  {
> -       u32 ie_words = plic->num_src / 32 + 1;
> -
> -       for (u32 i = 0; i < ie_words; i++)
> +       for (u32 i = 0; i < num; i++)
>                 plic_set_ie(plic, context_id, i, enable[i]);
>
>         plic_set_thresh(plic, context_id, threshold);
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 46d336f..f6f7df1 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -78,7 +78,7 @@ static u32 plic_threshold;
>
>  static void sun20i_d1_plic_save(void)
>  {
> -       fdt_plic_context_save(true, plic_sie, &plic_threshold);
> +       fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
>         fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
> @@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
>         fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> -       fdt_plic_context_restore(true, plic_sie, plic_threshold);
> +       fdt_plic_context_restore(true, plic_sie, plic_threshold,
> +                                PLIC_IE_WORDS);
>  }
>
>  /*
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Regards,
Anup


From anup at brainfault.org  Thu Dec  8 21:51:17 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 11:21:17 +0530
Subject: [PATCH] platform: generic: Make use of fdt_match_node()
In-Reply-To: <20221207161419.10259-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207161419.10259-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy3ZOs7VttrLFMvS+hv2Rf0mMivkWvEMm7MB-Tv5crxK-Q@mail.gmail.com>

On Wed, Dec 7, 2022 at 9:44 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
>
> It makes sense to use fdt_match_node() instead of fdt_find_match()
> in fw_platform_lookup_special() as we already have the start offset
> to search from.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> Based on the feedback provided by Anup [0].
>
> [0] https://patchwork.ozlabs.org/project/opensbi/patch/20221130220825.193693-7-prabhakar.mahadev-lad.rj at bp.renesas.com/#3015759
> ---
>  platform/generic/platform.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 595b0fd..bfe15f0 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -34,17 +34,17 @@ static const struct fdt_match *generic_plat_match = NULL;
>
>  static void fw_platform_lookup_special(void *fdt, int root_offset)
>  {
> -       int pos, noff;
>         const struct platform_override *plat;
>         const struct fdt_match *match;
> +       int pos;
>
>         for (pos = 0; pos < platform_override_modules_size; pos++) {
>                 plat = platform_override_modules[pos];
>                 if (!plat->match_table)
>                         continue;
>
> -               noff = fdt_find_match(fdt, -1, plat->match_table, &match);
> -               if (noff < 0)
> +               match = fdt_match_node(fdt, root_offset, plat->match_table);
> +               if (!match)
>                         continue;
>
>                 generic_plat = plat;
> --
> 2.17.1
>


From hchauhan at ventanamicro.com  Thu Dec  8 22:13:35 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Fri,  9 Dec 2022 11:43:35 +0530
Subject: [PATCH v2] scripts: use env to invoke bash
Message-ID: <20221209061335.1326839-1-hchauhan@ventanamicro.com>

Not all systems have bash at a fixed location like /bin/bash.
FreeBSD, for example, would typically have it at /usr/local/bin/bash.
When building OpenSBI on freebsd system, the build breaks.

Its advisable to use: #!/usr/bin/env bash

[v2] In this version:
* Change remaining two scripts to use env

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 scripts/carray.sh                | 2 +-
 scripts/create-binary-archive.sh | 2 +-
 scripts/d2c.sh                   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/scripts/carray.sh b/scripts/carray.sh
index 0c52bd6..13f9d36 100755
--- a/scripts/carray.sh
+++ b/scripts/carray.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 function usage()
 {
diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
index 261a45a..63781e1 100755
--- a/scripts/create-binary-archive.sh
+++ b/scripts/create-binary-archive.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 function usage()
 {
diff --git a/scripts/d2c.sh b/scripts/d2c.sh
index 33a3ccf..c411fcd 100755
--- a/scripts/d2c.sh
+++ b/scripts/d2c.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/usr/bin/env bash
 
 function usage()
 {
-- 
2.38.1



From uwu at icenowy.me  Thu Dec  8 23:01:17 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Fri,  9 Dec 2022 15:01:17 +0800
Subject: [PATCH 0/3] T-Head C9xx CLINT support
Message-ID: <20221209070120.944152-1-uwu@icenowy.me>

This patchset tries to add support for T-Head C9xx's CLINT to OpenSBI.

For MSWI part, the T-Head CLINT is fully compatible with the SiFive one,
so it's just simply adding a compatible string.

For MTIMER part, it's first needed to implement a quirk for
MTIME-less timer (thus only MTIMECMP is present), then the compatible
string is added and bound to the quirk.

To instantiate such a T-Head flavored CLINT via DT, this patchset
depends on DT bindings declared in [1].

[1] https://www.spinics.net/lists/kernel/msg4597447.html

Icenowy Zheng (3):
  lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
  lib: utils/timer: mtimer: add a quirk for lacking mtime register
  lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

 include/sbi_utils/timer/aclint_mtimer.h |  1 +
 lib/utils/ipi/fdt_ipi_mswi.c            |  1 +
 lib/utils/timer/aclint_mtimer.c         | 19 ++++++++++----
 lib/utils/timer/fdt_timer_mtimer.c      | 35 ++++++++++++++++++-------
 4 files changed, 42 insertions(+), 14 deletions(-)

-- 
2.38.1



From uwu at icenowy.me  Thu Dec  8 23:01:18 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Fri,  9 Dec 2022 15:01:18 +0800
Subject: [PATCH 1/3] lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
In-Reply-To: <20221209070120.944152-1-uwu@icenowy.me>
References: <20221209070120.944152-1-uwu@icenowy.me>
Message-ID: <20221209070120.944152-2-uwu@icenowy.me>

Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
MSWI part is compliant.

Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
the same codepath with SiFive CLINT.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index 0176941..4dc91f2 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const unsigned long clint_offset = CLINT_MSWI_OFFSET;
 static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
+	{ .compatible = "thead,c900-clint", .data = &clint_offset },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.38.1



From uwu at icenowy.me  Thu Dec  8 23:01:20 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Fri,  9 Dec 2022 15:01:20 +0800
Subject: [PATCH 3/3] lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible
In-Reply-To: <20221209070120.944152-1-uwu@icenowy.me>
References: <20221209070120.944152-1-uwu@icenowy.me>
Message-ID: <20221209070120.944152-4-uwu@icenowy.me>

As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
 lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 7ec3907..6a85326 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -125,9 +125,15 @@ static const struct timer_mtimer_quirks sifive_clint_quirks = {
 	.has_64bit_mmio	= true,
 };
 
+static const struct timer_mtimer_quirks thead_clint_quirks = {
+	.mtime_offset	= CLINT_MTIMER_OFFSET,
+	.without_mtime  = true,
+};
+
 static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
+	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.38.1



From uwu at icenowy.me  Thu Dec  8 23:01:19 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Fri,  9 Dec 2022 15:01:19 +0800
Subject: [PATCH 2/3] lib: utils/timer: mtimer: add a quirk for lacking mtime register
In-Reply-To: <20221209070120.944152-1-uwu@icenowy.me>
References: <20221209070120.944152-1-uwu@icenowy.me>
Message-ID: <20221209070120.944152-3-uwu@icenowy.me>

T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
 include/sbi_utils/timer/aclint_mtimer.h |  1 +
 lib/utils/timer/aclint_mtimer.c         | 19 +++++++++++-----
 lib/utils/timer/fdt_timer_mtimer.c      | 29 +++++++++++++++++--------
 3 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/include/sbi_utils/timer/aclint_mtimer.h b/include/sbi_utils/timer/aclint_mtimer.h
index 6ab8799..9724f53 100644
--- a/include/sbi_utils/timer/aclint_mtimer.h
+++ b/include/sbi_utils/timer/aclint_mtimer.h
@@ -35,6 +35,7 @@ struct aclint_mtimer_data {
 	u32 hart_count;
 	bool has_64bit_mmio;
 	bool has_shared_mtime;
+	bool has_mtime;
 	/* Private details (initialized and used by ACLINT MTIMER library) */
 	struct aclint_mtimer_data *time_delta_reference;
 	unsigned long time_delta_computed;
diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
index 3f00c21..f99857b 100644
--- a/lib/utils/timer/aclint_mtimer.c
+++ b/lib/utils/timer/aclint_mtimer.c
@@ -95,7 +95,7 @@ void aclint_mtimer_sync(struct aclint_mtimer_data *mt)
 	struct aclint_mtimer_data *reference;
 
 	/* Sync-up non-shared MTIME if reference is available */
-	if (mt->has_shared_mtime || !mt->time_delta_reference)
+	if (!mt->has_mtime || mt->has_shared_mtime || !mt->time_delta_reference)
 		return;
 
 	reference = mt->time_delta_reference;
@@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
 	int rc;
 
 	/* Sanity checks */
-	if (!mt || !mt->mtime_size ||
+	if (!mt || (mt->has_mtime && !mt->mtime_size) ||
 	    (mt->hart_count && !mt->mtimecmp_size) ||
-	    (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
-	    (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
+	    (mt->has_mtime && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
+	    (mt->has_mtime && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
 	    (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
 	    (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
 	    (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
@@ -179,7 +179,16 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
 		mtimer_hartid2data[mt->first_hartid + i] = mt;
 
 	/* Add MTIMER regions to the root domain */
-	if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
+	if (!mt->has_mtime) {
+		rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
+						mt->mtimecmp_size, MTIMER_REGION_ALIGN,
+						SBI_DOMAIN_MEMREGION_MMIO);
+		if (rc)
+			return rc;
+
+		/* Disable reading mtime when mtime is not available */
+		mtimer.timer_value = NULL;
+	} else if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
 		rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
 					mt->mtime_size + mt->mtimecmp_size,
 					MTIMER_REGION_ALIGN,
diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 7b8546b..7ec3907 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -18,6 +18,7 @@
 struct timer_mtimer_quirks {
 	unsigned int	mtime_offset;
 	bool		has_64bit_mmio;
+	bool		without_mtime;
 };
 
 static unsigned long mtimer_count = 0;
@@ -53,14 +54,19 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		/* Set CLINT addresses */
 		mt->mtimecmp_addr = addr[0] + ACLINT_DEFAULT_MTIMECMP_OFFSET;
 		mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
-		mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
-		mt->mtime_size = size[0] - mt->mtimecmp_size;
+		if (!quirks->without_mtime) {
+			mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
+			mt->mtime_size = size[0] - mt->mtimecmp_size;
+		}
 		/* Adjust MTIMER address and size for CLINT device */
-		mt->mtime_addr += quirks->mtime_offset;
+		if (!quirks->without_mtime) {
+			mt->mtime_addr += quirks->mtime_offset;
+			mt->mtime_size -= quirks->mtime_offset;
+		}
 		mt->mtimecmp_addr += quirks->mtime_offset;
-		mt->mtime_size -= quirks->mtime_offset;
 		/* Apply additional CLINT quirks */
 		mt->has_64bit_mmio = quirks->has_64bit_mmio;
+		mt->has_mtime = !quirks->without_mtime;
 	} else { /* RISC-V ACLINT MTIMER */
 		/* Set ACLINT MTIMER addresses */
 		mt->mtime_addr = addr[0];
@@ -70,12 +76,17 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 	}
 
 	/* Check if MTIMER device has shared MTIME address */
-	mt->has_shared_mtime = false;
-	for (i = 0; i < mtimer_count; i++) {
-		if (mtimer[i].mtime_addr == mt->mtime_addr) {
-			mt->has_shared_mtime = true;
-			break;
+	if (mt->has_mtime) {
+		mt->has_shared_mtime = false;
+		for (i = 0; i < mtimer_count; i++) {
+			if (mtimer[i].mtime_addr == mt->mtime_addr) {
+				mt->has_shared_mtime = true;
+				break;
+			}
 		}
+	} else {
+		/* Assume shared time CSR */
+		mt->has_shared_mtime = true;
 	}
 
 	/* Initialize the MTIMER device */
-- 
2.38.1



From anup at brainfault.org  Fri Dec  9 00:41:01 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 14:11:01 +0530
Subject: [PATCH v2 1/3] lib: fix is_region_valid()
In-Reply-To: <20221208011421.11624-2-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com> <20221208011421.11624-2-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy0M1gnmjv6YnPbU=5LB+ZTyRS+KGB3+pRbTKZEJuwPm-g@mail.gmail.com>

On Thu, Dec 8, 2022 at 6:44 AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> For 'reg->order == __riscv_xlen' the term 'BIT(reg->order)' is undefined.
>
> Addresses-Coverity-ID: 1529706 ("Bad bit shift operation")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> v2:
>         Make the logical constraint a bit easier to read.
> ---
>  lib/sbi/sbi_domain.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3302213..3205595 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -149,7 +149,7 @@ static bool is_region_valid(const struct sbi_domain_memregion *reg)
>         if (reg->order == __riscv_xlen && reg->base != 0)
>                 return FALSE;
>
> -       if (reg->base & (BIT(reg->order) - 1))
> +       if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
>                 return FALSE;
>
>         return TRUE;
> --
> 2.37.2
>


From anup at brainfault.org  Fri Dec  9 00:41:23 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 14:11:23 +0530
Subject: [PATCH v2 2/3] lib: fix __fdt_parse_region()
In-Reply-To: <20221208011421.11624-3-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com> <20221208011421.11624-3-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy25aTcMbw0m+wehcd13G2-LfUPV__5NZaA8GB4+2TpaZg@mail.gmail.com>

On Thu, Dec 8, 2022 at 6:44 AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> If fdt_getprop() returns NULL, this indicates an error. In this case lenp
> is set to an error code. But even if lenp = 0 we should not continue.
>
> If fdt_getprop() returns a wider value than we expect this is a separate
> error condition.
>
> In both cases the device-tree is invalid.
>
> Addresses-Coverity-ID: 1529703 ("Dereference after null check")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> v2:
>         correct the len requirements
> ---
>  lib/utils/fdt/fdt_domain.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
> index bd0eec3..0568603 100644
> --- a/lib/utils/fdt/fdt_domain.c
> +++ b/lib/utils/fdt/fdt_domain.c
> @@ -246,7 +246,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>
>         /* Read "base" DT property */
>         val = fdt_getprop(fdt, region_offset, "base", &len);
> -       if (!val && len >= 8)
> +       if (!val || len != 8)
>                 return SBI_EINVAL;
>         val64 = fdt32_to_cpu(val[0]);
>         val64 = (val64 << 32) | fdt32_to_cpu(val[1]);
> @@ -254,7 +254,7 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>
>         /* Read "order" DT property */
>         val = fdt_getprop(fdt, region_offset, "order", &len);
> -       if (!val && len >= 4)
> +       if (!val || len != 4)
>                 return SBI_EINVAL;
>         val32 = fdt32_to_cpu(*val);
>         if (val32 < 3 || __riscv_xlen < val32)
> --
> 2.37.2
>


From anup at brainfault.org  Fri Dec  9 00:41:49 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 14:11:49 +0530
Subject: [PATCH v2 3/3] lib: fix irqchip_plic_update_hartid_table
In-Reply-To: <20221208011421.11624-4-heinrich.schuchardt@canonical.com>
References: <20221208011421.11624-1-heinrich.schuchardt@canonical.com> <20221208011421.11624-4-heinrich.schuchardt@canonical.com>
Message-ID: <CAAhSdy2Q8p3qFNX-Xqs2ph0MXeVTjsYA_E-UbFJNcJ5p4mL56w@mail.gmail.com>

On Thu, Dec 8, 2022 at 6:44 AM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> After determining cpu_offset we have to check this value.
>
> Addresses-Coverity-ID: 1529706 ("Logically dead code")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> Reviewed-by: Xiang W <wxjstz at 126.com>
> Reviewed-by: Atish Patra <atishp at rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
> v2:
>         add reviewed-by lines
> ---
>  lib/utils/irqchip/fdt_irqchip_plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..fe08836 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -86,7 +86,7 @@ static int irqchip_plic_update_hartid_table(void *fdt, int nodeoff,
>                         continue;
>
>                 cpu_offset = fdt_parent_offset(fdt, cpu_intc_offset);
> -               if (cpu_intc_offset < 0)
> +               if (cpu_offset < 0)
>                         continue;
>
>                 err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> --
> 2.37.2
>


From anup at brainfault.org  Fri Dec  9 00:56:22 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 14:26:22 +0530
Subject: [PATCH] lib: sbi: Synchronize PMP settings with virtual memory system
In-Reply-To: <20221205164231.170617-1-hchauhan@ventanamicro.com>
References: <20221205164231.170617-1-hchauhan@ventanamicro.com>
Message-ID: <CAAhSdy2gGN0a0Zo9gbtfM0AVPJyRUqi00XczVmeedur5gut_4A@mail.gmail.com>

On Mon, Dec 5, 2022 at 10:13 PM Himanshu Chauhan
<hchauhan at ventanamicro.com> wrote:
>
> As per section 3.7.2 of RISC-V Privileged Specification,
> PMP settings must be synchronized with the virtual memory
> system after PMP settings have been written.
>
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_hart.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index dacab1a..5447c52 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -22,6 +22,7 @@
>  #include <sbi/sbi_pmu.h>
>  #include <sbi/sbi_string.h>
>  #include <sbi/sbi_trap.h>
> +#include <sbi/sbi_hfence.h>
>
>  extern void __sbi_expected_trap(void);
>  extern void __sbi_expected_trap_hext(void);
> @@ -321,6 +322,27 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
>                 }
>         }
>
> +       /*
> +        * As per section 3.7.2 of privileged specification v1.12,
> +        * virtual address translations can be speculatively performed
> +        * (even before actual access). These, along with PMP traslations,
> +        * can be cached. This can pose a problem with CPU hotplug
> +        * and non-retentive suspend scenario because PMP states are
> +        * not preserved.
> +        * It is advisable to flush the caching structures under such
> +        * conditions.
> +        */
> +       if (misa_extension('S')) {
> +               __asm__ __volatile__("sfence.vma");
> +
> +               /*
> +                * If hypervisor mode is supported, flush caching
> +                * structures in guest mode too.
> +                */
> +               if (misa_extension('H'))
> +                       __sbi_hfence_gvma_all();
> +       }
> +
>         return 0;
>  }
>
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec  9 01:04:04 2022
From: anup at brainfault.org (Anup Patel)
Date: Fri, 9 Dec 2022 14:34:04 +0530
Subject: [PATCH v4 5/5] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <20221207163233.10656-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221207163233.10656-6-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy0N+a_VtiELJ20gRrEKWgmP5Eh8Z7XmWAwJDMkpcT84PQ@mail.gmail.com>

On Wed, Dec 7, 2022 at 10:03 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
>
> This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> v3->v4
> * Added complete list of IP blocks
>
> v2->v3
> * Updated doc with new build command
>
> RFC->v2
> * Updated doc
> ---
>  docs/platform/platform.md       |   5 +
>  docs/platform/renesas-rzfive.md | 160 ++++++++++++++++++++++++++++++++
>  2 files changed, 165 insertions(+)
>  create mode 100644 docs/platform/renesas-rzfive.md
>
> diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> index f291931..4504d87 100644
> --- a/docs/platform/platform.md
> +++ b/docs/platform/platform.md
> @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
>    processor based SOCs. More details on this platform can be found in the
>    file *[shakti_cclass.md]*.
>
> +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
> +  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
> +  be found in the file *[renesas-rzfive.md]*.
> +
>  The code for these supported platforms can be used as example to implement
>  support for other platforms. The *platform/template* directory also provides
>  template files for implementing support for a new platform. The *objects.mk*,
> @@ -54,3 +58,4 @@ comments to facilitate the implementation.
>  [spike.md]: spike.md
>  [fpga-openpiton.md]: fpga-openpiton.md
>  [shakti_cclass.md]: shakti_cclass.md
> +[renesas-rzfive.md]: renesas-rzfive.md

Add an entry of your platform in docs/platform/generic.md since you are
using generic platform.

> diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
> new file mode 100644
> index 0000000..41edf36
> --- /dev/null
> +++ b/docs/platform/renesas-rzfive.md
> @@ -0,0 +1,160 @@
> +Renesas RZ/Five SoC (R9A07G043F) Platform
> +=========================================
> +The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
> +1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
> +- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits
> +- System RAM (RAM of 128 Kbytes (ECC))
> +- SPI Multi I/O Bus Controller 1ch
> +- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch
> +- Serial Sound Interface (SSI) 4ch
> +- Sampling Rate Converter (SRC) 1ch
> +- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only)
> +- Gigabit Ethernet Interface (GbE) 2ch
> +- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant)
> +- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits ? 8 channels, 32 bits ? 1 channel)
> +- Port Output Enable 3 (POE3)
> +- Watchdog Timer (WDT) 1ch
> +- General Timer (GTM) 3ch (32bits)
> +- I2C Bus Interface (I2C) 4ch
> +- Serial Communication Interface with FIFO (SCIFA) 5ch
> +- Serial Communication Interface (SCI) 2ch
> +- Renesas Serial Peripheral Interface (RSPI) 3ch
> +- A/D Converter (ADC) 2ch
> +making it ideal for applications such as entry-class social infrastructure
> +gateway control and industrial gateway control. More details can be found at
> +below link [0].
> +
> +[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> +
> +To build platform specific library and firmwares, provide the
> +*PLATFORM=generic* parameter to the top level make command.
> +
> +Platform Options
> +----------------
> +
> +The Renesas RZ/Five platform does not have any platform-specific options.
> +
> +Building Renesas RZ/Five Platform
> +---------------------------------
> +
> +```
> +make PLATFORM=generic
> +```
> +
> +DTS Example: (RZ/Five AX45MP)
> +-----------------------------
> +
> +```
> +       compatible = "renesas,r9a07g043";
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               timebase-frequency = <12000000>;
> +
> +               cpu0: cpu at 0 {
> +                       compatible = "andestech,ax45mp", "riscv";
> +                       device_type = "cpu";
> +                       reg = <0x0>;
> +                       status = "okay";
> +                       riscv,isa = "rv64imafdc";
> +                       mmu-type = "riscv,sv39";
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <0x40>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <0x40>;
> +                       clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
> +
> +                       cpu0_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               ranges;
> +
> +               scif0: serial at 1004b800 {
> +                       compatible = "renesas,scif-r9a07g043",
> +                                    "renesas,scif-r9a07g044";
> +                       reg = <0 0x1004b800 0 0x400>;
> +                       interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <414 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <415 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <413 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <416 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "eri", "rxi", "txi",
> +                                         "bri", "dri", "tei";
> +                       clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> +                       clock-names = "fck";
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> +                       status = "disabled";
> +               };
> +
> +               cpg: clock-controller at 11010000 {
> +                       compatible = "renesas,r9a07g043-cpg";
> +                       reg = <0 0x11010000 0 0x10000>;
> +                       clocks = <&extal_clk>;
> +                       clock-names = "extal";
> +                       #clock-cells = <2>;
> +                       #reset-cells = <1>;
> +                       #power-domain-cells = <0>;
> +               };
> +
> +               sysc: system-controller at 11020000 {
> +                       compatible = "renesas,r9a07g043-sysc";
> +                       reg = <0 0x11020000 0 0x10000>;
> +                       status = "disabled";
> +               };
> +
> +               pinctrl: pinctrl at 11030000 {
> +                       compatible = "renesas,r9a07g043-pinctrl";
> +                       reg = <0 0x11030000 0 0x10000>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       #interrupt-cells = <2>;
> +                       interrupt-controller;
> +                       gpio-ranges = <&pinctrl 0 0 152>;
> +                       clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg R9A07G043_GPIO_RSTN>,
> +                                <&cpg R9A07G043_GPIO_PORT_RESETN>,
> +                                <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> +               };
> +
> +               plmt0: plmt0 at 110c0000 {
> +                       compatible = "andestech,plmt0", "riscv,plmt0";
> +                       reg = <0x0 0x110c0000 0x0 0x10000>;
> +                       interrupts-extended = <&cpu0_intc 7>;
> +               };
> +
> +               plic: interrupt-controller at 12c00000 {
> +                       compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> +                       #interrupt-cells = <2>;
> +                       #address-cells = <0>;
> +                       riscv,ndev = <511>;
> +                       interrupt-controller;
> +                       reg = <0x0 0x12c00000 0x0 0x400000>;
> +                       clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> +                       interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> +               };
> +
> +               plicsw: interrupt-controller at 13000000 {
> +                       compatible = "andestech,plicsw";
> +                       reg = <0x0 0x13000000 0x0 0x400000>;
> +                       interrupts-extended = <&cpu0_intc 3>;
> +                       interrupt-controller;
> +                       #address-cells = <2>;
> +                       #interrupt-cells = <2>;
> +               };
> +       };
> +```
> --
> 2.17.1
>

Otherwise, it looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup


From wxjstz at 126.com  Fri Dec  9 01:11:34 2022
From: wxjstz at 126.com (Xiang W)
Date: Fri, 09 Dec 2022 17:11:34 +0800
Subject: [PATCH v2] scripts: use env to invoke bash
In-Reply-To: <20221209061335.1326839-1-hchauhan@ventanamicro.com>
References: <20221209061335.1326839-1-hchauhan@ventanamicro.com>
Message-ID: <bb27feef21e1ca3d3e4b843400a6df03f85e5592.camel@126.com>

? 2022-12-09???? 11:43 +0530?Himanshu Chauhan???
> Not all systems have bash at a fixed location like /bin/bash.
> FreeBSD, for example, would typically have it at /usr/local/bin/bash.
> When building OpenSBI on freebsd system, the build breaks.
> 
> Its advisable to use: #!/usr/bin/env bash
> 
> [v2] In this version:
> * Change remaining two scripts to use env
> 
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
LGTM

Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?scripts/carray.sh??????????????? | 2 +-
> ?scripts/create-binary-archive.sh | 2 +-
> ?scripts/d2c.sh?????????????????? | 2 +-
> ?3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/scripts/carray.sh b/scripts/carray.sh
> index 0c52bd6..13f9d36 100755
> --- a/scripts/carray.sh
> +++ b/scripts/carray.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
> ?
> ?function usage()
> ?{
> diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
> index 261a45a..63781e1 100755
> --- a/scripts/create-binary-archive.sh
> +++ b/scripts/create-binary-archive.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
> ?
> ?function usage()
> ?{
> diff --git a/scripts/d2c.sh b/scripts/d2c.sh
> index 33a3ccf..c411fcd 100755
> --- a/scripts/d2c.sh
> +++ b/scripts/d2c.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
> ?
> ?function usage()
> ?{
> -- 
> 2.38.1
> 
> 




From prabhakar.csengg at gmail.com  Fri Dec  9 03:06:00 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Fri, 9 Dec 2022 11:06:00 +0000
Subject: [PATCH v4 5/5] docs: platform: Add documentation for Renesas
 RZ/Five SoC
In-Reply-To: <CAAhSdy0N+a_VtiELJ20gRrEKWgmP5Eh8Z7XmWAwJDMkpcT84PQ@mail.gmail.com>
References: <20221207163233.10656-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20221207163233.10656-6-prabhakar.mahadev-lad.rj@bp.renesas.com> <CAAhSdy0N+a_VtiELJ20gRrEKWgmP5Eh8Z7XmWAwJDMkpcT84PQ@mail.gmail.com>
Message-ID: <CA+V-a8tr_aOKeqg4BSjJ5Wif++xQpvAgu_p89yY-rLyPEpqGgg@mail.gmail.com>

Hi Anup,

Thank you for the review.

On Fri, Dec 9, 2022 at 9:04 AM Anup Patel <anup at brainfault.org> wrote:
>
> On Wed, Dec 7, 2022 at 10:03 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
> >
> > This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > v3->v4
> > * Added complete list of IP blocks
> >
> > v2->v3
> > * Updated doc with new build command
> >
> > RFC->v2
> > * Updated doc
> > ---
> >  docs/platform/platform.md       |   5 +
> >  docs/platform/renesas-rzfive.md | 160 ++++++++++++++++++++++++++++++++
> >  2 files changed, 165 insertions(+)
> >  create mode 100644 docs/platform/renesas-rzfive.md
> >
> > diff --git a/docs/platform/platform.md b/docs/platform/platform.md
> > index f291931..4504d87 100644
> > --- a/docs/platform/platform.md
> > +++ b/docs/platform/platform.md
> > @@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
> >    processor based SOCs. More details on this platform can be found in the
> >    file *[shakti_cclass.md]*.
> >
> > +* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
> > +  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
> > +  be found in the file *[renesas-rzfive.md]*.
> > +
> >  The code for these supported platforms can be used as example to implement
> >  support for other platforms. The *platform/template* directory also provides
> >  template files for implementing support for a new platform. The *objects.mk*,
> > @@ -54,3 +58,4 @@ comments to facilitate the implementation.
> >  [spike.md]: spike.md
> >  [fpga-openpiton.md]: fpga-openpiton.md
> >  [shakti_cclass.md]: shakti_cclass.md
> > +[renesas-rzfive.md]: renesas-rzfive.md
>
> Add an entry of your platform in docs/platform/generic.md since you are
> using generic platform.
>
Sure will do and re-spin a v5.

Cheers,
Prabhakar


From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:06 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:06 +0000
Subject: [PATCH v5 0/5] Add support for Renesas RZ/Five SoC
Message-ID: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
is equipped with AX45MP AndesCore). Platform supports DT based probing.

Linux support is currently being upstreamed the latest patchset can be
found at [0](currently in linux-next, DT bindings can be seen here)

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

- PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
- PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
  and is used in a similar manner as compared Andes AE350 [1]
  [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
- SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79

Note:
- The PMA implementation is still in discussion [1] once its decided
corresponding patch to OpenSBI will be added to reserve the memory nodes
and vendor specific SBI EXT.
- U-boot from BSP release wont work with these patches, it requires additional
  patches (happy to share the u-boot branch if anyone wants to test this patchset)
- Patches apply on top of [2]

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
[2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/

v4->v5
* Included RB tag from Anup for patch 5/5
* Updated generic.md to include RZ/Five SoC

v3->v4
* Included RB tags
* Updated doc
* Sorted compatible string list
* Fixed minor issues related to scif driver

v2->v3
* Switched to generic platform
* Dropped all vendor specific SBI EXT
* Fixed review comments pointed by Bin for SCIF driver
* Updated doc

RFC->v2
* Fixed comments pointed by Xiang W
* Included RB tag from Yu Chien Peter Lin for patch #3

RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (5):
  lib: utils: serial: Add Renesas SCIF driver
  lib: utils: serial: Add FDT driver for Renesas SCIF
  lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
  platform: generic: Add Renesas RZ/Five initial support
  docs: platform: Add documentation for Renesas RZ/Five SoC

 docs/platform/generic.md                   |   2 +
 docs/platform/platform.md                  |   5 +
 docs/platform/renesas-rzfive.md            | 160 +++++++++++++++++++++
 include/sbi_utils/fdt/fdt_helper.h         |   3 +
 include/sbi_utils/serial/renesas-scif.h    |  11 ++
 lib/utils/fdt/fdt_helper.c                 |  11 ++
 lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
 lib/utils/serial/Kconfig                   |   9 ++
 lib/utils/serial/fdt_serial_renesas_scif.c |  31 ++++
 lib/utils/serial/objects.mk                |   4 +
 lib/utils/serial/renesas_scif.c            | 116 +++++++++++++++
 platform/generic/Kconfig                   |   4 +
 platform/generic/configs/defconfig         |   2 +
 platform/generic/renesas/rzfive/objects.mk |   8 ++
 platform/generic/renesas/rzfive/rzfive.c   |  17 +++
 15 files changed, 385 insertions(+), 1 deletion(-)
 create mode 100644 docs/platform/renesas-rzfive.md
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
 create mode 100644 lib/utils/serial/renesas_scif.c
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:07 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:07 +0000
Subject: [PATCH v5 1/5] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221210103011.7814-2-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add Renesas SCIF driver.

Based on a patch in the BSP by Takeki Hamada
<takeki.hamada.ak at bp.renesas.com>
Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
v4->v5
* No change

v3->v4
* Dropped returning from void func
* Dropped unnecessary volatile variable

v2->v3
* Fixed review comments pointed by Bin

RFC->v2
* Fixed comments pointed by Xiang W
---
 include/sbi_utils/serial/renesas-scif.h |  11 +++
 lib/utils/serial/Kconfig                |   4 +
 lib/utils/serial/objects.mk             |   1 +
 lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
 4 files changed, 132 insertions(+)
 create mode 100644 include/sbi_utils/serial/renesas-scif.h
 create mode 100644 lib/utils/serial/renesas_scif.c

diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
new file mode 100644
index 0000000..0002a1a
--- /dev/null
+++ b/include/sbi_utils/serial/renesas-scif.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#ifndef __SERIAL_RENESAS_SCIF_H__
+#define __SERIAL_RENESAS_SCIF_H__
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
+
+#endif /* __SERIAL_RENESAS_SCIF_H__ */
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index da549a7..f6ed803 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -59,6 +59,10 @@ config SERIAL_GAISLER
 	bool "Gaisler UART support"
 	default n
 
+config SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF support"
+	default n
+
 config SERIAL_SHAKTI
 	bool "Shakti UART support"
 	default n
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 98f3f9a..6520424 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
 
 libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
+libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
 libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
 libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
new file mode 100644
index 0000000..cbe9db4
--- /dev/null
+++ b/lib/utils/serial/renesas_scif.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_console.h>
+#include <sbi/sbi_timer.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+/* clang-format off */
+
+#define SCIF_REG_SMR		0x0
+#define SCIF_REG_BRR		0x2
+#define SCIF_REG_SCR		0x4
+#define SCIF_REG_FTDR		0x6
+#define SCIF_REG_FSR		0x8
+#define SCIF_REG_FCR		0xc
+#define SCIF_REG_LSR		0x12
+#define SCIF_REG_SEMR		0x14
+
+#define SCIF_FCR_RFRST		0x2 /* Reset assert receive-FIFO (bit[1]) */
+#define SCIF_FCR_TFRST		0x4 /* Reset assert transmit-FIFO(bit[2]) */
+
+#define SCIF_FCR_RST_ASSRT_RFTF	(SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
+#define SCIF_FCR_RST_NGATE_RFTF	0x0 /* Reset negate tx-FIFO & rx-FIFO */
+
+#define SCIF_SCR_RE		0x10 /* Enable receive (bit[4]) */
+#define SCIF_SCR_TE		0x20 /* Enable transmit(bit[5]) */
+#define SCIF_SCR_RCV_TRN_EN	(SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
+#define SCIF_SCR_RCV_TRN_DIS	0x0 /* Disable receive & transmit */
+
+#define SCIF_FSR_ER		0x80 /* Receive error flag */
+#define SCIF_FSR_TEND		0x40 /* Transmit End Flag */
+#define SCIF_FSR_TDFE		0x20 /* Transmit FIFO Data Empty Flag */
+#define SCIF_FSR_BRK		0x10 /* Detect break flag */
+#define SCIF_FSR_DR		0x1  /* Receive data ready flag */
+
+#define SCIF_FSR_TXD_CHK	(SCIF_FSR_TEND | SCIF_FSR_TDFE)
+
+#define SCIF_SEMR_MDDRS		0x10 /* MDDR access enable */
+
+#define SCIF_REG_8BIT(reg)	((reg == SCIF_REG_BRR) || \
+				 (reg == SCIF_REG_FTDR) || \
+				 (reg == SCIF_REG_SEMR))
+
+#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
+
+/* clang-format on */
+
+static volatile char *scif_base;
+
+static u32 get_reg(u32 offset)
+{
+	if (SCIF_REG_8BIT(offset))
+		return readb(scif_base + offset);
+
+	return readw(scif_base + offset);
+}
+
+static void set_reg(u32 offset, u32 val)
+{
+	if (SCIF_REG_8BIT(offset))
+		writeb(val, scif_base + offset);
+	else
+		writew(val, scif_base + offset);
+}
+
+static void renesas_scif_putc(char ch)
+{
+	uint16_t reg;
+
+	while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
+		;
+
+	set_reg(SCIF_REG_FTDR, ch);
+	reg = get_reg(SCIF_REG_FSR);
+	reg &= ~SCIF_FSR_TXD_CHK;
+	set_reg(SCIF_REG_FSR, reg);
+}
+
+static struct sbi_console_device renesas_scif_console = {
+	.name		= "renesas_scif",
+	.console_putc	= renesas_scif_putc,
+};
+
+int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
+{
+	uint16_t data16;
+
+	scif_base = (volatile char *)base;
+
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
+
+	data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
+	set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
+
+	data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
+	set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
+
+	set_reg(SCIF_REG_SCR, 0x0);
+
+	set_reg(SCIF_REG_SMR, 0x0);
+
+	data16 = get_reg(SCIF_REG_SEMR);
+	set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
+	set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
+
+	set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
+	set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
+
+	sbi_console_set_device(&renesas_scif_console);
+
+	return 0;
+}
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:09 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:09 +0000
Subject: [PATCH v5 3/5] lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221210103011.7814-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add compatible string for Andestech NCEPLIC100 found on Renesas RZ/Five SoC
which is equipped with AX45MP AndesCore.

While at it drop the comma after the sentinel as it does not make sense to
have a comma after a sentinel, as any new elements must be added before the
sentinel.

dts example (Single-core AX45MP):

    soc: soc {
          ....
          plic: interrupt-controller at 12c00000 {
              compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
              #interrupt-cells = <2>;
              #address-cells = <0>;
              riscv,ndev = <511>;
              interrupt-controller;
              reg = <0x0 0x12c00000 0 0x400000>;
              clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
              power-domains = <&cpg>;
              resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
              interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
          };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
Reviewed-by: Bin Meng <bmeng at tinylab.org>
---
v4->v5
* No change

v3->v4
* Sorted compatible string list

v2->v3
* Included RB tags

RFC->v2
* No change

DT binding [0]
[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml?h=next-20221111#n56
---
 lib/utils/irqchip/fdt_irqchip_plic.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index fe08836..8e90fa7 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -159,11 +159,12 @@ void thead_plic_restore(void)
 }
 
 static const struct fdt_match irqchip_plic_match[] = {
+	{ .compatible = "andestech,nceplic100" },
 	{ .compatible = "riscv,plic0" },
 	{ .compatible = "sifive,plic-1.0.0" },
 	{ .compatible = "thead,c900-plic",
 	  .data = thead_plic_plat_init },
-	{ },
+	{ /* sentinel */ }
 };
 
 struct fdt_irqchip fdt_irqchip_plic = {
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:08 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:08 +0000
Subject: [PATCH v5 2/5] lib: utils: serial: Add FDT driver for Renesas SCIF
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221210103011.7814-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add FDT driver for Renesas SCIF.

    dts example:

    soc: soc {
          ....
            scif0: serial at 1004b800 {
                    compatible = "renesas,scif-r9a07g043",
                                 "renesas,scif-r9a07g044";
                    reg = <0 0x1004b800 0 0x400>;
                    interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
                                 <414 IRQ_TYPE_LEVEL_HIGH>,
                                 <415 IRQ_TYPE_LEVEL_HIGH>,
                                 <413 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>,
                                 <416 IRQ_TYPE_LEVEL_HIGH>;
                    interrupt-names = "eri", "rxi", "txi",
                                      "bri", "dri", "tei";
                    clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
                    clock-names = "fck";
                    power-domains = <&cpg>;
                    resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
                    status = "disabled";
            };
          ....
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
v4->v5
* No change

v3->v4
* Included RB tag

v2->v3
* No change

RFC->v2
* Dropped DEFAULT_RENESAS_SCIF_REG_SHIFT and
  DEFAULT_RENESAS_SCIF_REG_IO_WIDTH macros.

DT binding [0].

[0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/serial/renesas,scif.yaml?h=next-20221111#n80
---
 include/sbi_utils/fdt/fdt_helper.h         |  3 +++
 lib/utils/fdt/fdt_helper.c                 | 11 ++++++++
 lib/utils/serial/Kconfig                   |  5 ++++
 lib/utils/serial/fdt_serial_renesas_scif.c | 31 ++++++++++++++++++++++
 lib/utils/serial/objects.mk                |  3 +++
 5 files changed, 53 insertions(+)
 create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c

diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
index c39f77a..09f3095 100644
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -59,6 +59,9 @@ int fdt_parse_timebase_frequency(void *fdt, unsigned long *freq);
 int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 				struct platform_uart_data *uart);
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart);
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart);
 
diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
index d4b38dc..48bc2fe 100644
--- a/lib/utils/fdt/fdt_helper.c
+++ b/lib/utils/fdt/fdt_helper.c
@@ -23,6 +23,9 @@
 #define DEFAULT_UART_REG_IO_WIDTH	1
 #define DEFAULT_UART_REG_OFFSET		0
 
+#define DEFAULT_RENESAS_SCIF_FREQ		100000000
+#define DEFAULT_RENESAS_SCIF_BAUD		115200
+
 #define DEFAULT_SIFIVE_UART_FREQ		0
 #define DEFAULT_SIFIVE_UART_BAUD		115200
 
@@ -355,6 +358,14 @@ int fdt_parse_gaisler_uart_node(void *fdt, int nodeoffset,
 					DEFAULT_UART_BAUD);
 }
 
+int fdt_parse_renesas_scif_node(void *fdt, int nodeoffset,
+				struct platform_uart_data *uart)
+{
+	return fdt_parse_uart_node_common(fdt, nodeoffset, uart,
+					  DEFAULT_RENESAS_SCIF_FREQ,
+					  DEFAULT_RENESAS_SCIF_BAUD);
+}
+
 int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
 			       struct platform_uart_data *uart)
 {
diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
index f6ed803..e3589ca 100644
--- a/lib/utils/serial/Kconfig
+++ b/lib/utils/serial/Kconfig
@@ -24,6 +24,11 @@ config FDT_SERIAL_HTIF
 	select SYS_HTIF
 	default n
 
+config FDT_SERIAL_RENESAS_SCIF
+	bool "Renesas SCIF FDT driver"
+	select SERIAL_RENESAS_SCIF
+	default n
+
 config FDT_SERIAL_SHAKTI
 	bool "Shakti UART FDT driver"
 	select SERIAL_SHAKTI
diff --git a/lib/utils/serial/fdt_serial_renesas_scif.c b/lib/utils/serial/fdt_serial_renesas_scif.c
new file mode 100644
index 0000000..c331ca1
--- /dev/null
+++ b/lib/utils/serial/fdt_serial_renesas_scif.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/serial/renesas-scif.h>
+
+static int serial_renesas_scif_init(void *fdt, int nodeoff,
+				    const struct fdt_match *match)
+{
+	struct platform_uart_data uart = { 0 };
+	int ret;
+
+	ret = fdt_parse_renesas_scif_node(fdt, nodeoff, &uart);
+	if (ret)
+		return ret;
+
+	return renesas_scif_init(uart.addr, uart.freq, uart.baud);
+}
+
+static const struct fdt_match serial_renesas_scif_match[] = {
+	{ .compatible = "renesas,scif-r9a07g043" },
+	{ /* sentinel */ }
+};
+
+struct fdt_serial fdt_serial_renesas_scif = {
+	.match_table = serial_renesas_scif_match,
+	.init = serial_renesas_scif_init
+};
diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
index 6520424..1e6bd2e 100644
--- a/lib/utils/serial/objects.mk
+++ b/lib/utils/serial/objects.mk
@@ -19,6 +19,9 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_GAISLER) += serial/fdt_serial_gaisler.o
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_HTIF) += fdt_serial_htif
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_HTIF) += serial/fdt_serial_htif.o
 
+carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += fdt_serial_renesas_scif
+libsbiutils-objs-$(CONFIG_FDT_SERIAL_RENESAS_SCIF) += serial/fdt_serial_renesas_scif.o
+
 carray-fdt_serial_drivers-$(CONFIG_FDT_SERIAL_SHAKTI) += fdt_serial_shakti
 libsbiutils-objs-$(CONFIG_FDT_SERIAL_SHAKTI) += serial/fdt_serial_shakti.o
 
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:10 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:10 +0000
Subject: [PATCH v5 4/5] platform: generic: Add Renesas RZ/Five initial support
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221210103011.7814-5-prabhakar.mahadev-lad.rj@bp.renesas.com>

This commit provides basic support for the Renesas RZ/Five
(R9A07G043F) SoC.

The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
- Gigabit Ethernet 2ch
- CAN interface (CAN-FD) 2ch
- USB 2.0 interface 2ch
- SD interface 2ch
- AD converter 2ch

Useful links:
-------------
Links: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Links: http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
v4->v5
* No change

v3->v4
* Replaced "renesas,r9a07g043" -> "renesas,r9a07g043f01"
* Included RB tag

v2->v3
* New patch
---
 platform/generic/Kconfig                   |  4 ++++
 platform/generic/configs/defconfig         |  2 ++
 platform/generic/renesas/rzfive/objects.mk |  8 ++++++++
 platform/generic/renesas/rzfive/rzfive.c   | 17 +++++++++++++++++
 4 files changed, 31 insertions(+)
 create mode 100644 platform/generic/renesas/rzfive/objects.mk
 create mode 100644 platform/generic/renesas/rzfive/rzfive.c

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 4b5d2cd..62c7a2d 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -32,6 +32,10 @@ config PLATFORM_ANDES_AE350
 	bool "Andes AE350 support"
 	default n
 
+config PLATFORM_RENESAS_RZFIVE
+	bool "Renesas RZ/Five support"
+	default n
+
 config PLATFORM_SIFIVE_FU540
 	bool "SiFive FU540 support"
 	default n
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 2eaeeb7..47fca95 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -1,5 +1,6 @@
 CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
+CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
 CONFIG_FDT_GPIO=y
@@ -24,6 +25,7 @@ CONFIG_FDT_SERIAL=y
 CONFIG_FDT_SERIAL_CADENCE=y
 CONFIG_FDT_SERIAL_GAISLER=y
 CONFIG_FDT_SERIAL_HTIF=y
+CONFIG_FDT_SERIAL_RENESAS_SCIF=y
 CONFIG_FDT_SERIAL_SHAKTI=y
 CONFIG_FDT_SERIAL_SIFIVE=y
 CONFIG_FDT_SERIAL_LITEX=y
diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
new file mode 100644
index 0000000..2e7e37f
--- /dev/null
+++ b/platform/generic/renesas/rzfive/objects.mk
@@ -0,0 +1,8 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (C) 2022 Renesas Electronics Corp.
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
+platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
new file mode 100644
index 0000000..ca182e3
--- /dev/null
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static const struct fdt_match renesas_rzfive_match[] = {
+	{ .compatible = "renesas,r9a07g043f01" },
+	{ /* sentinel */ }
+};
+
+const struct platform_override renesas_rzfive = {
+	.match_table = renesas_rzfive_match,
+};
-- 
2.17.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Sat Dec 10 02:30:11 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Sat, 10 Dec 2022 10:30:11 +0000
Subject: [PATCH v5 5/5] docs: platform: Add documentation for Renesas RZ/Five SoC
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <20221210103011.7814-6-prabhakar.mahadev-lad.rj@bp.renesas.com>

This patch adds documentation to build Renesas RZ/Five (R9A07G043F) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
v4->v5
* Updated generic.md to include RZ/Five SoC
* Included RB tag

v3->v4
* Added complete list of IP blocks

v2->v3
* Updated doc with new build command

RFC->v2
* Updated doc
---
 docs/platform/generic.md        |   2 +
 docs/platform/platform.md       |   5 +
 docs/platform/renesas-rzfive.md | 160 ++++++++++++++++++++++++++++++++
 3 files changed, 167 insertions(+)
 create mode 100644 docs/platform/renesas-rzfive.md

diff --git a/docs/platform/generic.md b/docs/platform/generic.md
index e8a3296..8e4cf2d 100644
--- a/docs/platform/generic.md
+++ b/docs/platform/generic.md
@@ -47,6 +47,7 @@ RISC-V Platforms Using Generic Platform
 
 * **Andes AE350 Platform** (*[andes-ae350.md]*)
 * **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
+* **Renesas RZ/Five SoC** (*[renesas-rzfive.md]*)
 * **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
 * **SiFive HiFive Unleashed** (*[sifive_fu540.md]*)
 * **Spike** (*[spike.md]*)
@@ -54,6 +55,7 @@ RISC-V Platforms Using Generic Platform
 
 [andes-ae350.md]: andse-ae350.md
 [qemu_virt.md]: qemu_virt.md
+[renesas-rzfive.md]: renesas-rzfive.md
 [shakti_cclass.md]: shakti_cclass.md
 [sifive_fu540.md]: sifive_fu540.md
 [spike.md]: spike.md
diff --git a/docs/platform/platform.md b/docs/platform/platform.md
index f291931..4504d87 100644
--- a/docs/platform/platform.md
+++ b/docs/platform/platform.md
@@ -39,6 +39,10 @@ OpenSBI currently supports the following virtual and hardware platforms:
   processor based SOCs. More details on this platform can be found in the
   file *[shakti_cclass.md]*.
 
+* **Renesas RZ/Five SoC**: Platform support for Renesas RZ/Five (R9A07G043F) SoC
+  used on the Renesas RZ/Five SMARC EVK board. More details on this platform can
+  be found in the file *[renesas-rzfive.md]*.
+
 The code for these supported platforms can be used as example to implement
 support for other platforms. The *platform/template* directory also provides
 template files for implementing support for a new platform. The *objects.mk*,
@@ -54,3 +58,4 @@ comments to facilitate the implementation.
 [spike.md]: spike.md
 [fpga-openpiton.md]: fpga-openpiton.md
 [shakti_cclass.md]: shakti_cclass.md
+[renesas-rzfive.md]: renesas-rzfive.md
diff --git a/docs/platform/renesas-rzfive.md b/docs/platform/renesas-rzfive.md
new file mode 100644
index 0000000..a73c53f
--- /dev/null
+++ b/docs/platform/renesas-rzfive.md
@@ -0,0 +1,160 @@
+Renesas RZ/Five SoC (R9A07G043F) Platform
+=========================================
+The RZ/Five microprocessor includes a single RISC-V CPU Core (Andes AX45MP)
+1.0 GHz, 16-bit DDR3L/DDR4 interface. Supported interfaces include:
+- Memory controller for DDR4-1600 / DDR3L-1333 with 16 bits
+- System RAM (RAM of 128 Kbytes (ECC))
+- SPI Multi I/O Bus Controller 1ch
+- SD Card Host Interface/Multimedia Card Interface (SD/MMC) 2ch
+- Serial Sound Interface (SSI) 4ch
+- Sampling Rate Converter (SRC) 1ch
+- USB2.0 host/function interface 2ch (ch0: Host-Function ch1: Host only)
+- Gigabit Ethernet Interface (GbE) 2ch
+- Controller Area Network Interface (CAN) 2ch (CAN-FD ISO 11898-1 (CD2014) compliant)
+- Multi-function Timer Pulse Unit 3 (MTU3a) 9 ch (16 bits ? 8 channels, 32 bits ? 1 channel)
+- Port Output Enable 3 (POE3)
+- Watchdog Timer (WDT) 1ch
+- General Timer (GTM) 3ch (32bits)
+- I2C Bus Interface (I2C) 4ch
+- Serial Communication Interface with FIFO (SCIFA) 5ch
+- Serial Communication Interface (SCI) 2ch
+- Renesas Serial Peripheral Interface (RSPI) 3ch
+- A/D Converter (ADC) 2ch
+making it ideal for applications such as entry-class social infrastructure
+gateway control and industrial gateway control. More details can be found at
+below link [0].
+
+[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
+
+To build platform specific library and firmwares, provide the
+*PLATFORM=generic* parameter to the top level make command.
+
+Platform Options
+----------------
+
+The Renesas RZ/Five platform does not have any platform-specific options.
+
+Building Renesas RZ/Five Platform
+---------------------------------
+
+```
+make PLATFORM=generic
+```
+
+DTS Example: (RZ/Five AX45MP)
+-----------------------------
+
+```
+	compatible = "renesas,r9a07g043f01", "renesas,r9a07g043";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <12000000>;
+
+		cpu0: cpu at 0 {
+			compatible = "andestech,ax45mp", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		ranges;
+
+		scif0: serial at 1004b800 {
+			compatible = "renesas,scif-r9a07g043",
+				     "renesas,scif-r9a07g044";
+			reg = <0 0x1004b800 0 0x400>;
+			interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+				     <414 IRQ_TYPE_LEVEL_HIGH>,
+				     <415 IRQ_TYPE_LEVEL_HIGH>,
+				     <413 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>,
+				     <416 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller at 11010000 {
+			compatible = "renesas,r9a07g043-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller at 11020000 {
+			compatible = "renesas,r9a07g043-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl at 11030000 {
+			compatible = "renesas,r9a07g043-pinctrl";
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			gpio-ranges = <&pinctrl 0 0 152>;
+			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_GPIO_RSTN>,
+				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
+				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+		};
+
+		plmt0: plmt0 at 110c0000 {
+			compatible = "andestech,plmt0", "riscv,plmt0";
+			reg = <0x0 0x110c0000 0x0 0x10000>;
+			interrupts-extended = <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller at 12c00000 {
+			compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+			#interrupt-cells = <2>;
+			#address-cells = <0>;
+			riscv,ndev = <511>;
+			interrupt-controller;
+			reg = <0x0 0x12c00000 0x0 0x400000>;
+			clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+		};
+
+		plicsw: interrupt-controller at 13000000 {
+			compatible = "andestech,plicsw";
+			reg = <0x0 0x13000000 0x0 0x400000>;
+			interrupts-extended = <&cpu0_intc 3>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#interrupt-cells = <2>;
+		};
+	};
+```
-- 
2.17.1



From anup at brainfault.org  Sat Dec 10 06:21:44 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 10 Dec 2022 19:51:44 +0530
Subject: [PATCH v2] lib: utils/fdt: Add full valid detection for __fdt_parse_region
In-Reply-To: <20221207173644.1106040-1-wxjstz@126.com>
References: <20221207173644.1106040-1-wxjstz@126.com>
Message-ID: <CAAhSdy0W0zRDDjJ1vUP2F3yrEf_EV2P-VJnqm09RLokyGfuiBw@mail.gmail.com>

On Wed, Dec 7, 2022 at 11:07 PM Xiang W <wxjstz at 126.com> wrote:
>
> The original code only detects region->order, and a certain relationship
> needs to be satisfied between region->order and region->base. This patch
> detects whether the region in fdt is valid through sbi_is_region_valid

The sbi_domain_register() already checks is_region_valid() on each
region via sanitize_domain().

Calling is_region_valid() in __fdt_parse_region() is unnecessary.

Regards,
Anup

>
> Signed-off-by: Xiang W <wxjstz at 126.com>
> ---
> REF -> v2
> * is_region_valid is local function, change it public and rename
>   sbi_is_region_valid
> ---
>  include/sbi/sbi_domain.h   | 7 +++++++
>  lib/sbi/sbi_domain.c       | 4 ++--
>  lib/utils/fdt/fdt_domain.c | 5 +++--
>  3 files changed, 12 insertions(+), 4 deletions(-)
> diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> index 5553d21..fdd73a9 100644
> --- a/include/sbi/sbi_domain.h
> +++ b/include/sbi/sbi_domain.h
> @@ -109,6 +109,13 @@ extern struct sbi_domain *domidx_to_domain_table[];
>  #define sbi_domain_for_each_memregion(__d, __r) \
>         for ((__r) = (__d)->regions; (__r)->order; (__r)++)
>
> +/**
> + * Check if sbi_domain_memregion is valid
> + * @param reg pointrt to the sbi_domain_memregion that needs to be check
> + * @return True if reg is vaild sbi_domain_memregion
> +*/
> +bool sbi_is_region_valid(const struct sbi_domain_memregion *reg);
> +
>  /**
>   * Check whether given HART is assigned to specified domain
>   * @param dom pointer to domain
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3302213..08f0ea6 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -141,7 +141,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
>  }
>
>  /* Check if region complies with constraints */
> -static bool is_region_valid(const struct sbi_domain_memregion *reg)
> +bool sbi_is_region_valid(const struct sbi_domain_memregion *reg)
>  {
>         if (reg->order < 3 || __riscv_xlen < reg->order)
>                 return FALSE;
> @@ -226,7 +226,7 @@ static int sanitize_domain(const struct sbi_platform *plat,
>                 return SBI_EINVAL;
>         }
>         sbi_domain_for_each_memregion(dom, reg) {
> -               if (!is_region_valid(reg)) {
> +               if (!sbi_is_region_valid(reg)) {
>                         sbi_printf("%s: %s has invalid region base=0x%lx "
>                                    "order=%lu flags=0x%lx\n", __func__,
>                                    dom->name, reg->base, reg->order,
> diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
> index bd0eec3..49908f5 100644
> --- a/lib/utils/fdt/fdt_domain.c
> +++ b/lib/utils/fdt/fdt_domain.c
> @@ -257,8 +257,6 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>         if (!val && len >= 4)
>                 return SBI_EINVAL;
>         val32 = fdt32_to_cpu(*val);
> -       if (val32 < 3 || __riscv_xlen < val32)
> -               return SBI_EINVAL;
>         region->order = val32;
>
>         /* Read "mmio" DT property */
> @@ -266,6 +264,9 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
>         if (fdt_get_property(fdt, region_offset, "mmio", NULL))
>                 region->flags |= SBI_DOMAIN_MEMREGION_MMIO;
>
> +       if(!sbi_is_region_valid(region))
> +               return SBI_EINVAL;
> +
>         (*region_count)++;
>
>         return 0;
> --
> 2.30.2
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sat Dec 10 08:24:30 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 10 Dec 2022 21:54:30 +0530
Subject: [PATCH v2] scripts: use env to invoke bash
In-Reply-To: <20221209061335.1326839-1-hchauhan@ventanamicro.com>
References: <20221209061335.1326839-1-hchauhan@ventanamicro.com>
Message-ID: <CAAhSdy3SfVWKe-HvsynXAbiM7vSMmieqZHgVMYArJNu+ycUk=w@mail.gmail.com>

On Fri, Dec 9, 2022 at 11:43 AM Himanshu Chauhan
<hchauhan at ventanamicro.com> wrote:
>
> Not all systems have bash at a fixed location like /bin/bash.
> FreeBSD, for example, would typically have it at /usr/local/bin/bash.
> When building OpenSBI on freebsd system, the build breaks.
>
> Its advisable to use: #!/usr/bin/env bash
>
> [v2] In this version:
> * Change remaining two scripts to use env

The change log should be after the "---" line below for a
single patch otherwise it becomes part of the commit description.

>
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  scripts/carray.sh                | 2 +-
>  scripts/create-binary-archive.sh | 2 +-
>  scripts/d2c.sh                   | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/scripts/carray.sh b/scripts/carray.sh
> index 0c52bd6..13f9d36 100755
> --- a/scripts/carray.sh
> +++ b/scripts/carray.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
>
>  function usage()
>  {
> diff --git a/scripts/create-binary-archive.sh b/scripts/create-binary-archive.sh
> index 261a45a..63781e1 100755
> --- a/scripts/create-binary-archive.sh
> +++ b/scripts/create-binary-archive.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
>
>  function usage()
>  {
> diff --git a/scripts/d2c.sh b/scripts/d2c.sh
> index 33a3ccf..c411fcd 100755
> --- a/scripts/d2c.sh
> +++ b/scripts/d2c.sh
> @@ -1,4 +1,4 @@
> -#!/bin/bash
> +#!/usr/bin/env bash
>
>  function usage()
>  {
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sat Dec 10 08:26:08 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 10 Dec 2022 21:56:08 +0530
Subject: [PATCH v5 1/5] lib: utils: serial: Add Renesas SCIF driver
In-Reply-To: <20221210103011.7814-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221210103011.7814-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2FtC0MnFA8SbzKYnRw0oR59waGxUP6bN4dx2Apc_FU1w@mail.gmail.com>

On Sat, Dec 10, 2022 at 4:00 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
>
> Add Renesas SCIF driver.
>
> Based on a patch in the BSP by Takeki Hamada
> <takeki.hamada.ak at bp.renesas.com>
> Link: https://github.com/renesas-rz/rz_opensbi/commits/work/OpenSBI-PMA
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> v4->v5
> * No change
>
> v3->v4
> * Dropped returning from void func
> * Dropped unnecessary volatile variable
>
> v2->v3
> * Fixed review comments pointed by Bin
>
> RFC->v2
> * Fixed comments pointed by Xiang W
> ---
>  include/sbi_utils/serial/renesas-scif.h |  11 +++
>  lib/utils/serial/Kconfig                |   4 +
>  lib/utils/serial/objects.mk             |   1 +
>  lib/utils/serial/renesas_scif.c         | 116 ++++++++++++++++++++++++
>  4 files changed, 132 insertions(+)
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/renesas_scif.c
>
> diff --git a/include/sbi_utils/serial/renesas-scif.h b/include/sbi_utils/serial/renesas-scif.h
> new file mode 100644
> index 0000000..0002a1a
> --- /dev/null
> +++ b/include/sbi_utils/serial/renesas-scif.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#ifndef __SERIAL_RENESAS_SCIF_H__
> +#define __SERIAL_RENESAS_SCIF_H__
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate);
> +
> +#endif /* __SERIAL_RENESAS_SCIF_H__ */
> diff --git a/lib/utils/serial/Kconfig b/lib/utils/serial/Kconfig
> index da549a7..f6ed803 100644
> --- a/lib/utils/serial/Kconfig
> +++ b/lib/utils/serial/Kconfig
> @@ -59,6 +59,10 @@ config SERIAL_GAISLER
>         bool "Gaisler UART support"
>         default n
>
> +config SERIAL_RENESAS_SCIF
> +       bool "Renesas SCIF support"
> +       default n
> +
>  config SERIAL_SHAKTI
>         bool "Shakti UART support"
>         default n
> diff --git a/lib/utils/serial/objects.mk b/lib/utils/serial/objects.mk
> index 98f3f9a..6520424 100644
> --- a/lib/utils/serial/objects.mk
> +++ b/lib/utils/serial/objects.mk
> @@ -36,6 +36,7 @@ libsbiutils-objs-$(CONFIG_FDT_SERIAL_XILINX_UARTLITE) += serial/fdt_serial_xlnx_
>
>  libsbiutils-objs-$(CONFIG_SERIAL_CADENCE) += serial/cadence-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_GAISLER) += serial/gaisler-uart.o
> +libsbiutils-objs-$(CONFIG_SERIAL_RENESAS_SCIF) += serial/renesas_scif.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SHAKTI) += serial/shakti-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_SIFIVE) += serial/sifive-uart.o
>  libsbiutils-objs-$(CONFIG_SERIAL_LITEX) += serial/litex-uart.o
> diff --git a/lib/utils/serial/renesas_scif.c b/lib/utils/serial/renesas_scif.c
> new file mode 100644
> index 0000000..cbe9db4
> --- /dev/null
> +++ b/lib/utils/serial/renesas_scif.c
> @@ -0,0 +1,116 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corporation
> + */
> +
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_timer.h>
> +#include <sbi_utils/serial/renesas-scif.h>
> +
> +/* clang-format off */
> +
> +#define SCIF_REG_SMR           0x0
> +#define SCIF_REG_BRR           0x2
> +#define SCIF_REG_SCR           0x4
> +#define SCIF_REG_FTDR          0x6
> +#define SCIF_REG_FSR           0x8
> +#define SCIF_REG_FCR           0xc
> +#define SCIF_REG_LSR           0x12
> +#define SCIF_REG_SEMR          0x14
> +
> +#define SCIF_FCR_RFRST         0x2 /* Reset assert receive-FIFO (bit[1]) */
> +#define SCIF_FCR_TFRST         0x4 /* Reset assert transmit-FIFO(bit[2]) */
> +
> +#define SCIF_FCR_RST_ASSRT_RFTF        (SCIF_FCR_RFRST | SCIF_FCR_TFRST) /* Reset assert tx-FIFO & rx-FIFO */
> +#define SCIF_FCR_RST_NGATE_RFTF        0x0 /* Reset negate tx-FIFO & rx-FIFO */
> +
> +#define SCIF_SCR_RE            0x10 /* Enable receive (bit[4]) */
> +#define SCIF_SCR_TE            0x20 /* Enable transmit(bit[5]) */
> +#define SCIF_SCR_RCV_TRN_EN    (SCIF_SCR_RE | SCIF_SCR_TE) /* Enable receive & transmit */
> +#define SCIF_SCR_RCV_TRN_DIS   0x0 /* Disable receive & transmit */
> +
> +#define SCIF_FSR_ER            0x80 /* Receive error flag */
> +#define SCIF_FSR_TEND          0x40 /* Transmit End Flag */
> +#define SCIF_FSR_TDFE          0x20 /* Transmit FIFO Data Empty Flag */
> +#define SCIF_FSR_BRK           0x10 /* Detect break flag */
> +#define SCIF_FSR_DR            0x1  /* Receive data ready flag */
> +
> +#define SCIF_FSR_TXD_CHK       (SCIF_FSR_TEND | SCIF_FSR_TDFE)
> +
> +#define SCIF_SEMR_MDDRS                0x10 /* MDDR access enable */
> +
> +#define SCIF_REG_8BIT(reg)     ((reg == SCIF_REG_BRR) || \
> +                                (reg == SCIF_REG_FTDR) || \
> +                                (reg == SCIF_REG_SEMR))
> +
> +#define SCBRR_VALUE(clk, baudrate) ((clk) / (32 * (baudrate)) - 1)
> +
> +/* clang-format on */
> +
> +static volatile char *scif_base;
> +
> +static u32 get_reg(u32 offset)
> +{
> +       if (SCIF_REG_8BIT(offset))
> +               return readb(scif_base + offset);
> +
> +       return readw(scif_base + offset);
> +}
> +
> +static void set_reg(u32 offset, u32 val)
> +{
> +       if (SCIF_REG_8BIT(offset))
> +               writeb(val, scif_base + offset);
> +       else
> +               writew(val, scif_base + offset);
> +}
> +
> +static void renesas_scif_putc(char ch)
> +{
> +       uint16_t reg;
> +
> +       while (!(SCIF_FSR_TXD_CHK & get_reg(SCIF_REG_FSR)))
> +               ;
> +
> +       set_reg(SCIF_REG_FTDR, ch);
> +       reg = get_reg(SCIF_REG_FSR);
> +       reg &= ~SCIF_FSR_TXD_CHK;
> +       set_reg(SCIF_REG_FSR, reg);
> +}
> +
> +static struct sbi_console_device renesas_scif_console = {
> +       .name           = "renesas_scif",
> +       .console_putc   = renesas_scif_putc,
> +};
> +
> +int renesas_scif_init(unsigned long base, u32 in_freq, u32 baudrate)
> +{
> +       uint16_t data16;
> +
> +       scif_base = (volatile char *)base;
> +
> +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_DIS);
> +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_ASSRT_RFTF);
> +
> +       data16 = get_reg(SCIF_REG_FSR); /* Dummy read */
> +       set_reg(SCIF_REG_FSR, 0x0); /* Clear all error bit */
> +
> +       data16 = get_reg(SCIF_REG_LSR); /* Dummy read */
> +       set_reg(SCIF_REG_LSR, 0x0); /* Clear ORER bit */
> +
> +       set_reg(SCIF_REG_SCR, 0x0);
> +
> +       set_reg(SCIF_REG_SMR, 0x0);
> +
> +       data16 = get_reg(SCIF_REG_SEMR);
> +       set_reg(SCIF_REG_SEMR, data16 & (~SCIF_SEMR_MDDRS));
> +       set_reg(SCIF_REG_BRR, SCBRR_VALUE(in_freq, baudrate));
> +
> +       set_reg(SCIF_REG_FCR, SCIF_FCR_RST_NGATE_RFTF);
> +       set_reg(SCIF_REG_SCR, SCIF_SCR_RCV_TRN_EN);
> +
> +       sbi_console_set_device(&renesas_scif_console);
> +
> +       return 0;
> +}
> --
> 2.17.1
>


From anup at brainfault.org  Sat Dec 10 08:45:17 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 10 Dec 2022 22:15:17 +0530
Subject: [PATCH 1/3] lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
In-Reply-To: <20221209070120.944152-2-uwu@icenowy.me>
References: <20221209070120.944152-1-uwu@icenowy.me> <20221209070120.944152-2-uwu@icenowy.me>
Message-ID: <CAAhSdy2u_P9aCWUHnVWHLN+Tn_rTbV-X76YZvxwCGR43T7822Q@mail.gmail.com>

On Fri, Dec 9, 2022 at 12:31 PM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
> MSWI part is compliant.
>
> Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
> the same codepath with SiFive CLINT.
>
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  lib/utils/ipi/fdt_ipi_mswi.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
> index 0176941..4dc91f2 100644
> --- a/lib/utils/ipi/fdt_ipi_mswi.c
> +++ b/lib/utils/ipi/fdt_ipi_mswi.c
> @@ -56,6 +56,7 @@ static const unsigned long clint_offset = CLINT_MSWI_OFFSET;
>  static const struct fdt_match ipi_mswi_match[] = {
>         { .compatible = "riscv,clint0", .data = &clint_offset },
>         { .compatible = "sifive,clint0", .data = &clint_offset },
> +       { .compatible = "thead,c900-clint", .data = &clint_offset },
>         { .compatible = "riscv,aclint-mswi" },
>         { },
>  };
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From wxjstz at 126.com  Sat Dec 10 08:54:21 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 11 Dec 2022 00:54:21 +0800
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221203213929.206429-3-geomatsi@gmail.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
	 <20221203213929.206429-3-geomatsi@gmail.com>
Message-ID: <92833f1aeda3262f4ccb4b7fc796ee4de36c7ef0.camel@126.com>

? 2022-12-04???? 00:39 +0300?Sergey Matyukevich???
> From: Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> 
> RISC-V Debug specification includes Sdtrig ISA extension.
> This extension describes Trigger Module. Triggers can cause
> a breakpoint exception, entry into Debug Mode, or a trace
> action without having to execute a special instruction. For
> native debugging triggers can be used to implement hardware
> breakpoints and watchpoints.
> 
> Software support for triggers consists of the following
> major components:
> - U-mode: gdb
> - S-mode: hardware breakpoints framework in Linux kernel
> - M-mode: SBI firmware code to handle triggers
> 
> SBI Debug Trigger extension proposal has been posted by
> Anup Patel to lists.riscv.org tech-debug mailing list:
> https://lists.riscv.org/g/tech-debug/topic/92375492
> 
> This patch provides initial implementation of SBI Debug
> Trigger Extension in OpenSBI library based on the
> suggested extension proposal.
> 
> Initial implementation has the following limitations:
> - supported triggers: mcontrol, mcontrol6
> - no support for chained triggers
> - only build test for RV32
> 
> ---
> ?include/sbi/riscv_dbtr.h????????? | 179 +++++++++++
> ?include/sbi/riscv_encoding.h????? |?? 1 +
> ?include/sbi/sbi_dbtr.h??????????? |? 80 +++++
> ?include/sbi/sbi_ecall_interface.h |? 10 +
> ?lib/sbi/Kconfig?????????????????? |?? 4 +
> ?lib/sbi/objects.mk??????????????? |?? 4 +
> ?lib/sbi/sbi_dbtr.c??????????????? | 481 ++++++++++++++++++++++++++++++
> ?lib/sbi/sbi_ecall_dbtr.c????????? |? 68 +++++
> ?lib/sbi/sbi_init.c??????????????? |?? 9 +
> ?9 files changed, 836 insertions(+)
> ?create mode 100644 include/sbi/riscv_dbtr.h
> ?create mode 100644 include/sbi/sbi_dbtr.h
> ?create mode 100644 lib/sbi/sbi_dbtr.c
> ?create mode 100644 lib/sbi/sbi_ecall_dbtr.c
> 
> diff --git a/include/sbi/riscv_dbtr.h b/include/sbi/riscv_dbtr.h
> new file mode 100644
> index 0000000..9944547
> --- /dev/null
> +++ b/include/sbi/riscv_dbtr.h
> @@ -0,0 +1,179 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __RISCV_DBTR_H__
> +#define __RISCV_DBTR_H__
> +
> +#define RV_MAX_TRIGGERS????????32
> +
> +enum {
> +???????RISCV_DBTR_TRIG_NONE = 0,
> +???????RISCV_DBTR_TRIG_LEGACY,
> +???????RISCV_DBTR_TRIG_MCONTROL,
> +???????RISCV_DBTR_TRIG_ICOUNT,
> +???????RISCV_DBTR_TRIG_ITRIGGER,
> +???????RISCV_DBTR_TRIG_ETRIGGER,
> +???????RISCV_DBTR_TRIG_MCONTROL6,
> +};
> +
> +union riscv_dbtr_tdata1 {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long data:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +#if __riscv_xlen == 64
> +???????????????unsigned long data:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long data:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +union riscv_dbtr_tdata1_mcontrol {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long maskmax:6;
> +#if __riscv_xlen >= 64
> +???????????????unsigned long _res1:30;
> +???????????????unsigned long sizehi:2;
> +#endif
> +???????????????unsigned long hit:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long sizelo:2;
> +???????????????unsigned long action:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long m:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +???????????????unsigned long load:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long m:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long action:4;
> +???????????????unsigned long sizelo:2;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long hit:1;
> +#if __riscv_xlen >= 64
> +???????????????unsigned long sizehi:2;
> +???????????????unsigned long _res1:30;
> +#endif
> +???????????????unsigned long maskmax:6;
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +#define MCONTROL_U_OFFSET??????3
> +#define MCONTROL_S_OFFSET??????4
> +#define MCONTROL_M_OFFSET??????6
> +
> +union riscv_dbtr_tdata1_mcontrol6 {
> +???????unsigned long value;
> +???????struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +???????????????unsigned long type:4;
> +???????????????unsigned long dmode:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long vs:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long hit:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long size:4;
> +???????????????unsigned long action:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long m:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long load:1;
> +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> +???????????????unsigned long load:1;
> +???????????????unsigned long store:1;
> +???????????????unsigned long execute:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long _res2:1;
> +???????????????unsigned long m:1;
> +???????????????unsigned long match:4;
> +???????????????unsigned long chain:1;
> +???????????????unsigned long action:4;
> +???????????????unsigned long size:4;
> +???????????????unsigned long timing:1;
> +???????????????unsigned long select:1;
> +???????????????unsigned long hit:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long vs:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long _res1:34;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long _res1:2;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????????????unsigned long dmode:1;
> +???????????????unsigned long type:4;
> +#else
> +#error "Unexpected endianness"
> +#endif
> +???????};
> +};
> +
> +#define MCONTROL6_U_OFFSET?????3
> +#define MCONTROL6_S_OFFSET?????4
> +#define MCONTROL6_M_OFFSET?????6
> +#define MCONTROL6_VU_OFFSET????23
> +#define MCONTROL6_VS_OFFSET????24
> +
> +#endif /* __RISCV_DBTR_H__ */
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index b0f08c8..2041ab7 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -671,6 +671,7 @@
> ?#define CSR_TDATA1?????????????????????0x7a1
> ?#define CSR_TDATA2?????????????????????0x7a2
> ?#define CSR_TDATA3?????????????????????0x7a3
> +#define CSR_TINFO??????????????????????0x7a4
> ?
> ?/* Debug Mode Registers */
> ?#define CSR_DCSR???????????????????????0x7b0
> diff --git a/include/sbi/sbi_dbtr.h b/include/sbi/sbi_dbtr.h
> new file mode 100644
> index 0000000..5ef6166
> --- /dev/null
> +++ b/include/sbi/sbi_dbtr.h
> @@ -0,0 +1,80 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#ifndef __SBI_DBTR_H__
> +#define __SBI_DBTR_H__
> +
> +#include <sbi/riscv_endian.h>
> +#include <sbi/riscv_dbtr.h>
> +
> +#include <sbi/sbi_hartmask.h>
> +#include <sbi/sbi_scratch.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_types.h>
> +
> +/** Representation of trigger state */
> +union sbi_dbtr_trig_state {
> +???????unsigned long value;
> +???????struct {
> +???????????????unsigned long mapped:1;
> +???????????????unsigned long u:1;
> +???????????????unsigned long s:1;
> +???????????????unsigned long vu:1;
> +???????????????unsigned long vs:1;
> +#if __riscv_xlen == 64
> +???????????????unsigned long reserved:59;
> +#elif __riscv_xlen == 32
> +???????????????unsigned long reserved:27;
> +#else
> +#error "Unexpected __riscv_xlen"
> +#endif
> +???????};
> +};
> +
> +struct sbi_dbtr_trig_info {
> +???????unsigned long type_mask;
> +???????union sbi_dbtr_trig_state state;
> +???????unsigned long tdata1;
> +???????unsigned long tdata2;
> +???????unsigned long tdata3;
tdata1~tdata3 can be removed and written directly to scr during install
> +};
> +
> +/** SBI shared mem messages layout */
> +struct sbi_dbtr_data_msg {
> +???????unsigned long tstate;
> +???????unsigned long tdata1;
> +???????unsigned long tdata2;
> +???????unsigned long tdata3;
> +};
> +
> +struct sbi_dbtr_id_msg {
> +???????unsigned long idx;
> +};
> +
> +/** Initialize PMU */
> +int sbi_dbtr_init(struct sbi_scratch *scratch);
> +
> +/** SBI DBTR extension functions */
> +int sbi_dbtr_probe(unsigned long *out);
> +int sbi_dbtr_num_trig(unsigned long trig_tdata1, unsigned long *out);
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_count,
> +???????????????unsigned long out_addr_div_by_16);
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16, unsigned long *out);
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16);
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask);
> +
> +#endif
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index a3f2bf4..3c1b1ea 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -29,6 +29,7 @@
> ?#define SBI_EXT_HSM????????????????????????????0x48534D
> ?#define SBI_EXT_SRST???????????????????????????0x53525354
> ?#define SBI_EXT_PMU????????????????????????????0x504D55
> +#define SBI_EXT_DBTR???????????????????????????0x44425452
> ?
> ?/* SBI function IDs for BASE extension*/
> ?#define SBI_EXT_BASE_GET_SPEC_VERSION??????????0x0
> @@ -100,6 +101,15 @@
> ?#define SBI_EXT_PMU_COUNTER_STOP???????0x4
> ?#define SBI_EXT_PMU_COUNTER_FW_READ????0x5
> ?
> +/* SBI function IDs for DBTR extension */
> +#define SBI_EXT_DBTR_NUM_TRIGGERS??????0x0
> +#define SBI_EXT_DBTR_TRIGGER_READ??????0x1
> +#define SBI_EXT_DBTR_TRIGGER_INSTALL???0x2
> +#define SBI_EXT_DBTR_TRIGGER_UNINSTALL?0x3
> +#define SBI_EXT_DBTR_TRIGGER_ENABLE????0x4
> +#define SBI_EXT_DBTR_TRIGGER_UPDATE????0x5
> +#define SBI_EXT_DBTR_TRIGGER_DISABLE???0x6
> +
> ?/** General pmu event codes specified in SBI PMU extension */
> ?enum sbi_pmu_hw_generic_events_t {
> ????????SBI_PMU_HW_NO_EVENT?????????????????????= 0,
> diff --git a/lib/sbi/Kconfig b/lib/sbi/Kconfig
> index df74bba..e3a7955 100644
> --- a/lib/sbi/Kconfig
> +++ b/lib/sbi/Kconfig
> @@ -34,4 +34,8 @@ config SBI_ECALL_VENDOR
> ????????bool "Platform-defined vendor extensions"
> ????????default y
> ?
> +config SBI_ECALL_DBTR
> +???????bool "Debug Trigger Extension"
> +???????default y
> +
> ?endmenu
> diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk
> index c774ebb..36276e8 100644
> --- a/lib/sbi/objects.mk
> +++ b/lib/sbi/objects.mk
> @@ -43,6 +43,9 @@ libsbi-objs-$(CONFIG_SBI_ECALL_LEGACY) += sbi_ecall_legacy.o
> ?carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_VENDOR) += ecall_vendor
> ?libsbi-objs-$(CONFIG_SBI_ECALL_VENDOR) += sbi_ecall_vendor.o
> ?
> +carray-sbi_ecall_exts-$(CONFIG_SBI_ECALL_DBTR) += ecall_dbtr
> +libsbi-objs-$(CONFIG_SBI_ECALL_DBTR) += sbi_ecall_dbtr.o
> +
> ?libsbi-objs-y += sbi_bitmap.o
> ?libsbi-objs-y += sbi_bitops.o
> ?libsbi-objs-y += sbi_console.o
> @@ -60,6 +63,7 @@ libsbi-objs-y += sbi_irqchip.o
> ?libsbi-objs-y += sbi_misaligned_ldst.o
> ?libsbi-objs-y += sbi_platform.o
> ?libsbi-objs-y += sbi_pmu.o
> +libsbi-objs-y += sbi_dbtr.o
> ?libsbi-objs-y += sbi_scratch.o
> ?libsbi-objs-y += sbi_string.o
> ?libsbi-objs-y += sbi_system.o
> diff --git a/lib/sbi/sbi_dbtr.c b/lib/sbi/sbi_dbtr.c
> new file mode 100644
> index 0000000..bbad0cf
> --- /dev/null
> +++ b/lib/sbi/sbi_dbtr.c
> @@ -0,0 +1,481 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_csr_detect.h>
> +#include <sbi/sbi_platform.h>
> +#include <sbi/sbi_console.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +#include <sbi/riscv_encoding.h>
> +#include <sbi/riscv_asm.h>
> +
> +static struct sbi_dbtr_trig_info triggers[SBI_HARTMASK_MAX_BITS][RV_MAX_TRIGGERS] = {0};
> +static uint32_t total_trigs;
> +
> +static void sbi_triggers_table_init(u32 hartid, int idx, unsigned long type_mask)
> +{
> +???????triggers[hartid][idx].type_mask = type_mask;
> +???????triggers[hartid][idx].state.value = 0;
> +???????triggers[hartid][idx].tdata1 = 0;
> +???????triggers[hartid][idx].tdata2 = 0;
> +???????triggers[hartid][idx].tdata3 = 0;
> +}
> +
> +int sbi_dbtr_init(struct sbi_scratch *scratch)
> +{
> +???????struct sbi_trap_info trap = {0};
> +???????u32 hartid = current_hartid();
> +???????union riscv_dbtr_tdata1 tdata1;
> +???????unsigned long val;
> +???????int i;
> +
> +???????total_trigs = 0;
> +
> +???????for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> +???????????????csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
> +???????????????if (trap.cause)
> +???????????????????????break;
> +
> +???????????????val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
> +???????????????if (trap.cause)
> +???????????????????????break;
> +
> +???????????????/* Read back tselect and check that it contains the written value */
> +???????????????if (val != i)
> +???????????????????????break;
> +
> +???????????????val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
> +???????????????if (trap.cause) {
> +???????????????????????/**
> +??????????????????????? * If reading tinfo caused an exception, the debugger
> +??????????????????????? * must read tdata1 to discover the type.
> +??????????????????????? */
> +???????????????????????tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
> +???????????????????????if (trap.cause)
> +???????????????????????????????break;
> +
> +???????????????????????if (tdata1.type == 0)
> +???????????????????????????????break;
> +
> +
> +???????????????????????sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
> +???????????????????????total_trigs++;
> +???????????????} else {
> +???????????????????????if (val == 1)
> +???????????????????????????????break;
tinfo = 0 have to break, this is a invalid value.
> +
> +???????????????????????sbi_triggers_table_init(hartid, i, val);
> +???????????????????????total_trigs++;
> +???????????????}
> +???????}
> +
> +???????return 0;
> +}
> +
> +int sbi_dbtr_probe(unsigned long *out)
> +{
> +???????*out? = total_trigs;
> +
> +???????return 0;
> +}
> +
> +
> +static void dbtr_trigger_init(unsigned int hartid, unsigned int idx,
> +???????????????????????????? struct sbi_dbtr_data_msg *recv)
> +{
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????triggers[hartid][idx].tdata1 = lle_to_cpu(recv->tdata1);
> +???????triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +???????triggers[hartid][idx].tdata3 = lle_to_cpu(recv->tdata3);
> +???????triggers[hartid][idx].state.mapped = 1;
> +
> +???????tdata1.value = lle_to_cpu(recv->tdata1);
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????triggers[hartid][idx].state.u = __test_bit(MCONTROL_U_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.s = __test_bit(MCONTROL_S_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vu = 0;
> +???????????????triggers[hartid][idx].state.vs = 0;
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????triggers[hartid][idx].state.u = __test_bit(MCONTROL6_U_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.s = __test_bit(MCONTROL6_S_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vu = __test_bit(MCONTROL6_VU_OFFSET, &tdata1.value);
> +???????????????triggers[hartid][idx].state.vs = __test_bit(MCONTROL6_VS_OFFSET, &tdata1.value);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +}
> +
> +static inline void update_bit(unsigned long new, int nr, volatile unsigned long *addr)
> +{
> +???????if (new)
> +???????????????__set_bit(nr, addr);
> +???????else
> +???????????????__clear_bit(nr, addr);
> +}
> +
> +static void dbtr_trigger_enable(unsigned int hartid, unsigned int idx)
> +{
> +???????union sbi_dbtr_trig_state state;
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????state.value = triggers[hartid][idx].state.value;
> +???????tdata1.value = triggers[hartid][idx].tdata1;
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????update_bit(state.u, MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.s, MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????update_bit(state.vu, MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.vs, MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.u, MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????update_bit(state.s, MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????/*
> +??????? * RISC-V Debug Support v1.0.0 section 5.5:
> +??????? * Debugger cannot simply set a trigger by writing tdata1, then tdata2, etc. The current
> +??????? * value of tdata2 might not be legal with the new value of tdata1. To help with this
> +??????? * situation, it is guaranteed that writing 0 to tdata1 disables the trigger, and
> +??????? * leaves it in a state where tdata2 and tdata3 can be written with any value
> +??????? * that makes sense for any trigger type supported by this trigger.
> +??????? */
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, 0x0);
> +???????csr_write(CSR_TDATA2, triggers[hartid][idx].tdata2);
> +???????csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_disable(unsigned int hartid, unsigned int idx)
> +{
> +???????union riscv_dbtr_tdata1 tdata1;
> +
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????tdata1.value = triggers[hartid][idx].tdata1;
> +
> +???????switch (tdata1.type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????__clear_bit(MCONTROL_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????__clear_bit(MCONTROL6_VU_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_VS_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_U_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????__clear_bit(MCONTROL6_S_OFFSET, &triggers[hartid][idx].tdata1);
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, triggers[hartid][idx].tdata1);
> +}
> +
> +static void dbtr_trigger_clear(unsigned int hartid, unsigned int idx)
> +{
> +???????if (!triggers[hartid][idx].state.mapped)
> +???????????????return;
> +
> +???????csr_write(CSR_TSELECT, idx);
> +???????csr_write(CSR_TDATA1, 0x0);
> +???????csr_write(CSR_TDATA2, 0x0);
> +}
> +
> +static int dbtr_trigger_supported(unsigned long type)
> +{
> +???????switch (type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????return 1;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????return 0;
> +}
> +
> +static int dbtr_trigger_valid(unsigned long type, unsigned long tdata)
> +{
> +???????union riscv_dbtr_tdata1_mcontrol6 control6;
> +???????union riscv_dbtr_tdata1_mcontrol control;
> +
> +???????switch (type) {
> +???????case RISCV_DBTR_TRIG_MCONTROL:
> +???????????????control.value = tdata;
> +???????????????if (!control.action && !control.dmode && !control.m)
> +???????????????????????return 1;
> +???????????????break;
> +???????case RISCV_DBTR_TRIG_MCONTROL6:
> +???????????????control6.value = tdata;
> +???????????????if (!control6.action && !control6.dmode && !control6.m)
> +???????????????????????return 1;
> +???????????????break;
> +???????default:
> +???????????????break;
> +???????}
> +
> +???????return 0;
> +}
> +
> +int sbi_dbtr_num_trig(unsigned long data, unsigned long *out)
> +{
> +???????unsigned long type = ((union riscv_dbtr_tdata1)data).type;
> +???????u32 hartid = current_hartid();
> +???????unsigned long total = 0;
> +???????int i;
> +
> +
> +???????if (data == 0) {
> +???????????????sbi_dprintf("%s: hart%d: total triggers: %u\n",
> +?????????????????????????? __func__, hartid, total_trigs);
> +???????????????*out = total_trigs;
> +???????????????return SBI_SUCCESS;
> +???????}
> +
> +???????for (i = 0; i < total_trigs; i++) {
> +???????????????if (__test_bit(type, &triggers[hartid][i].type_mask))
> +???????????????????????total++;
> +???????}
> +
> +
> +???????sbi_dprintf("%s: hart%d: total triggers of type %lu: %lu\n",
> +?????????????????? __func__, hartid, type, total);
> +
> +???????*out = total;
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_read_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_count,
> +???????????????unsigned long out_addr_div_by_16)
> +{
> +???????unsigned long out_addr = (out_addr_div_by_16 << 4);
> +???????struct sbi_dbtr_data_msg *xmit;
> +???????u32 hartid = current_hartid();
> +???????int i;
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????if (trig_idx_base >= total_trigs || trig_idx_base + trig_count >= total_trigs) {
> +???????????????sbi_dprintf("%s: hart%d: invalid trigger index\n", __func__, hartid);
> +???????????????return SBI_ERR_INVALID_PARAM;
> +???????}
> +
> +???????for (i = 0; i < trig_count; i++) {
> +???????????????xmit = (struct sbi_dbtr_data_msg *)(out_addr + i * sizeof(*xmit));
> +
> +???????????????sbi_dprintf("%s: hart%d: read trigger %d\n", __func__, hartid, i);
> +
> +???????????????xmit->tstate = cpu_to_lle(triggers[hartid][i + trig_idx_base].state.value);
> +???????????????xmit->tdata1 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata1);
> +???????????????xmit->tdata2 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata2);
> +???????????????xmit->tdata3 = cpu_to_lle(triggers[hartid][i + trig_idx_base].tdata3);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_install_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_count, unsigned long in_addr_div_by_16,
> +???????????????unsigned long out_addr_div_by_16, unsigned long *out)
> +{
> +???????unsigned long out_addr = (out_addr_div_by_16 << 4);
> +???????unsigned long in_addr = (in_addr_div_by_16 << 4);
> +???????u32 hartid = current_hartid();
> +???????struct sbi_dbtr_data_msg *recv;
> +???????struct sbi_dbtr_id_msg *xmit;
> +???????union riscv_dbtr_tdata1 ctrl;
> +???????int i, k;
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +???????if (dom && !sbi_domain_check_addr(dom, out_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????/* TODO: check chained triggers configurations */
> +
> +???????/* Check requested triggers configuration */
> +???????for (k = 0; k < trig_count; k++) {
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +???????????????ctrl = (union riscv_dbtr_tdata1)recv->tdata1;
> +
> +???????????????if (!dbtr_trigger_supported(ctrl.type)) {
> +???????????????????????sbi_dprintf("%s: invalid type of trigger %d\n", __func__, k);
> +???????????????????????*out = k;
> +???????????????????????return SBI_ERR_FAILED;
> +???????????????}
> +
> +???????????????if (!dbtr_trigger_valid(ctrl.type, ctrl.value)) {
> +???????????????????????sbi_dprintf("%s: invalid configuration of trigger %d\n", __func__, k);
> +???????????????????????*out = k;
> +???????????????????????return SBI_ERR_FAILED;
> +???????????????}
> +???????}
> +
> +???????/* Check if we have enough spare triggers */
> +???????for (i = 0, k = 0; i < total_trigs; i++) {
> +???????????????if (!triggers[hartid][i].state.mapped)
> +???????????????????????k++;
> +???????}
> +
> +???????if (k < trig_count) {
> +???????????????sbi_dprintf("%s: hartid%d: not enough spare triggers\n", __func__, hartid);
> +???????????????*out = k;
> +???????????????return SBI_ERR_FAILED;
> +???????}
> +
> +???????/* Install triggers */
> +???????for (i = 0, k = 0; i < total_trigs; i++) {
> +???????????????if (triggers[hartid][i].state.mapped)
> +???????????????????????continue;
> +
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + k * sizeof(*recv));
> +???????????????xmit = (struct sbi_dbtr_id_msg *)(out_addr + k * sizeof(*xmit));
> +
> +???????????????sbi_dprintf("%s: hart%d: idx[%d] tdata1[0x%lx] tdata2[0x%lx]\n",
> +?????????????????????????? __func__, hartid, i, recv->tdata1, recv->tdata2);
> +
> +???????????????dbtr_trigger_init(hartid, i,? recv);
> +???????????????dbtr_trigger_enable(hartid, i);
> +???????????????xmit->idx = cpu_to_lle(i);
> +
> +???????????????if (++k >= trig_count)
> +???????????????????????break;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_uninstall_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????if (!triggers[hartid][idx].state.mapped) {
> +???????????????????????sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +???????????????????????return SBI_ERR_INVALID_PARAM;
> +???????????????}
> +
> +???????????????sbi_dprintf("%s: clear trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_clear(hartid, idx);
> +
> +???????????????triggers[hartid][idx].state.value = 0;
> +???????????????triggers[hartid][idx].tdata1 = 0;
> +???????????????triggers[hartid][idx].tdata2 = 0;
> +???????????????triggers[hartid][idx].tdata3 = 0;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_enable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????sbi_dprintf("%s: enable trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_enable(hartid, idx);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_update_trig(const struct sbi_domain *dom, unsigned long smode,
> +???????????????unsigned long trig_idx_base, unsigned long trig_idx_mask,
> +???????????????unsigned long in_addr_div_by_16)
> +{
> +???????unsigned long in_addr = (in_addr_div_by_16 << 4);
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +???????struct sbi_dbtr_data_msg *recv;
> +???????unsigned long uidx = 0;
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????if (smode != PRV_S)
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
> +???????????????return SBI_ERR_DENIED;
> +???????if (dom && !sbi_domain_check_addr(dom, in_addr, smode, SBI_DOMAIN_READ | SBI_DOMAIN_WRITE))
> +???????????????return SBI_ERR_INVALID_ADDRESS;
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????if (!triggers[hartid][idx].state.mapped) {
> +???????????????????????sbi_dprintf("%s: trigger %lu not mapped\n", __func__, idx);
> +???????????????????????return SBI_ERR_INVALID_PARAM;
> +???????????????}
> +
> +???????????????recv = (struct sbi_dbtr_data_msg *)(in_addr + uidx * sizeof(*recv));
> +
> +???????????????sbi_dprintf("%s: update trigger %lu: newaddr 0x%lx\n",
> +?????????????????????????? __func__, idx, recv->tdata2);
> +
> +???????????????triggers[hartid][idx].tdata2 = lle_to_cpu(recv->tdata2);
> +???????????????dbtr_trigger_enable(hartid, idx);
> +???????????????uidx++;
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> +
> +int sbi_dbtr_disable_trig(unsigned long trig_idx_base, unsigned long trig_idx_mask)
> +{
> +???????unsigned long trig_mask = trig_idx_mask << trig_idx_base;
> +???????unsigned long idx = trig_idx_base;
> +???????u32 hartid = current_hartid();
> +
> +???????sbi_dprintf("%s: hart%d: triggers mask: 0x%lx\n",
> +?????????????????? __func__, hartid, trig_mask);
> +
> +???????for_each_set_bit_from(idx, &trig_mask, total_trigs) {
> +???????????????sbi_dprintf("%s: disable trigger %lu\n", __func__, idx);
> +???????????????dbtr_trigger_disable(hartid, idx);
> +???????}
> +
> +???????return SBI_SUCCESS;
> +}
> diff --git a/lib/sbi/sbi_ecall_dbtr.c b/lib/sbi/sbi_ecall_dbtr.c
> new file mode 100644
> index 0000000..d013b3e
> --- /dev/null
> +++ b/lib/sbi/sbi_ecall_dbtr.c
> @@ -0,0 +1,68 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 Syntacore
> + *
> + * Authors:
> + *?? Sergey Matyukevich <sergey.matyukevich at syntacore.com>
> + *
> + */
> +
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_ecall.h>
> +#include <sbi/sbi_domain.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_trap.h>
> +#include <sbi/sbi_version.h>
> +#include <sbi/sbi_dbtr.h>
> +
> +static int sbi_ecall_dbtr_handler(unsigned long extid, unsigned long funcid,
> +???????????????????????????????? const struct sbi_trap_regs *regs,
> +???????????????????????????????? unsigned long *out_val,
> +???????????????????????????????? struct sbi_trap_info *out_trap)
> +{
> +???????unsigned long smode = (csr_read(CSR_MSTATUS) & MSTATUS_MPP) >>
> +???????????????????????MSTATUS_MPP_SHIFT;
> +???????const struct sbi_domain *dom = sbi_domain_thishart_ptr();
> +???????int ret = 0;
> +
> +???????switch (funcid) {
> +???????case SBI_EXT_DBTR_NUM_TRIGGERS:
> +???????????????ret = sbi_dbtr_num_trig(regs->a0, out_val);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_READ:
> +???????????????ret = sbi_dbtr_read_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_INSTALL:
> +???????????????ret = sbi_dbtr_install_trig(dom, smode, regs->a0, regs->a1, regs->a2, out_val);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_UNINSTALL:
> +???????????????ret = sbi_dbtr_uninstall_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_ENABLE:
> +???????????????ret = sbi_dbtr_enable_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_UPDATE:
> +???????????????ret = sbi_dbtr_update_trig(dom, smode, regs->a0, regs->a1, regs->a2);
> +???????????????break;
> +???????case SBI_EXT_DBTR_TRIGGER_DISABLE:
> +???????????????ret = sbi_dbtr_disable_trig(regs->a0, regs->a1);
> +???????????????break;
> +???????default:
> +???????????????ret = SBI_ENOTSUPP;
> +???????};
> +
> +???????return ret;
> +}
> +
> +static int sbi_ecall_dbtr_probe(unsigned long extid, unsigned long *out_val)
> +{
> +???????return sbi_dbtr_probe(out_val);
> +}
> +
> +struct sbi_ecall_extension ecall_dbtr = {
> +???????.extid_start = SBI_EXT_DBTR,
> +???????.extid_end = SBI_EXT_DBTR,
> +???????.handle = sbi_ecall_dbtr_handler,
> +???????.probe = sbi_ecall_dbtr_probe,
> +};
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..956afae 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -21,6 +21,7 @@
> ?#include <sbi/sbi_irqchip.h>
> ?#include <sbi/sbi_platform.h>
> ?#include <sbi/sbi_pmu.h>
> +#include <sbi/sbi_dbtr.h>
> ?#include <sbi/sbi_system.h>
> ?#include <sbi/sbi_string.h>
> ?#include <sbi/sbi_timer.h>
> @@ -275,6 +276,10 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
> ????????if (rc)
> ????????????????sbi_hart_hang();
> ?
> +???????rc = sbi_dbtr_init(scratch);
> +???????if (rc)
> +???????????????sbi_hart_hang();
> +
> ????????sbi_boot_print_banner(scratch);
> ?
> ????????rc = sbi_irqchip_init(scratch, TRUE);
> @@ -380,6 +385,10 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
> ????????if (rc)
> ????????????????sbi_hart_hang();
> ?
> +???????rc = sbi_dbtr_init(scratch);
> +???????if (rc)
> +???????????????sbi_hart_hang();
> +
> ????????rc = sbi_irqchip_init(scratch, FALSE);
> ????????if (rc)
> ????????????????sbi_hart_hang();
> -- 
> 2.38.1
> 
> 




From anup at brainfault.org  Sat Dec 10 08:58:37 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 10 Dec 2022 22:28:37 +0530
Subject: [PATCH 2/3] lib: utils/timer: mtimer: add a quirk for lacking
 mtime register
In-Reply-To: <20221209070120.944152-3-uwu@icenowy.me>
References: <20221209070120.944152-1-uwu@icenowy.me> <20221209070120.944152-3-uwu@icenowy.me>
Message-ID: <CAAhSdy03jnPBFMtUnrTtsmxF-X9+NLz8H+49JszSSMUTOgD7Bw@mail.gmail.com>

On Fri, Dec 9, 2022 at 12:31 PM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> T-Head developers surely have a different understanding of time CSR and
> CLINT's mtime register with SiFive ones, that they did not implement
> the mtime register at all -- as shown in openC906 source code, their
> time CSR value is just exposed at the top of their processor IP block
> and expects an external continous counter, which makes it not
> overrideable, and thus mtime register is not implemented, even not for
> reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
> extended CSR, these systems still rely on the mtimecmp registers to
> generate timer interrupts. This makes it necessary to implement T-Head
> C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
> reading mtime register and falls back to default code that reads time
> CSR.
>
> Add a quirk into MTIMER driver, which represents a mtime register is
> lacking and time CSR value should be used instead.
>
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
> ---
>  include/sbi_utils/timer/aclint_mtimer.h |  1 +
>  lib/utils/timer/aclint_mtimer.c         | 19 +++++++++++-----
>  lib/utils/timer/fdt_timer_mtimer.c      | 29 +++++++++++++++++--------
>  3 files changed, 35 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/timer/aclint_mtimer.h b/include/sbi_utils/timer/aclint_mtimer.h
> index 6ab8799..9724f53 100644
> --- a/include/sbi_utils/timer/aclint_mtimer.h
> +++ b/include/sbi_utils/timer/aclint_mtimer.h
> @@ -35,6 +35,7 @@ struct aclint_mtimer_data {
>         u32 hart_count;
>         bool has_64bit_mmio;
>         bool has_shared_mtime;
> +       bool has_mtime;

No need for a separate "has_mtime" flag.

If "mtime_size != 0" then MTIME mmio register is present else it is absent.

Update this patch accordingly.

>         /* Private details (initialized and used by ACLINT MTIMER library) */
>         struct aclint_mtimer_data *time_delta_reference;
>         unsigned long time_delta_computed;
> diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
> index 3f00c21..f99857b 100644
> --- a/lib/utils/timer/aclint_mtimer.c
> +++ b/lib/utils/timer/aclint_mtimer.c
> @@ -95,7 +95,7 @@ void aclint_mtimer_sync(struct aclint_mtimer_data *mt)
>         struct aclint_mtimer_data *reference;
>
>         /* Sync-up non-shared MTIME if reference is available */
> -       if (mt->has_shared_mtime || !mt->time_delta_reference)
> +       if (!mt->has_mtime || mt->has_shared_mtime || !mt->time_delta_reference)
>                 return;
>
>         reference = mt->time_delta_reference;
> @@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
>         int rc;
>
>         /* Sanity checks */
> -       if (!mt || !mt->mtime_size ||
> +       if (!mt || (mt->has_mtime && !mt->mtime_size) ||
>             (mt->hart_count && !mt->mtimecmp_size) ||
> -           (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> -           (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> +           (mt->has_mtime && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
> +           (mt->has_mtime && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
>             (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
>             (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
>             (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
> @@ -179,7 +179,16 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
>                 mtimer_hartid2data[mt->first_hartid + i] = mt;
>
>         /* Add MTIMER regions to the root domain */
> -       if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
> +       if (!mt->has_mtime) {
> +               rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
> +                                               mt->mtimecmp_size, MTIMER_REGION_ALIGN,
> +                                               SBI_DOMAIN_MEMREGION_MMIO);
> +               if (rc)
> +                       return rc;
> +
> +               /* Disable reading mtime when mtime is not available */
> +               mtimer.timer_value = NULL;
> +       } else if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {

No need for this "if ()" block since "mt->mtime_size == 0" can imply
MTIME is absent.

You only need a separate "if ()" for setting "mtimer.timer_value = NULL;".

>                 rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
>                                         mt->mtime_size + mt->mtimecmp_size,
>                                         MTIMER_REGION_ALIGN,
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index 7b8546b..7ec3907 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -18,6 +18,7 @@
>  struct timer_mtimer_quirks {
>         unsigned int    mtime_offset;
>         bool            has_64bit_mmio;
> +       bool            without_mtime;
>  };
>
>  static unsigned long mtimer_count = 0;
> @@ -53,14 +54,19 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                 /* Set CLINT addresses */
>                 mt->mtimecmp_addr = addr[0] + ACLINT_DEFAULT_MTIMECMP_OFFSET;
>                 mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
> -               mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> -               mt->mtime_size = size[0] - mt->mtimecmp_size;
> +               if (!quirks->without_mtime) {
> +                       mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> +                       mt->mtime_size = size[0] - mt->mtimecmp_size;
> +               }
>                 /* Adjust MTIMER address and size for CLINT device */
> -               mt->mtime_addr += quirks->mtime_offset;
> +               if (!quirks->without_mtime) {
> +                       mt->mtime_addr += quirks->mtime_offset;
> +                       mt->mtime_size -= quirks->mtime_offset;
> +               }
>                 mt->mtimecmp_addr += quirks->mtime_offset;
> -               mt->mtime_size -= quirks->mtime_offset;
>                 /* Apply additional CLINT quirks */
>                 mt->has_64bit_mmio = quirks->has_64bit_mmio;
> +               mt->has_mtime = !quirks->without_mtime;
>         } else { /* RISC-V ACLINT MTIMER */
>                 /* Set ACLINT MTIMER addresses */
>                 mt->mtime_addr = addr[0];
> @@ -70,12 +76,17 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>         }
>
>         /* Check if MTIMER device has shared MTIME address */
> -       mt->has_shared_mtime = false;
> -       for (i = 0; i < mtimer_count; i++) {
> -               if (mtimer[i].mtime_addr == mt->mtime_addr) {
> -                       mt->has_shared_mtime = true;
> -                       break;
> +       if (mt->has_mtime) {
> +               mt->has_shared_mtime = false;
> +               for (i = 0; i < mtimer_count; i++) {
> +                       if (mtimer[i].mtime_addr == mt->mtime_addr) {
> +                               mt->has_shared_mtime = true;
> +                               break;
> +                       }
>                 }
> +       } else {
> +               /* Assume shared time CSR */
> +               mt->has_shared_mtime = true;
>         }
>
>         /* Initialize the MTIMER device */
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

Regards,
Anup


From geomatsi at gmail.com  Sat Dec 10 11:15:57 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sat, 10 Dec 2022 22:15:57 +0300
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <92833f1aeda3262f4ccb4b7fc796ee4de36c7ef0.camel@126.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
 <20221203213929.206429-3-geomatsi@gmail.com>
 <92833f1aeda3262f4ccb4b7fc796ee4de36c7ef0.camel@126.com>
Message-ID: <Y5Ta7XTiBLwRmxBe@curiosity>

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> > 
> > Software support for triggers consists of the following
> > major components:
> > - U-mode: gdb
> > - S-mode: hardware breakpoints framework in Linux kernel
> > - M-mode: SBI firmware code to handle triggers
> > 
> > SBI Debug Trigger extension proposal has been posted by
> > Anup Patel to lists.riscv.org tech-debug mailing list:
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> > 
> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> > 
> > Initial implementation has the following limitations:
> > - supported triggers: mcontrol, mcontrol6
> > - no support for chained triggers
> > - only build test for RV32

... [snip]

> > +struct sbi_dbtr_trig_info {
> > +???????unsigned long type_mask;
> > +???????union sbi_dbtr_trig_state state;
> > +???????unsigned long tdata1;
> > +???????unsigned long tdata2;
> > +???????unsigned long tdata3;
> tdata1~tdata3 can be removed and written directly to scr during install

We need to write those values not only when we install triggers. We have
to rewrite them when we re-enable triggers after disabling or updating.
So I think it is more convenient to keep the whole state at hand.

> > +};
> > +
> > +/** SBI shared mem messages layout */
> > +struct sbi_dbtr_data_msg {
> > +???????unsigned long tstate;
> > +???????unsigned long tdata1;
> > +???????unsigned long tdata2;
> > +???????unsigned long tdata3;
> > +};
> > +
> > +struct sbi_dbtr_id_msg {
> > +???????unsigned long idx;
> > +};

... [snip]

> > +int sbi_dbtr_init(struct sbi_scratch *scratch)
> > +{
> > +???????struct sbi_trap_info trap = {0};
> > +???????u32 hartid = current_hartid();
> > +???????union riscv_dbtr_tdata1 tdata1;
> > +???????unsigned long val;
> > +???????int i;
> > +
> > +???????total_trigs = 0;
> > +
> > +???????for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> > +???????????????csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
> > +???????????????if (trap.cause)
> > +???????????????????????break;
> > +
> > +???????????????val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
> > +???????????????if (trap.cause)
> > +???????????????????????break;
> > +
> > +???????????????/* Read back tselect and check that it contains the written value */
> > +???????????????if (val != i)
> > +???????????????????????break;
> > +
> > +???????????????val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
> > +???????????????if (trap.cause) {
> > +???????????????????????/**
> > +??????????????????????? * If reading tinfo caused an exception, the debugger
> > +??????????????????????? * must read tdata1 to discover the type.
> > +??????????????????????? */
> > +???????????????????????tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
> > +???????????????????????if (trap.cause)
> > +???????????????????????????????break;
> > +
> > +???????????????????????if (tdata1.type == 0)
> > +???????????????????????????????break;
> > +
> > +
> > +???????????????????????sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
> > +???????????????????????total_trigs++;
> > +???????????????} else {
> > +???????????????????????if (val == 1)
> > +???????????????????????????????break;
> tinfo = 0 have to break, this is a invalid value.

Good catch! But it looks like a grey area in the spec.  This function
follows enumeration procedure described in the section 5.1 of Debug
spec v1.0.0. That procedure has the following steps for tinfo:

: 3. Read tinfo.
: 4. If that caused an exception, the debugger must read tdata1 to discover the type.
     (If type is 0, this trigger doesn?t exist. Exit the loop.)
: 5. If info is 1, this trigger doesn?t exist. Exit the loop.
: 6. Otherwise, the selected trigger supports the types discovered in info.
: 7. Repeat, incrementing the value in tselect.

So it looks like tinfo = 0 can be interpreted as valid. For instance,
tinfo = 0 can be returned for a trigger disabled on a hardware level.
Note that type 0 (tinfo = 1) can not be used to do the same since that
value prevents futher enumeration.

I will write to riscv tech-debug mailing list to clarify this point so
that the next revision of patches will include either fix (as per your
comment) or appropriate comment.

Regards,
Sergey


From geomatsi at gmail.com  Sat Dec 10 12:42:22 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Sat, 10 Dec 2022 23:42:22 +0300
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <20221208124904.qi5n6b6k7tamt22t@archlinux>
References: <20221203213929.206429-1-geomatsi@gmail.com>
 <20221203213929.206429-3-geomatsi@gmail.com>
 <20221208124904.qi5n6b6k7tamt22t@archlinux>
Message-ID: <Y5TvLphl1IZj/k9r@curiosity>

> > RISC-V Debug specification includes Sdtrig ISA extension.
> > This extension describes Trigger Module. Triggers can cause
> > a breakpoint exception, entry into Debug Mode, or a trace
> > action without having to execute a special instruction. For
> > native debugging triggers can be used to implement hardware
> > breakpoints and watchpoints.
> > 
> > Software support for triggers consists of the following
> > major components:
> > - U-mode: gdb
> > - S-mode: hardware breakpoints framework in Linux kernel
> > - M-mode: SBI firmware code to handle triggers
> > 
> > SBI Debug Trigger extension proposal has been posted by
> > Anup Patel to lists.riscv.org tech-debug mailing list:
> > https://lists.riscv.org/g/tech-debug/topic/92375492
> > 
> > This patch provides initial implementation of SBI Debug
> > Trigger Extension in OpenSBI library based on the
> > suggested extension proposal.
> > 
> > Initial implementation has the following limitations:
> > - supported triggers: mcontrol, mcontrol6
> > - no support for chained triggers
> > - only build test for RV32

... [snip]

> > +union riscv_dbtr_tdata1 {
> > +	unsigned long value;
> > +	struct {
> > +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> > +		unsigned long type:4;
> > +		unsigned long dmode:1;
> > +#if __riscv_xlen == 64
> > +		unsigned long data:59;
> > +#elif __riscv_xlen == 32
> > +		unsigned long data:27;
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif
> > +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> > +#if __riscv_xlen == 64
> > +		unsigned long data:59;
> > +#elif __riscv_xlen == 32
> > +		unsigned long data:27;
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif
> > +		unsigned long dmode:1;
> > +		unsigned long type:4;
> > +#else
> > +#error "Unexpected endianness"
> > +#endif
> > +	};
> > +};
> 
> Since, RISC-V implementations can allow a combination of different endianness for
> M-mode and S-mode software. I am wondering how would this be handled if S-mode
> software is actually different endianess?

This approach is not suitable for universal binaries that will work
on both LE and BE hardware. This is a build-time approach when you
know the target platform that you are building for. SBI Debug Trigger
extension requires LE word format in messages passed between S-mode
software and M-mode SBI firmware. That is handled by endiannes
conversion macros added in the previous patch in this series.

IIUC the initial discussion around endianness has been inspired by heavy
use of bitfields in this patch. I probably should replace them by
something less controversial )

However if there is a serious intention to move towards proper LE/BE
support in OpenSBI (including different M/S endianness combinations),
then it should be done separately from these SBI debug extension
patches.

> > +
> > +union riscv_dbtr_tdata1_mcontrol {
> > +	unsigned long value;
> > +	struct {
> > +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> > +		unsigned long type:4;
> > +		unsigned long dmode:1;
> > +		unsigned long maskmax:6;
> > +#if __riscv_xlen >= 64
> > +		unsigned long _res1:30;
> > +		unsigned long sizehi:2;
> > +#endif
> > +		unsigned long hit:1;
> > +		unsigned long select:1;
> > +		unsigned long timing:1;
> > +		unsigned long sizelo:2;
> > +		unsigned long action:4;
> > +		unsigned long chain:1;
> > +		unsigned long match:4;
> > +		unsigned long m:1;
> > +		unsigned long _res2:1;
> > +		unsigned long s:1;
> > +		unsigned long u:1;
> > +		unsigned long execute:1;
> > +		unsigned long store:1;
> > +		unsigned long load:1;
> > +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> > +		unsigned long load:1;
> > +		unsigned long store:1;
> > +		unsigned long execute:1;
> > +		unsigned long u:1;
> > +		unsigned long s:1;
> > +		unsigned long _res2:1;
> > +		unsigned long m:1;
> > +		unsigned long match:4;
> > +		unsigned long chain:1;
> > +		unsigned long action:4;
> > +		unsigned long sizelo:2;
> > +		unsigned long timing:1;
> > +		unsigned long select:1;
> > +		unsigned long hit:1;
> > +#if __riscv_xlen >= 64
> > +		unsigned long sizehi:2;
> > +		unsigned long _res1:30;
> > +#endif
> > +		unsigned long maskmax:6;
> > +		unsigned long dmode:1;
> > +		unsigned long type:4;
> > +#else
> > +#error "Unexpected endianness"
> > +#endif
> > +	};
> > +};
> > +
> > +#define MCONTROL_U_OFFSET	3
> > +#define MCONTROL_S_OFFSET	4
> > +#define MCONTROL_M_OFFSET	6
> > +
> > +union riscv_dbtr_tdata1_mcontrol6 {
> > +	unsigned long value;
> > +	struct {
> > +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> > +		unsigned long type:4;
> > +		unsigned long dmode:1;
> > +#if __riscv_xlen == 64
> > +		unsigned long _res1:34;
> > +#elif __riscv_xlen == 32
> > +		unsigned long _res1:2;
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif
> > +		unsigned long vs:1;
> > +		unsigned long vu:1;
> > +		unsigned long hit:1;
> > +		unsigned long select:1;
> > +		unsigned long timing:1;
> > +		unsigned long size:4;
> > +		unsigned long action:4;
> > +		unsigned long chain:1;
> > +		unsigned long match:4;
> > +		unsigned long m:1;
> > +		unsigned long _res2:1;
> > +		unsigned long s:1;
> > +		unsigned long u:1;
> > +		unsigned long execute:1;
> > +		unsigned long store:1;
> > +		unsigned long load:1;
> > +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
> > +		unsigned long load:1;
> > +		unsigned long store:1;
> > +		unsigned long execute:1;
> > +		unsigned long u:1;
> > +		unsigned long s:1;
> > +		unsigned long _res2:1;
> > +		unsigned long m:1;
> > +		unsigned long match:4;
> > +		unsigned long chain:1;
> > +		unsigned long action:4;
> > +		unsigned long size:4;
> > +		unsigned long timing:1;
> > +		unsigned long select:1;
> > +		unsigned long hit:1;
> > +		unsigned long vu:1;
> > +		unsigned long vs:1;
> > +#if __riscv_xlen == 64
> > +		unsigned long _res1:34;
> > +#elif __riscv_xlen == 32
> > +		unsigned long _res1:2;
> > +#else
> > +#error "Unexpected __riscv_xlen"
> > +#endif
> > +		unsigned long dmode:1;
> > +		unsigned long type:4;
> > +#else
> > +#error "Unexpected endianness"
> > +#endif
> > +	};
> > +};
> Also, IMHO, these definitions defined under aren't maintenance friendly.

I assume that if Debug spec v1.0.0 is frozen and ratified,
then those definitions will not need a lot of changes.
So could you please clarify your concern ?

 
> > +
> > +#define MCONTROL6_U_OFFSET	3
> > +#define MCONTROL6_S_OFFSET	4
> > +#define MCONTROL6_M_OFFSET	6
> > +#define MCONTROL6_VU_OFFSET	23
> > +#define MCONTROL6_VS_OFFSET	24
> > +
> > +#endif /* __RISCV_DBTR_H__ */

Regards,
Sergey


From wxjstz at 126.com  Sat Dec 10 17:40:03 2022
From: wxjstz at 126.com (Xiang W)
Date: Sun, 11 Dec 2022 09:40:03 +0800
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <Y5Ta7XTiBLwRmxBe@curiosity>
References: <20221203213929.206429-1-geomatsi@gmail.com>
	 <20221203213929.206429-3-geomatsi@gmail.com>
	 <92833f1aeda3262f4ccb4b7fc796ee4de36c7ef0.camel@126.com>
	 <Y5Ta7XTiBLwRmxBe@curiosity>
Message-ID: <cd24a0c91272bf5e636c90c2071f6e22bd500cf9.camel@126.com>

? 2022-12-10???? 22:15 +0300?Sergey Matyukevich???
> > > RISC-V Debug specification includes Sdtrig ISA extension.
> > > This extension describes Trigger Module. Triggers can cause
> > > a breakpoint exception, entry into Debug Mode, or a trace
> > > action without having to execute a special instruction. For
> > > native debugging triggers can be used to implement hardware
> > > breakpoints and watchpoints.
> > > 
> > > Software support for triggers consists of the following
> > > major components:
> > > - U-mode: gdb
> > > - S-mode: hardware breakpoints framework in Linux kernel
> > > - M-mode: SBI firmware code to handle triggers
> > > 
> > > SBI Debug Trigger extension proposal has been posted by
> > > Anup Patel to lists.riscv.org tech-debug mailing list:
> > > https://lists.riscv.org/g/tech-debug/topic/92375492
> > > 
> > > This patch provides initial implementation of SBI Debug
> > > Trigger Extension in OpenSBI library based on the
> > > suggested extension proposal.
> > > 
> > > Initial implementation has the following limitations:
> > > - supported triggers: mcontrol, mcontrol6
> > > - no support for chained triggers
> > > - only build test for RV32
> 
> ... [snip]
> 
> > > +struct sbi_dbtr_trig_info {
> > > +???????unsigned long type_mask;
> > > +???????union sbi_dbtr_trig_state state;
> > > +???????unsigned long tdata1;
> > > +???????unsigned long tdata2;
> > > +???????unsigned long tdata3;
> > tdata1~tdata3 can be removed and written directly to scr during install
> 
> We need to write those values not only when we install triggers. We have
> to rewrite them when we re-enable triggers after disabling or updating.
> So I think it is more convenient to keep the whole state at hand.

when install, write directly to tdata1~data3
when read, read from tdata1~tdata3, and OR the vs/vu/s/u bits in trig_status with tdata1  
when disable, clear vs/vu/s/u in tdata1 
when enable, write vs/vu/s/u in trig_state to tdata1
when updat, Only need write recv to tdata2

Does not require more memory to save tdata1~tdata3

Regards,
Xiang W
> 
> > > +};
> > > +
> > > +/** SBI shared mem messages layout */
> > > +struct sbi_dbtr_data_msg {
> > > +???????unsigned long tstate;
> > > +???????unsigned long tdata1;
> > > +???????unsigned long tdata2;
> > > +???????unsigned long tdata3;
> > > +};
> > > +
> > > +struct sbi_dbtr_id_msg {
> > > +???????unsigned long idx;
> > > +};
> 
> ... [snip]
> 
> > > +int sbi_dbtr_init(struct sbi_scratch *scratch)
> > > +{
> > > +???????struct sbi_trap_info trap = {0};
> > > +???????u32 hartid = current_hartid();
> > > +???????union riscv_dbtr_tdata1 tdata1;
> > > +???????unsigned long val;
> > > +???????int i;
> > > +
> > > +???????total_trigs = 0;
> > > +
> > > +???????for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> > > +???????????????csr_write_allowed(CSR_TSELECT, (ulong)&trap, i);
> > > +???????????????if (trap.cause)
> > > +???????????????????????break;
> > > +
> > > +???????????????val = csr_read_allowed(CSR_TSELECT, (ulong)&trap);
> > > +???????????????if (trap.cause)
> > > +???????????????????????break;
> > > +
> > > +???????????????/* Read back tselect and check that it contains the written value */
> > > +???????????????if (val != i)
> > > +???????????????????????break;
> > > +
> > > +???????????????val = csr_read_allowed(CSR_TINFO, (ulong)&trap);
> > > +???????????????if (trap.cause) {
> > > +???????????????????????/**
> > > +??????????????????????? * If reading tinfo caused an exception, the debugger
> > > +??????????????????????? * must read tdata1 to discover the type.
> > > +??????????????????????? */
> > > +???????????????????????tdata1.value = csr_read_allowed(CSR_TDATA1, (ulong)&trap);
> > > +???????????????????????if (trap.cause)
> > > +???????????????????????????????break;
> > > +
> > > +???????????????????????if (tdata1.type == 0)
> > > +???????????????????????????????break;
> > > +
> > > +
> > > +???????????????????????sbi_triggers_table_init(hartid, i, BIT(tdata1.type));
> > > +???????????????????????total_trigs++;
> > > +???????????????} else {
> > > +???????????????????????if (val == 1)
> > > +???????????????????????????????break;
> > tinfo = 0 have to break, this is a invalid value.
> 
> Good catch! But it looks like a grey area in the spec.? This function
> follows enumeration procedure described in the section 5.1 of Debug
> spec v1.0.0. That procedure has the following steps for tinfo:
> 
> : 3. Read tinfo.
> : 4. If that caused an exception, the debugger must read tdata1 to discover the type.
> ???? (If type is 0, this trigger doesn?t exist. Exit the loop.)
> : 5. If info is 1, this trigger doesn?t exist. Exit the loop.
> : 6. Otherwise, the selected trigger supports the types discovered in info.
> : 7. Repeat, incrementing the value in tselect.
> 
> So it looks like tinfo = 0 can be interpreted as valid. For instance,
> tinfo = 0 can be returned for a trigger disabled on a hardware level.
> Note that type 0 (tinfo = 1) can not be used to do the same since that
> value prevents futher enumeration.
> 
> I will write to riscv tech-debug mailing list to clarify this point so
> that the next revision of patches will include either fix (as per your
> comment) or appropriate comment.
> 
> Regards,
> Sergey




From bmeng at tinylab.org  Sat Dec 10 22:54:22 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun, 11 Dec 2022 14:54:22 +0800
Subject: [PATCH v3 3/5] lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <20221211065424.806478-3-bmeng@tinylab.org>

The number of interrupt enable register in words was once correct,
but was wrongly changed to have an off-by-one error since
commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").

Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Anup Patel <anup at brainfault.org>

---

(no changes since v2)

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()

 lib/utils/irqchip/plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index dca5678..568f814 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -127,7 +127,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
 	if (!plic || context_id < 0)
 		return SBI_EINVAL;
 
-	ie_words = (plic->num_src + 31) / 32;
+	ie_words = plic->num_src / 32 + 1;
 	ie_value = enable ? 0xffffffffU : 0U;
 
 	for (u32 i = 0; i < ie_words; i++)
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec 10 22:54:20 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun, 11 Dec 2022 14:54:20 +0800
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers
Message-ID: <20221211065424.806478-1-bmeng@tinylab.org>

Interrupt source 0 is reserved. Hence the irq should start from 1.

Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Anup Patel <anup at brainfault.org>
---

(no changes since v1)

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 73d7788..4df9020 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 
 void plic_priority_save(const struct plic_data *plic, u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
 {
-	for (u32 i = 0; i < plic->num_src; i++)
+	for (u32 i = 1; i <= plic->num_src; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec 10 22:54:21 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun, 11 Dec 2022 14:54:21 +0800
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <20221211065424.806478-2-bmeng@tinylab.org>

Currently the priority save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v3:
- fix the size limit check
- move the size limit check to plic_priority_save/restore
- add parameter description to fdt_plic_priority_save/restore

Changes in v2:
- new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h | 14 ++++++++++++--
 include/sbi_utils/irqchip/plic.h             |  5 +++--
 lib/utils/irqchip/fdt_irqchip_plic.c         |  8 ++++----
 lib/utils/irqchip/plic.c                     | 15 +++++++++++----
 platform/generic/allwinner/sun20i-d1.c       |  4 ++--
 5 files changed, 32 insertions(+), 14 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index 98d4de5..d5b1c60 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -9,9 +9,19 @@
 
 #include <sbi/sbi_types.h>
 
-void fdt_plic_priority_save(u8 *priority);
+/**
+ * Save the PLIC priority state
+ * @param priority pointer to the memory region for the saved priority
+ * @param num size of the memory region including interrupt source 0
+ */
+void fdt_plic_priority_save(u8 *priority, u32 num);
 
-void fdt_plic_priority_restore(const u8 *priority);
+/**
+ * Restore the PLIC priority state
+ * @param priority pointer to the memory region for the saved priority
+ * @param num size of the memory region including interrupt source 0
+ */
+void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 48c24f0..38704a1 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -18,9 +18,10 @@ struct plic_data {
 };
 
 /* So far, priorities on all consumers of these functions fit in 8 bits. */
-void plic_priority_save(const struct plic_data *plic, u8 *priority);
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index fe08836..7d76c5b 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -24,18 +24,18 @@ static struct plic_data plic[PLIC_MAX_NR];
 static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
 static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
 
-void fdt_plic_priority_save(u8 *priority)
+void fdt_plic_priority_save(u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_save(plic, priority);
+	plic_priority_save(plic, priority, num);
 }
 
-void fdt_plic_priority_restore(const u8 *priority)
+void fdt_plic_priority_restore(const u8 *priority, u32 num)
 {
 	struct plic_data *plic = plic_hartid2data[current_hartid()];
 
-	plic_priority_restore(plic, priority);
+	plic_priority_restore(plic, priority, num);
 }
 
 void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 4df9020..dca5678 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -36,15 +36,22 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 	writel(val, plic_priority);
 }
 
-void plic_priority_save(const struct plic_data *plic, u8 *priority)
+void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	if (num > plic->num_src)
+		num = plic->num_src;
+
+	for (u32 i = 1; i <= num; i++)
 		priority[i] = plic_get_priority(plic, i);
 }
 
-void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
+void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
+			   u32 num)
 {
-	for (u32 i = 1; i <= plic->num_src; i++)
+	if (num > plic->num_src)
+		num = plic->num_src;
+
+	for (u32 i = 1; i <= num; i++)
 		plic_set_priority(plic, i, priority[i]);
 }
 
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 18d330d..1f27575 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -79,13 +79,13 @@ static u32 plic_threshold;
 static void sun20i_d1_plic_save(void)
 {
 	fdt_plic_context_save(true, plic_sie, &plic_threshold);
-	fdt_plic_priority_save(plic_priority);
+	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
 static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
-	fdt_plic_priority_restore(plic_priority);
+	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
 	fdt_plic_context_restore(true, plic_sie, plic_threshold);
 }
 
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec 10 22:54:24 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun, 11 Dec 2022 14:54:24 +0800
Subject: [PATCH v3 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <20221211065424.806478-5-bmeng@tinylab.org>

Currently the context save/restore helpers writes/reads the provided
array using an index whose maximum value is determined by PLIC, which
potentially may disagree with the caller to these helpers.

Add a parameter to ask the caller to provide the size limit of the
array to ensure no out-of-bound access happens.

Signed-off-by: Bin Meng <bmeng at tinylab.org>

---

Changes in v3:
- move the size limit check to plic_context_save/restore

Changes in v2:
- new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers

 include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
 include/sbi_utils/irqchip/plic.h             |  4 ++--
 lib/utils/irqchip/fdt_irqchip_plic.c         |  9 +++++----
 lib/utils/irqchip/plic.c                     | 14 ++++++++++----
 platform/generic/allwinner/sun20i-d1.c       |  5 +++--
 5 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
index d5b1c60..df645dd 100644
--- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
+++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
@@ -23,9 +23,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
  */
 void fdt_plic_priority_restore(const u8 *priority, u32 num);
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num);
 
 void thead_plic_restore(void);
 
diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
index 38704a1..112a714 100644
--- a/include/sbi_utils/irqchip/plic.h
+++ b/include/sbi_utils/irqchip/plic.h
@@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
 			   u32 num);
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold);
+		       u32 *enable, u32 *threshold, u32 num);
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold);
+			  const u32 *enable, u32 threshold, u32 num);
 
 int plic_context_init(const struct plic_data *plic, int context_id,
 		      bool enable, u32 threshold);
diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
index 7d76c5b..c54f45c 100644
--- a/lib/utils/irqchip/fdt_irqchip_plic.c
+++ b/lib/utils/irqchip/fdt_irqchip_plic.c
@@ -38,22 +38,23 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
 	plic_priority_restore(plic, priority, num);
 }
 
-void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
+void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
 {
 	u32 hartid = current_hartid();
 
 	plic_context_save(plic_hartid2data[hartid],
 			  plic_hartid2context[hartid][smode],
-			  enable, threshold);
+			  enable, threshold, num);
 }
 
-void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
+void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
+			      u32 num)
 {
 	u32 hartid = current_hartid();
 
 	plic_context_restore(plic_hartid2data[hartid],
 			     plic_hartid2context[hartid][smode],
-			     enable, threshold);
+			     enable, threshold, num);
 }
 
 static int irqchip_plic_warm_init(void)
diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index b152bb7..8089a0b 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -98,22 +98,28 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 }
 
 void plic_context_save(const struct plic_data *plic, int context_id,
-		       u32 *enable, u32 *threshold)
+		       u32 *enable, u32 *threshold, u32 num)
 {
 	u32 ie_words = plic->num_src / 32 + 1;
 
-	for (u32 i = 0; i < ie_words; i++)
+	if (num > ie_words)
+		num = ie_words;
+
+	for (u32 i = 0; i < num; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
 
 	*threshold = plic_get_thresh(plic, context_id);
 }
 
 void plic_context_restore(const struct plic_data *plic, int context_id,
-			  const u32 *enable, u32 threshold)
+			  const u32 *enable, u32 threshold, u32 num)
 {
 	u32 ie_words = plic->num_src / 32 + 1;
 
-	for (u32 i = 0; i < ie_words; i++)
+	if (num > ie_words)
+		num = ie_words;
+
+	for (u32 i = 0; i < num; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
 
 	plic_set_thresh(plic, context_id, threshold);
diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 1f27575..1da9e5b 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -78,7 +78,7 @@ static u32 plic_threshold;
 
 static void sun20i_d1_plic_save(void)
 {
-	fdt_plic_context_save(true, plic_sie, &plic_threshold);
+	fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
 	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
 }
 
@@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
 {
 	thead_plic_restore();
 	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
-	fdt_plic_context_restore(true, plic_sie, plic_threshold);
+	fdt_plic_context_restore(true, plic_sie, plic_threshold,
+				 PLIC_IE_WORDS);
 }
 
 /*
-- 
2.34.1



From bmeng at tinylab.org  Sat Dec 10 22:54:23 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sun, 11 Dec 2022 14:54:23 +0800
Subject: [PATCH v3 4/5] lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <20221211065424.806478-4-bmeng@tinylab.org>

plic->num_src holds the number of interrupt sources without interrupt
source 0 but the interrupt enable register includes a bit for the
interrupt source 0 in the first word.

Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
Reviewed-by: Anup Patel <anup at brainfault.org>

---

(no changes since v2)

Changes in v2:
- new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers

 lib/utils/irqchip/plic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index 568f814..b152bb7 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -100,7 +100,7 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
 void plic_context_save(const struct plic_data *plic, int context_id,
 		       u32 *enable, u32 *threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		enable[i] = plic_get_ie(plic, context_id, i);
@@ -111,7 +111,7 @@ void plic_context_save(const struct plic_data *plic, int context_id,
 void plic_context_restore(const struct plic_data *plic, int context_id,
 			  const u32 *enable, u32 threshold)
 {
-	u32 ie_words = (plic->num_src + 31) / 32;
+	u32 ie_words = plic->num_src / 32 + 1;
 
 	for (u32 i = 0; i < ie_words; i++)
 		plic_set_ie(plic, context_id, i, enable[i]);
-- 
2.34.1



From schwab at linux-m68k.org  Sun Dec 11 02:07:01 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Sun, 11 Dec 2022 11:07:01 +0100
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one
 error in priority save/restore helpers
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org> (Bin Meng's message
	of "Sun, 11 Dec 2022 14:54:20 +0800")
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <87a63ufe4a.fsf@linux-m68k.org>

On Dez 11 2022, Bin Meng wrote:

> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 73d7788..4df9020 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>  
>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>  {
> -	for (u32 i = 0; i < plic->num_src; i++)
> +	for (u32 i = 1; i <= plic->num_src; i++)
>  		priority[i] = plic_get_priority(plic, i);

That needs to adjust the index into the priority array.

>  void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
>  {
> -	for (u32 i = 0; i < plic->num_src; i++)
> +	for (u32 i = 1; i <= plic->num_src; i++)
>  		plic_set_priority(plic, i, priority[i]);

Likewise.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From bmeng.cn at gmail.com  Sun Dec 11 02:18:07 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sun, 11 Dec 2022 18:18:07 +0800
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in priority save/restore helpers
In-Reply-To: <87a63ufe4a.fsf@linux-m68k.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <87a63ufe4a.fsf@linux-m68k.org>
Message-ID: <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>

On Sun, Dec 11, 2022 at 6:08 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>
> On Dez 11 2022, Bin Meng wrote:
>
> > diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> > index 73d7788..4df9020 100644
> > --- a/lib/utils/irqchip/plic.c
> > +++ b/lib/utils/irqchip/plic.c
> > @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
> >
> >  void plic_priority_save(const struct plic_data *plic, u8 *priority)
> >  {
> > -     for (u32 i = 0; i < plic->num_src; i++)
> > +     for (u32 i = 1; i <= plic->num_src; i++)
> >               priority[i] = plic_get_priority(plic, i);
>
> That needs to adjust the index into the priority array.

Does that help anything? It just confuses people more.

I added function parameter descriptions in patch 2 to make it crystal
clear, that the priority array needs to include interrupt source 0.

>
> >  void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> >  {
> > -     for (u32 i = 0; i < plic->num_src; i++)
> > +     for (u32 i = 1; i <= plic->num_src; i++)
> >               plic_set_priority(plic, i, priority[i]);
>
> Likewise.
>

Regards,
Bin


From schwab at linux-m68k.org  Sun Dec 11 02:52:33 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Sun, 11 Dec 2022 11:52:33 +0100
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one
 error in priority save/restore helpers
In-Reply-To: <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
	(Bin Meng's message of "Sun, 11 Dec 2022 18:18:07 +0800")
References: <20221211065424.806478-1-bmeng@tinylab.org>
	<87a63ufe4a.fsf@linux-m68k.org>
	<CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
Message-ID: <875yeifc0e.fsf@linux-m68k.org>

On Dez 11 2022, Bin Meng wrote:

> On Sun, Dec 11, 2022 at 6:08 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>>
>> On Dez 11 2022, Bin Meng wrote:
>>
>> > diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
>> > index 73d7788..4df9020 100644
>> > --- a/lib/utils/irqchip/plic.c
>> > +++ b/lib/utils/irqchip/plic.c
>> > @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>> >
>> >  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>> >  {
>> > -     for (u32 i = 0; i < plic->num_src; i++)
>> > +     for (u32 i = 1; i <= plic->num_src; i++)
>> >               priority[i] = plic_get_priority(plic, i);
>>
>> That needs to adjust the index into the priority array.
>
> Does that help anything?

Yes, it fixes an off-by-one error.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From anup at brainfault.org  Sun Dec 11 04:03:20 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 11 Dec 2022 17:33:20 +0530
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <20221211065424.806478-2-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-2-bmeng@tinylab.org>
Message-ID: <CAAhSdy3F56KnQeULDWdRJU7JeZybCUxgXp=7V07bywMtVjYepA@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:25 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the priority save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

>
> ---
>
> Changes in v3:
> - fix the size limit check
> - move the size limit check to plic_priority_save/restore
> - add parameter description to fdt_plic_priority_save/restore
>
> Changes in v2:
> - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h | 14 ++++++++++++--
>  include/sbi_utils/irqchip/plic.h             |  5 +++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  8 ++++----
>  lib/utils/irqchip/plic.c                     | 15 +++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
>  5 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 98d4de5..d5b1c60 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -9,9 +9,19 @@
>
>  #include <sbi/sbi_types.h>
>
> -void fdt_plic_priority_save(u8 *priority);
> +/**
> + * Save the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_save(u8 *priority, u32 num);
>
> -void fdt_plic_priority_restore(const u8 *priority);
> +/**
> + * Restore the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 48c24f0..38704a1 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -18,9 +18,10 @@ struct plic_data {
>  };
>
>  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
>                        u32 *enable, u32 *threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index fe08836..7d76c5b 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -24,18 +24,18 @@ static struct plic_data plic[PLIC_MAX_NR];
>  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
>  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
>
> -void fdt_plic_priority_save(u8 *priority)
> +void fdt_plic_priority_save(u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_save(plic, priority);
> +       plic_priority_save(plic, priority, num);
>  }
>
> -void fdt_plic_priority_restore(const u8 *priority)
> +void fdt_plic_priority_restore(const u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_restore(plic, priority);
> +       plic_priority_restore(plic, priority, num);
>  }
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 4df9020..dca5678 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -36,15 +36,22 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>         writel(val, plic_priority);
>  }
>
> -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       if (num > plic->num_src)
> +               num = plic->num_src;
> +
> +       for (u32 i = 1; i <= num; i++)
>                 priority[i] = plic_get_priority(plic, i);
>  }
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       if (num > plic->num_src)
> +               num = plic->num_src;
> +
> +       for (u32 i = 1; i <= num; i++)
>                 plic_set_priority(plic, i, priority[i]);
>  }
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 18d330d..1f27575 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>  static void sun20i_d1_plic_save(void)
>  {
>         fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -       fdt_plic_priority_save(plic_priority);
> +       fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
>  static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
> -       fdt_plic_priority_restore(plic_priority);
> +       fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>         fdt_plic_context_restore(true, plic_sie, plic_threshold);
>  }
>
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sun Dec 11 04:06:03 2022
From: anup at brainfault.org (Anup Patel)
Date: Sun, 11 Dec 2022 17:36:03 +0530
Subject: [PATCH v3 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in context save/restore helpers
In-Reply-To: <20221211065424.806478-5-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-5-bmeng@tinylab.org>
Message-ID: <CAAhSdy1Mo_pMOFvF6Wvc2t3LRnQt2MKeo=nqKzYoGp+9pv=yGw@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:25 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the context save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

>
> ---
>
> Changes in v3:
> - move the size limit check to plic_context_save/restore
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
>  include/sbi_utils/irqchip/plic.h             |  4 ++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  9 +++++----
>  lib/utils/irqchip/plic.c                     | 14 ++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  5 +++--
>  5 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index d5b1c60..df645dd 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -23,9 +23,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
>   */
>  void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num);
>
>  void thead_plic_restore(void);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 38704a1..112a714 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
>                            u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold);
> +                      u32 *enable, u32 *threshold, u32 num);
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold);
> +                         const u32 *enable, u32 threshold, u32 num);
>
>  int plic_context_init(const struct plic_data *plic, int context_id,
>                       bool enable, u32 threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index 7d76c5b..c54f45c 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -38,22 +38,23 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
>         plic_priority_restore(plic, priority, num);
>  }
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
>  {
>         u32 hartid = current_hartid();
>
>         plic_context_save(plic_hartid2data[hartid],
>                           plic_hartid2context[hartid][smode],
> -                         enable, threshold);
> +                         enable, threshold, num);
>  }
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num)
>  {
>         u32 hartid = current_hartid();
>
>         plic_context_restore(plic_hartid2data[hartid],
>                              plic_hartid2context[hartid][smode],
> -                            enable, threshold);
> +                            enable, threshold, num);
>  }
>
>  static int irqchip_plic_warm_init(void)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index b152bb7..8089a0b 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -98,22 +98,28 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
>  }
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold)
> +                      u32 *enable, u32 *threshold, u32 num)
>  {
>         u32 ie_words = plic->num_src / 32 + 1;
>
> -       for (u32 i = 0; i < ie_words; i++)
> +       if (num > ie_words)
> +               num = ie_words;
> +
> +       for (u32 i = 0; i < num; i++)
>                 enable[i] = plic_get_ie(plic, context_id, i);
>
>         *threshold = plic_get_thresh(plic, context_id);
>  }
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold)
> +                         const u32 *enable, u32 threshold, u32 num)
>  {
>         u32 ie_words = plic->num_src / 32 + 1;
>
> -       for (u32 i = 0; i < ie_words; i++)
> +       if (num > ie_words)
> +               num = ie_words;
> +
> +       for (u32 i = 0; i < num; i++)
>                 plic_set_ie(plic, context_id, i, enable[i]);
>
>         plic_set_thresh(plic, context_id, threshold);
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 1f27575..1da9e5b 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -78,7 +78,7 @@ static u32 plic_threshold;
>
>  static void sun20i_d1_plic_save(void)
>  {
> -       fdt_plic_context_save(true, plic_sie, &plic_threshold);
> +       fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
>         fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
> @@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
>         fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> -       fdt_plic_context_restore(true, plic_sie, plic_threshold);
> +       fdt_plic_context_restore(true, plic_sie, plic_threshold,
> +                                PLIC_IE_WORDS);
>  }
>
>  /*
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From schwab at linux-m68k.org  Sun Dec 11 04:11:46 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Sun, 11 Dec 2022 13:11:46 +0100
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one
 error in priority save/restore helpers
In-Reply-To: <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
	(Bin Meng's message of "Sun, 11 Dec 2022 18:18:07 +0800")
References: <20221211065424.806478-1-bmeng@tinylab.org>
	<87a63ufe4a.fsf@linux-m68k.org>
	<CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
Message-ID: <87v8miqgvx.fsf@igel.home>

On Dez 11 2022, Bin Meng wrote:

> I added function parameter descriptions in patch 2 to make it crystal
> clear, that the priority array needs to include interrupt source 0.

It should say that the array size must be one more than the maximum
number of sources.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From schwab at linux-m68k.org  Sun Dec 11 04:11:53 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Sun, 11 Dec 2022 13:11:53 +0100
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <20221211065424.806478-2-bmeng@tinylab.org> (Bin Meng's message
	of "Sun, 11 Dec 2022 14:54:21 +0800")
References: <20221211065424.806478-1-bmeng@tinylab.org>
	<20221211065424.806478-2-bmeng@tinylab.org>
Message-ID: <87tu22qgvq.fsf@igel.home>

On Dez 11 2022, Bin Meng wrote:

> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 18d330d..1f27575 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>  static void sun20i_d1_plic_save(void)
>  {
>  	fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -	fdt_plic_priority_save(plic_priority);
> +	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>  
>  static void sun20i_d1_plic_restore(void)
>  {
>  	thead_plic_restore();
> -	fdt_plic_priority_restore(plic_priority);
> +	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>  	fdt_plic_context_restore(true, plic_sie, plic_threshold);
>  }

That fails to update the size of the plic_priority arraay.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From debug at rivosinc.com  Sun Dec 11 19:08:02 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Sun, 11 Dec 2022 19:08:02 -0800
Subject: [PATCH Zisslpcfi 0/2] Support for zisslpcfi in opensbi
Message-ID: <20221212030804.927309-1-debug@rivosinc.com>

Zisslpcfi [1] extension extends risc-v architecture to mitigate against
control-flow integrity attacks (ROP/JOP/COP). 

Zisslpcfi uses bits (b23-b29) in (m/s/vs) status CSR for enabling cfi in
lesser privileged mode and record cfi state. One such state is expected
landing pad (ELP). If forward cfi is enabled, indirect call/jmp updates
hart's ELP state (1bit) to true. ELP state is cleared only by a landing 
pad instruction else trap is delivered with ELP state recorded in sstatus
CSR.

This two patch series adds following changes to opensbi
    - Adds support in opensbi to detect zisslpcfi
    - trap redirection updates ELP state accordingly

[1] - https://github.com/riscv/riscv-cfi

Deepak Gupta (2):
  include: adding support for zsslpcfi encodings
  lib: sbi: zsslpcfi detection and elp cfi state reflect back in status

 include/sbi/riscv_encoding.h |  6 ++++++
 include/sbi/sbi_hart.h       |  2 ++
 lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
 lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
 4 files changed, 47 insertions(+)

-- 
2.25.1



From debug at rivosinc.com  Sun Dec 11 19:08:03 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Sun, 11 Dec 2022 19:08:03 -0800
Subject: [PATCH Zisslpcfi 1/2] include: adding support for zsslpcfi encodings
In-Reply-To: <20221212030804.927309-1-debug@rivosinc.com>
References: <20221212030804.927309-1-debug@rivosinc.com>
Message-ID: <20221212030804.927309-2-debug@rivosinc.com>

zsslpcfi extension (see links) introduces b60 (CFI) in menvcfg CSR to
enable shadow stack and landing pad for machine and lesser privileged
modes. Additionally extension introduces new bits in xstatus for cfi
state.

Links:https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug at rivosinc.com>
---
 include/sbi/riscv_encoding.h | 4 ++++
 include/sbi/sbi_hart.h       | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index b0f08c8..1fb520f 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -210,9 +210,11 @@
 #if __riscv_xlen > 32
 #define ENVCFG_STCE			(_ULL(1) << 63)
 #define ENVCFG_PBMTE			(_ULL(1) << 62)
+#define ENVCFG_CFI			(_ULL(1) << 60)
 #else
 #define ENVCFGH_STCE			(_UL(1) << 31)
 #define ENVCFGH_PBMTE			(_UL(1) << 30)
+#define ENVCFGH_CFI			(_UL(1) << 28)
 #endif
 #define ENVCFG_CBZE			(_UL(1) << 7)
 #define ENVCFG_CBCFE			(_UL(1) << 6)
@@ -229,6 +231,8 @@
 #define CSR_USTATUS			0x000
 #define CSR_UIE				0x004
 #define CSR_UTVEC			0x005
+#define CSR_LPLR			0x006
+#define CSR_SSP				0x020
 
 /* User Trap Handling (N-extension) */
 #define CSR_USCRATCH			0x040
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 95b40e7..d25227d 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -36,6 +36,8 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_SMSTATEEN,
 	/** HART has Sstc extension */
 	SBI_HART_EXT_SSTC,
+	/** HART has sslpcfi extension */
+	SBI_HART_EXT_SSLPCFI,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
-- 
2.25.1



From debug at rivosinc.com  Sun Dec 11 19:08:04 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Sun, 11 Dec 2022 19:08:04 -0800
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi state reflect back in status
In-Reply-To: <20221212030804.927309-1-debug@rivosinc.com>
References: <20221212030804.927309-1-debug@rivosinc.com>
Message-ID: <20221212030804.927309-3-debug@rivosinc.com>

This patch adds support for zsslpcfi detection in sbi_hart.c
If zsslpcfi is detected, this turns on menvcfg.CFI

zsslpcfi records status of cfi state in xstatus csr. Missing landing pad
sets MPELP in mstatus. When SBI is redirecting back to S/VS/HS, SPELP is
set in sstatus/vsstatus.

Signed-off-by: Deepak Gupta <debug at rivosinc.com>
---
 include/sbi/riscv_encoding.h |  2 ++
 lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
 lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
 3 files changed, 41 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 1fb520f..d7886e7 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -32,6 +32,8 @@
 #define MSTATUS_TVM			_UL(0x00100000)
 #define MSTATUS_TW			_UL(0x00200000)
 #define MSTATUS_TSR			_UL(0x00400000)
+#define MSTATUS_SPELP     		_UL(0x10000000)
+#define MSTATUS_MPELP     		_UL(0x20000000)
 #define MSTATUS32_SD			_UL(0x80000000)
 #if __riscv_xlen == 64
 #define MSTATUS_UXL			_ULL(0x0000000300000000)
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5447c52..6beae2d 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -157,6 +157,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
 		}
 
+		if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSLPCFI)) {
+#if __riscv_xlen == 32
+			unsigned long menvcfgh_val;
+			menvcfgh_val = csr_read(CSR_MENVCFGH);
+			menvcfgh_val |= ENVCFGH_CFI;
+			csr_write(CSR_MENVCFGH, menvcfgh_val);
+#else
+			menvcfg_val |= ENVCFG_CFI;
+#endif
+		}
 		csr_write(CSR_MENVCFG, menvcfg_val);
 	}
 
@@ -555,6 +565,7 @@ static int hart_detect_features(struct sbi_scratch *scratch)
 		sbi_scratch_offset_ptr(scratch, hart_features_offset);
 	unsigned long val, oldval;
 	int rc;
+	int ssp_exist, lplr_exist;
 
 	/* If hart features already detected then do nothing */
 	if (hfeatures->detected)
@@ -693,6 +704,16 @@ __mhpm_skip:
 					SBI_HART_EXT_SMSTATEEN, true);
 	}
 
+	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
+		val = csr_read_allowed(CSR_SSP, (unsigned long)&trap);
+		ssp_exist = trap.cause?0:1;
+		val = csr_read_allowed(CSR_LPLR, (unsigned long)&trap);
+		lplr_exist = trap.cause?0:1;
+		if (lplr_exist & ssp_exist)
+			__sbi_hart_update_extension(hfeatures,
+					SBI_HART_EXT_SSLPCFI, true);
+	}
+
 	/* Let platform populate extensions */
 	rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
 					  hfeatures);
diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
index c875c90..a700041 100644
--- a/lib/sbi/sbi_trap.c
+++ b/lib/sbi/sbi_trap.c
@@ -87,6 +87,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		      struct sbi_trap_info *trap)
 {
 	ulong hstatus, vsstatus, prev_mode;
+	bool elp = FALSE;
 #if __riscv_xlen == 32
 	bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
 #else
@@ -100,6 +101,13 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 	if (prev_mode != PRV_S && prev_mode != PRV_U)
 		return SBI_ENOTSUPP;
 
+	/* If extension has support for CFI, clear MPELP because redirecting to VS or (H)S */
+	if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSLPCFI)) {
+		elp = (regs->mstatus & MSTATUS_MPELP)? TRUE: FALSE;
+		/* Since redirecting, clear mpelp unconditionally */
+		regs->mstatus &= ~MSTATUS_MPELP;
+	}
+
 	/* If exceptions came from VS/VU-mode, redirect to VS-mode if
 	 * delegated in hedeleg
 	 */
@@ -153,6 +161,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		/* Get VS-mode SSTATUS CSR */
 		vsstatus = csr_read(CSR_VSSTATUS);
 
+		/*if elp was set, set it back in vsstatus */
+		if (elp) {
+			vsstatus |= MSTATUS_SPELP;
+		}
+
 		/* Set SPP for VS-mode */
 		vsstatus &= ~SSTATUS_SPP;
 		if (prev_mode == PRV_S)
@@ -193,6 +206,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 
 		/* Clear SIE for S-mode */
 		regs->mstatus &= ~MSTATUS_SIE;
+
+		/* if elp was set, set it back in mstatus */
+		if (elp) {
+			regs->mstatus |= MSTATUS_SPELP;
+		}
 	}
 
 	return 0;
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:19:57 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:19:57 +0800
Subject: [PATCH v3 1/3] lib: sbi: Allow platform to influence cold boot HART selection
Message-ID: <20221212051959.169231-1-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..566eee3 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return TRUE if HART is allowed to do cold boot and FALSE otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return TRUE;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d4902d9 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = TRUE;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:19:58 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:19:58 +0800
Subject: [PATCH v3 1/3] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
Message-ID: <20221212051959.169231-2-weiliang.lim@starfivetech.com>

>From 1f466b9e2945b57adc18d075b45b9ecdb304a38a Mon Sep 17 00:00:00 2001
From: Anup Patel <apatel at ventanamicro.com>
Date: Fri, 2 Dec 2022 14:23:22 +0530
Subject: [PATCH v3 2/3] platform: generic: Allow platform_override to select
 cold boot HART

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..80961f0 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat && generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return TRUE;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:19:59 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:19:59 +0800
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
Message-ID: <20221212051959.169231-3-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 ++++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 ++++++
 4 files changed, 38 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 4b5d2cd..a6e467d 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 2eaeeb7..ef6aad9 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..1c76975
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static bool starfive_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	return (hartid == 1);
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.cold_boot_allowed = starfive_cold_boot_allowed,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From debug at rivosinc.com  Sun Dec 11 21:33:38 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Sun, 11 Dec 2022 21:33:38 -0800
Subject: [PATCH Zisslpcfi 0/2] Support for zisslpcfi in opensbi
In-Reply-To: <20221212030804.927309-1-debug@rivosinc.com>
References: <20221212030804.927309-1-debug@rivosinc.com>
Message-ID: <20221212053338.GA937267@debug.ba.rivosinc.com>

I forgot to include URLs to qemu and linux implementation of Zisslpcfi

This is where I am maintaining qemu implementation
https://github.com/deepak0414/qemu/tree/gh_Zisslpcfi-0.1

And kernel implementation here
https://github.com/deepak0414/linux-riscv-cfi/tree/Zisslpcfi-0.1_v6.1-rc2

On Sun, Dec 11, 2022 at 07:08:02PM -0800, Deepak Gupta wrote:
>Zisslpcfi [1] extension extends risc-v architecture to mitigate against
>control-flow integrity attacks (ROP/JOP/COP).
>
>Zisslpcfi uses bits (b23-b29) in (m/s/vs) status CSR for enabling cfi in
>lesser privileged mode and record cfi state. One such state is expected
>landing pad (ELP). If forward cfi is enabled, indirect call/jmp updates
>hart's ELP state (1bit) to true. ELP state is cleared only by a landing
>pad instruction else trap is delivered with ELP state recorded in sstatus
>CSR.
>
>This two patch series adds following changes to opensbi
>    - Adds support in opensbi to detect zisslpcfi
>    - trap redirection updates ELP state accordingly
>
>[1] - https://github.com/riscv/riscv-cfi
>
>Deepak Gupta (2):
>  include: adding support for zsslpcfi encodings
>  lib: sbi: zsslpcfi detection and elp cfi state reflect back in status
>
> include/sbi/riscv_encoding.h |  6 ++++++
> include/sbi/sbi_hart.h       |  2 ++
> lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
> lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
> 4 files changed, 47 insertions(+)
>
>-- 
>2.25.1
>


From jrtc27 at jrtc27.com  Sun Dec 11 21:39:41 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Mon, 12 Dec 2022 05:39:41 +0000
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <20221212051959.169231-3-weiliang.lim@starfivetech.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
 <20221212051959.169231-3-weiliang.lim@starfivetech.com>
Message-ID: <373F2524-3650-4058-AF29-F8CEA7613CF6@jrtc27.com>

On 12 Dec 2022, at 05:19, Wei Liang Lim <weiliang.lim at starfivetech.com> wrote:
> 
> Add Starfive JH7110 platform implementation
> 
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
> platform/generic/Kconfig             |  4 ++++
> platform/generic/configs/defconfig   |  1 +
> platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
> platform/generic/starfive/objects.mk |  6 ++++++
> 4 files changed, 38 insertions(+)
> create mode 100644 platform/generic/starfive/jh7110.c
> create mode 100644 platform/generic/starfive/objects.mk
> 
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 4b5d2cd..a6e467d 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
> 	depends on FDT_RESET && FDT_I2C
> 	default n
> 
> +config PLATFORM_STARFIVE_JH7110
> +	bool "StarFive JH7110 support"
> +	default n
> +
> endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 2eaeeb7..ef6aad9 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
> CONFIG_PLATFORM_ANDES_AE350=y
> CONFIG_PLATFORM_SIFIVE_FU540=y
> CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_STARFIVE_JH7110=y
> CONFIG_FDT_GPIO=y
> CONFIG_FDT_GPIO_SIFIVE=y
> CONFIG_FDT_I2C=y
> diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
> new file mode 100644
> index 0000000..1c76975
> --- /dev/null
> +++ b/platform/generic/starfive/jh7110.c
> @@ -0,0 +1,27 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 StarFive
> + *
> + * Authors:
> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> + */
> +
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static bool starfive_cold_boot_allowed(u32 hartid,
> +				   const struct fdt_match *match)
> +{
> +	return (hartid == 1);

Why? I thought in an earlier thread it was said this was just a
debugging thing and you should fix whatever bug this masks another way.

This at least needs a justification in the source code.

Jess

> +}
> +
> +static const struct fdt_match starfive_jh7110_match[] = {
> +	{ .compatible = "starfive,jh7110" },
> +	{ },
> +};
> +
> +const struct platform_override starfive_jh7110 = {
> +	.match_table = starfive_jh7110_match,
> +	.cold_boot_allowed = starfive_cold_boot_allowed,
> +};
> diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
> new file mode 100644
> index 0000000..0b900fb
> --- /dev/null
> +++ b/platform/generic/starfive/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
> -- 
> 2.25.1
> 
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



From weiliang.lim at starfivetech.com  Sun Dec 11 21:40:15 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:40:15 +0800
Subject: [PATCH v3 0/3] generic/starfive: Enable Starfive JH7110 platform preferred boot hart implementation
Message-ID: <20221212054018.169408-1-weiliang.lim@starfivetech.com>

This is patchset to enable Starfive JH7110 platform preferred boot hart implementation.

Anup Patel (2):
  lib: sbi: Allow platform to influence cold boot HART selection
  platform: generic: Allow platform_override to select cold boot HART

Wei Liang Lim (1):
  generic/starfive: Add Starfive JH7110 platform implementation

 include/sbi/sbi_platform.h                   | 20 +++++++++++++++
 lib/sbi/sbi_init.c                           |  7 +++--
 platform/generic/Kconfig                     |  4 +++
 platform/generic/configs/defconfig           |  1 +
 platform/generic/include/platform_override.h |  1 +
 platform/generic/platform.c                  |  9 +++++++
 platform/generic/starfive/jh7110.c           | 27 ++++++++++++++++++++
 platform/generic/starfive/objects.mk         |  6 +++++
 8 files changed, 73 insertions(+), 2 deletions(-)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:40:16 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:40:16 +0800
Subject: [PATCH v3 1/3] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
Message-ID: <20221212054018.169408-2-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..566eee3 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return TRUE if HART is allowed to do cold boot and FALSE otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return TRUE;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d4902d9 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = TRUE;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:40:17 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:40:17 +0800
Subject: [PATCH v3 2/3] platform: generic: Allow platform_override to select cold boot HART
In-Reply-To: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
Message-ID: <20221212054018.169408-3-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..80961f0 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat && generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return TRUE;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 21:40:18 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Mon, 12 Dec 2022 13:40:18 +0800
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
Message-ID: <20221212054018.169408-4-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 ++++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 ++++++
 4 files changed, 38 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 4b5d2cd..a6e467d 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 2eaeeb7..ef6aad9 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
 CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..1c76975
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static bool starfive_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	return (hartid == 1);
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.cold_boot_allowed = starfive_cold_boot_allowed,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From weiliang.lim at starfivetech.com  Sun Dec 11 22:04:06 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Mon, 12 Dec 2022 06:04:06 +0000
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <373F2524-3650-4058-AF29-F8CEA7613CF6@jrtc27.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
 <20221212051959.169231-3-weiliang.lim@starfivetech.com>
 <373F2524-3650-4058-AF29-F8CEA7613CF6@jrtc27.com>
Message-ID: <26169619ad974ed5a57b60f4b31a4a53@EXMBX163.cuchost.com>



> -----Original Message-----
> From: Jessica Clarke <jrtc27 at jrtc27.com>
> Sent: Monday, December 12, 2022 1:40 PM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi <opensbi at lists.infradead.org>; Anup Patel
> <apatel at ventanamicro.com>; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
> implementation
> 
> On 12 Dec 2022, at 05:19, Wei Liang Lim <weiliang.lim at starfivetech.com>
> wrote:
> >
> > Add Starfive JH7110 platform implementation
> >
> > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > ---
> > platform/generic/Kconfig             |  4 ++++
> > platform/generic/configs/defconfig   |  1 +
> > platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
> > platform/generic/starfive/objects.mk |  6 ++++++
> > 4 files changed, 38 insertions(+)
> > create mode 100644 platform/generic/starfive/jh7110.c
> > create mode 100644 platform/generic/starfive/objects.mk
> >
> > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index
> > 4b5d2cd..a6e467d 100644
> > --- a/platform/generic/Kconfig
> > +++ b/platform/generic/Kconfig
> > @@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
> > 	depends on FDT_RESET && FDT_I2C
> > 	default n
> >
> > +config PLATFORM_STARFIVE_JH7110
> > +	bool "StarFive JH7110 support"
> > +	default n
> > +
> > endif
> > diff --git a/platform/generic/configs/defconfig
> > b/platform/generic/configs/defconfig
> > index 2eaeeb7..ef6aad9 100644
> > --- a/platform/generic/configs/defconfig
> > +++ b/platform/generic/configs/defconfig
> > @@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
> > CONFIG_PLATFORM_ANDES_AE350=y CONFIG_PLATFORM_SIFIVE_FU540=y
> > CONFIG_PLATFORM_SIFIVE_FU740=y
> > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> > CONFIG_FDT_GPIO=y
> > CONFIG_FDT_GPIO_SIFIVE=y
> > CONFIG_FDT_I2C=y
> > diff --git a/platform/generic/starfive/jh7110.c
> > b/platform/generic/starfive/jh7110.c
> > new file mode 100644
> > index 0000000..1c76975
> > --- /dev/null
> > +++ b/platform/generic/starfive/jh7110.c
> > @@ -0,0 +1,27 @@
> > +/*
> > + * SPDX-License-Identifier: BSD-2-Clause
> > + *
> > + * Copyright (c) 2022 StarFive
> > + *
> > + * Authors:
> > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > + */
> > +
> > +#include <platform_override.h>
> > +#include <sbi_utils/fdt/fdt_helper.h>
> > +
> > +static bool starfive_cold_boot_allowed(u32 hartid,
> > +				   const struct fdt_match *match) {
> > +	return (hartid == 1);
> 
> Why? I thought in an earlier thread it was said this was just a debugging thing
> and you should fix whatever bug this masks another way.
> 
> This at least needs a justification in the source code.
> 
> Jess

Hi Jess,

Sorry I did something wrong previously causing some patch being missed out.
Please refer to my latest submission.
In earlier conversation, Anup helped to review and suggested patches to allow platform to influence cold boot HART selection and allow platform_override to select cold boot HART. Together with Anup's patches I have included StarFive platform specific implementation.

Thanks

> 
> > +}
> > +
> > +static const struct fdt_match starfive_jh7110_match[] = {
> > +	{ .compatible = "starfive,jh7110" },
> > +	{ },
> > +};
> > +
> > +const struct platform_override starfive_jh7110 = {
> > +	.match_table = starfive_jh7110_match,
> > +	.cold_boot_allowed = starfive_cold_boot_allowed, };
> > diff --git a/platform/generic/starfive/objects.mk
> > b/platform/generic/starfive/objects.mk
> > new file mode 100644
> > index 0000000..0b900fb
> > --- /dev/null
> > +++ b/platform/generic/starfive/objects.mk
> > @@ -0,0 +1,6 @@
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause #
> > +
> > +carray-platform_override_modules-
> $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > ++= starfive_jh7110
> > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> starfive/jh7110.o
> > --
> > 2.25.1
> >
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi



From jrtc27 at jrtc27.com  Sun Dec 11 22:05:26 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Mon, 12 Dec 2022 06:05:26 +0000
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <26169619ad974ed5a57b60f4b31a4a53@EXMBX163.cuchost.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
 <20221212051959.169231-3-weiliang.lim@starfivetech.com>
 <373F2524-3650-4058-AF29-F8CEA7613CF6@jrtc27.com>
 <26169619ad974ed5a57b60f4b31a4a53@EXMBX163.cuchost.com>
Message-ID: <B86CE53A-BFD4-4FF7-A597-BF482E492365@jrtc27.com>

On 12 Dec 2022, at 06:04, WeiLiang Lim <weiliang.lim at starfivetech.com> wrote:
> 
> 
> 
>> -----Original Message-----
>> From: Jessica Clarke <jrtc27 at jrtc27.com>
>> Sent: Monday, December 12, 2022 1:40 PM
>> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
>> Cc: opensbi <opensbi at lists.infradead.org>; Anup Patel
>> <apatel at ventanamicro.com>; Cheehong Ang
>> <cheehong.ang at starfivetech.com>; JunLiang Tan
>> <junliang.tan at starfivetech.com>
>> Subject: Re: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
>> implementation
>> 
>> On 12 Dec 2022, at 05:19, Wei Liang Lim <weiliang.lim at starfivetech.com>
>> wrote:
>>> 
>>> Add Starfive JH7110 platform implementation
>>> 
>>> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
>>> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
>>> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
>>> ---
>>> platform/generic/Kconfig             |  4 ++++
>>> platform/generic/configs/defconfig   |  1 +
>>> platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
>>> platform/generic/starfive/objects.mk |  6 ++++++
>>> 4 files changed, 38 insertions(+)
>>> create mode 100644 platform/generic/starfive/jh7110.c
>>> create mode 100644 platform/generic/starfive/objects.mk
>>> 
>>> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index
>>> 4b5d2cd..a6e467d 100644
>>> --- a/platform/generic/Kconfig
>>> +++ b/platform/generic/Kconfig
>>> @@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
>>> 	depends on FDT_RESET && FDT_I2C
>>> 	default n
>>> 
>>> +config PLATFORM_STARFIVE_JH7110
>>> +	bool "StarFive JH7110 support"
>>> +	default n
>>> +
>>> endif
>>> diff --git a/platform/generic/configs/defconfig
>>> b/platform/generic/configs/defconfig
>>> index 2eaeeb7..ef6aad9 100644
>>> --- a/platform/generic/configs/defconfig
>>> +++ b/platform/generic/configs/defconfig
>>> @@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
>>> CONFIG_PLATFORM_ANDES_AE350=y CONFIG_PLATFORM_SIFIVE_FU540=y
>>> CONFIG_PLATFORM_SIFIVE_FU740=y
>>> +CONFIG_PLATFORM_STARFIVE_JH7110=y
>>> CONFIG_FDT_GPIO=y
>>> CONFIG_FDT_GPIO_SIFIVE=y
>>> CONFIG_FDT_I2C=y
>>> diff --git a/platform/generic/starfive/jh7110.c
>>> b/platform/generic/starfive/jh7110.c
>>> new file mode 100644
>>> index 0000000..1c76975
>>> --- /dev/null
>>> +++ b/platform/generic/starfive/jh7110.c
>>> @@ -0,0 +1,27 @@
>>> +/*
>>> + * SPDX-License-Identifier: BSD-2-Clause
>>> + *
>>> + * Copyright (c) 2022 StarFive
>>> + *
>>> + * Authors:
>>> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
>>> + */
>>> +
>>> +#include <platform_override.h>
>>> +#include <sbi_utils/fdt/fdt_helper.h>
>>> +
>>> +static bool starfive_cold_boot_allowed(u32 hartid,
>>> +				   const struct fdt_match *match) {
>>> +	return (hartid == 1);
>> 
>> Why? I thought in an earlier thread it was said this was just a debugging thing
>> and you should fix whatever bug this masks another way.
>> 
>> This at least needs a justification in the source code.
>> 
>> Jess
> 
> Hi Jess,
> 
> Sorry I did something wrong previously causing some patch being missed out.
> Please refer to my latest submission.
> In earlier conversation, Anup helped to review and suggested patches to allow platform to influence cold boot HART selection and allow platform_override to select cold boot HART. Together with Anup's patches I have included StarFive platform specific implementation.

But why does the JH110 need this?

Jess

>> 
>>> +}
>>> +
>>> +static const struct fdt_match starfive_jh7110_match[] = {
>>> +	{ .compatible = "starfive,jh7110" },
>>> +	{ },
>>> +};
>>> +
>>> +const struct platform_override starfive_jh7110 = {
>>> +	.match_table = starfive_jh7110_match,
>>> +	.cold_boot_allowed = starfive_cold_boot_allowed, };
>>> diff --git a/platform/generic/starfive/objects.mk
>>> b/platform/generic/starfive/objects.mk
>>> new file mode 100644
>>> index 0000000..0b900fb
>>> --- /dev/null
>>> +++ b/platform/generic/starfive/objects.mk
>>> @@ -0,0 +1,6 @@
>>> +#
>>> +# SPDX-License-Identifier: BSD-2-Clause #
>>> +
>>> +carray-platform_override_modules-
>> $(CONFIG_PLATFORM_STARFIVE_JH7110)
>>> ++= starfive_jh7110
>>> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
>> starfive/jh7110.o
>>> --
>>> 2.25.1
>>> 
>>> 
>>> --
>>> opensbi mailing list
>>> opensbi at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/opensbi



From samuel at sholland.org  Sun Dec 11 22:40:20 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 00:40:20 -0600
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in priority save/restore helpers
In-Reply-To: <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <87a63ufe4a.fsf@linux-m68k.org>
 <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
Message-ID: <65db953b-fc55-7323-7c8b-754c9b8f6d85@sholland.org>

On 12/11/22 04:18, Bin Meng wrote:
> On Sun, Dec 11, 2022 at 6:08 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>>
>> On Dez 11 2022, Bin Meng wrote:
>>
>>> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
>>> index 73d7788..4df9020 100644
>>> --- a/lib/utils/irqchip/plic.c
>>> +++ b/lib/utils/irqchip/plic.c
>>> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>>>
>>>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>>>  {
>>> -     for (u32 i = 0; i < plic->num_src; i++)
>>> +     for (u32 i = 1; i <= plic->num_src; i++)
>>>               priority[i] = plic_get_priority(plic, i);
>>
>> That needs to adjust the index into the priority array.
> 
> Does that help anything? It just confuses people more.
> 
> I added function parameter descriptions in patch 2 to make it crystal
> clear, that the priority array needs to include interrupt source 0.

To me, it is more confusing that when I ask to save the priority for N
sources, I need to allocate an array with >N elements. And leaving array
element 0 unused wastes memory.

Regards,
Samuel



From samuel at sholland.org  Sun Dec 11 22:45:24 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 00:45:24 -0600
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <87tu22qgvq.fsf@igel.home>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <20221211065424.806478-2-bmeng@tinylab.org> <87tu22qgvq.fsf@igel.home>
Message-ID: <ed95c5e0-b3cd-5c0e-6708-415edfc50bbd@sholland.org>

On 12/11/22 06:11, Andreas Schwab wrote:
> On Dez 11 2022, Bin Meng wrote:
> 
>> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
>> index 18d330d..1f27575 100644
>> --- a/platform/generic/allwinner/sun20i-d1.c
>> +++ b/platform/generic/allwinner/sun20i-d1.c
>> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>>  static void sun20i_d1_plic_save(void)
>>  {
>>  	fdt_plic_context_save(true, plic_sie, &plic_threshold);
>> -	fdt_plic_priority_save(plic_priority);
>> +	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>>  }
>>  
>>  static void sun20i_d1_plic_restore(void)
>>  {
>>  	thead_plic_restore();
>> -	fdt_plic_priority_restore(plic_priority);
>> +	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>>  	fdt_plic_context_restore(true, plic_sie, plic_threshold);
>>  }
> 
> That fails to update the size of the plic_priority array.

PLIC_SOURCES is 176, and I later corrected riscv,ndev in the DT to 175,
so technically this does not create a bug.

Regards,
Samuel



From samuel at sholland.org  Sun Dec 11 22:49:32 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 00:49:32 -0600
Subject: [PATCH v3 3/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in plic_context_init()
In-Reply-To: <20221211065424.806478-3-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <20221211065424.806478-3-bmeng@tinylab.org>
Message-ID: <0ff639d3-9229-7656-ed6b-80b025bfe25f@sholland.org>

On 12/11/22 00:54, Bin Meng wrote:
> The number of interrupt enable register in words was once correct,
> but was wrongly changed to have an off-by-one error since
> commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").

Indeed, as far as I can tell from my recent reading, I misinterpreted
the binding. I don't like that it excludes the reserved source 0, but I
don't get to make that decision.

> Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Reviewed-by: Samuel Holland <samuel at sholland.org>

> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
> 
>  lib/utils/irqchip/plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index dca5678..568f814 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -127,7 +127,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
>  	if (!plic || context_id < 0)
>  		return SBI_EINVAL;
>  
> -	ie_words = (plic->num_src + 31) / 32;
> +	ie_words = plic->num_src / 32 + 1;
>  	ie_value = enable ? 0xffffffffU : 0U;
>  
>  	for (u32 i = 0; i < ie_words; i++)



From samuel at sholland.org  Sun Dec 11 22:57:34 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 00:57:34 -0600
Subject: [PATCH v3 4/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in context save/restore helpers
In-Reply-To: <20221211065424.806478-4-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <20221211065424.806478-4-bmeng@tinylab.org>
Message-ID: <bf5bb572-085e-6591-bfa1-641cbdd44bda@sholland.org>

On 12/11/22 00:54, Bin Meng wrote:
> plic->num_src holds the number of interrupt sources without interrupt
> source 0 but the interrupt enable register includes a bit for the
> interrupt source 0 in the first word.

On the other hand, it is not really feasible to exclude the first bit
here, so maybe it makes sense to leave patch 1 as it is for consistency.

> Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Anup Patel <anup at brainfault.org>
> 
> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
> 
>  lib/utils/irqchip/plic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Samuel Holland <samuel at sholland.org>



From samuel at sholland.org  Sun Dec 11 23:00:46 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 01:00:46 -0600
Subject: [PATCH v3 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in context save/restore helpers
In-Reply-To: <20221211065424.806478-5-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <20221211065424.806478-5-bmeng@tinylab.org>
Message-ID: <17261da5-b988-f1f2-2a39-34cd4c0321ae@sholland.org>

On 12/11/22 00:54, Bin Meng wrote:
> Currently the context save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
> 
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> 
> ---
> 
> Changes in v3:
> - move the size limit check to plic_context_save/restore
> 
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
> 
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
>  include/sbi_utils/irqchip/plic.h             |  4 ++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  9 +++++----
>  lib/utils/irqchip/plic.c                     | 14 ++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  5 +++--
>  5 files changed, 23 insertions(+), 14 deletions(-)
> 
[...]
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 1f27575..1da9e5b 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -78,7 +78,7 @@ static u32 plic_threshold;
>  
>  static void sun20i_d1_plic_save(void)
>  {
> -	fdt_plic_context_save(true, plic_sie, &plic_threshold);
> +	fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);

While the actual value ends up being the same, you should update the
definition of PLIC_IE_WORDS to use the same formula used elsewhere.

Regards,
Samuel

>  	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>  
> @@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
>  {
>  	thead_plic_restore();
>  	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> -	fdt_plic_context_restore(true, plic_sie, plic_threshold);
> +	fdt_plic_context_restore(true, plic_sie, plic_threshold,
> +				 PLIC_IE_WORDS);
>  }
>  
>  /*



From weiliang.lim at starfivetech.com  Sun Dec 11 23:03:32 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Mon, 12 Dec 2022 07:03:32 +0000
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <B86CE53A-BFD4-4FF7-A597-BF482E492365@jrtc27.com>
References: <20221212051959.169231-1-weiliang.lim@starfivetech.com>
 <20221212051959.169231-3-weiliang.lim@starfivetech.com>
 <373F2524-3650-4058-AF29-F8CEA7613CF6@jrtc27.com>
 <26169619ad974ed5a57b60f4b31a4a53@EXMBX163.cuchost.com>
 <B86CE53A-BFD4-4FF7-A597-BF482E492365@jrtc27.com>
Message-ID: <02f8d505695a42178e8419ec28c5f8ca@EXMBX163.cuchost.com>



> -----Original Message-----
> From: Jessica Clarke <jrtc27 at jrtc27.com>
> Sent: Monday, December 12, 2022 2:05 PM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi <opensbi at lists.infradead.org>; Anup Patel
> <apatel at ventanamicro.com>; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform
> implementation
> 
> On 12 Dec 2022, at 06:04, WeiLiang Lim <weiliang.lim at starfivetech.com>
> wrote:
> >
> >
> >
> >> -----Original Message-----
> >> From: Jessica Clarke <jrtc27 at jrtc27.com>
> >> Sent: Monday, December 12, 2022 1:40 PM
> >> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> >> Cc: opensbi <opensbi at lists.infradead.org>; Anup Patel
> >> <apatel at ventanamicro.com>; Cheehong Ang
> >> <cheehong.ang at starfivetech.com>; JunLiang Tan
> >> <junliang.tan at starfivetech.com>
> >> Subject: Re: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110
> >> platform implementation
> >>
> >> On 12 Dec 2022, at 05:19, Wei Liang Lim
> >> <weiliang.lim at starfivetech.com>
> >> wrote:
> >>>
> >>> Add Starfive JH7110 platform implementation
> >>>
> >>> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> >>> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> >>> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> >>> ---
> >>> platform/generic/Kconfig             |  4 ++++
> >>> platform/generic/configs/defconfig   |  1 +
> >>> platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
> >>> platform/generic/starfive/objects.mk |  6 ++++++
> >>> 4 files changed, 38 insertions(+)
> >>> create mode 100644 platform/generic/starfive/jh7110.c
> >>> create mode 100644 platform/generic/starfive/objects.mk
> >>>
> >>> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> >>> index 4b5d2cd..a6e467d 100644
> >>> --- a/platform/generic/Kconfig
> >>> +++ b/platform/generic/Kconfig
> >>> @@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
> >>> 	depends on FDT_RESET && FDT_I2C
> >>> 	default n
> >>>
> >>> +config PLATFORM_STARFIVE_JH7110
> >>> +	bool "StarFive JH7110 support"
> >>> +	default n
> >>> +
> >>> endif
> >>> diff --git a/platform/generic/configs/defconfig
> >>> b/platform/generic/configs/defconfig
> >>> index 2eaeeb7..ef6aad9 100644
> >>> --- a/platform/generic/configs/defconfig
> >>> +++ b/platform/generic/configs/defconfig
> >>> @@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
> >>> CONFIG_PLATFORM_ANDES_AE350=y
> CONFIG_PLATFORM_SIFIVE_FU540=y
> >>> CONFIG_PLATFORM_SIFIVE_FU740=y
> >>> +CONFIG_PLATFORM_STARFIVE_JH7110=y
> >>> CONFIG_FDT_GPIO=y
> >>> CONFIG_FDT_GPIO_SIFIVE=y
> >>> CONFIG_FDT_I2C=y
> >>> diff --git a/platform/generic/starfive/jh7110.c
> >>> b/platform/generic/starfive/jh7110.c
> >>> new file mode 100644
> >>> index 0000000..1c76975
> >>> --- /dev/null
> >>> +++ b/platform/generic/starfive/jh7110.c
> >>> @@ -0,0 +1,27 @@
> >>> +/*
> >>> + * SPDX-License-Identifier: BSD-2-Clause
> >>> + *
> >>> + * Copyright (c) 2022 StarFive
> >>> + *
> >>> + * Authors:
> >>> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> >>> + */
> >>> +
> >>> +#include <platform_override.h>
> >>> +#include <sbi_utils/fdt/fdt_helper.h>
> >>> +
> >>> +static bool starfive_cold_boot_allowed(u32 hartid,
> >>> +				   const struct fdt_match *match) {
> >>> +	return (hartid == 1);
> >>
> >> Why? I thought in an earlier thread it was said this was just a
> >> debugging thing and you should fix whatever bug this masks another way.
> >>
> >> This at least needs a justification in the source code.
> >>
> >> Jess
> >
> > Hi Jess,
> >
> > Sorry I did something wrong previously causing some patch being missed out.
> > Please refer to my latest submission.
> > In earlier conversation, Anup helped to review and suggested patches to
> allow platform to influence cold boot HART selection and allow
> platform_override to select cold boot HART. Together with Anup's patches I
> have included StarFive platform specific implementation.
> 
> But why does the JH110 need this?
> 
> Jess
> 

Hi Jess,

This is mainly to support our customer request which they need a preferred boot hart in their product application.
For better flexibility, we are planning for a v4 version where user can have the option to specify the preferred boot hart in dts chosen node. If unspecified, it will just use the current default lottery mechanism.

Thanks


> >>
> >>> +}
> >>> +
> >>> +static const struct fdt_match starfive_jh7110_match[] = {
> >>> +	{ .compatible = "starfive,jh7110" },
> >>> +	{ },
> >>> +};
> >>> +
> >>> +const struct platform_override starfive_jh7110 = {
> >>> +	.match_table = starfive_jh7110_match,
> >>> +	.cold_boot_allowed = starfive_cold_boot_allowed, };
> >>> diff --git a/platform/generic/starfive/objects.mk
> >>> b/platform/generic/starfive/objects.mk
> >>> new file mode 100644
> >>> index 0000000..0b900fb
> >>> --- /dev/null
> >>> +++ b/platform/generic/starfive/objects.mk
> >>> @@ -0,0 +1,6 @@
> >>> +#
> >>> +# SPDX-License-Identifier: BSD-2-Clause #
> >>> +
> >>> +carray-platform_override_modules-
> >> $(CONFIG_PLATFORM_STARFIVE_JH7110)
> >>> ++= starfive_jh7110
> >>> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> >> starfive/jh7110.o
> >>> --
> >>> 2.25.1
> >>>
> >>>
> >>> --
> >>> opensbi mailing list
> >>> opensbi at lists.infradead.org
> >>> http://lists.infradead.org/mailman/listinfo/opensbi



From samuel at sholland.org  Sun Dec 11 23:04:33 2022
From: samuel at sholland.org (Samuel Holland)
Date: Mon, 12 Dec 2022 01:04:33 -0600
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <20221211065424.806478-2-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
 <20221211065424.806478-2-bmeng@tinylab.org>
Message-ID: <a515eb8a-4f5e-68ff-327f-082d948362f3@sholland.org>

On 12/11/22 00:54, Bin Meng wrote:
> Currently the priority save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
> 
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> 
> ---
> 
> Changes in v3:
> - fix the size limit check
> - move the size limit check to plic_priority_save/restore
> - add parameter description to fdt_plic_priority_save/restore
> 
> Changes in v2:
> - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
> 
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h | 14 ++++++++++++--
>  include/sbi_utils/irqchip/plic.h             |  5 +++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  8 ++++----
>  lib/utils/irqchip/plic.c                     | 15 +++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
>  5 files changed, 32 insertions(+), 14 deletions(-)
> 
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 98d4de5..d5b1c60 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -9,9 +9,19 @@
>  
>  #include <sbi/sbi_types.h>
>  
> -void fdt_plic_priority_save(u8 *priority);
> +/**
> + * Save the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_save(u8 *priority, u32 num);
>  
> -void fdt_plic_priority_restore(const u8 *priority);
> +/**
> + * Restore the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_restore(const u8 *priority, u32 num);
>  
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
>  
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 48c24f0..38704a1 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -18,9 +18,10 @@ struct plic_data {
>  };
>  
>  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
>  
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +			   u32 num);
>  
>  void plic_context_save(const struct plic_data *plic, int context_id,
>  		       u32 *enable, u32 *threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index fe08836..7d76c5b 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -24,18 +24,18 @@ static struct plic_data plic[PLIC_MAX_NR];
>  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
>  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
>  
> -void fdt_plic_priority_save(u8 *priority)
> +void fdt_plic_priority_save(u8 *priority, u32 num)
>  {
>  	struct plic_data *plic = plic_hartid2data[current_hartid()];
>  
> -	plic_priority_save(plic, priority);
> +	plic_priority_save(plic, priority, num);
>  }
>  
> -void fdt_plic_priority_restore(const u8 *priority)
> +void fdt_plic_priority_restore(const u8 *priority, u32 num)
>  {
>  	struct plic_data *plic = plic_hartid2data[current_hartid()];
>  
> -	plic_priority_restore(plic, priority);
> +	plic_priority_restore(plic, priority, num);
>  }
>  
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 4df9020..dca5678 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -36,15 +36,22 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>  	writel(val, plic_priority);
>  }
>  
> -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>  {
> -	for (u32 i = 1; i <= plic->num_src; i++)
> +	if (num > plic->num_src)
> +		num = plic->num_src;

This check is not really necessary. If the caller tries to save/restore
more sources then actually exist, then the extra register writes will
just be ignored. We already access extra bits by doing word accesses.

For bounds checking, the only things that need to match are the array
size and the loop. With your change to the loop condition, plic->num_src
is not relevant at all anymore.

Regards,
Samuel

> +
> +	for (u32 i = 1; i <= num; i++)
>  		priority[i] = plic_get_priority(plic, i);
>  }
>  
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +			   u32 num)
>  {
> -	for (u32 i = 1; i <= plic->num_src; i++)
> +	if (num > plic->num_src)
> +		num = plic->num_src;
> +
> +	for (u32 i = 1; i <= num; i++)
>  		plic_set_priority(plic, i, priority[i]);
>  }
>  
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 18d330d..1f27575 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>  static void sun20i_d1_plic_save(void)
>  {
>  	fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -	fdt_plic_priority_save(plic_priority);
> +	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>  
>  static void sun20i_d1_plic_restore(void)
>  {
>  	thead_plic_restore();
> -	fdt_plic_priority_restore(plic_priority);
> +	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>  	fdt_plic_context_restore(true, plic_sie, plic_threshold);
>  }
>  



From uwu at icenowy.me  Mon Dec 12 00:22:35 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Mon, 12 Dec 2022 16:22:35 +0800
Subject: [PATCH v2 0/3] T-Head C9xx CLINT support
Message-ID: <20221212082238.265281-1-uwu@icenowy.me>

This patchset tries to add support for T-Head C9xx's CLINT to OpenSBI.

For MSWI part, the T-Head CLINT is fully compatible with the SiFive one,
so it's just simply adding a compatible string.

For MTIMER part, it's first needed to implement a quirk for
MTIME-less timer (thus only MTIMECMP is present), then the compatible
string is added and bound to the quirk.

To instantiate such a T-Head flavored CLINT via DT, this patchset
depends on DT bindings declared in [1].

[1] https://www.spinics.net/lists/kernel/msg4597447.html

Icenowy Zheng (3):
  lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
  lib: utils/timer: mtimer: add a quirk for lacking mtime register
  lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

 lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
 lib/utils/timer/aclint_mtimer.c    | 11 ++++++---
 lib/utils/timer/fdt_timer_mtimer.c | 36 +++++++++++++++++++++---------
 3 files changed, 35 insertions(+), 13 deletions(-)

-- 
2.38.1



From uwu at icenowy.me  Mon Dec 12 00:22:36 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Mon, 12 Dec 2022 16:22:36 +0800
Subject: [PATCH v2 1/3] lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
In-Reply-To: <20221212082238.265281-1-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me>
Message-ID: <20221212082238.265281-2-uwu@icenowy.me>

Althoug the MTIMER part of a C9xx CLINT differs from a SiFive one, the
MSWI part is compliant.

Add T-Head C9xx CLINT compatible string to fdt_ipi_mswi code, sharing
the same codepath with SiFive CLINT.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
Reviewed-by: Anup Patel <anup at brainfault.org>
---
Changes in v2:
- Added Anup's reviewed tag.

 lib/utils/ipi/fdt_ipi_mswi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/ipi/fdt_ipi_mswi.c b/lib/utils/ipi/fdt_ipi_mswi.c
index 0176941..4dc91f2 100644
--- a/lib/utils/ipi/fdt_ipi_mswi.c
+++ b/lib/utils/ipi/fdt_ipi_mswi.c
@@ -56,6 +56,7 @@ static const unsigned long clint_offset = CLINT_MSWI_OFFSET;
 static const struct fdt_match ipi_mswi_match[] = {
 	{ .compatible = "riscv,clint0", .data = &clint_offset },
 	{ .compatible = "sifive,clint0", .data = &clint_offset },
+	{ .compatible = "thead,c900-clint", .data = &clint_offset },
 	{ .compatible = "riscv,aclint-mswi" },
 	{ },
 };
-- 
2.38.1



From uwu at icenowy.me  Mon Dec 12 00:22:37 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Mon, 12 Dec 2022 16:22:37 +0800
Subject: [PATCH v2 2/3] lib: utils/timer: mtimer: add a quirk for lacking mtime register
In-Reply-To: <20221212082238.265281-1-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me>
Message-ID: <20221212082238.265281-3-uwu@icenowy.me>

T-Head developers surely have a different understanding of time CSR and
CLINT's mtime register with SiFive ones, that they did not implement
the mtime register at all -- as shown in openC906 source code, their
time CSR value is just exposed at the top of their processor IP block
and expects an external continous counter, which makes it not
overrideable, and thus mtime register is not implemented, even not for
reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
extended CSR, these systems still rely on the mtimecmp registers to
generate timer interrupts. This makes it necessary to implement T-Head
C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
reading mtime register and falls back to default code that reads time
CSR.

Add a quirk into MTIMER driver, which represents a mtime register is
lacking and time CSR value should be used instead.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
Changes in v2:
- Dropped has_mtime field in aclint_mtimer_data, use mtime_size = 0
  (which is disallowed before) to mark absence of mtime.
- Dropped the code that specially handle the existence of mtime when
  registering memory ranges -- the function will just be a no-op when
  size is 0.

 lib/utils/timer/aclint_mtimer.c    | 11 ++++++++---
 lib/utils/timer/fdt_timer_mtimer.c | 30 ++++++++++++++++++++----------
 2 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
index 3f00c21..1846a9a 100644
--- a/lib/utils/timer/aclint_mtimer.c
+++ b/lib/utils/timer/aclint_mtimer.c
@@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
 	int rc;
 
 	/* Sanity checks */
-	if (!mt || !mt->mtime_size ||
+	if (!mt ||
 	    (mt->hart_count && !mt->mtimecmp_size) ||
-	    (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
-	    (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
+	    (mt->mtime_size && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
+	    (mt->mtime_size && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
 	    (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
 	    (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
 	    (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
@@ -178,6 +178,11 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
 	for (i = 0; i < mt->hart_count; i++)
 		mtimer_hartid2data[mt->first_hartid + i] = mt;
 
+	if (!mt->mtime_size) {
+		/* Disable reading mtime when mtime is not available */
+		mtimer.timer_value = NULL;
+	}
+
 	/* Add MTIMER regions to the root domain */
 	if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
 		rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index 7b8546b..a0adc70 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -18,6 +18,7 @@
 struct timer_mtimer_quirks {
 	unsigned int	mtime_offset;
 	bool		has_64bit_mmio;
+	bool		without_mtime;
 };
 
 static unsigned long mtimer_count = 0;
@@ -53,12 +54,16 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 		/* Set CLINT addresses */
 		mt->mtimecmp_addr = addr[0] + ACLINT_DEFAULT_MTIMECMP_OFFSET;
 		mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
-		mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
-		mt->mtime_size = size[0] - mt->mtimecmp_size;
-		/* Adjust MTIMER address and size for CLINT device */
-		mt->mtime_addr += quirks->mtime_offset;
+		if (!quirks->without_mtime) {
+			mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
+			mt->mtime_size = size[0] - mt->mtimecmp_size;
+			/* Adjust MTIMER address and size for CLINT device */
+			mt->mtime_addr += quirks->mtime_offset;
+			mt->mtime_size -= quirks->mtime_offset;
+		} else {
+			mt->mtime_addr = mt->mtime_size = 0;
+		}
 		mt->mtimecmp_addr += quirks->mtime_offset;
-		mt->mtime_size -= quirks->mtime_offset;
 		/* Apply additional CLINT quirks */
 		mt->has_64bit_mmio = quirks->has_64bit_mmio;
 	} else { /* RISC-V ACLINT MTIMER */
@@ -70,12 +75,17 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
 	}
 
 	/* Check if MTIMER device has shared MTIME address */
-	mt->has_shared_mtime = false;
-	for (i = 0; i < mtimer_count; i++) {
-		if (mtimer[i].mtime_addr == mt->mtime_addr) {
-			mt->has_shared_mtime = true;
-			break;
+	if (mt->mtime_size) {
+		mt->has_shared_mtime = false;
+		for (i = 0; i < mtimer_count; i++) {
+			if (mtimer[i].mtime_addr == mt->mtime_addr) {
+				mt->has_shared_mtime = true;
+				break;
+			}
 		}
+	} else {
+		/* Assume shared time CSR */
+		mt->has_shared_mtime = true;
 	}
 
 	/* Initialize the MTIMER device */
-- 
2.38.1



From uwu at icenowy.me  Mon Dec 12 00:22:38 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Mon, 12 Dec 2022 16:22:38 +0800
Subject: [PATCH v2 3/3] lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible
In-Reply-To: <20221212082238.265281-1-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me>
Message-ID: <20221212082238.265281-4-uwu@icenowy.me>

As we already added the quirk for lacking mtime register to MTIMER
driver, add T-Head C9xx CLINT compatible to it and wire the quirk.

Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
---
No changes in v2.

 lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
index a0adc70..5244f98 100644
--- a/lib/utils/timer/fdt_timer_mtimer.c
+++ b/lib/utils/timer/fdt_timer_mtimer.c
@@ -124,9 +124,15 @@ static const struct timer_mtimer_quirks sifive_clint_quirks = {
 	.has_64bit_mmio	= true,
 };
 
+static const struct timer_mtimer_quirks thead_clint_quirks = {
+	.mtime_offset	= CLINT_MTIMER_OFFSET,
+	.without_mtime  = true,
+};
+
 static const struct fdt_match timer_mtimer_match[] = {
 	{ .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
 	{ .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
+	{ .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
 	{ .compatible = "riscv,aclint-mtimer" },
 	{ },
 };
-- 
2.38.1



From prabhakar.mahadev-lad.rj at bp.renesas.com  Mon Dec 12 01:44:21 2022
From: prabhakar.mahadev-lad.rj at bp.renesas.com (Lad Prabhakar)
Date: Mon, 12 Dec 2022 09:44:21 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure the PMA
Message-ID: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support to configure the PMA regions and create a corresponding
reserve memory node and propagate it to the higher boot stack.

&L2 {
       andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
                                (AX45MP_PMACFG_ETYP_NAPOT |
                                 AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
};

PMA regions are passed as part of L2 cache node to OpenSBI, these regions
are parsed and configured in the OpenSBI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
---
Hi All,

This patch is based on the discussion [0] so sending this as an RFC
patch so that we get the Linux side of things accepeted first and once its
finalized I'll send a non RFC patch for this.

[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/

Cheers,
Prabhakar
---
 platform/generic/renesas/rzfive/objects.mk   |   1 +
 platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
 platform/generic/renesas/rzfive/rzfive-pma.h |  12 +
 platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
 4 files changed, 421 insertions(+)
 create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
 create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h

diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
index 2e7e37f..d666417 100644
--- a/platform/generic/renesas/rzfive/objects.mk
+++ b/platform/generic/renesas/rzfive/objects.mk
@@ -6,3 +6,4 @@
 
 carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
 platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
+platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive-pma.o
diff --git a/platform/generic/renesas/rzfive/rzfive-pma.c b/platform/generic/renesas/rzfive/rzfive-pma.c
new file mode 100644
index 0000000..a3c0126
--- /dev/null
+++ b/platform/generic/renesas/rzfive/rzfive-pma.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ * Copyright (c) 2020 Andes Technology Corporation
+ *
+ * Authors:
+ *      Nick Hu <nickhu at andestech.com>
+ *      Nylon Chen <nylon7 at andestech.com>
+ */
+
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_io.h>
+#include <sbi/sbi_error.h>
+
+/* Configuration Registers */
+#define CSR_MMSC_CFG		0xfc2
+
+#define PMA_MMSC_CFG		(1 << 30)
+
+#define PMAADDR_0		0xBD0
+#define PMAADDR_1		0xBD1
+#define PMAADDR_2		0xBD2
+#define PMAADDR_3		0xBD3
+#define PMAADDR_4		0xBD4
+#define PMAADDR_5		0xBD5
+#define PMAADDR_6		0xBD6
+#define PMAADDR_7		0xBD7
+#define PMAADDR_8		0xBD8
+#define PMAADDR_9		0xBD9
+#define PMAADDR_10		0xBDA
+#define PMAADDR_11		0xBDB
+#define PMAADDR_12		0xBDC
+#define PMAADDR_13		0xBDD
+#define PMAADDR_14		0xBDE
+#define PMAADDR_15		0xBDF
+
+/* n = 0 - 3 */
+#define PMACFG_n(n)		(0xbc0 + (n))
+
+static inline unsigned long rzfive_read_pmacfg(unsigned int i)
+{
+	unsigned long val = 0;
+
+	if (!i)
+		val = csr_read(PMACFG_n(0));
+	else if (i == 1)
+		val = csr_read(PMACFG_n(2));
+
+	return val;
+}
+
+static inline void rzfive_write_pmacfg(unsigned int i, unsigned long val)
+{
+	if (!i)
+		csr_write(PMACFG_n(0), val);
+	else if (i == 1)
+		csr_write(PMACFG_n(2), val);
+}
+
+static inline void rzfive_write_pmaaddr(unsigned int i, unsigned long val)
+{
+	if (i == 0)
+		csr_write(PMAADDR_0, val);
+	else if (i == 1)
+		csr_write(PMAADDR_1, val);
+	else if (i == 2)
+		csr_write(PMAADDR_2, val);
+	else if (i == 3)
+		csr_write(PMAADDR_3, val);
+	else if (i == 4)
+		csr_write(PMAADDR_4, val);
+	else if (i == 5)
+		csr_write(PMAADDR_5, val);
+	else if (i == 6)
+		csr_write(PMAADDR_6, val);
+	else if (i == 7)
+		csr_write(PMAADDR_7, val);
+	else if (i == 8)
+		csr_write(PMAADDR_8, val);
+	else if (i == 9)
+		csr_write(PMAADDR_9, val);
+	else if (i == 10)
+		csr_write(PMAADDR_10, val);
+	else if (i == 11)
+		csr_write(PMAADDR_11, val);
+	else if (i == 12)
+		csr_write(PMAADDR_12, val);
+	else if (i == 13)
+		csr_write(PMAADDR_13, val);
+	else if (i == 14)
+		csr_write(PMAADDR_14, val);
+	else if (i == 15)
+		csr_write(PMAADDR_15, val);
+}
+
+static inline unsigned long rzfive_read_pmaaddr(unsigned int i)
+{
+	unsigned long ret = 0;
+
+	if (i == 0)
+		ret = csr_read(PMAADDR_0);
+	else if (i == 1)
+		ret = csr_read(PMAADDR_1);
+	else if (i == 2)
+		ret = csr_read(PMAADDR_2);
+	else if (i == 3)
+		ret = csr_read(PMAADDR_3);
+	else if (i == 4)
+		ret = csr_read(PMAADDR_4);
+	else if (i == 5)
+		ret = csr_read(PMAADDR_5);
+	else if (i == 6)
+		ret =  csr_read(PMAADDR_6);
+	else if (i == 7)
+		ret = csr_read(PMAADDR_7);
+	else if (i == 8)
+		ret = csr_read(PMAADDR_8);
+	else if (i == 9)
+		ret = csr_read(PMAADDR_9);
+	else if (i == 10)
+		ret = csr_read(PMAADDR_10);
+	else if (i == 11)
+		ret = csr_read(PMAADDR_11);
+	else if (i == 12)
+		ret = csr_read(PMAADDR_12);
+	else if (i == 13)
+		ret = csr_read(PMAADDR_13);
+	else if (i == 14)
+		ret = csr_read(PMAADDR_14);
+	else if (i == 15)
+		ret = csr_read(PMAADDR_15);
+
+	return ret;
+}
+
+unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
+				      int entry_id, u32 flag)
+{
+	unsigned long size_tmp, shift = 0, pmacfg_val;
+	unsigned long mmsc = csr_read(CSR_MMSC_CFG);
+	unsigned long pa = addr;
+	char *pmaxcfg;
+	int power = 0;
+
+	if (flag > 0xff || entry_id > 15)
+		return SBI_EINVAL;
+
+	if ((mmsc & PMA_MMSC_CFG) == 0)
+		return 0;
+
+	size_tmp = size;
+	if ((pa & (size_tmp - 1)) != 0) {
+		pa = pa & ~(size_tmp - 1);
+		size_tmp = size_tmp << 1;
+	}
+
+	/* Calculate the NAPOT table for pmaaddr */
+	size_tmp = size;
+	while (size_tmp != 0x1) {
+		size_tmp = size_tmp >> 1;
+		power++;
+		if (power > 3)
+			shift = (shift << 1) | 0x1;
+	}
+
+	pmacfg_val = rzfive_read_pmacfg(entry_id / 8);
+	pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
+	*pmaxcfg = 0;
+	*pmaxcfg = (u8)flag;
+
+	rzfive_write_pmacfg(entry_id / 8, pmacfg_val);
+
+	pa = pa >> 2;
+	pa |= shift;
+	pa = pa & ~(0x1 << (power - 3));
+
+	rzfive_write_pmaaddr(entry_id, pa);
+
+	return rzfive_read_pmaaddr(entry_id) == pa ? pa : SBI_EINVAL;
+}
diff --git a/platform/generic/renesas/rzfive/rzfive-pma.h b/platform/generic/renesas/rzfive/rzfive-pma.h
new file mode 100644
index 0000000..0ae3b79
--- /dev/null
+++ b/platform/generic/renesas/rzfive/rzfive-pma.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#ifndef _RZFIVE_PMA_H_
+#define _RZFIVE_PMA_H_
+
+unsigned long rzfive_setup_pma_region(unsigned long pa, unsigned long size,
+				      int entry_id, u32 flag);
+
+#endif /* _RZFIVE_PMA_H_ */
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index ca182e3..356df07 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -4,9 +4,234 @@
  *
  */
 
+#include <libfdt.h>
 #include <platform_override.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_console.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
+#include "rzfive-pma.h"
+
+/* AX45MP registers */
+#define AX45MP_CSR_MISA_CFG			0x301
+#define AX45MP_CSR_MICM_CFG			0xfc0
+#define AX45MP_CSR_MDCM_CFG			0xfc1
+#define AX45MP_CSR_MMSC_CFG			0xfc2
+#define AX45MP_CSR_MCACHE_CTL			0x7ca
+
+/* AX45MP register bit offsets and masks */
+#define AX45MP_MISA_20_OFFSET			20
+#define AX45MP_MISA_20_MASK			(0x1 << AX45MP_MISA_20_OFFSET)
+
+#define AX45MP_MICM_CFG_ISZ_OFFSET		6
+#define AX45MP_MICM_CFG_ISZ_MASK		(0x7  << AX45MP_MICM_CFG_ISZ_OFFSET)
+
+#define AX45MP_MDCM_CFG_DSZ_OFFSET		6
+#define AX45MP_MDCM_CFG_DSZ_MASK		(0x7  << AX45MP_MDCM_CFG_DSZ_OFFSET)
+
+#define AX45MP_MMSC_CFG_CCTLCSR_OFFSET		16
+#define AX45MP_MMSC_CFG_CCTLCSR_MASK		(0x1 << AX45MP_MMSC_CFG_CCTLCSR_OFFSET)
+#define AX45MP_MMSC_IOCP_OFFSET			47
+#define AX45MP_MMSC_IOCP_MASK			(0x1ULL << AX45MP_MMSC_IOCP_OFFSET)
+
+#define AX45MP_MCACHE_CTL_CCTL_SUEN_OFFSET	8
+#define AX45MP_MCACHE_CTL_CCTL_SUEN_MASK	(0x1 << AX45MP_MCACHE_CTL_CCTL_SUEN_OFFSET)
+
+#define AX45MP_MAX_PMA_REGIONS			16
+
+enum rzfive_sbi_ext_fid {
+	RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND = 0,
+};
+
+static bool rzfive_cpu_cache_controlable(void)
+{
+	return (((csr_read(AX45MP_CSR_MICM_CFG) & AX45MP_MICM_CFG_ISZ_MASK) ||
+		 (csr_read(AX45MP_CSR_MDCM_CFG) & AX45MP_MDCM_CFG_DSZ_MASK)) &&
+		(csr_read(AX45MP_CSR_MISA_CFG) & AX45MP_MISA_20_MASK) &&
+		(csr_read(AX45MP_CSR_MMSC_CFG) & AX45MP_MMSC_CFG_CCTLCSR_MASK) &&
+		(csr_read(AX45MP_CSR_MCACHE_CTL) & AX45MP_MCACHE_CTL_CCTL_SUEN_MASK));
+}
+
+static bool rzfive_cpu_iocp_disabled(void)
+{
+	return (csr_read(AX45MP_CSR_MMSC_CFG) & AX45MP_MMSC_IOCP_MASK) ? false : true;
+}
+
+static bool rzfive_apply_iocp_sw_workaround(void)
+{
+	return rzfive_cpu_cache_controlable() & rzfive_cpu_iocp_disabled();
+}
+
+static int fdt_resv_memory_update_node(void *fdt, unsigned long addr,
+				       unsigned long size, int index,
+				       int parent)
+{
+	int na = fdt_address_cells(fdt, 0);
+	int ns = fdt_size_cells(fdt, 0);
+	fdt32_t addr_high, addr_low;
+	fdt32_t size_high, size_low;
+	int subnode, err;
+	fdt32_t reg[4];
+	fdt32_t *val;
+	char name[32];
+
+	addr_high = (u64)addr >> 32;
+	addr_low = addr;
+	size_high = (u64)size >> 32;
+	size_low = size;
+
+	if (na > 1 && addr_high)
+		sbi_snprintf(name, sizeof(name),
+			     "pma_resv%d@%x,%x", index,
+			     addr_high, addr_low);
+	else
+		sbi_snprintf(name, sizeof(name),
+			     "pma_resv%d@%x", index,
+			     addr_low);
+
+	subnode = fdt_add_subnode(fdt, parent, name);
+	if (subnode < 0)
+		return subnode;
+
+	err = fdt_setprop_string(fdt, subnode, "compatible", "shared-dma-pool");
+	if (err < 0)
+		return err;
+
+	err = fdt_setprop_empty(fdt, subnode, "no-map");
+	if (err < 0)
+		return err;
+
+	/*
+	 * Linux allows single linux,dma-default region so lets mark
+	 * the first pma region as linux,dma-default
+	 */
+	if (!index) {
+		err = fdt_setprop_empty(fdt, subnode, "linux,dma-default");
+		if (err < 0)
+			return err;
+	}
+
+	/* encode the <reg> property value */
+	val = reg;
+	if (na > 1)
+		*val++ = cpu_to_fdt32(addr_high);
+	*val++ = cpu_to_fdt32(addr_low);
+	if (ns > 1)
+		*val++ = cpu_to_fdt32(size_high);
+	*val++ = cpu_to_fdt32(size_low);
+
+	err = fdt_setprop(fdt, subnode, "reg", reg,
+			  (na + ns) * sizeof(fdt32_t));
+	if (err < 0)
+		return err;
+
+	return 0;
+}
+
+static int fdt_reserved_memory_fixup(void *fdt, unsigned long addr,
+				     unsigned long size, int entry)
+{
+	int na = fdt_address_cells(fdt, 0);
+	int ns = fdt_size_cells(fdt, 0);
+	int err, parent;
+
+	/* try to locate the reserved memory node */
+	parent = fdt_path_offset(fdt, "/reserved-memory");
+	if (parent < 0) {
+		/* if such node does not exist, create one */
+		parent = fdt_add_subnode(fdt, 0, "reserved-memory");
+		if (parent < 0)
+			return parent;
+
+		err = fdt_setprop_empty(fdt, parent, "ranges");
+		if (err < 0)
+			return err;
+
+		err = fdt_setprop_u32(fdt, parent, "#size-cells", ns);
+		if (err < 0)
+			return err;
+
+		err = fdt_setprop_u32(fdt, parent, "#address-cells", na);
+		if (err < 0)
+			return err;
+	}
+
+	return fdt_resv_memory_update_node(fdt, addr, size, entry, parent);
+}
+
+static int rzfive_configure_pma_regions(void)
+{
+	void *fdt = fdt_get_address();
+	unsigned long start[16], size[16];
+	unsigned long pma_addr;
+	unsigned int i, j;
+	int cells_count;
+	u32 flags[16];
+	int l2c_off;
+	u32 *cells;
+	int ret;
+
+	l2c_off = fdt_node_offset_by_compatible(fdt, 0, "v5l2cache");
+	if (l2c_off < 0)
+		return 0;
+
+	cells = (u32 *)fdt_getprop(fdt, l2c_off,
+				   "andestech,pma-regions", &cells_count);
+	if (!cells)
+		return 0;
+
+	cells_count = cells_count / sizeof(u32);
+	if (!cells_count)
+		return 0;
+
+	if (cells_count % 5 || (cells_count / 5) > AX45MP_MAX_PMA_REGIONS)
+		return SBI_EINVAL;
+
+	for (i = 0, j = 0; i < cells_count; i += 5, j++) {
+		start[j] = ((u64)fdt32_to_cpu(cells[i]) << 32) | fdt32_to_cpu(cells[i + 1]);
+		size[j] = ((u64)fdt32_to_cpu(cells[i + 2]) << 32) | fdt32_to_cpu(cells[i + 3]);
+		flags[j] = fdt32_to_cpu(cells[i + 4]);
+		pma_addr = rzfive_setup_pma_region(start[j], size[j], j, flags[j]);
+		if (pma_addr == SBI_EINVAL)
+			return SBI_EINVAL;
+	}
+
+	ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + (64 * j));
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < j; i++) {
+		ret = fdt_reserved_memory_fixup(fdt, start[i], size[i], i);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rzf_final_init(bool cold_boot, const struct fdt_match *match)
+{
+	return rzfive_configure_pma_regions();
+}
+
+static int rzfive_vendor_ext_provider(long extid, long funcid,
+				      const struct sbi_trap_regs *regs,
+				      unsigned long *out_value,
+				      struct sbi_trap_info *out_trap,
+				      const struct fdt_match *match)
+{
+	switch (funcid) {
+	case RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND:
+		*out_value = rzfive_apply_iocp_sw_workaround();
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
 static const struct fdt_match renesas_rzfive_match[] = {
 	{ .compatible = "renesas,r9a07g043f01" },
 	{ /* sentinel */ }
@@ -14,4 +239,6 @@ static const struct fdt_match renesas_rzfive_match[] = {
 
 const struct platform_override renesas_rzfive = {
 	.match_table = renesas_rzfive_match,
+	.final_init = rzf_final_init,
+	.vendor_ext_provider = rzfive_vendor_ext_provider,
 };
-- 
2.17.1



From anup at brainfault.org  Mon Dec 12 05:28:53 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 12 Dec 2022 18:58:53 +0530
Subject: [PATCH v5 0/5] Add support for Renesas RZ/Five SoC
In-Reply-To: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221210103011.7814-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAAhSdy2ANrHhbq4AYNVdcuSo8AL3UbH5Ej8S-MZanJNksYUH+w@mail.gmail.com>

On Sat, Dec 10, 2022 at 4:00 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
>
> Hi All,
>
> This patch series adds initial support to RZ/Five (R9A07G043F) SoC (which
> is equipped with AX45MP AndesCore). Platform supports DT based probing.
>
> Linux support is currently being upstreamed the latest patchset can be
> found at [0](currently in linux-next, DT bindings can be seen here)
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/20221028165921.94487-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> - PLIC binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml#L57
> - PLMT and PLICSW are not used by any driver in kernel hence DT bindings for it
>   and is used in a similar manner as compared Andes AE350 [1]
>   [1] https://github.com/andestech/linux/commits/v6.0.y_ae350-ax45mp/Documentation/devicetree/bindings
> - SCIF binding - https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/serial/renesas,scif.yaml#L79
>
> Note:
> - The PMA implementation is still in discussion [1] once its decided
> corresponding patch to OpenSBI will be added to reserve the memory nodes
> and vendor specific SBI EXT.
> - U-boot from BSP release wont work with these patches, it requires additional
>   patches (happy to share the u-boot branch if anyone wants to test this patchset)
> - Patches apply on top of [2]
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> [2] https://patchwork.ozlabs.org/project/opensbi/cover/20221128083046.6799-1-peterlin at andestech.com/
>
> v4->v5
> * Included RB tag from Anup for patch 5/5
> * Updated generic.md to include RZ/Five SoC
>
> v3->v4
> * Included RB tags
> * Updated doc
> * Sorted compatible string list
> * Fixed minor issues related to scif driver
>
> v2->v3
> * Switched to generic platform
> * Dropped all vendor specific SBI EXT
> * Fixed review comments pointed by Bin for SCIF driver
> * Updated doc
>
> RFC->v2
> * Fixed comments pointed by Xiang W
> * Included RB tag from Yu Chien Peter Lin for patch #3
>
> RFC: https://patchwork.ozlabs.org/project/opensbi/cover/20221028004042.135549-1-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (5):
>   lib: utils: serial: Add Renesas SCIF driver
>   lib: utils: serial: Add FDT driver for Renesas SCIF
>   lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
>   platform: generic: Add Renesas RZ/Five initial support
>   docs: platform: Add documentation for Renesas RZ/Five SoC

Applied this series to the riscv/opensbi repo.

Thanks,
Anup

>
>  docs/platform/generic.md                   |   2 +
>  docs/platform/platform.md                  |   5 +
>  docs/platform/renesas-rzfive.md            | 160 +++++++++++++++++++++
>  include/sbi_utils/fdt/fdt_helper.h         |   3 +
>  include/sbi_utils/serial/renesas-scif.h    |  11 ++
>  lib/utils/fdt/fdt_helper.c                 |  11 ++
>  lib/utils/irqchip/fdt_irqchip_plic.c       |   3 +-
>  lib/utils/serial/Kconfig                   |   9 ++
>  lib/utils/serial/fdt_serial_renesas_scif.c |  31 ++++
>  lib/utils/serial/objects.mk                |   4 +
>  lib/utils/serial/renesas_scif.c            | 116 +++++++++++++++
>  platform/generic/Kconfig                   |   4 +
>  platform/generic/configs/defconfig         |   2 +
>  platform/generic/renesas/rzfive/objects.mk |   8 ++
>  platform/generic/renesas/rzfive/rzfive.c   |  17 +++
>  15 files changed, 385 insertions(+), 1 deletion(-)
>  create mode 100644 docs/platform/renesas-rzfive.md
>  create mode 100644 include/sbi_utils/serial/renesas-scif.h
>  create mode 100644 lib/utils/serial/fdt_serial_renesas_scif.c
>  create mode 100644 lib/utils/serial/renesas_scif.c
>  create mode 100644 platform/generic/renesas/rzfive/objects.mk
>  create mode 100644 platform/generic/renesas/rzfive/rzfive.c
>
> --
> 2.17.1
>


From apatel at ventanamicro.com  Mon Dec 12 05:38:01 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Mon, 12 Dec 2022 19:08:01 +0530
Subject: [PATCH v3 2/3] platform: generic: Allow platform_override to
 select cold boot HART
In-Reply-To: <20221212054018.169408-3-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com> <20221212054018.169408-3-weiliang.lim@starfivetech.com>
Message-ID: <CAK9=C2XXSr50Vnw==WnOU2DYdUcRdWnqWxJurb=3-0HMnoqJzQ@mail.gmail.com>

On Mon, Dec 12, 2022 at 11:10 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> From: Anup Patel <apatel at ventanamicro.com>
>
> We add a generic platform override callback to allow platform specific
> selection of cold boot HART.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  platform/generic/include/platform_override.h | 1 +
>  platform/generic/platform.c                  | 9 +++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index 7f1558d..21354e9 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -18,6 +18,7 @@ struct platform_override {
>         const struct fdt_match *match_table;
>         u64 (*features)(const struct fdt_match *match);
>         u64 (*tlbr_flush_limit)(const struct fdt_match *match);
> +       bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
>         int (*early_init)(bool cold_boot, const struct fdt_match *match);
>         int (*final_init)(bool cold_boot, const struct fdt_match *match);
>         void (*early_exit)(const struct fdt_match *match);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index bfe15f0..80961f0 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -122,6 +122,14 @@ fail:
>                 wfi();
>  }
>
> +static bool generic_cold_boot_allowed(u32 hartid)
> +{
> +       if (generic_plat && generic_plat->cold_boot_allowed)
> +               return generic_plat && generic_plat->cold_boot_allowed(
> +                                               hartid, generic_plat_match);

There is a typo here. This line should be:
"return generic_plat->cold_boot_allowed(hartid, generic_plat_match);"

> +       return TRUE;
> +}
> +
>  static int generic_nascent_init(void)
>  {
>         if (platform_has_mlevel_imsic)
> @@ -261,6 +269,7 @@ static int generic_console_init(void)
>  }
>
>  const struct sbi_platform_operations platform_ops = {
> +       .cold_boot_allowed      = generic_cold_boot_allowed,
>         .nascent_init           = generic_nascent_init,
>         .early_init             = generic_early_init,
>         .final_init             = generic_final_init,
> --
> 2.25.1
>

Regards,
Anup


From anup at brainfault.org  Mon Dec 12 05:42:17 2022
From: anup at brainfault.org (Anup Patel)
Date: Mon, 12 Dec 2022 19:12:17 +0530
Subject: [PATCH v3 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221212054018.169408-4-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com> <20221212054018.169408-4-weiliang.lim@starfivetech.com>
Message-ID: <CAAhSdy1Vy2MX0GyC3Cw0zH89un0ETbH6h0a09SNtPVEkJEQTbQ@mail.gmail.com>

On Mon, Dec 12, 2022 at 11:11 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> Add Starfive JH7110 platform implementation
>
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  platform/generic/Kconfig             |  4 ++++
>  platform/generic/configs/defconfig   |  1 +
>  platform/generic/starfive/jh7110.c   | 27 +++++++++++++++++++++++++++
>  platform/generic/starfive/objects.mk |  6 ++++++
>  4 files changed, 38 insertions(+)
>  create mode 100644 platform/generic/starfive/jh7110.c
>  create mode 100644 platform/generic/starfive/objects.mk
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 4b5d2cd..a6e467d 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -41,4 +41,8 @@ config PLATFORM_SIFIVE_FU740
>         depends on FDT_RESET && FDT_I2C
>         default n
>
> +config PLATFORM_STARFIVE_JH7110
> +       bool "StarFive JH7110 support"
> +       default n
> +
>  endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 2eaeeb7..ef6aad9 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -2,6 +2,7 @@ CONFIG_PLATFORM_ALLWINNER_D1=y
>  CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_FDT_GPIO=y
>  CONFIG_FDT_GPIO_SIFIVE=y
>  CONFIG_FDT_I2C=y
> diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
> new file mode 100644
> index 0000000..1c76975
> --- /dev/null
> +++ b/platform/generic/starfive/jh7110.c
> @@ -0,0 +1,27 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 StarFive
> + *
> + * Authors:
> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> + */
> +
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static bool starfive_cold_boot_allowed(u32 hartid,
> +                                  const struct fdt_match *match)
> +{
> +       return (hartid == 1);
> +}
> +
> +static const struct fdt_match starfive_jh7110_match[] = {
> +       { .compatible = "starfive,jh7110" },
> +       { },
> +};
> +
> +const struct platform_override starfive_jh7110 = {
> +       .match_table = starfive_jh7110_match,
> +       .cold_boot_allowed = starfive_cold_boot_allowed,
> +};
> diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
> new file mode 100644
> index 0000000..0b900fb
> --- /dev/null
> +++ b/platform/generic/starfive/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
> --
> 2.25.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Mon Dec 12 23:48:19 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 13 Dec 2022 13:18:19 +0530
Subject: [PATCH v2 3/3] lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible
In-Reply-To: <20221212082238.265281-4-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me> <20221212082238.265281-4-uwu@icenowy.me>
Message-ID: <CAAhSdy0um025HXxDpUOjWVpLGAWmjoQ2RYS2u8W_ja5VQTFB0g@mail.gmail.com>

On Mon, Dec 12, 2022 at 1:53 PM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> As we already added the quirk for lacking mtime register to MTIMER
> driver, add T-Head C9xx CLINT compatible to it and wire the quirk.
>
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> No changes in v2.
>
>  lib/utils/timer/fdt_timer_mtimer.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index a0adc70..5244f98 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -124,9 +124,15 @@ static const struct timer_mtimer_quirks sifive_clint_quirks = {
>         .has_64bit_mmio = true,
>  };
>
> +static const struct timer_mtimer_quirks thead_clint_quirks = {
> +       .mtime_offset   = CLINT_MTIMER_OFFSET,
> +       .without_mtime  = true,
> +};
> +
>  static const struct fdt_match timer_mtimer_match[] = {
>         { .compatible = "riscv,clint0", .data = &sifive_clint_quirks },
>         { .compatible = "sifive,clint0", .data = &sifive_clint_quirks },
> +       { .compatible = "thead,c900-clint", .data = &thead_clint_quirks },
>         { .compatible = "riscv,aclint-mtimer" },
>         { },
>  };
> --
> 2.38.1
>


From anup at brainfault.org  Mon Dec 12 23:50:34 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 13 Dec 2022 13:20:34 +0530
Subject: [PATCH v2 2/3] lib: utils/timer: mtimer: add a quirk for lacking
 mtime register
In-Reply-To: <20221212082238.265281-3-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me> <20221212082238.265281-3-uwu@icenowy.me>
Message-ID: <CAAhSdy1HnZ-QFVnvm+94LTrGABHyyUk+dtHeageHw9VPMNaPNA@mail.gmail.com>

On Mon, Dec 12, 2022 at 1:53 PM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> T-Head developers surely have a different understanding of time CSR and
> CLINT's mtime register with SiFive ones, that they did not implement
> the mtime register at all -- as shown in openC906 source code, their
> time CSR value is just exposed at the top of their processor IP block
> and expects an external continous counter, which makes it not
> overrideable, and thus mtime register is not implemented, even not for
> reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
> extended CSR, these systems still rely on the mtimecmp registers to
> generate timer interrupts. This makes it necessary to implement T-Head
> C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
> reading mtime register and falls back to default code that reads time
> CSR.
>
> Add a quirk into MTIMER driver, which represents a mtime register is
> lacking and time CSR value should be used instead.
>
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
> Changes in v2:
> - Dropped has_mtime field in aclint_mtimer_data, use mtime_size = 0
>   (which is disallowed before) to mark absence of mtime.
> - Dropped the code that specially handle the existence of mtime when
>   registering memory ranges -- the function will just be a no-op when
>   size is 0.
>
>  lib/utils/timer/aclint_mtimer.c    | 11 ++++++++---
>  lib/utils/timer/fdt_timer_mtimer.c | 30 ++++++++++++++++++++----------
>  2 files changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
> index 3f00c21..1846a9a 100644
> --- a/lib/utils/timer/aclint_mtimer.c
> +++ b/lib/utils/timer/aclint_mtimer.c
> @@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
>         int rc;
>
>         /* Sanity checks */
> -       if (!mt || !mt->mtime_size ||
> +       if (!mt ||
>             (mt->hart_count && !mt->mtimecmp_size) ||
> -           (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> -           (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> +           (mt->mtime_size && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
> +           (mt->mtime_size && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
>             (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
>             (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
>             (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
> @@ -178,6 +178,11 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
>         for (i = 0; i < mt->hart_count; i++)
>                 mtimer_hartid2data[mt->first_hartid + i] = mt;
>
> +       if (!mt->mtime_size) {
> +               /* Disable reading mtime when mtime is not available */
> +               mtimer.timer_value = NULL;
> +       }
> +
>         /* Add MTIMER regions to the root domain */
>         if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
>                 rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index 7b8546b..a0adc70 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -18,6 +18,7 @@
>  struct timer_mtimer_quirks {
>         unsigned int    mtime_offset;
>         bool            has_64bit_mmio;
> +       bool            without_mtime;
>  };
>
>  static unsigned long mtimer_count = 0;
> @@ -53,12 +54,16 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>                 /* Set CLINT addresses */
>                 mt->mtimecmp_addr = addr[0] + ACLINT_DEFAULT_MTIMECMP_OFFSET;
>                 mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
> -               mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> -               mt->mtime_size = size[0] - mt->mtimecmp_size;
> -               /* Adjust MTIMER address and size for CLINT device */
> -               mt->mtime_addr += quirks->mtime_offset;
> +               if (!quirks->without_mtime) {
> +                       mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> +                       mt->mtime_size = size[0] - mt->mtimecmp_size;
> +                       /* Adjust MTIMER address and size for CLINT device */
> +                       mt->mtime_addr += quirks->mtime_offset;
> +                       mt->mtime_size -= quirks->mtime_offset;
> +               } else {
> +                       mt->mtime_addr = mt->mtime_size = 0;
> +               }
>                 mt->mtimecmp_addr += quirks->mtime_offset;
> -               mt->mtime_size -= quirks->mtime_offset;
>                 /* Apply additional CLINT quirks */
>                 mt->has_64bit_mmio = quirks->has_64bit_mmio;
>         } else { /* RISC-V ACLINT MTIMER */
> @@ -70,12 +75,17 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
>         }
>
>         /* Check if MTIMER device has shared MTIME address */
> -       mt->has_shared_mtime = false;
> -       for (i = 0; i < mtimer_count; i++) {
> -               if (mtimer[i].mtime_addr == mt->mtime_addr) {
> -                       mt->has_shared_mtime = true;
> -                       break;
> +       if (mt->mtime_size) {
> +               mt->has_shared_mtime = false;
> +               for (i = 0; i < mtimer_count; i++) {
> +                       if (mtimer[i].mtime_addr == mt->mtime_addr) {
> +                               mt->has_shared_mtime = true;
> +                               break;
> +                       }
>                 }
> +       } else {
> +               /* Assume shared time CSR */
> +               mt->has_shared_mtime = true;
>         }
>
>         /* Initialize the MTIMER device */
> --
> 2.38.1
>


From wxjstz at 126.com  Tue Dec 13 00:01:43 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 13 Dec 2022 16:01:43 +0800
Subject: [PATCH v2 2/3] lib: utils/timer: mtimer: add a quirk for
 lacking mtime register
In-Reply-To: <20221212082238.265281-3-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me>
	 <20221212082238.265281-3-uwu@icenowy.me>
Message-ID: <27234f248aa70b8b7d994e16113f0a2d414debdd.camel@126.com>

? 2022-12-12???? 16:22 +0800?Icenowy Zheng???
> T-Head developers surely have a different understanding of time CSR and
> CLINT's mtime register with SiFive ones, that they did not implement
> the mtime register at all -- as shown in openC906 source code, their
> time CSR value is just exposed at the top of their processor IP block
> and expects an external continous counter, which makes it not
> overrideable, and thus mtime register is not implemented, even not for
> reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
> extended CSR, these systems still rely on the mtimecmp registers to
> generate timer interrupts. This makes it necessary to implement T-Head
> C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
> reading mtime register and falls back to default code that reads time
> CSR.
> 
> Add a quirk into MTIMER driver, which represents a mtime register is
> lacking and time CSR value should be used instead.
> 
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
> ---
> Changes in v2:
> - Dropped has_mtime field in aclint_mtimer_data, use mtime_size = 0
> ? (which is disallowed before) to mark absence of mtime.
> - Dropped the code that specially handle the existence of mtime when
> ? registering memory ranges -- the function will just be a no-op when
> ? size is 0.
> 
> ?lib/utils/timer/aclint_mtimer.c??? | 11 ++++++++---
> ?lib/utils/timer/fdt_timer_mtimer.c | 30 ++++++++++++++++++++----------
> ?2 files changed, 28 insertions(+), 13 deletions(-)
> 
> diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
> index 3f00c21..1846a9a 100644
> --- a/lib/utils/timer/aclint_mtimer.c
> +++ b/lib/utils/timer/aclint_mtimer.c
> @@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
> ????????int rc;
> ?
> ????????/* Sanity checks */
> -???????if (!mt || !mt->mtime_size ||
> +???????if (!mt ||
> ??????????? (mt->hart_count && !mt->mtimecmp_size) ||
> -?????????? (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> -?????????? (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> +?????????? (mt->mtime_size && (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1))) ||
typo.
mt->mtime_size should be mt->mtime_addr.

Regards,
Xiang W
> +?????????? (mt->mtime_size && (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1))) ||
> ??????????? (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> ??????????? (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> ??????????? (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
> @@ -178,6 +178,11 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
> ????????for (i = 0; i < mt->hart_count; i++)
> ????????????????mtimer_hartid2data[mt->first_hartid + i] = mt;
> ?
> +???????if (!mt->mtime_size) {
> +???????????????/* Disable reading mtime when mtime is not available */
> +???????????????mtimer.timer_value = NULL;
> +???????}
> +
> ????????/* Add MTIMER regions to the root domain */
> ????????if (mt->mtime_addr == (mt->mtimecmp_addr + mt->mtimecmp_size)) {
> ????????????????rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
> diff --git a/lib/utils/timer/fdt_timer_mtimer.c b/lib/utils/timer/fdt_timer_mtimer.c
> index 7b8546b..a0adc70 100644
> --- a/lib/utils/timer/fdt_timer_mtimer.c
> +++ b/lib/utils/timer/fdt_timer_mtimer.c
> @@ -18,6 +18,7 @@
> ?struct timer_mtimer_quirks {
> ????????unsigned int????mtime_offset;
> ????????bool????????????has_64bit_mmio;
> +???????bool????????????without_mtime;
> ?};
> ?
> ?static unsigned long mtimer_count = 0;
> @@ -53,12 +54,16 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> ????????????????/* Set CLINT addresses */
> ????????????????mt->mtimecmp_addr = addr[0] + ACLINT_DEFAULT_MTIMECMP_OFFSET;
> ????????????????mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
> -???????????????mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> -???????????????mt->mtime_size = size[0] - mt->mtimecmp_size;
> -???????????????/* Adjust MTIMER address and size for CLINT device */
> -???????????????mt->mtime_addr += quirks->mtime_offset;
> +???????????????if (!quirks->without_mtime) {
> +???????????????????????mt->mtime_addr = addr[0] + ACLINT_DEFAULT_MTIME_OFFSET;
> +???????????????????????mt->mtime_size = size[0] - mt->mtimecmp_size;
> +???????????????????????/* Adjust MTIMER address and size for CLINT device */
> +???????????????????????mt->mtime_addr += quirks->mtime_offset;
> +???????????????????????mt->mtime_size -= quirks->mtime_offset;
> +???????????????} else {
> +???????????????????????mt->mtime_addr = mt->mtime_size = 0;
> +???????????????}
> ????????????????mt->mtimecmp_addr += quirks->mtime_offset;
> -???????????????mt->mtime_size -= quirks->mtime_offset;
> ????????????????/* Apply additional CLINT quirks */
> ????????????????mt->has_64bit_mmio = quirks->has_64bit_mmio;
> ????????} else { /* RISC-V ACLINT MTIMER */
> @@ -70,12 +75,17 @@ static int timer_mtimer_cold_init(void *fdt, int nodeoff,
> ????????}
> ?
> ????????/* Check if MTIMER device has shared MTIME address */
> -???????mt->has_shared_mtime = false;
> -???????for (i = 0; i < mtimer_count; i++) {
> -???????????????if (mtimer[i].mtime_addr == mt->mtime_addr) {
> -???????????????????????mt->has_shared_mtime = true;
> -???????????????????????break;
> +???????if (mt->mtime_size) {
> +???????????????mt->has_shared_mtime = false;
> +???????????????for (i = 0; i < mtimer_count; i++) {
> +???????????????????????if (mtimer[i].mtime_addr == mt->mtime_addr) {
> +???????????????????????????????mt->has_shared_mtime = true;
> +???????????????????????????????break;
> +???????????????????????}
> ????????????????}
> +???????} else {
> +???????????????/* Assume shared time CSR */
> +???????????????mt->has_shared_mtime = true;
> ????????}
> ?
> ????????/* Initialize the MTIMER device */
> -- 
> 2.38.1
> 
> 




From uwu at icenowy.me  Tue Dec 13 00:51:10 2022
From: uwu at icenowy.me (Icenowy Zheng)
Date: Tue, 13 Dec 2022 16:51:10 +0800
Subject: [PATCH v2 2/3] lib: utils/timer: mtimer: add a quirk for
 lacking mtime register
In-Reply-To: <27234f248aa70b8b7d994e16113f0a2d414debdd.camel@126.com>
References: <20221212082238.265281-1-uwu@icenowy.me>
	 <20221212082238.265281-3-uwu@icenowy.me>
	 <27234f248aa70b8b7d994e16113f0a2d414debdd.camel@126.com>
Message-ID: <b83e8c033064be95b4fe1e542887ced1a85bec3c.camel@icenowy.me>

? 2022-12-13???? 16:01 +0800?Xiang W???
> ? 2022-12-12???? 16:22 +0800?Icenowy Zheng???
> > T-Head developers surely have a different understanding of time CSR
> > and
> > CLINT's mtime register with SiFive ones, that they did not
> > implement
> > the mtime register at all -- as shown in openC906 source code,
> > their
> > time CSR value is just exposed at the top of their processor IP
> > block
> > and expects an external continous counter, which makes it not
> > overrideable, and thus mtime register is not implemented, even not
> > for
> > reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
> > extended CSR, these systems still rely on the mtimecmp registers to
> > generate timer interrupts. This makes it necessary to implement T-
> > Head
> > C9xx CLINT support in OpenSBI MTIMER driver, which skips
> > implementing
> > reading mtime register and falls back to default code that reads
> > time
> > CSR.
> > 
> > Add a quirk into MTIMER driver, which represents a mtime register
> > is
> > lacking and time CSR value should be used instead.
> > 
> > Signed-off-by: Icenowy Zheng <uwu at icenowy.me>
> > ---
> > Changes in v2:
> > - Dropped has_mtime field in aclint_mtimer_data, use mtime_size = 0
> > ? (which is disallowed before) to mark absence of mtime.
> > - Dropped the code that specially handle the existence of mtime
> > when
> > ? registering memory ranges -- the function will just be a no-op
> > when
> > ? size is 0.
> > 
> > ?lib/utils/timer/aclint_mtimer.c??? | 11 ++++++++---
> > ?lib/utils/timer/fdt_timer_mtimer.c | 30 ++++++++++++++++++++------
> > ----
> > ?2 files changed, 28 insertions(+), 13 deletions(-)
> > 
> > diff --git a/lib/utils/timer/aclint_mtimer.c
> > b/lib/utils/timer/aclint_mtimer.c
> > index 3f00c21..1846a9a 100644
> > --- a/lib/utils/timer/aclint_mtimer.c
> > +++ b/lib/utils/timer/aclint_mtimer.c
> > @@ -149,10 +149,10 @@ int aclint_mtimer_cold_init(struct
> > aclint_mtimer_data *mt,
> > ????????int rc;
> > ?
> > ????????/* Sanity checks */
> > -???????if (!mt || !mt->mtime_size ||
> > +???????if (!mt ||
> > ??????????? (mt->hart_count && !mt->mtimecmp_size) ||
> > -?????????? (mt->mtime_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> > -?????????? (mt->mtime_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> > +?????????? (mt->mtime_size && (mt->mtime_addr &
> > (ACLINT_MTIMER_ALIGN - 1))) ||
> typo.

Not a typo, mtime_size = 0 here means the mtime register is just not
available, so we do sanity check on mtime_addr based on the existence
of mtime, thus mtime_size.

> mt->mtime_size should be mt->mtime_addr.
> 
> Regards,
> Xiang W
> > +?????????? (mt->mtime_size && (mt->mtime_size &
> > (ACLINT_MTIMER_ALIGN - 1))) ||
> > ??????????? (mt->mtimecmp_addr & (ACLINT_MTIMER_ALIGN - 1)) ||
> > ??????????? (mt->mtimecmp_size & (ACLINT_MTIMER_ALIGN - 1)) ||
> > ??????????? (mt->first_hartid >= SBI_HARTMASK_MAX_BITS) ||
> > @@ -178,6 +178,11 @@ int aclint_mtimer_cold_init(struct
> > aclint_mtimer_data *mt,
> > ????????for (i = 0; i < mt->hart_count; i++)
> > ????????????????mtimer_hartid2data[mt->first_hartid + i] = mt;
> > ?
> > +???????if (!mt->mtime_size) {
> > +???????????????/* Disable reading mtime when mtime is not
> > available */
> > +???????????????mtimer.timer_value = NULL;
> > +???????}
> > +
> > ????????/* Add MTIMER regions to the root domain */
> > ????????if (mt->mtime_addr == (mt->mtimecmp_addr + mt-
> > >mtimecmp_size)) {
> > ????????????????rc = sbi_domain_root_add_memrange(mt-
> > >mtimecmp_addr,
> > diff --git a/lib/utils/timer/fdt_timer_mtimer.c
> > b/lib/utils/timer/fdt_timer_mtimer.c
> > index 7b8546b..a0adc70 100644
> > --- a/lib/utils/timer/fdt_timer_mtimer.c
> > +++ b/lib/utils/timer/fdt_timer_mtimer.c
> > @@ -18,6 +18,7 @@
> > ?struct timer_mtimer_quirks {
> > ????????unsigned int????mtime_offset;
> > ????????bool????????????has_64bit_mmio;
> > +???????bool????????????without_mtime;
> > ?};
> > ?
> > ?static unsigned long mtimer_count = 0;
> > @@ -53,12 +54,16 @@ static int timer_mtimer_cold_init(void *fdt,
> > int nodeoff,
> > ????????????????/* Set CLINT addresses */
> > ????????????????mt->mtimecmp_addr = addr[0] +
> > ACLINT_DEFAULT_MTIMECMP_OFFSET;
> > ????????????????mt->mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE;
> > -???????????????mt->mtime_addr = addr[0] +
> > ACLINT_DEFAULT_MTIME_OFFSET;
> > -???????????????mt->mtime_size = size[0] - mt->mtimecmp_size;
> > -???????????????/* Adjust MTIMER address and size for CLINT device
> > */
> > -???????????????mt->mtime_addr += quirks->mtime_offset;
> > +???????????????if (!quirks->without_mtime) {
> > +???????????????????????mt->mtime_addr = addr[0] +
> > ACLINT_DEFAULT_MTIME_OFFSET;
> > +???????????????????????mt->mtime_size = size[0] - mt-
> > >mtimecmp_size;
> > +???????????????????????/* Adjust MTIMER address and size for CLINT
> > device */
> > +???????????????????????mt->mtime_addr += quirks->mtime_offset;
> > +???????????????????????mt->mtime_size -= quirks->mtime_offset;
> > +???????????????} else {
> > +???????????????????????mt->mtime_addr = mt->mtime_size = 0;
> > +???????????????}
> > ????????????????mt->mtimecmp_addr += quirks->mtime_offset;
> > -???????????????mt->mtime_size -= quirks->mtime_offset;
> > ????????????????/* Apply additional CLINT quirks */
> > ????????????????mt->has_64bit_mmio = quirks->has_64bit_mmio;
> > ????????} else { /* RISC-V ACLINT MTIMER */
> > @@ -70,12 +75,17 @@ static int timer_mtimer_cold_init(void *fdt,
> > int nodeoff,
> > ????????}
> > ?
> > ????????/* Check if MTIMER device has shared MTIME address */
> > -???????mt->has_shared_mtime = false;
> > -???????for (i = 0; i < mtimer_count; i++) {
> > -???????????????if (mtimer[i].mtime_addr == mt->mtime_addr) {
> > -???????????????????????mt->has_shared_mtime = true;
> > -???????????????????????break;
> > +???????if (mt->mtime_size) {
> > +???????????????mt->has_shared_mtime = false;
> > +???????????????for (i = 0; i < mtimer_count; i++) {
> > +???????????????????????if (mtimer[i].mtime_addr == mt->mtime_addr)
> > {
> > +???????????????????????????????mt->has_shared_mtime = true;
> > +???????????????????????????????break;
> > +???????????????????????}
> > ????????????????}
> > +???????} else {
> > +???????????????/* Assume shared time CSR */
> > +???????????????mt->has_shared_mtime = true;
> > ????????}
> > ?
> > ????????/* Initialize the MTIMER device */
> > -- 
> > 2.38.1
> > 
> > 
> 
> 


From geomatsi at gmail.com  Tue Dec 13 11:43:20 2022
From: geomatsi at gmail.com (Sergey Matyukevich)
Date: Tue, 13 Dec 2022 22:43:20 +0300
Subject: [PATCH RFC v2 2/2] lib: sbi: add support for debug triggers
In-Reply-To: <cd24a0c91272bf5e636c90c2071f6e22bd500cf9.camel@126.com>
References: <20221203213929.206429-1-geomatsi@gmail.com>
 <20221203213929.206429-3-geomatsi@gmail.com>
 <92833f1aeda3262f4ccb4b7fc796ee4de36c7ef0.camel@126.com>
 <Y5Ta7XTiBLwRmxBe@curiosity>
 <cd24a0c91272bf5e636c90c2071f6e22bd500cf9.camel@126.com>
Message-ID: <Y5jV2CPg9nDmOvfO@curiosity>

> > > > RISC-V Debug specification includes Sdtrig ISA extension.
> > > > This extension describes Trigger Module. Triggers can cause
> > > > a breakpoint exception, entry into Debug Mode, or a trace
> > > > action without having to execute a special instruction. For
> > > > native debugging triggers can be used to implement hardware
> > > > breakpoints and watchpoints.
> > > > 
> > > > Software support for triggers consists of the following
> > > > major components:
> > > > - U-mode: gdb
> > > > - S-mode: hardware breakpoints framework in Linux kernel
> > > > - M-mode: SBI firmware code to handle triggers
> > > > 
> > > > SBI Debug Trigger extension proposal has been posted by
> > > > Anup Patel to lists.riscv.org tech-debug mailing list:
> > > > https://lists.riscv.org/g/tech-debug/topic/92375492
> > > > 
> > > > This patch provides initial implementation of SBI Debug
> > > > Trigger Extension in OpenSBI library based on the
> > > > suggested extension proposal.
> > > > 
> > > > Initial implementation has the following limitations:
> > > > - supported triggers: mcontrol, mcontrol6
> > > > - no support for chained triggers
> > > > - only build test for RV32
> > 
> > ... [snip]
> > 
> > > > +struct sbi_dbtr_trig_info {
> > > > +???????unsigned long type_mask;
> > > > +???????union sbi_dbtr_trig_state state;
> > > > +???????unsigned long tdata1;
> > > > +???????unsigned long tdata2;
> > > > +???????unsigned long tdata3;
> > > tdata1~tdata3 can be removed and written directly to scr during install
> > 
> > We need to write those values not only when we install triggers. We have
> > to rewrite them when we re-enable triggers after disabling or updating.
> > So I think it is more convenient to keep the whole state at hand.
> 
> when install, write directly to tdata1~data3
> when read, read from tdata1~tdata3, and OR the vs/vu/s/u bits in trig_status with tdata1  
> when disable, clear vs/vu/s/u in tdata1 
> when enable, write vs/vu/s/u in trig_state to tdata1

Ok for these four.

> when updat, Only need write recv to tdata2

Not for this one. You may need to update tdata1 as well. Besides, nothing
in spec requires hardware to support partial trigger updates on the fly.
On the other hand, we can read all CSRs, update some, and write back.
Ok, I agree that there is a value in saving quite a few extra bytes.
I will double-check this approach for v3.

Regards,
Sergey


From apatel at ventanamicro.com  Fri Dec 16 19:21:37 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Sat, 17 Dec 2022 08:51:37 +0530
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in priority save/restore helpers
In-Reply-To: <65db953b-fc55-7323-7c8b-754c9b8f6d85@sholland.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <87a63ufe4a.fsf@linux-m68k.org>
 <CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com> <65db953b-fc55-7323-7c8b-754c9b8f6d85@sholland.org>
Message-ID: <CAK9=C2Xqy21AqKZ=OJq=J=fGv1j0ySFoVNTjs8=U3FLrzZQ_zw@mail.gmail.com>

On Mon, Dec 12, 2022 at 12:10 PM Samuel Holland <samuel at sholland.org> wrote:
>
> On 12/11/22 04:18, Bin Meng wrote:
> > On Sun, Dec 11, 2022 at 6:08 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
> >>
> >> On Dez 11 2022, Bin Meng wrote:
> >>
> >>> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> >>> index 73d7788..4df9020 100644
> >>> --- a/lib/utils/irqchip/plic.c
> >>> +++ b/lib/utils/irqchip/plic.c
> >>> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
> >>>
> >>>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
> >>>  {
> >>> -     for (u32 i = 0; i < plic->num_src; i++)
> >>> +     for (u32 i = 1; i <= plic->num_src; i++)
> >>>               priority[i] = plic_get_priority(plic, i);
> >>
> >> That needs to adjust the index into the priority array.
> >
> > Does that help anything? It just confuses people more.
> >
> > I added function parameter descriptions in patch 2 to make it crystal
> > clear, that the priority array needs to include interrupt source 0.
>
> To me, it is more confusing that when I ask to save the priority for N
> sources, I need to allocate an array with >N elements. And leaving array
> element 0 unused wastes memory.

This can be a separate improvement patch.

Regards,
Anup

>
> Regards,
> Samuel
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From apatel at ventanamicro.com  Fri Dec 16 19:27:41 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Sat, 17 Dec 2022 08:57:41 +0530
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <a515eb8a-4f5e-68ff-327f-082d948362f3@sholland.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-2-bmeng@tinylab.org>
 <a515eb8a-4f5e-68ff-327f-082d948362f3@sholland.org>
Message-ID: <CAK9=C2Vmz2i5jAw-ij1bT-d96LKxH9T6jO_KQpj20u_Mkh77Qw@mail.gmail.com>

On Mon, Dec 12, 2022 at 12:34 PM Samuel Holland <samuel at sholland.org> wrote:
>
> On 12/11/22 00:54, Bin Meng wrote:
> > Currently the priority save/restore helpers writes/reads the provided
> > array using an index whose maximum value is determined by PLIC, which
> > potentially may disagree with the caller to these helpers.
> >
> > Add a parameter to ask the caller to provide the size limit of the
> > array to ensure no out-of-bound access happens.
> >
> > Signed-off-by: Bin Meng <bmeng at tinylab.org>
> >
> > ---
> >
> > Changes in v3:
> > - fix the size limit check
> > - move the size limit check to plic_priority_save/restore
> > - add parameter description to fdt_plic_priority_save/restore
> >
> > Changes in v2:
> > - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
> >
> >  include/sbi_utils/irqchip/fdt_irqchip_plic.h | 14 ++++++++++++--
> >  include/sbi_utils/irqchip/plic.h             |  5 +++--
> >  lib/utils/irqchip/fdt_irqchip_plic.c         |  8 ++++----
> >  lib/utils/irqchip/plic.c                     | 15 +++++++++++----
> >  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
> >  5 files changed, 32 insertions(+), 14 deletions(-)
> >
> > diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > index 98d4de5..d5b1c60 100644
> > --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> > @@ -9,9 +9,19 @@
> >
> >  #include <sbi/sbi_types.h>
> >
> > -void fdt_plic_priority_save(u8 *priority);
> > +/**
> > + * Save the PLIC priority state
> > + * @param priority pointer to the memory region for the saved priority
> > + * @param num size of the memory region including interrupt source 0
> > + */
> > +void fdt_plic_priority_save(u8 *priority, u32 num);
> >
> > -void fdt_plic_priority_restore(const u8 *priority);
> > +/**
> > + * Restore the PLIC priority state
> > + * @param priority pointer to the memory region for the saved priority
> > + * @param num size of the memory region including interrupt source 0
> > + */
> > +void fdt_plic_priority_restore(const u8 *priority, u32 num);
> >
> >  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
> >
> > diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> > index 48c24f0..38704a1 100644
> > --- a/include/sbi_utils/irqchip/plic.h
> > +++ b/include/sbi_utils/irqchip/plic.h
> > @@ -18,9 +18,10 @@ struct plic_data {
> >  };
> >
> >  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> > -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> > +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
> >
> > -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> > +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> > +                        u32 num);
> >
> >  void plic_context_save(const struct plic_data *plic, int context_id,
> >                      u32 *enable, u32 *threshold);
> > diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> > index fe08836..7d76c5b 100644
> > --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> > +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> > @@ -24,18 +24,18 @@ static struct plic_data plic[PLIC_MAX_NR];
> >  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
> >  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
> >
> > -void fdt_plic_priority_save(u8 *priority)
> > +void fdt_plic_priority_save(u8 *priority, u32 num)
> >  {
> >       struct plic_data *plic = plic_hartid2data[current_hartid()];
> >
> > -     plic_priority_save(plic, priority);
> > +     plic_priority_save(plic, priority, num);
> >  }
> >
> > -void fdt_plic_priority_restore(const u8 *priority)
> > +void fdt_plic_priority_restore(const u8 *priority, u32 num)
> >  {
> >       struct plic_data *plic = plic_hartid2data[current_hartid()];
> >
> > -     plic_priority_restore(plic, priority);
> > +     plic_priority_restore(plic, priority, num);
> >  }
> >
> >  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> > diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> > index 4df9020..dca5678 100644
> > --- a/lib/utils/irqchip/plic.c
> > +++ b/lib/utils/irqchip/plic.c
> > @@ -36,15 +36,22 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
> >       writel(val, plic_priority);
> >  }
> >
> > -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> > +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
> >  {
> > -     for (u32 i = 1; i <= plic->num_src; i++)
> > +     if (num > plic->num_src)
> > +             num = plic->num_src;
>
> This check is not really necessary. If the caller tries to save/restore
> more sources then actually exist, then the extra register writes will
> just be ignored. We already access extra bits by doing word accesses.
>
> For bounds checking, the only things that need to match are the array
> size and the loop. With your change to the loop condition, plic->num_src
> is not relevant at all anymore.

Okay, I will drop the bound checks at the time of merging this patch
since the motivation of this patch is mainly to avoid out-of-bound
access to the array passed by the caller.

If required, let's have a separate patch for this.

Regards,
Anup

>
> Regards,
> Samuel
>
> > +
> > +     for (u32 i = 1; i <= num; i++)
> >               priority[i] = plic_get_priority(plic, i);
> >  }
> >
> > -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> > +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> > +                        u32 num)
> >  {
> > -     for (u32 i = 1; i <= plic->num_src; i++)
> > +     if (num > plic->num_src)
> > +             num = plic->num_src;
> > +
> > +     for (u32 i = 1; i <= num; i++)
> >               plic_set_priority(plic, i, priority[i]);
> >  }
> >
> > diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> > index 18d330d..1f27575 100644
> > --- a/platform/generic/allwinner/sun20i-d1.c
> > +++ b/platform/generic/allwinner/sun20i-d1.c
> > @@ -79,13 +79,13 @@ static u32 plic_threshold;
> >  static void sun20i_d1_plic_save(void)
> >  {
> >       fdt_plic_context_save(true, plic_sie, &plic_threshold);
> > -     fdt_plic_priority_save(plic_priority);
> > +     fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
> >  }
> >
> >  static void sun20i_d1_plic_restore(void)
> >  {
> >       thead_plic_restore();
> > -     fdt_plic_priority_restore(plic_priority);
> > +     fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> >       fdt_plic_context_restore(true, plic_sie, plic_threshold);
> >  }
> >
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec 16 19:39:03 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:09:03 +0530
Subject: [PATCH v3 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in context save/restore helpers
In-Reply-To: <17261da5-b988-f1f2-2a39-34cd4c0321ae@sholland.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-5-bmeng@tinylab.org>
 <17261da5-b988-f1f2-2a39-34cd4c0321ae@sholland.org>
Message-ID: <CAAhSdy0G+E8ynXNsZP4Y4bP33Vz7XpJiS9UnoBYN62Zyp6CBMg@mail.gmail.com>

On Mon, Dec 12, 2022 at 12:30 PM Samuel Holland <samuel at sholland.org> wrote:
>
> On 12/11/22 00:54, Bin Meng wrote:
> > Currently the context save/restore helpers writes/reads the provided
> > array using an index whose maximum value is determined by PLIC, which
> > potentially may disagree with the caller to these helpers.
> >
> > Add a parameter to ask the caller to provide the size limit of the
> > array to ensure no out-of-bound access happens.
> >
> > Signed-off-by: Bin Meng <bmeng at tinylab.org>
> >
> > ---
> >
> > Changes in v3:
> > - move the size limit check to plic_context_save/restore
> >
> > Changes in v2:
> > - new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
> >
> >  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
> >  include/sbi_utils/irqchip/plic.h             |  4 ++--
> >  lib/utils/irqchip/fdt_irqchip_plic.c         |  9 +++++----
> >  lib/utils/irqchip/plic.c                     | 14 ++++++++++----
> >  platform/generic/allwinner/sun20i-d1.c       |  5 +++--
> >  5 files changed, 23 insertions(+), 14 deletions(-)
> >
> [...]
> > diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> > index 1f27575..1da9e5b 100644
> > --- a/platform/generic/allwinner/sun20i-d1.c
> > +++ b/platform/generic/allwinner/sun20i-d1.c
> > @@ -78,7 +78,7 @@ static u32 plic_threshold;
> >
> >  static void sun20i_d1_plic_save(void)
> >  {
> > -     fdt_plic_context_save(true, plic_sie, &plic_threshold);
> > +     fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
>
> While the actual value ends up being the same, you should update the
> definition of PLIC_IE_WORDS to use the same formula used elsewhere.

Let's have a separate patch for this.

Regards,
Anup

>
> Regards,
> Samuel
>
> >       fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
> >  }
> >
> > @@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
> >  {
> >       thead_plic_restore();
> >       fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> > -     fdt_plic_context_restore(true, plic_sie, plic_threshold);
> > +     fdt_plic_context_restore(true, plic_sie, plic_threshold,
> > +                              PLIC_IE_WORDS);
> >  }
> >
> >  /*
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec 16 19:40:03 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:10:03 +0530
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in priority save/restore helpers
In-Reply-To: <20221211065424.806478-1-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org>
Message-ID: <CAAhSdy1RtGeOVHE3gKN=09eNyvHu-FYYg-kri5r8oioVnC313A@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:24 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> Interrupt source 0 is reserved. Hence the irq should start from 1.
>
> Fixes: 2b79b694a805 ("lib: irqchip/plic: Add priority save/restore helpers")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>
> (no changes since v1)
>
>  lib/utils/irqchip/plic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 73d7788..4df9020 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>
>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>  {
> -       for (u32 i = 0; i < plic->num_src; i++)
> +       for (u32 i = 1; i <= plic->num_src; i++)
>                 priority[i] = plic_get_priority(plic, i);
>  }
>
>  void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
>  {
> -       for (u32 i = 0; i < plic->num_src; i++)
> +       for (u32 i = 1; i <= plic->num_src; i++)
>                 plic_set_priority(plic, i, priority[i]);
>  }
>
> --
> 2.34.1
>


From anup at brainfault.org  Fri Dec 16 19:40:16 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:10:16 +0530
Subject: [PATCH v3 2/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <20221211065424.806478-2-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-2-bmeng@tinylab.org>
Message-ID: <CAAhSdy3z_D56BDo47_MH-sJn+zqB8xsL4rxjKxBduyFwLxmmHg@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:25 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the priority save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> ---
>
> Changes in v3:
> - fix the size limit check
> - move the size limit check to plic_priority_save/restore
> - add parameter description to fdt_plic_priority_save/restore
>
> Changes in v2:
> - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h | 14 ++++++++++++--
>  include/sbi_utils/irqchip/plic.h             |  5 +++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  8 ++++----
>  lib/utils/irqchip/plic.c                     | 15 +++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  4 ++--
>  5 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 98d4de5..d5b1c60 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -9,9 +9,19 @@
>
>  #include <sbi/sbi_types.h>
>
> -void fdt_plic_priority_save(u8 *priority);
> +/**
> + * Save the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_save(u8 *priority, u32 num);
>
> -void fdt_plic_priority_restore(const u8 *priority);
> +/**
> + * Restore the PLIC priority state
> + * @param priority pointer to the memory region for the saved priority
> + * @param num size of the memory region including interrupt source 0
> + */
> +void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 48c24f0..38704a1 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -18,9 +18,10 @@ struct plic_data {
>  };
>
>  /* So far, priorities on all consumers of these functions fit in 8 bits. */
> -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
>                        u32 *enable, u32 *threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index fe08836..7d76c5b 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -24,18 +24,18 @@ static struct plic_data plic[PLIC_MAX_NR];
>  static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
>  static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
>
> -void fdt_plic_priority_save(u8 *priority)
> +void fdt_plic_priority_save(u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_save(plic, priority);
> +       plic_priority_save(plic, priority, num);
>  }
>
> -void fdt_plic_priority_restore(const u8 *priority)
> +void fdt_plic_priority_restore(const u8 *priority, u32 num)
>  {
>         struct plic_data *plic = plic_hartid2data[current_hartid()];
>
> -       plic_priority_restore(plic, priority);
> +       plic_priority_restore(plic, priority, num);
>  }
>
>  void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 4df9020..dca5678 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -36,15 +36,22 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>         writel(val, plic_priority);
>  }
>
> -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       if (num > plic->num_src)
> +               num = plic->num_src;
> +
> +       for (u32 i = 1; i <= num; i++)
>                 priority[i] = plic_get_priority(plic, i);
>  }
>
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +                          u32 num)
>  {
> -       for (u32 i = 1; i <= plic->num_src; i++)
> +       if (num > plic->num_src)
> +               num = plic->num_src;
> +
> +       for (u32 i = 1; i <= num; i++)
>                 plic_set_priority(plic, i, priority[i]);
>  }
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 18d330d..1f27575 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>  static void sun20i_d1_plic_save(void)
>  {
>         fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -       fdt_plic_priority_save(plic_priority);
> +       fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
>  static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
> -       fdt_plic_priority_restore(plic_priority);
> +       fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>         fdt_plic_context_restore(true, plic_sie, plic_threshold);
>  }
>
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec 16 19:40:33 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:10:33 +0530
Subject: [PATCH v3 3/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in plic_context_init()
In-Reply-To: <20221211065424.806478-3-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-3-bmeng@tinylab.org>
Message-ID: <CAAhSdy0OcHsWfvfa6bS=-tVMM1xxoVaEBCO52jyNWsJfj+=HRQ@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:24 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> The number of interrupt enable register in words was once correct,
> but was wrongly changed to have an off-by-one error since
> commit 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function").
>
> Fixes: 8c362e7d065e ("lib: irqchip/plic: Factor out a context init function")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init()
>
>  lib/utils/irqchip/plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index dca5678..568f814 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -127,7 +127,7 @@ int plic_context_init(const struct plic_data *plic, int context_id,
>         if (!plic || context_id < 0)
>                 return SBI_EINVAL;
>
> -       ie_words = (plic->num_src + 31) / 32;
> +       ie_words = plic->num_src / 32 + 1;
>         ie_value = enable ? 0xffffffffU : 0U;
>
>         for (u32 i = 0; i < ie_words; i++)
> --
> 2.34.1
>


From anup at brainfault.org  Fri Dec 16 19:40:52 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:10:52 +0530
Subject: [PATCH v3 4/5] lib: utils/irqchip: plic: Fix the off-by-one error
 in context save/restore helpers
In-Reply-To: <20221211065424.806478-4-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-4-bmeng@tinylab.org>
Message-ID: <CAAhSdy3WMZRcC__EFbLxXZQL9cSMDWN757rAp9LeFPvyGMZSdA@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:24 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> plic->num_src holds the number of interrupt sources without interrupt
> source 0 but the interrupt enable register includes a bit for the
> interrupt source 0 in the first word.
>
> Fixes: 415ecf28f7ad ("lib: irqchip/plic: Add context save/restore helpers")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers
>
>  lib/utils/irqchip/plic.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 568f814..b152bb7 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -100,7 +100,7 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
>  void plic_context_save(const struct plic_data *plic, int context_id,
>                        u32 *enable, u32 *threshold)
>  {
> -       u32 ie_words = (plic->num_src + 31) / 32;
> +       u32 ie_words = plic->num_src / 32 + 1;
>
>         for (u32 i = 0; i < ie_words; i++)
>                 enable[i] = plic_get_ie(plic, context_id, i);
> @@ -111,7 +111,7 @@ void plic_context_save(const struct plic_data *plic, int context_id,
>  void plic_context_restore(const struct plic_data *plic, int context_id,
>                           const u32 *enable, u32 threshold)
>  {
> -       u32 ie_words = (plic->num_src + 31) / 32;
> +       u32 ie_words = plic->num_src / 32 + 1;
>
>         for (u32 i = 0; i < ie_words; i++)
>                 plic_set_ie(plic, context_id, i, enable[i]);
> --
> 2.34.1
>


From anup at brainfault.org  Fri Dec 16 19:41:10 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 09:11:10 +0530
Subject: [PATCH v3 5/5] lib: utils/irqchip: plic: Ensure no out-of-bound
 access in context save/restore helpers
In-Reply-To: <20221211065424.806478-5-bmeng@tinylab.org>
References: <20221211065424.806478-1-bmeng@tinylab.org> <20221211065424.806478-5-bmeng@tinylab.org>
Message-ID: <CAAhSdy1X_Zr1D1tACg4NiL076mZhGMF_fOSQXkwPg-gJDVEvbw@mail.gmail.com>

On Sun, Dec 11, 2022 at 12:25 PM Bin Meng <bmeng at tinylab.org> wrote:
>
> Currently the context save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
>
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

>
> ---
>
> Changes in v3:
> - move the size limit check to plic_context_save/restore
>
> Changes in v2:
> - new patch: lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers
>
>  include/sbi_utils/irqchip/fdt_irqchip_plic.h |  5 +++--
>  include/sbi_utils/irqchip/plic.h             |  4 ++--
>  lib/utils/irqchip/fdt_irqchip_plic.c         |  9 +++++----
>  lib/utils/irqchip/plic.c                     | 14 ++++++++++----
>  platform/generic/allwinner/sun20i-d1.c       |  5 +++--
>  5 files changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index d5b1c60..df645dd 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -23,9 +23,10 @@ void fdt_plic_priority_save(u8 *priority, u32 num);
>   */
>  void fdt_plic_priority_restore(const u8 *priority, u32 num);
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num);
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold);
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num);
>
>  void thead_plic_restore(void);
>
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 38704a1..112a714 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -24,10 +24,10 @@ void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
>                            u32 num);
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold);
> +                      u32 *enable, u32 *threshold, u32 num);
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold);
> +                         const u32 *enable, u32 threshold, u32 num);
>
>  int plic_context_init(const struct plic_data *plic, int context_id,
>                       bool enable, u32 threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index 7d76c5b..c54f45c 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -38,22 +38,23 @@ void fdt_plic_priority_restore(const u8 *priority, u32 num)
>         plic_priority_restore(plic, priority, num);
>  }
>
> -void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> +void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold, u32 num)
>  {
>         u32 hartid = current_hartid();
>
>         plic_context_save(plic_hartid2data[hartid],
>                           plic_hartid2context[hartid][smode],
> -                         enable, threshold);
> +                         enable, threshold, num);
>  }
>
> -void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold)
> +void fdt_plic_context_restore(bool smode, const u32 *enable, u32 threshold,
> +                             u32 num)
>  {
>         u32 hartid = current_hartid();
>
>         plic_context_restore(plic_hartid2data[hartid],
>                              plic_hartid2context[hartid][smode],
> -                            enable, threshold);
> +                            enable, threshold, num);
>  }
>
>  static int irqchip_plic_warm_init(void)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index b152bb7..8089a0b 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -98,22 +98,28 @@ static void plic_set_ie(const struct plic_data *plic, u32 cntxid,
>  }
>
>  void plic_context_save(const struct plic_data *plic, int context_id,
> -                      u32 *enable, u32 *threshold)
> +                      u32 *enable, u32 *threshold, u32 num)
>  {
>         u32 ie_words = plic->num_src / 32 + 1;
>
> -       for (u32 i = 0; i < ie_words; i++)
> +       if (num > ie_words)
> +               num = ie_words;
> +
> +       for (u32 i = 0; i < num; i++)
>                 enable[i] = plic_get_ie(plic, context_id, i);
>
>         *threshold = plic_get_thresh(plic, context_id);
>  }
>
>  void plic_context_restore(const struct plic_data *plic, int context_id,
> -                         const u32 *enable, u32 threshold)
> +                         const u32 *enable, u32 threshold, u32 num)
>  {
>         u32 ie_words = plic->num_src / 32 + 1;
>
> -       for (u32 i = 0; i < ie_words; i++)
> +       if (num > ie_words)
> +               num = ie_words;
> +
> +       for (u32 i = 0; i < num; i++)
>                 plic_set_ie(plic, context_id, i, enable[i]);
>
>         plic_set_thresh(plic, context_id, threshold);
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 1f27575..1da9e5b 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -78,7 +78,7 @@ static u32 plic_threshold;
>
>  static void sun20i_d1_plic_save(void)
>  {
> -       fdt_plic_context_save(true, plic_sie, &plic_threshold);
> +       fdt_plic_context_save(true, plic_sie, &plic_threshold, PLIC_IE_WORDS);
>         fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
>  }
>
> @@ -86,7 +86,8 @@ static void sun20i_d1_plic_restore(void)
>  {
>         thead_plic_restore();
>         fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
> -       fdt_plic_context_restore(true, plic_sie, plic_threshold);
> +       fdt_plic_context_restore(true, plic_sie, plic_threshold,
> +                                PLIC_IE_WORDS);
>  }
>
>  /*
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec 16 21:19:11 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 10:49:11 +0530
Subject: [PATCH v3 0/3] generic/starfive: Enable Starfive JH7110 platform
 preferred boot hart implementation
In-Reply-To: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
Message-ID: <CAAhSdy1vEvSepUwe6ZnXHLKFSDikyjoa9CR=KYboEmbS3tsyQw@mail.gmail.com>

On Mon, Dec 12, 2022 at 11:11 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> This is patchset to enable Starfive JH7110 platform preferred boot hart implementation.
>
> Anup Patel (2):
>   lib: sbi: Allow platform to influence cold boot HART selection
>   platform: generic: Allow platform_override to select cold boot HART
>
> Wei Liang Lim (1):
>   generic/starfive: Add Starfive JH7110 platform implementation

Applied this series to the riscv/opensbi repo.

Thanks,
Anup

>
>  include/sbi/sbi_platform.h                   | 20 +++++++++++++++
>  lib/sbi/sbi_init.c                           |  7 +++--
>  platform/generic/Kconfig                     |  4 +++
>  platform/generic/configs/defconfig           |  1 +
>  platform/generic/include/platform_override.h |  1 +
>  platform/generic/platform.c                  |  9 +++++++
>  platform/generic/starfive/jh7110.c           | 27 ++++++++++++++++++++
>  platform/generic/starfive/objects.mk         |  6 +++++
>  8 files changed, 73 insertions(+), 2 deletions(-)
>  create mode 100644 platform/generic/starfive/jh7110.c
>  create mode 100644 platform/generic/starfive/objects.mk
>
> --
> 2.25.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From jrtc27 at jrtc27.com  Fri Dec 16 21:21:29 2022
From: jrtc27 at jrtc27.com (Jessica Clarke)
Date: Sat, 17 Dec 2022 05:21:29 +0000
Subject: [PATCH v3 0/3] generic/starfive: Enable Starfive JH7110 platform
 preferred boot hart implementation
In-Reply-To: <CAAhSdy1vEvSepUwe6ZnXHLKFSDikyjoa9CR=KYboEmbS3tsyQw@mail.gmail.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
 <CAAhSdy1vEvSepUwe6ZnXHLKFSDikyjoa9CR=KYboEmbS3tsyQw@mail.gmail.com>
Message-ID: <EB6573CE-04BD-4FD5-B676-8DA41559855C@jrtc27.com>

On 17 Dec 2022, at 05:19, Anup Patel <anup at brainfault.org> wrote:
> 
> On Mon, Dec 12, 2022 at 11:11 AM Wei Liang Lim
> <weiliang.lim at starfivetech.com> wrote:
>> 
>> This is patchset to enable Starfive JH7110 platform preferred boot hart implementation.
>> 
>> Anup Patel (2):
>>  lib: sbi: Allow platform to influence cold boot HART selection
>>  platform: generic: Allow platform_override to select cold boot HART
>> 
>> Wei Liang Lim (1):
>>  generic/starfive: Add Starfive JH7110 platform implementation
> 
> Applied this series to the riscv/opensbi repo.

Why? I had objections and they said they?d do a v4.

Jess

> Thanks,
> Anup
> 
>> 
>> include/sbi/sbi_platform.h                   | 20 +++++++++++++++
>> lib/sbi/sbi_init.c                           |  7 +++--
>> platform/generic/Kconfig                     |  4 +++
>> platform/generic/configs/defconfig           |  1 +
>> platform/generic/include/platform_override.h |  1 +
>> platform/generic/platform.c                  |  9 +++++++
>> platform/generic/starfive/jh7110.c           | 27 ++++++++++++++++++++
>> platform/generic/starfive/objects.mk         |  6 +++++
>> 8 files changed, 73 insertions(+), 2 deletions(-)
>> create mode 100644 platform/generic/starfive/jh7110.c
>> create mode 100644 platform/generic/starfive/objects.mk
>> 
>> --
>> 2.25.1
>> 
>> 
>> --
>> opensbi mailing list
>> opensbi at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/opensbi
> 
> -- 
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



From anup at brainfault.org  Fri Dec 16 21:29:38 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 10:59:38 +0530
Subject: [PATCH v2 0/3] T-Head C9xx CLINT support
In-Reply-To: <20221212082238.265281-1-uwu@icenowy.me>
References: <20221212082238.265281-1-uwu@icenowy.me>
Message-ID: <CAAhSdy3BpAsg=UsxBbFBu1J19F2NR0Hf5Qf4nS61jBtY=R-TxA@mail.gmail.com>

On Mon, Dec 12, 2022 at 1:53 PM Icenowy Zheng <uwu at icenowy.me> wrote:
>
> This patchset tries to add support for T-Head C9xx's CLINT to OpenSBI.
>
> For MSWI part, the T-Head CLINT is fully compatible with the SiFive one,
> so it's just simply adding a compatible string.
>
> For MTIMER part, it's first needed to implement a quirk for
> MTIME-less timer (thus only MTIMECMP is present), then the compatible
> string is added and bound to the quirk.
>
> To instantiate such a T-Head flavored CLINT via DT, this patchset
> depends on DT bindings declared in [1].
>
> [1] https://www.spinics.net/lists/kernel/msg4597447.html
>
> Icenowy Zheng (3):
>   lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
>   lib: utils/timer: mtimer: add a quirk for lacking mtime register
>   lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible

Applied this series to the riscv/opensbi repo.

Thanks,
Anup

>
>  lib/utils/ipi/fdt_ipi_mswi.c       |  1 +
>  lib/utils/timer/aclint_mtimer.c    | 11 ++++++---
>  lib/utils/timer/fdt_timer_mtimer.c | 36 +++++++++++++++++++++---------
>  3 files changed, 35 insertions(+), 13 deletions(-)
>
> --
> 2.38.1
>


From anup at brainfault.org  Fri Dec 16 21:33:44 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 11:03:44 +0530
Subject: [PATCH v3 0/3] generic/starfive: Enable Starfive JH7110 platform
 preferred boot hart implementation
In-Reply-To: <EB6573CE-04BD-4FD5-B676-8DA41559855C@jrtc27.com>
References: <20221212054018.169408-1-weiliang.lim@starfivetech.com>
 <CAAhSdy1vEvSepUwe6ZnXHLKFSDikyjoa9CR=KYboEmbS3tsyQw@mail.gmail.com> <EB6573CE-04BD-4FD5-B676-8DA41559855C@jrtc27.com>
Message-ID: <CAAhSdy1ZPrpUqPvfqdyTQtEg5-sWjh-YNh8U8=C0fVSK75H85A@mail.gmail.com>

On Sat, Dec 17, 2022 at 10:51 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>
> On 17 Dec 2022, at 05:19, Anup Patel <anup at brainfault.org> wrote:
> >
> > On Mon, Dec 12, 2022 at 11:11 AM Wei Liang Lim
> > <weiliang.lim at starfivetech.com> wrote:
> >>
> >> This is patchset to enable Starfive JH7110 platform preferred boot hart implementation.
> >>
> >> Anup Patel (2):
> >>  lib: sbi: Allow platform to influence cold boot HART selection
> >>  platform: generic: Allow platform_override to select cold boot HART
> >>
> >> Wei Liang Lim (1):
> >>  generic/starfive: Add Starfive JH7110 platform implementation
> >
> > Applied this series to the riscv/opensbi repo.
>
> Why? I had objections and they said they?d do a v4.

Ahh, my bad. I overlooked comments on the PATCH3.

I have removed these patches from riscv/opensbi and I will
re-consider it after OpenSBI v1.2 release.

Regards,
Anup

>
> Jess
>
> > Thanks,
> > Anup
> >
> >>
> >> include/sbi/sbi_platform.h                   | 20 +++++++++++++++
> >> lib/sbi/sbi_init.c                           |  7 +++--
> >> platform/generic/Kconfig                     |  4 +++
> >> platform/generic/configs/defconfig           |  1 +
> >> platform/generic/include/platform_override.h |  1 +
> >> platform/generic/platform.c                  |  9 +++++++
> >> platform/generic/starfive/jh7110.c           | 27 ++++++++++++++++++++
> >> platform/generic/starfive/objects.mk         |  6 +++++
> >> 8 files changed, 73 insertions(+), 2 deletions(-)
> >> create mode 100644 platform/generic/starfive/jh7110.c
> >> create mode 100644 platform/generic/starfive/objects.mk
> >>
> >> --
> >> 2.25.1
> >>
> >>
> >> --
> >> opensbi mailing list
> >> opensbi at lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/opensbi
> >
> > --
> > opensbi mailing list
> > opensbi at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi
>


From anup at brainfault.org  Fri Dec 16 21:41:58 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 17 Dec 2022 11:11:58 +0530
Subject: Upcoming OpenSBI v1.2 release
Message-ID: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>

Hi All,

We are close to the OpenSBI v1.2 release. I plan to complete this
release before the end of next week (i.e. 24th December 2022).

Next week, I won't be merging patches unless it's a critical fix.
Also, I request everyone to test the latest OpenSBI on their RISC-V
platforms.

Thanks & Regards,
Anup


From schwab at linux-m68k.org  Sat Dec 17 04:50:45 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Sat, 17 Dec 2022 13:50:45 +0100
Subject: [PATCH v3 1/5] lib: utils/irqchip: plic: Fix the off-by-one
 error in priority save/restore helpers
In-Reply-To: <CAK9=C2Xqy21AqKZ=OJq=J=fGv1j0ySFoVNTjs8=U3FLrzZQ_zw@mail.gmail.com>
	(Anup Patel's message of "Sat, 17 Dec 2022 08:51:37 +0530")
References: <20221211065424.806478-1-bmeng@tinylab.org>
	<87a63ufe4a.fsf@linux-m68k.org>
	<CAEUhbmWJCB=i7OkeCMvtz0ut9xcCjiO8fTQ379GZWU=vHuzhwg@mail.gmail.com>
	<65db953b-fc55-7323-7c8b-754c9b8f6d85@sholland.org>
	<CAK9=C2Xqy21AqKZ=OJq=J=fGv1j0ySFoVNTjs8=U3FLrzZQ_zw@mail.gmail.com>
Message-ID: <87cz8iry6y.fsf@igel.home>

On Dez 17 2022, Anup Patel wrote:

> On Mon, Dec 12, 2022 at 12:10 PM Samuel Holland <samuel at sholland.org> wrote:
>>
>> On 12/11/22 04:18, Bin Meng wrote:
>> > On Sun, Dec 11, 2022 at 6:08 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>> >>
>> >> On Dez 11 2022, Bin Meng wrote:
>> >>
>> >>> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
>> >>> index 73d7788..4df9020 100644
>> >>> --- a/lib/utils/irqchip/plic.c
>> >>> +++ b/lib/utils/irqchip/plic.c
>> >>> @@ -38,13 +38,13 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>> >>>
>> >>>  void plic_priority_save(const struct plic_data *plic, u8 *priority)
>> >>>  {
>> >>> -     for (u32 i = 0; i < plic->num_src; i++)
>> >>> +     for (u32 i = 1; i <= plic->num_src; i++)
>> >>>               priority[i] = plic_get_priority(plic, i);
>> >>
>> >> That needs to adjust the index into the priority array.
>> >
>> > Does that help anything? It just confuses people more.
>> >
>> > I added function parameter descriptions in patch 2 to make it crystal
>> > clear, that the priority array needs to include interrupt source 0.
>>
>> To me, it is more confusing that when I ask to save the priority for N
>> sources, I need to allocate an array with >N elements. And leaving array
>> element 0 unused wastes memory.
>
> This can be a separate improvement patch.

It is a bug fix, not just an improvement.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From weiliang.lim at starfivetech.com  Mon Dec 19 19:41:02 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Tue, 20 Dec 2022 11:41:02 +0800
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
Message-ID: <20221220034102.150151-4-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 ++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 57 ++++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 +++
 4 files changed, 68 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 62c7a2d..47c10e5 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 47fca95..4b0842e 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..5d3ab6f
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,57 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <libfdt.h>
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static bool hart_cold_booted = FALSE;
+
+static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	const fdt32_t *val;
+	int len, coff;
+
+	if (hart_cold_booted)
+		return FALSE;
+
+	void *fdt = fdt_get_address();
+
+	coff = fdt_path_offset(fdt, "/chosen");
+	if (-1 < coff) {
+		val = fdt_getprop(fdt, coff, "boot-hart", &len);
+		if (val && len) {
+			u32 selected_hartid = (u32) fdt32_to_cpu(*val);
+			return (selected_hartid == hartid);
+		}
+	}
+
+	return TRUE;
+}
+
+static int starfive_jh7110_early_init(bool cold_boot,
+				   const struct fdt_match *match)
+{
+	if (cold_boot)
+		hart_cold_booted = TRUE;
+
+	return 0;
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.early_init = starfive_jh7110_early_init,
+	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From weiliang.lim at starfivetech.com  Mon Dec 19 19:40:59 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Tue, 20 Dec 2022 11:40:59 +0800
Subject: [PATCH v4 0/3] generic/starfive: Enable Starfive JH7110 platform preferred cold boot HART implementation
Message-ID: <20221220034102.150151-1-weiliang.lim@starfivetech.com>

This is patchset to enable Starfive JH7110 platform preferred cold boot HART implementation.
User has the option to specify preferred cold boot HART in the device tree. If unspecified, the existing lottery mechanism will be used.

Anup Patel (2):
  lib: sbi: Allow platform to influence cold boot HART selection
  platform: generic: Allow platform_override to select cold boot HART

Wei Liang Lim (1):
  generic/starfive: Add Starfive JH7110 platform implementation

 include/sbi/sbi_platform.h                   | 20 +++++++
 lib/sbi/sbi_init.c                           |  7 ++-
 platform/generic/Kconfig                     |  4 ++
 platform/generic/configs/defconfig           |  1 +
 platform/generic/include/platform_override.h |  1 +
 platform/generic/platform.c                  |  9 ++++
 platform/generic/starfive/jh7110.c           | 57 ++++++++++++++++++++
 platform/generic/starfive/objects.mk         |  6 +++
 8 files changed, 103 insertions(+), 2 deletions(-)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

-- 
2.25.1



From weiliang.lim at starfivetech.com  Mon Dec 19 19:41:00 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Tue, 20 Dec 2022 11:41:00 +0800
Subject: [PATCH v4 1/3] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
Message-ID: <20221220034102.150151-2-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..566eee3 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return TRUE if HART is allowed to do cold boot and FALSE otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return TRUE;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d4902d9 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = TRUE;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Mon Dec 19 19:41:01 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Tue, 20 Dec 2022 11:41:01 +0800
Subject: [PATCH v4 2/3] platform: generic: Allow platform_override to select cold boot HART
In-Reply-To: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
Message-ID: <20221220034102.150151-3-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..16aa4f3 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return TRUE;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From wxjstz at 126.com  Tue Dec 20 02:28:40 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 20 Dec 2022 18:28:40 +0800
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <20221220034102.150151-4-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
	 <20221220034102.150151-4-weiliang.lim@starfivetech.com>
Message-ID: <8ed3bd53b96841953b8679fbb7f585ad85d5056a.camel@126.com>

? 2022-12-20???? 11:41 +0800?Wei Liang Lim???
> Add Starfive JH7110 platform implementation
> 
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
> ?platform/generic/Kconfig???????????? |? 4 ++
> ?platform/generic/configs/defconfig?? |? 1 +
> ?platform/generic/starfive/jh7110.c?? | 57 ++++++++++++++++++++++++++++
> ?platform/generic/starfive/objects.mk |? 6 +++
> ?4 files changed, 68 insertions(+)
> ?create mode 100644 platform/generic/starfive/jh7110.c
> ?create mode 100644 platform/generic/starfive/objects.mk
> 
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 62c7a2d..47c10e5 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> ????????depends on FDT_RESET && FDT_I2C
> ????????default n
> ?
> +config PLATFORM_STARFIVE_JH7110
> +???????bool "StarFive JH7110 support"
> +???????default n
> +
> ?endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 47fca95..4b0842e 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> ?CONFIG_PLATFORM_RENESAS_RZFIVE=y
> ?CONFIG_PLATFORM_SIFIVE_FU540=y
> ?CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_STARFIVE_JH7110=y
> ?CONFIG_FDT_GPIO=y
> ?CONFIG_FDT_GPIO_SIFIVE=y
> ?CONFIG_FDT_I2C=y
> diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
> new file mode 100644
> index 0000000..5d3ab6f
> --- /dev/null
> +++ b/platform/generic/starfive/jh7110.c
> @@ -0,0 +1,57 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 StarFive
> + *
> + * Authors:
> + *?? Wei Liang Lim <weiliang.lim at starfivetech.com>
> + */
> +
> +#include <libfdt.h>
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static bool hart_cold_booted = FALSE;
hart_cold_booted is not necessary, because coldboot_lottery will be
1 after the first boot, which will guarantee that the second
init_coldboot will not be executed
> +
> +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> +????????????????????????????????? const struct fdt_match *match)
> +{
> +???????const fdt32_t *val;
> +???????int len, coff;
> +
> +???????if (hart_cold_booted)
> +???????????????return FALSE;
> +
> +???????void *fdt = fdt_get_address();
> +
> +???????coff = fdt_path_offset(fdt, "/chosen");
> +???????if (-1 < coff) {
> +???????????????val = fdt_getprop(fdt, coff, "boot-hart", &len);
> +???????????????if (val && len) {
> +???????????????????????u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> +???????????????????????return (selected_hartid == hartid);
> +???????????????}
> +???????}
You can define selected_hartid as a static variable with an initial
value of -1, and get it from fdt when the initial value is -1. In this
way, there is no need to analyze fdt every time.

Regards,
Xiang W
> +
> +???????return TRUE;
> +}
> +

> +static int starfive_jh7110_early_init(bool cold_boot,
> +????????????????????????????????? const struct fdt_match *match)
> +{
> +???????if (cold_boot)
> +???????????????hart_cold_booted = TRUE;
> +
> +???????return 0;
> +}
> +
> +static const struct fdt_match starfive_jh7110_match[] = {
> +???????{ .compatible = "starfive,jh7110" },
> +???????{ },
> +};
> +
> +const struct platform_override starfive_jh7110 = {
> +???????.match_table = starfive_jh7110_match,
> +???????.early_init = starfive_jh7110_early_init,
> +???????.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> +};
> diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
> new file mode 100644
> index 0000000..0b900fb
> --- /dev/null
> +++ b/platform/generic/starfive/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
> -- 
> 2.25.1
> 
> 




From wxjstz at 126.com  Tue Dec 20 02:29:19 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 20 Dec 2022 18:29:19 +0800
Subject: [PATCH v4 1/3] lib: sbi: Allow platform to influence cold boot
 HART selection
In-Reply-To: <20221220034102.150151-2-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
	 <20221220034102.150151-2-weiliang.lim@starfivetech.com>
Message-ID: <7a8bdc8bac2df7b357f01e3334757543a27967ba.camel@126.com>

? 2022-12-20???? 11:41 +0800?Wei Liang Lim???
> From: Anup Patel <apatel at ventanamicro.com>
> 
> We add an optional cold_boot_allowed() platform callback which allows
> platform support to decide which HARTs can do cold boot initialization.
> 
> If this platform callback is not available then any HART can do cold
> boot initialization.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
> ?lib/sbi/sbi_init.c???????? |? 7 +++++--
> ?2 files changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 722f27a..566eee3 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -65,6 +65,9 @@ enum sbi_platform_features {
> ?
> ?/** Platform functions */
> ?struct sbi_platform_operations {
> +???????/* Check if specified HART is allowed to do cold boot */
> +???????bool (*cold_boot_allowed)(u32 hartid);
> +
> ????????/* Platform nascent initialization */
> ????????int (*nascent_init)(void);
> ?
> @@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
> ????????return FALSE;
> ?}
> ?
> +/**
> + * Check whether given HART is allowed to do cold boot
> + *
> + * @param plat pointer to struct sbi_platform
> + * @param hartid HART ID
> + *
> + * @return TRUE if HART is allowed to do cold boot and FALSE otherwise
> + */
> +static inline bool sbi_platform_cold_boot_allowed(
> +???????????????????????????????????????const struct sbi_platform *plat,
> +???????????????????????????????????????u32 hartid)
> +{
> +???????if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
> +???????????????return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
> +???????return TRUE;
> +}
> +
> ?/**
> ? * Nascent (very early) initialization for current HART
> ? *
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..d4902d9 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
> ???????? * HARTs which satisfy above condition.
> ???????? */
> ?
> -???????if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> -???????????????coldboot = TRUE;
> +???????if (sbi_platform_cold_boot_allowed(plat, hartid)) {
> +???????????????if (next_mode_supported &&
> +?????????????????? atomic_xchg(&coldboot_lottery, 1) == 0)
> +???????????????????????coldboot = TRUE;
> +???????}
> ?
> ????????/*
> ???????? * Do platform specific nascent (very early) initialization so
> -- 
> 2.25.1
> 
> 




From wxjstz at 126.com  Tue Dec 20 02:29:43 2022
From: wxjstz at 126.com (Xiang W)
Date: Tue, 20 Dec 2022 18:29:43 +0800
Subject: [PATCH v4 2/3] platform: generic: Allow platform_override to
 select cold boot HART
In-Reply-To: <20221220034102.150151-3-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
	 <20221220034102.150151-3-weiliang.lim@starfivetech.com>
Message-ID: <5969a072cc8b54de6a33c2730406e42cafef44ee.camel@126.com>

? 2022-12-20???? 11:41 +0800?Wei Liang Lim???
> From: Anup Patel <apatel at ventanamicro.com>
> 
> We add a generic platform override callback to allow platform specific
> selection of cold boot HART.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
Reviewed-by: Xiang W <wxjstz at 126.com>
> ---
> ?platform/generic/include/platform_override.h | 1 +
> ?platform/generic/platform.c????????????????? | 9 +++++++++
> ?2 files changed, 10 insertions(+)
> 
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index 7f1558d..21354e9 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -18,6 +18,7 @@ struct platform_override {
> ????????const struct fdt_match *match_table;
> ????????u64 (*features)(const struct fdt_match *match);
> ????????u64 (*tlbr_flush_limit)(const struct fdt_match *match);
> +???????bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
> ????????int (*early_init)(bool cold_boot, const struct fdt_match *match);
> ????????int (*final_init)(bool cold_boot, const struct fdt_match *match);
> ????????void (*early_exit)(const struct fdt_match *match);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index bfe15f0..16aa4f3 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -122,6 +122,14 @@ fail:
> ????????????????wfi();
> ?}
> ?
> +static bool generic_cold_boot_allowed(u32 hartid)
> +{
> +???????if (generic_plat && generic_plat->cold_boot_allowed)
> +???????????????return generic_plat->cold_boot_allowed(
> +???????????????????????????????????????????????hartid, generic_plat_match);
> +???????return TRUE;
> +}
> +
> ?static int generic_nascent_init(void)
> ?{
> ????????if (platform_has_mlevel_imsic)
> @@ -261,6 +269,7 @@ static int generic_console_init(void)
> ?}
> ?
> ?const struct sbi_platform_operations platform_ops = {
> +???????.cold_boot_allowed??????= generic_cold_boot_allowed,
> ????????.nascent_init???????????= generic_nascent_init,
> ????????.early_init?????????????= generic_early_init,
> ????????.final_init?????????????= generic_final_init,
> -- 
> 2.25.1
> 
> 




From hchauhan at ventanamicro.com  Tue Dec 20 02:46:17 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:17 +0530
Subject: [PATCH 1/9] include: sbi: Fine grain the permissions for M and SU modes
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-2-hchauhan@ventanamicro.com>

Split the permissions for M-mode and SU-mode. This would
help if different sections of OpenSBI need to be given
different permissions and if M-mode has different permisssions
than the SU-mode over a region.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 include/sbi/sbi_domain.h | 40 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..955ffa3 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -36,11 +36,41 @@ struct sbi_domain_memregion {
 	 */
 	unsigned long base;
 	/** Flags representing memory region attributes */
-#define SBI_DOMAIN_MEMREGION_READABLE		(1UL << 0)
-#define SBI_DOMAIN_MEMREGION_WRITEABLE		(1UL << 1)
-#define SBI_DOMAIN_MEMREGION_EXECUTABLE		(1UL << 2)
-#define SBI_DOMAIN_MEMREGION_MMODE		(1UL << 3)
-#define SBI_DOMAIN_MEMREGION_ACCESS_MASK	(0xfUL)
+#define SBI_DOMAIN_MEMREGION_M_READABLE		(1UL << 0)
+#define SBI_DOMAIN_MEMREGION_M_WRITABLE		(1UL << 1)
+#define SBI_DOMAIN_MEMREGION_M_EXECUTABLE	(1UL << 2)
+#define SBI_DOMAIN_MEMREGION_SU_READABLE	(1UL << 3)
+#define SBI_DOMAIN_MEMREGION_SU_WRITABLE	(1UL << 4)
+#define SBI_DOMAIN_MEMREGION_SU_EXECUTABLE	(1UL << 5)
+
+	/** Bit to control if permissions are enforced on all modes */
+#define SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS	(1UL << 6)
+
+#define SBI_DOMAIN_MEMREGION_M_RWX		(SBI_DOMAIN_MEMREGION_M_READABLE | \
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE | \
+						 SBI_DOMAIN_MEMREGION_M_EXECUTABLE)
+
+	/* Unrestricted M-mode accesses but enfoced on SU-mode */
+#define SBI_DOMAIN_MEMREGION_READABLE		(SBI_DOMAIN_MEMREGION_SU_READABLE | \
+						 SBI_DOMAIN_MEMREGION_M_RWX)
+#define SBI_DOMAIN_MEMREGION_WRITEABLE		(SBI_DOMAIN_MEMREGION_SU_WRITABLE | \
+						 SBI_DOMAIN_MEMREGION_M_RWX)
+#define SBI_DOMAIN_MEMREGION_EXECUTABLE		(SBI_DOMAIN_MEMREGION_SU_EXECUTABLE | \
+						 SBI_DOMAIN_MEMREGION_M_RWX)
+
+	/* Enforced accesses across all modes */
+#define SBI_DOMAIN_MEMREGION_ENF_READABLE	(SBI_DOMAIN_MEMREGION_SU_READABLE | \
+						 SBI_DOMAIN_MEMREGION_M_READABLE)
+#define SBI_DOMAIN_MEMREGION_ENF_WRITABLE	(SBI_DOMAIN_MEMREGION_SU_WRITABLE | \
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE)
+#define SBI_DOMAIN_MEMREGION_ENF_EXECUTABLE	(SBI_DOMAIN_MEMREGION_SU_EXECUTABLE | \
+						 SBI_DOMAIN_MEMREGION_M_EXECUTABLE)
+
+#define SBI_DOMAIN_MEMREGION_ACCESS_MASK	(0x3fUL)
+#define SBI_DOMAIN_MEMREGION_M_ACCESS_MASK	(0x7UL)
+#define SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK	(0x38UL)
+
+#define SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT	(3)
 
 #define SBI_DOMAIN_MEMREGION_MMIO		(1UL << 31)
 	unsigned long flags;
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:16 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:16 +0530
Subject: [PATCH 0/9] Split region permissions into M-mode and SU-mode
Message-ID: <20221220104625.80667-1-hchauhan@ventanamicro.com>

This is first series in the series of forthcoming patches that
would add support for different access permission for different
sections of OpenSBI (RO, RX, RW). Eventually, this would lead
to support of smepmp extension.

This patch series splits the current R/W/X permissions to
M-mode R/W/X and SU-mode R/W/X. The split is in such a way
that current permission semantics are not broken.


Himanshu Chauhan (9):
  include: sbi: Fine grain the permissions for M and SU modes
  lib: sbi: Use finer permission semantics for address validation
  lib: sbi: Add permissions for the firmware start till end
  lib: sbi: Use finer permission sematics to decide on PMP bits
  lib: sbi: Modify the boot time region flag prints
  lib: utils: Use SU-{R/W/X} flags for region permissions during parsing
  lib: utils: Disallow non-root domains from adding M-mode regions
  lib: utils: Add M-mode {R/W} flags to the MMIO regions
  docs: Update domain's region permissions and requirements

 docs/domain_support.md          |  7 +++--
 include/sbi/sbi_domain.h        | 45 ++++++++++++++++++++++++++++----
 lib/sbi/sbi_domain.c            | 46 +++++++++++++++++++++++----------
 lib/sbi/sbi_hart.c              | 16 ++++++++----
 lib/utils/fdt/fdt_domain.c      | 20 +++++++++++---
 lib/utils/ipi/aclint_mswi.c     |  4 ++-
 lib/utils/irqchip/aplic.c       |  4 ++-
 lib/utils/irqchip/imsic.c       |  4 ++-
 lib/utils/timer/aclint_mtimer.c | 16 +++++++++---
 9 files changed, 127 insertions(+), 35 deletions(-)

-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:18 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:18 +0530
Subject: [PATCH 2/9] lib: sbi: Use finer permission semantics for address validation
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-3-hchauhan@ventanamicro.com>

Use the fine grained permisssion semantics for address validation
of a given region.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_domain.c | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3205595..8f9306c 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -107,24 +107,33 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 {
 	bool rmmio, mmio = FALSE;
 	struct sbi_domain_memregion *reg;
-	unsigned long rstart, rend, rflags, rwx = 0;
+	unsigned long rstart, rend, rflags, rwx = 0, rrwx = 0;
 
 	if (!dom)
 		return FALSE;
 
+	/*
+	 * Use M_{R/W/X} bits because the SU-bits are at the
+	 * same relative offsets. If the mode is not M, the SU
+	 * bits will fall at same offsets after the shift.
+	 */
 	if (access_flags & SBI_DOMAIN_READ)
-		rwx |= SBI_DOMAIN_MEMREGION_READABLE;
+		rwx |= SBI_DOMAIN_MEMREGION_M_READABLE;
+
 	if (access_flags & SBI_DOMAIN_WRITE)
-		rwx |= SBI_DOMAIN_MEMREGION_WRITEABLE;
+		rwx |= SBI_DOMAIN_MEMREGION_M_WRITABLE;
+
 	if (access_flags & SBI_DOMAIN_EXECUTE)
-		rwx |= SBI_DOMAIN_MEMREGION_EXECUTABLE;
+		rwx |= SBI_DOMAIN_MEMREGION_M_EXECUTABLE;
+
 	if (access_flags & SBI_DOMAIN_MMIO)
 		mmio = TRUE;
 
 	sbi_domain_for_each_memregion(dom, reg) {
 		rflags = reg->flags;
-		if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
-			continue;
+		rrwx = (mode == PRV_M ? (rflags & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK)
+			: (rflags & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK)
+			>> SBI_DOMAIN_MEMREGION_SU_ACCESS_SHIFT);
 
 		rstart = reg->base;
 		rend = (reg->order < __riscv_xlen) ?
@@ -133,7 +142,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
 			if (mmio != rmmio)
 				return FALSE;
-			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
+			return ((rrwx & rwx) == rwx) ? TRUE : FALSE;
 		}
 	}
 
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:19 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:19 +0530
Subject: [PATCH 3/9] lib: sbi: Add permissions for the firmware start till end
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-4-hchauhan@ventanamicro.com>

Change the zero flag to M-mode R/W/X flag for the firmware
region.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_domain.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 8f9306c..01eff18 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -628,7 +628,8 @@ int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid)
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 	/* Root domain firmware memory region */
-	sbi_domain_memregion_init(scratch->fw_start, scratch->fw_size, 0,
+	sbi_domain_memregion_init(scratch->fw_start, scratch->fw_size,
+				  SBI_DOMAIN_MEMREGION_M_RWX,
 				  &root_fw_region);
 	domain_memregion_initfw(&root_memregs[root_memregs_count++]);
 
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:21 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:21 +0530
Subject: [PATCH 5/9] lib: sbi: Modify the boot time region flag prints
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-6-hchauhan@ventanamicro.com>

With the finer permission semantics, the region access
permissions must be displayed separately for M and SU mode.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_domain.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 01eff18..39a00f3 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -344,15 +344,25 @@ void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
 			   dom->index, i, suffix, rstart, rend);
 
 		k = 0;
-		if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
-			sbi_printf("%cM", (k++) ? ',' : '(');
+
+		sbi_printf("M: ");
 		if (reg->flags & SBI_DOMAIN_MEMREGION_MMIO)
 			sbi_printf("%cI", (k++) ? ',' : '(');
-		if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
+		if (reg->flags & SBI_DOMAIN_MEMREGION_M_READABLE)
+			sbi_printf("%cR", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_M_WRITABLE)
+			sbi_printf("%cW", (k++) ? ',' : '(');
+		if (reg->flags & SBI_DOMAIN_MEMREGION_M_EXECUTABLE)
+			sbi_printf("%cX", (k++) ? ',' : '(');
+		sbi_printf("%s ", (k++) ? ")" : "()");
+
+		k = 0;
+		sbi_printf("S/U: ");
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
 			sbi_printf("%cR", (k++) ? ',' : '(');
-		if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
 			sbi_printf("%cW", (k++) ? ',' : '(');
-		if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
 			sbi_printf("%cX", (k++) ? ',' : '(');
 		sbi_printf("%s\n", (k++) ? ")" : "()");
 
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:22 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:22 +0530
Subject: [PATCH 6/9] lib: utils: Use SU-{R/W/X} flags for region permissions during parsing
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-7-hchauhan@ventanamicro.com>

Use the newer SU-{R/W/X} flags for checking and assigning region
permissions.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/utils/fdt/fdt_domain.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index 0568603..f979343 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -338,9 +338,9 @@ static int __fdt_parse_domain(void *fdt, int domain_offset, void *opaque)
 	 * 2) mmio regions protecting M-mode only mmio devices
 	 */
 	sbi_domain_for_each_memregion(&root, reg) {
-		if ((reg->flags & SBI_DOMAIN_MEMREGION_READABLE) ||
-		    (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE) ||
-		    (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE))
+		if ((reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE) ||
+		    (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE) ||
+		    (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE))
 			continue;
 		if (FDT_DOMAIN_REGION_MAX_COUNT <= val32)
 			return SBI_EINVAL;
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:20 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:20 +0530
Subject: [PATCH 4/9] lib: sbi: Use finer permission sematics to decide on PMP bits
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-5-hchauhan@ventanamicro.com>

Use the fine grained permission bits to decide if the region
permissions are to enforced on all modes. Also use the new
permission bits for deciding on R/W/X bits in pmpcfg register.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5447c52..2ded55b 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -303,14 +303,20 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 			break;
 
 		pmp_flags = 0;
-		if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
+
+		/*
+		 * If permissions are to be enforced for all modes on this region,
+		 * the lock bit should be set.
+		 */
+		if (reg->flags & SBI_DOMAIN_MEMREGION_ENF_PERMISSIONS)
+			pmp_flags |= PMP_L;
+
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_READABLE)
 			pmp_flags |= PMP_R;
-		if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_WRITABLE)
 			pmp_flags |= PMP_W;
-		if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
+		if (reg->flags & SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
 			pmp_flags |= PMP_X;
-		if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
-			pmp_flags |= PMP_L;
 
 		pmp_addr =  reg->base >> PMP_SHIFT;
 		if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:25 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:25 +0530
Subject: [PATCH 9/9] docs: Update domain's region permissions and requirements
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-10-hchauhan@ventanamicro.com>

Updated the various permissions bits available for domains
defined in DT node and restrictions on them.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 docs/domain_support.md | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/docs/domain_support.md b/docs/domain_support.md
index 8963b57..e533bf7 100644
--- a/docs/domain_support.md
+++ b/docs/domain_support.md
@@ -160,8 +160,11 @@ The DT properties of a domain instance DT node are as follows:
 * **regions** (Optional) - The list of domain memory region DT node phandle
   and access permissions for the domain instance. Each list entry is a pair
   of DT node phandle and access permissions. The access permissions are
-  represented as a 32bit bitmask having bits: **readable** (BIT[0]),
-  **writeable** (BIT[1]), **executable** (BIT[2]), and **m-mode** (BIT[3]).
+  represented as a 32bit bitmask having bits: **M readable** (BIT[0]),
+  **M writeable** (BIT[1]), **M executable** (BIT[2]), **SU readable**
+  (BIT[3]), **SU writable** (BIT[4]), and **SU executable** (BIT[5]).
+  Any region of a domain defined in DT node cannot have only M-bits set
+  in access permissions i.e. it cannot be an m-mode only accessible region.
 * **boot-hart** (Optional) - The DT node phandle of the HART booting the
   domain instance. If coldboot HART is assigned to the domain instance then
   this DT property is ignored and the coldboot HART is assumed to be the
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:23 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:23 +0530
Subject: [PATCH 7/9] lib: utils: Disallow non-root domains from adding M-mode regions
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-8-hchauhan@ventanamicro.com>

The M-mode regions can only be added by root domain. The non-root
domains shouldn't be able to add them from FDT.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 include/sbi/sbi_domain.h   |  5 +++++
 lib/utils/fdt/fdt_domain.c | 14 ++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 955ffa3..3f5d28e 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -50,6 +50,11 @@ struct sbi_domain_memregion {
 						 SBI_DOMAIN_MEMREGION_M_WRITABLE | \
 						 SBI_DOMAIN_MEMREGION_M_EXECUTABLE)
 
+#define SBI_DOMAIN_MEMREGION_SU_RWX		(SBI_DOMAIN_MEMREGION_SU_READABLE | \
+						 SBI_DOMAIN_MEMREGION_SU_WRITABLE | \
+						 SBI_DOMAIN_MEMREGION_SU_EXECUTABLE)
+
+
 	/* Unrestricted M-mode accesses but enfoced on SU-mode */
 #define SBI_DOMAIN_MEMREGION_READABLE		(SBI_DOMAIN_MEMREGION_SU_READABLE | \
 						 SBI_DOMAIN_MEMREGION_M_RWX)
diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index f979343..838aeca 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -239,6 +239,20 @@ static int __fdt_parse_region(void *fdt, int domain_offset,
 	u32 *region_count = opaque;
 	struct sbi_domain_memregion *region;
 
+	/*
+	 * Non-root domains cannot add a region with only M-mode
+	 * access permissions. M-mode regions can only be part of
+	 * root domain.
+	 *
+	 * SU permission bits can't be all zeroes and M-mode permission
+	 * bits must be all set.
+	 */
+	if (!((region_access & SBI_DOMAIN_MEMREGION_SU_ACCESS_MASK)
+	     & SBI_DOMAIN_MEMREGION_SU_RWX)
+	    && ((region_access & SBI_DOMAIN_MEMREGION_M_ACCESS_MASK)
+		& SBI_DOMAIN_MEMREGION_M_RWX))
+		return SBI_EINVAL;
+
 	/* Find next region of the domain */
 	if (FDT_DOMAIN_REGION_MAX_COUNT <= *region_count)
 		return SBI_EINVAL;
-- 
2.39.0



From hchauhan at ventanamicro.com  Tue Dec 20 02:46:24 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Tue, 20 Dec 2022 16:16:24 +0530
Subject: [PATCH 8/9] lib: utils: Add M-mode {R/W} flags to the MMIO regions
In-Reply-To: <20221220104625.80667-1-hchauhan@ventanamicro.com>
References: <20221220104625.80667-1-hchauhan@ventanamicro.com>
Message-ID: <20221220104625.80667-9-hchauhan@ventanamicro.com>

Add the M-mode readable/writable flags to mmio regions
of various drivers.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/utils/ipi/aclint_mswi.c     |  4 +++-
 lib/utils/irqchip/aplic.c       |  4 +++-
 lib/utils/irqchip/imsic.c       |  4 +++-
 lib/utils/timer/aclint_mtimer.c | 16 ++++++++++++----
 4 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/lib/utils/ipi/aclint_mswi.c b/lib/utils/ipi/aclint_mswi.c
index 832e223..c714a89 100644
--- a/lib/utils/ipi/aclint_mswi.c
+++ b/lib/utils/ipi/aclint_mswi.c
@@ -88,7 +88,9 @@ int aclint_mswi_cold_init(struct aclint_mswi_data *mswi)
 		region_size = ((mswi->size - pos) < ACLINT_MSWI_ALIGN) ?
 			      (mswi->size - pos) : ACLINT_MSWI_ALIGN;
 		sbi_domain_memregion_init(mswi->addr + pos, region_size,
-					  SBI_DOMAIN_MEMREGION_MMIO, &reg);
+					  (SBI_DOMAIN_MEMREGION_MMIO |
+					   SBI_DOMAIN_MEMREGION_M_READABLE |
+					   SBI_DOMAIN_MEMREGION_M_WRITABLE), &reg);
 		rc = sbi_domain_root_add_memregion(&reg);
 		if (rc)
 			return rc;
diff --git a/lib/utils/irqchip/aplic.c b/lib/utils/irqchip/aplic.c
index 0a8469b..858e9b2 100644
--- a/lib/utils/irqchip/aplic.c
+++ b/lib/utils/irqchip/aplic.c
@@ -269,7 +269,9 @@ int aplic_cold_irqchip_init(struct aplic_data *aplic)
 	    (last_deleg_irq == aplic->num_source) &&
 	    (first_deleg_irq == 1))) {
 		sbi_domain_memregion_init(aplic->addr, aplic->size,
-					  SBI_DOMAIN_MEMREGION_MMIO, &reg);
+					  (SBI_DOMAIN_MEMREGION_MMIO |
+					   SBI_DOMAIN_MEMREGION_M_READABLE |
+					   SBI_DOMAIN_MEMREGION_M_WRITABLE), &reg);
 		rc = sbi_domain_root_add_memregion(&reg);
 		if (rc)
 			return rc;
diff --git a/lib/utils/irqchip/imsic.c b/lib/utils/irqchip/imsic.c
index 98f2cb6..ada4f3b 100644
--- a/lib/utils/irqchip/imsic.c
+++ b/lib/utils/irqchip/imsic.c
@@ -313,7 +313,9 @@ int imsic_cold_irqchip_init(struct imsic_data *imsic)
 	for (i = 0; i < IMSIC_MAX_REGS && imsic->regs[i].size; i++) {
 		sbi_domain_memregion_init(imsic->regs[i].addr,
 					  imsic->regs[i].size,
-					  SBI_DOMAIN_MEMREGION_MMIO, &reg);
+					  (SBI_DOMAIN_MEMREGION_MMIO |
+					   SBI_DOMAIN_MEMREGION_M_READABLE |
+					   SBI_DOMAIN_MEMREGION_M_WRITABLE), &reg);
 		rc = sbi_domain_root_add_memregion(&reg);
 		if (rc)
 			return rc;
diff --git a/lib/utils/timer/aclint_mtimer.c b/lib/utils/timer/aclint_mtimer.c
index 1846a9a..84ded4e 100644
--- a/lib/utils/timer/aclint_mtimer.c
+++ b/lib/utils/timer/aclint_mtimer.c
@@ -188,26 +188,34 @@ int aclint_mtimer_cold_init(struct aclint_mtimer_data *mt,
 		rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
 					mt->mtime_size + mt->mtimecmp_size,
 					MTIMER_REGION_ALIGN,
-					SBI_DOMAIN_MEMREGION_MMIO);
+					(SBI_DOMAIN_MEMREGION_MMIO |
+					 SBI_DOMAIN_MEMREGION_M_READABLE |
+					 SBI_DOMAIN_MEMREGION_M_WRITABLE));
 		if (rc)
 			return rc;
 	} else if (mt->mtimecmp_addr == (mt->mtime_addr + mt->mtime_size)) {
 		rc = sbi_domain_root_add_memrange(mt->mtime_addr,
 					mt->mtime_size + mt->mtimecmp_size,
 					MTIMER_REGION_ALIGN,
-					SBI_DOMAIN_MEMREGION_MMIO);
+					(SBI_DOMAIN_MEMREGION_MMIO |
+					 SBI_DOMAIN_MEMREGION_M_READABLE |
+					 SBI_DOMAIN_MEMREGION_M_WRITABLE));
 		if (rc)
 			return rc;
 	} else {
 		rc = sbi_domain_root_add_memrange(mt->mtime_addr,
 						mt->mtime_size, MTIMER_REGION_ALIGN,
-						SBI_DOMAIN_MEMREGION_MMIO);
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
 		if (rc)
 			return rc;
 
 		rc = sbi_domain_root_add_memrange(mt->mtimecmp_addr,
 						mt->mtimecmp_size, MTIMER_REGION_ALIGN,
-						SBI_DOMAIN_MEMREGION_MMIO);
+						(SBI_DOMAIN_MEMREGION_MMIO |
+						 SBI_DOMAIN_MEMREGION_M_READABLE |
+						 SBI_DOMAIN_MEMREGION_M_WRITABLE));
 		if (rc)
 			return rc;
 	}
-- 
2.39.0



From apatel at ventanamicro.com  Tue Dec 20 03:05:10 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 20 Dec 2022 16:35:10 +0530
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221220034102.150151-4-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com> <20221220034102.150151-4-weiliang.lim@starfivetech.com>
Message-ID: <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>

On Tue, Dec 20, 2022 at 9:12 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> Add Starfive JH7110 platform implementation
>
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
>  platform/generic/Kconfig             |  4 ++
>  platform/generic/configs/defconfig   |  1 +
>  platform/generic/starfive/jh7110.c   | 57 ++++++++++++++++++++++++++++
>  platform/generic/starfive/objects.mk |  6 +++
>  4 files changed, 68 insertions(+)
>  create mode 100644 platform/generic/starfive/jh7110.c
>  create mode 100644 platform/generic/starfive/objects.mk
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 62c7a2d..47c10e5 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
>         depends on FDT_RESET && FDT_I2C
>         default n
>
> +config PLATFORM_STARFIVE_JH7110
> +       bool "StarFive JH7110 support"
> +       default n
> +
>  endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 47fca95..4b0842e 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_FDT_GPIO=y
>  CONFIG_FDT_GPIO_SIFIVE=y
>  CONFIG_FDT_I2C=y
> diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
> new file mode 100644
> index 0000000..5d3ab6f
> --- /dev/null
> +++ b/platform/generic/starfive/jh7110.c
> @@ -0,0 +1,57 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 StarFive
> + *
> + * Authors:
> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> + */
> +
> +#include <libfdt.h>
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static bool hart_cold_booted = FALSE;
> +
> +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> +                                  const struct fdt_match *match)
> +{
> +       const fdt32_t *val;
> +       int len, coff;
> +
> +       if (hart_cold_booted)
> +               return FALSE;
> +
> +       void *fdt = fdt_get_address();

starfive_jh7110_cold_boot_allowed() will be called at runtime
during CPU hotplug or CPU non-retentive suspend so don't
access FDT in this function because it might have been
corrupted/over-written by S-mode software.

You can save data from FDT in starfive_jh7110_early_init()
when cold_boot == TRUE.

Regards,
Anup

> +
> +       coff = fdt_path_offset(fdt, "/chosen");
> +       if (-1 < coff) {
> +               val = fdt_getprop(fdt, coff, "boot-hart", &len);
> +               if (val && len) {
> +                       u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> +                       return (selected_hartid == hartid);
> +               }
> +       }
> +
> +       return TRUE;
> +}
> +
> +static int starfive_jh7110_early_init(bool cold_boot,
> +                                  const struct fdt_match *match)
> +{
> +       if (cold_boot)
> +               hart_cold_booted = TRUE;
> +
> +       return 0;
> +}
> +
> +static const struct fdt_match starfive_jh7110_match[] = {
> +       { .compatible = "starfive,jh7110" },
> +       { },
> +};
> +
> +const struct platform_override starfive_jh7110 = {
> +       .match_table = starfive_jh7110_match,
> +       .early_init = starfive_jh7110_early_init,
> +       .cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> +};
> diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
> new file mode 100644
> index 0000000..0b900fb
> --- /dev/null
> +++ b/platform/generic/starfive/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
> --
> 2.25.1
>


From cheehong.ang at starfivetech.com  Tue Dec 20 03:38:12 2022
From: cheehong.ang at starfivetech.com (Cheehong Ang)
Date: Tue, 20 Dec 2022 11:38:12 +0000
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
 <20221220034102.150151-4-weiliang.lim@starfivetech.com>
 <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>
Message-ID: <b94eeb4f4a544b13bcc036235e80026b@EXMBX168.cuchost.com>



> -----Original Message-----
> From: Anup Patel <apatel at ventanamicro.com>
> Sent: Tuesday, December 20, 2022 7:05 PM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi at lists.infradead.org; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
> implementation
> 
> On Tue, Dec 20, 2022 at 9:12 AM Wei Liang Lim
> <weiliang.lim at starfivetech.com> wrote:
> >
> > Add Starfive JH7110 platform implementation
> >
> > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > ---
> >  platform/generic/Kconfig             |  4 ++
> >  platform/generic/configs/defconfig   |  1 +
> >  platform/generic/starfive/jh7110.c   | 57 ++++++++++++++++++++++++++++
> >  platform/generic/starfive/objects.mk |  6 +++
> >  4 files changed, 68 insertions(+)
> >  create mode 100644 platform/generic/starfive/jh7110.c
> >  create mode 100644 platform/generic/starfive/objects.mk
> >
> > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index
> > 62c7a2d..47c10e5 100644
> > --- a/platform/generic/Kconfig
> > +++ b/platform/generic/Kconfig
> > @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> >         depends on FDT_RESET && FDT_I2C
> >         default n
> >
> > +config PLATFORM_STARFIVE_JH7110
> > +       bool "StarFive JH7110 support"
> > +       default n
> > +
> >  endif
> > diff --git a/platform/generic/configs/defconfig
> > b/platform/generic/configs/defconfig
> > index 47fca95..4b0842e 100644
> > --- a/platform/generic/configs/defconfig
> > +++ b/platform/generic/configs/defconfig
> > @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> > CONFIG_PLATFORM_RENESAS_RZFIVE=y
> CONFIG_PLATFORM_SIFIVE_FU540=y
> > CONFIG_PLATFORM_SIFIVE_FU740=y
> > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> >  CONFIG_FDT_GPIO=y
> >  CONFIG_FDT_GPIO_SIFIVE=y
> >  CONFIG_FDT_I2C=y
> > diff --git a/platform/generic/starfive/jh7110.c
> > b/platform/generic/starfive/jh7110.c
> > new file mode 100644
> > index 0000000..5d3ab6f
> > --- /dev/null
> > +++ b/platform/generic/starfive/jh7110.c
> > @@ -0,0 +1,57 @@
> > +/*
> > + * SPDX-License-Identifier: BSD-2-Clause
> > + *
> > + * Copyright (c) 2022 StarFive
> > + *
> > + * Authors:
> > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > + */
> > +
> > +#include <libfdt.h>
> > +#include <platform_override.h>
> > +#include <sbi_utils/fdt/fdt_helper.h>
> > +
> > +static bool hart_cold_booted = FALSE;
> > +
> > +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> > +                                  const struct fdt_match *match) {
> > +       const fdt32_t *val;
> > +       int len, coff;
> > +
> > +       if (hart_cold_booted)
> > +               return FALSE;
> > +
> > +       void *fdt = fdt_get_address();
> 
> starfive_jh7110_cold_boot_allowed() will be called at runtime during CPU
> hotplug or CPU non-retentive suspend so don't access FDT in this function
> because it might have been corrupted/over-written by S-mode software.
> 
> You can save data from FDT in starfive_jh7110_early_init() when cold_boot ==
> TRUE.
> 
The problem is early_init() is called from init_coldboot() and init_warm_startup() which is right after cold_boot_allowed(). Therefore, we have to access the FDT here, this is why we add a
'hart_cold_booted' boolean to ensure the FDT will not be accessed again once the FDT is read in cold boot path for the first time.
This is to avoid the issue you mentioned above. The code here already ensure the FDT will not be accessed again when the cold_boot_allowed() function is called during
HSM SBI calls. This is the reason in the beginning of the cold_boot_allowed() function, we check whether the 'hart_cold_booted' is set to TRUE which mean the FDT should not be accessed
again.

> Regards,
> Anup
> 
> > +
> > +       coff = fdt_path_offset(fdt, "/chosen");
> > +       if (-1 < coff) {
> > +               val = fdt_getprop(fdt, coff, "boot-hart", &len);
> > +               if (val && len) {
> > +                       u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> > +                       return (selected_hartid == hartid);
> > +               }
> > +       }
> > +
> > +       return TRUE;
> > +}
> > +
> > +static int starfive_jh7110_early_init(bool cold_boot,
> > +                                  const struct fdt_match *match) {
> > +       if (cold_boot)
> > +               hart_cold_booted = TRUE;
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct fdt_match starfive_jh7110_match[] = {
> > +       { .compatible = "starfive,jh7110" },
> > +       { },
> > +};
> > +
> > +const struct platform_override starfive_jh7110 = {
> > +       .match_table = starfive_jh7110_match,
> > +       .early_init = starfive_jh7110_early_init,
> > +       .cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> > +};
> > diff --git a/platform/generic/starfive/objects.mk
> > b/platform/generic/starfive/objects.mk
> > new file mode 100644
> > index 0000000..0b900fb
> > --- /dev/null
> > +++ b/platform/generic/starfive/objects.mk
> > @@ -0,0 +1,6 @@
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause #
> > +
> > +carray-platform_override_modules-
> $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > ++= starfive_jh7110
> > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> starfive/jh7110.o
> > --
> > 2.25.1
> >

From apatel at ventanamicro.com  Tue Dec 20 04:04:24 2022
From: apatel at ventanamicro.com (Anup Patel)
Date: Tue, 20 Dec 2022 17:34:24 +0530
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <b94eeb4f4a544b13bcc036235e80026b@EXMBX168.cuchost.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
 <20221220034102.150151-4-weiliang.lim@starfivetech.com> <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>
 <b94eeb4f4a544b13bcc036235e80026b@EXMBX168.cuchost.com>
Message-ID: <CAK9=C2UecME1zNtTE6vX+zYKGviJWxgZVF7_ksVFWnYRZxwjvQ@mail.gmail.com>

On Tue, Dec 20, 2022 at 5:08 PM Cheehong Ang
<cheehong.ang at starfivetech.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Anup Patel <apatel at ventanamicro.com>
> > Sent: Tuesday, December 20, 2022 7:05 PM
> > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > <junliang.tan at starfivetech.com>
> > Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
> > implementation
> >
> > On Tue, Dec 20, 2022 at 9:12 AM Wei Liang Lim
> > <weiliang.lim at starfivetech.com> wrote:
> > >
> > > Add Starfive JH7110 platform implementation
> > >
> > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > ---
> > >  platform/generic/Kconfig             |  4 ++
> > >  platform/generic/configs/defconfig   |  1 +
> > >  platform/generic/starfive/jh7110.c   | 57 ++++++++++++++++++++++++++++
> > >  platform/generic/starfive/objects.mk |  6 +++
> > >  4 files changed, 68 insertions(+)
> > >  create mode 100644 platform/generic/starfive/jh7110.c
> > >  create mode 100644 platform/generic/starfive/objects.mk
> > >
> > > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index
> > > 62c7a2d..47c10e5 100644
> > > --- a/platform/generic/Kconfig
> > > +++ b/platform/generic/Kconfig
> > > @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> > >         depends on FDT_RESET && FDT_I2C
> > >         default n
> > >
> > > +config PLATFORM_STARFIVE_JH7110
> > > +       bool "StarFive JH7110 support"
> > > +       default n
> > > +
> > >  endif
> > > diff --git a/platform/generic/configs/defconfig
> > > b/platform/generic/configs/defconfig
> > > index 47fca95..4b0842e 100644
> > > --- a/platform/generic/configs/defconfig
> > > +++ b/platform/generic/configs/defconfig
> > > @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> > > CONFIG_PLATFORM_RENESAS_RZFIVE=y
> > CONFIG_PLATFORM_SIFIVE_FU540=y
> > > CONFIG_PLATFORM_SIFIVE_FU740=y
> > > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> > >  CONFIG_FDT_GPIO=y
> > >  CONFIG_FDT_GPIO_SIFIVE=y
> > >  CONFIG_FDT_I2C=y
> > > diff --git a/platform/generic/starfive/jh7110.c
> > > b/platform/generic/starfive/jh7110.c
> > > new file mode 100644
> > > index 0000000..5d3ab6f
> > > --- /dev/null
> > > +++ b/platform/generic/starfive/jh7110.c
> > > @@ -0,0 +1,57 @@
> > > +/*
> > > + * SPDX-License-Identifier: BSD-2-Clause
> > > + *
> > > + * Copyright (c) 2022 StarFive
> > > + *
> > > + * Authors:
> > > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > + */
> > > +
> > > +#include <libfdt.h>
> > > +#include <platform_override.h>
> > > +#include <sbi_utils/fdt/fdt_helper.h>
> > > +
> > > +static bool hart_cold_booted = FALSE;
> > > +
> > > +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> > > +                                  const struct fdt_match *match) {
> > > +       const fdt32_t *val;
> > > +       int len, coff;
> > > +
> > > +       if (hart_cold_booted)
> > > +               return FALSE;
> > > +
> > > +       void *fdt = fdt_get_address();
> >
> > starfive_jh7110_cold_boot_allowed() will be called at runtime during CPU
> > hotplug or CPU non-retentive suspend so don't access FDT in this function
> > because it might have been corrupted/over-written by S-mode software.
> >
> > You can save data from FDT in starfive_jh7110_early_init() when cold_boot ==
> > TRUE.
> >
> The problem is early_init() is called from init_coldboot() and init_warm_startup() which is right after cold_boot_allowed(). Therefore, we have to access the FDT here, this is why we add a
> 'hart_cold_booted' boolean to ensure the FDT will not be accessed again once the FDT is read in cold boot path for the first time.
> This is to avoid the issue you mentioned above. The code here already ensure the FDT will not be accessed again when the cold_boot_allowed() function is called during
> HSM SBI calls. This is the reason in the beginning of the cold_boot_allowed() function, we check whether the 'hart_cold_booted' is set to TRUE which mean the FDT should not be accessed
> again.

I see but there is another way to do this.

You do the following as a separate PATCH before this PATCH:
1) Add "void (*fw_init)(void *fdt, const struct fdt_match *match)" in
    "struct platform_override"
2) Update fw_platform_init() to call generic_plat->fw_init() right
   after fw_platform_lookup_special() call.

Your current patch can simply implement fw_init() callback which
will parse the chosen boot-hart-id. You will not need hart_cold_booted
boolean with this approach.

Regards,
Anup

>
> > Regards,
> > Anup
> >
> > > +
> > > +       coff = fdt_path_offset(fdt, "/chosen");
> > > +       if (-1 < coff) {
> > > +               val = fdt_getprop(fdt, coff, "boot-hart", &len);
> > > +               if (val && len) {
> > > +                       u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> > > +                       return (selected_hartid == hartid);
> > > +               }
> > > +       }
> > > +
> > > +       return TRUE;
> > > +}
> > > +
> > > +static int starfive_jh7110_early_init(bool cold_boot,
> > > +                                  const struct fdt_match *match) {
> > > +       if (cold_boot)
> > > +               hart_cold_booted = TRUE;
> > > +
> > > +       return 0;
> > > +}
> > > +
> > > +static const struct fdt_match starfive_jh7110_match[] = {
> > > +       { .compatible = "starfive,jh7110" },
> > > +       { },
> > > +};
> > > +
> > > +const struct platform_override starfive_jh7110 = {
> > > +       .match_table = starfive_jh7110_match,
> > > +       .early_init = starfive_jh7110_early_init,
> > > +       .cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> > > +};
> > > diff --git a/platform/generic/starfive/objects.mk
> > > b/platform/generic/starfive/objects.mk
> > > new file mode 100644
> > > index 0000000..0b900fb
> > > --- /dev/null
> > > +++ b/platform/generic/starfive/objects.mk
> > > @@ -0,0 +1,6 @@
> > > +#
> > > +# SPDX-License-Identifier: BSD-2-Clause #
> > > +
> > > +carray-platform_override_modules-
> > $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > > ++= starfive_jh7110
> > > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> > starfive/jh7110.o
> > > --
> > > 2.25.1
> > >


From cheehong.ang at starfivetech.com  Tue Dec 20 04:32:41 2022
From: cheehong.ang at starfivetech.com (Cheehong Ang)
Date: Tue, 20 Dec 2022 12:32:41 +0000
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <CAK9=C2UecME1zNtTE6vX+zYKGviJWxgZVF7_ksVFWnYRZxwjvQ@mail.gmail.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
 <20221220034102.150151-4-weiliang.lim@starfivetech.com>
 <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>
 <b94eeb4f4a544b13bcc036235e80026b@EXMBX168.cuchost.com>
 <CAK9=C2UecME1zNtTE6vX+zYKGviJWxgZVF7_ksVFWnYRZxwjvQ@mail.gmail.com>
Message-ID: <86d58fe538e94baab146976c161efc27@EXMBX168.cuchost.com>

> -----Original Message-----
> From: Anup Patel <apatel at ventanamicro.com>
> Sent: Tuesday, December 20, 2022 8:04 PM
> To: Cheehong Ang <cheehong.ang at starfivetech.com>
> Cc: WeiLiang Lim <weiliang.lim at starfivetech.com>;
> opensbi at lists.infradead.org; JunLiang Tan <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
> implementation
> 
> On Tue, Dec 20, 2022 at 5:08 PM Cheehong Ang
> <cheehong.ang at starfivetech.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Anup Patel <apatel at ventanamicro.com>
> > > Sent: Tuesday, December 20, 2022 7:05 PM
> > > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > > <junliang.tan at starfivetech.com>
> > > Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110
> > > platform implementation
> > >
> > > On Tue, Dec 20, 2022 at 9:12 AM Wei Liang Lim
> > > <weiliang.lim at starfivetech.com> wrote:
> > > >
> > > > Add Starfive JH7110 platform implementation
> > > >
> > > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > > ---
> > > >  platform/generic/Kconfig             |  4 ++
> > > >  platform/generic/configs/defconfig   |  1 +
> > > >  platform/generic/starfive/jh7110.c   | 57
> ++++++++++++++++++++++++++++
> > > >  platform/generic/starfive/objects.mk |  6 +++
> > > >  4 files changed, 68 insertions(+)  create mode 100644
> > > > platform/generic/starfive/jh7110.c
> > > >  create mode 100644 platform/generic/starfive/objects.mk
> > > >
> > > > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> > > > index
> > > > 62c7a2d..47c10e5 100644
> > > > --- a/platform/generic/Kconfig
> > > > +++ b/platform/generic/Kconfig
> > > > @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> > > >         depends on FDT_RESET && FDT_I2C
> > > >         default n
> > > >
> > > > +config PLATFORM_STARFIVE_JH7110
> > > > +       bool "StarFive JH7110 support"
> > > > +       default n
> > > > +
> > > >  endif
> > > > diff --git a/platform/generic/configs/defconfig
> > > > b/platform/generic/configs/defconfig
> > > > index 47fca95..4b0842e 100644
> > > > --- a/platform/generic/configs/defconfig
> > > > +++ b/platform/generic/configs/defconfig
> > > > @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> > > > CONFIG_PLATFORM_RENESAS_RZFIVE=y
> > > CONFIG_PLATFORM_SIFIVE_FU540=y
> > > > CONFIG_PLATFORM_SIFIVE_FU740=y
> > > > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> > > >  CONFIG_FDT_GPIO=y
> > > >  CONFIG_FDT_GPIO_SIFIVE=y
> > > >  CONFIG_FDT_I2C=y
> > > > diff --git a/platform/generic/starfive/jh7110.c
> > > > b/platform/generic/starfive/jh7110.c
> > > > new file mode 100644
> > > > index 0000000..5d3ab6f
> > > > --- /dev/null
> > > > +++ b/platform/generic/starfive/jh7110.c
> > > > @@ -0,0 +1,57 @@
> > > > +/*
> > > > + * SPDX-License-Identifier: BSD-2-Clause
> > > > + *
> > > > + * Copyright (c) 2022 StarFive
> > > > + *
> > > > + * Authors:
> > > > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > + */
> > > > +
> > > > +#include <libfdt.h>
> > > > +#include <platform_override.h>
> > > > +#include <sbi_utils/fdt/fdt_helper.h>
> > > > +
> > > > +static bool hart_cold_booted = FALSE;
> > > > +
> > > > +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> > > > +                                  const struct fdt_match *match) {
> > > > +       const fdt32_t *val;
> > > > +       int len, coff;
> > > > +
> > > > +       if (hart_cold_booted)
> > > > +               return FALSE;
> > > > +
> > > > +       void *fdt = fdt_get_address();
> > >
> > > starfive_jh7110_cold_boot_allowed() will be called at runtime during
> > > CPU hotplug or CPU non-retentive suspend so don't access FDT in this
> > > function because it might have been corrupted/over-written by S-mode
> software.
> > >
> > > You can save data from FDT in starfive_jh7110_early_init() when
> > > cold_boot == TRUE.
> > >
> > The problem is early_init() is called from init_coldboot() and
> > init_warm_startup() which is right after cold_boot_allowed(). Therefore, we
> have to access the FDT here, this is why we add a 'hart_cold_booted' boolean
> to ensure the FDT will not be accessed again once the FDT is read in cold boot
> path for the first time.
> > This is to avoid the issue you mentioned above. The code here already
> > ensure the FDT will not be accessed again when the cold_boot_allowed()
> > function is called during HSM SBI calls. This is the reason in the beginning of
> the cold_boot_allowed() function, we check whether the 'hart_cold_booted' is
> set to TRUE which mean the FDT should not be accessed again.
> 
> I see but there is another way to do this.
> 
> You do the following as a separate PATCH before this PATCH:
> 1) Add "void (*fw_init)(void *fdt, const struct fdt_match *match)" in
>     "struct platform_override"
> 2) Update fw_platform_init() to call generic_plat->fw_init() right
>    after fw_platform_lookup_special() call.
> 
> Your current patch can simply implement fw_init() callback which will parse
> the chosen boot-hart-id. You will not need hart_cold_booted boolean with this
> approach.
Thanks. Will do. This shall also resolved Xiang's comment in other thread that the FDT is read multiple times when multiple
harts call cold_boot_allowed(). I believe the fw_platform_init() in fw_base.S is only called once from initial boot hart.
I don't think fdt_get_address() can be called in fw_platform_init() as the scratch area is not initialized yet.
But I think we can still get the FDT location from one of the arguments passed to fw_platform_init().
> 
> Regards,
> Anup
> 
> >
> > > Regards,
> > > Anup
> > >
> > > > +
> > > > +       coff = fdt_path_offset(fdt, "/chosen");
> > > > +       if (-1 < coff) {
> > > > +               val = fdt_getprop(fdt, coff, "boot-hart", &len);
> > > > +               if (val && len) {
> > > > +                       u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> > > > +                       return (selected_hartid == hartid);
> > > > +               }
> > > > +       }
> > > > +
> > > > +       return TRUE;
> > > > +}
> > > > +
> > > > +static int starfive_jh7110_early_init(bool cold_boot,
> > > > +                                  const struct fdt_match *match) {
> > > > +       if (cold_boot)
> > > > +               hart_cold_booted = TRUE;
> > > > +
> > > > +       return 0;
> > > > +}
> > > > +
> > > > +static const struct fdt_match starfive_jh7110_match[] = {
> > > > +       { .compatible = "starfive,jh7110" },
> > > > +       { },
> > > > +};
> > > > +
> > > > +const struct platform_override starfive_jh7110 = {
> > > > +       .match_table = starfive_jh7110_match,
> > > > +       .early_init = starfive_jh7110_early_init,
> > > > +       .cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> > > > +};
> > > > diff --git a/platform/generic/starfive/objects.mk
> > > > b/platform/generic/starfive/objects.mk
> > > > new file mode 100644
> > > > index 0000000..0b900fb
> > > > --- /dev/null
> > > > +++ b/platform/generic/starfive/objects.mk
> > > > @@ -0,0 +1,6 @@
> > > > +#
> > > > +# SPDX-License-Identifier: BSD-2-Clause #
> > > > +
> > > > +carray-platform_override_modules-
> > > $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > > > ++= starfive_jh7110
> > > > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> > > starfive/jh7110.o
> > > > --
> > > > 2.25.1
> > > >

From anup at brainfault.org  Tue Dec 20 04:50:42 2022
From: anup at brainfault.org (Anup Patel)
Date: Tue, 20 Dec 2022 18:20:42 +0530
Subject: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <86d58fe538e94baab146976c161efc27@EXMBX168.cuchost.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com>
 <20221220034102.150151-4-weiliang.lim@starfivetech.com> <CAK9=C2WQSv-MFDUrzfiG9CP_-Wb+Ru1e8WCwoezLzNFEWztUOw@mail.gmail.com>
 <b94eeb4f4a544b13bcc036235e80026b@EXMBX168.cuchost.com> <CAK9=C2UecME1zNtTE6vX+zYKGviJWxgZVF7_ksVFWnYRZxwjvQ@mail.gmail.com>
 <86d58fe538e94baab146976c161efc27@EXMBX168.cuchost.com>
Message-ID: <CAAhSdy1MyBAMXSrdVvTGWv0Zc+Q3ksyw2Xfac0=geJxJgBUrqw@mail.gmail.com>

On Tue, Dec 20, 2022 at 6:03 PM Cheehong Ang
<cheehong.ang at starfivetech.com> wrote:
>
> > -----Original Message-----
> > From: Anup Patel <apatel at ventanamicro.com>
> > Sent: Tuesday, December 20, 2022 8:04 PM
> > To: Cheehong Ang <cheehong.ang at starfivetech.com>
> > Cc: WeiLiang Lim <weiliang.lim at starfivetech.com>;
> > opensbi at lists.infradead.org; JunLiang Tan <junliang.tan at starfivetech.com>
> > Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110 platform
> > implementation
> >
> > On Tue, Dec 20, 2022 at 5:08 PM Cheehong Ang
> > <cheehong.ang at starfivetech.com> wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Anup Patel <apatel at ventanamicro.com>
> > > > Sent: Tuesday, December 20, 2022 7:05 PM
> > > > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > > > Cc: opensbi at lists.infradead.org; Cheehong Ang
> > > > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > > > <junliang.tan at starfivetech.com>
> > > > Subject: Re: [PATCH v4 3/3] generic/starfive: Add Starfive JH7110
> > > > platform implementation
> > > >
> > > > On Tue, Dec 20, 2022 at 9:12 AM Wei Liang Lim
> > > > <weiliang.lim at starfivetech.com> wrote:
> > > > >
> > > > > Add Starfive JH7110 platform implementation
> > > > >
> > > > > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > > > > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > > > > ---
> > > > >  platform/generic/Kconfig             |  4 ++
> > > > >  platform/generic/configs/defconfig   |  1 +
> > > > >  platform/generic/starfive/jh7110.c   | 57
> > ++++++++++++++++++++++++++++
> > > > >  platform/generic/starfive/objects.mk |  6 +++
> > > > >  4 files changed, 68 insertions(+)  create mode 100644
> > > > > platform/generic/starfive/jh7110.c
> > > > >  create mode 100644 platform/generic/starfive/objects.mk
> > > > >
> > > > > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> > > > > index
> > > > > 62c7a2d..47c10e5 100644
> > > > > --- a/platform/generic/Kconfig
> > > > > +++ b/platform/generic/Kconfig
> > > > > @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> > > > >         depends on FDT_RESET && FDT_I2C
> > > > >         default n
> > > > >
> > > > > +config PLATFORM_STARFIVE_JH7110
> > > > > +       bool "StarFive JH7110 support"
> > > > > +       default n
> > > > > +
> > > > >  endif
> > > > > diff --git a/platform/generic/configs/defconfig
> > > > > b/platform/generic/configs/defconfig
> > > > > index 47fca95..4b0842e 100644
> > > > > --- a/platform/generic/configs/defconfig
> > > > > +++ b/platform/generic/configs/defconfig
> > > > > @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> > > > > CONFIG_PLATFORM_RENESAS_RZFIVE=y
> > > > CONFIG_PLATFORM_SIFIVE_FU540=y
> > > > > CONFIG_PLATFORM_SIFIVE_FU740=y
> > > > > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> > > > >  CONFIG_FDT_GPIO=y
> > > > >  CONFIG_FDT_GPIO_SIFIVE=y
> > > > >  CONFIG_FDT_I2C=y
> > > > > diff --git a/platform/generic/starfive/jh7110.c
> > > > > b/platform/generic/starfive/jh7110.c
> > > > > new file mode 100644
> > > > > index 0000000..5d3ab6f
> > > > > --- /dev/null
> > > > > +++ b/platform/generic/starfive/jh7110.c
> > > > > @@ -0,0 +1,57 @@
> > > > > +/*
> > > > > + * SPDX-License-Identifier: BSD-2-Clause
> > > > > + *
> > > > > + * Copyright (c) 2022 StarFive
> > > > > + *
> > > > > + * Authors:
> > > > > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > > > > + */
> > > > > +
> > > > > +#include <libfdt.h>
> > > > > +#include <platform_override.h>
> > > > > +#include <sbi_utils/fdt/fdt_helper.h>
> > > > > +
> > > > > +static bool hart_cold_booted = FALSE;
> > > > > +
> > > > > +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> > > > > +                                  const struct fdt_match *match) {
> > > > > +       const fdt32_t *val;
> > > > > +       int len, coff;
> > > > > +
> > > > > +       if (hart_cold_booted)
> > > > > +               return FALSE;
> > > > > +
> > > > > +       void *fdt = fdt_get_address();
> > > >
> > > > starfive_jh7110_cold_boot_allowed() will be called at runtime during
> > > > CPU hotplug or CPU non-retentive suspend so don't access FDT in this
> > > > function because it might have been corrupted/over-written by S-mode
> > software.
> > > >
> > > > You can save data from FDT in starfive_jh7110_early_init() when
> > > > cold_boot == TRUE.
> > > >
> > > The problem is early_init() is called from init_coldboot() and
> > > init_warm_startup() which is right after cold_boot_allowed(). Therefore, we
> > have to access the FDT here, this is why we add a 'hart_cold_booted' boolean
> > to ensure the FDT will not be accessed again once the FDT is read in cold boot
> > path for the first time.
> > > This is to avoid the issue you mentioned above. The code here already
> > > ensure the FDT will not be accessed again when the cold_boot_allowed()
> > > function is called during HSM SBI calls. This is the reason in the beginning of
> > the cold_boot_allowed() function, we check whether the 'hart_cold_booted' is
> > set to TRUE which mean the FDT should not be accessed again.
> >
> > I see but there is another way to do this.
> >
> > You do the following as a separate PATCH before this PATCH:
> > 1) Add "void (*fw_init)(void *fdt, const struct fdt_match *match)" in
> >     "struct platform_override"
> > 2) Update fw_platform_init() to call generic_plat->fw_init() right
> >    after fw_platform_lookup_special() call.
> >
> > Your current patch can simply implement fw_init() callback which will parse
> > the chosen boot-hart-id. You will not need hart_cold_booted boolean with this
> > approach.
> Thanks. Will do. This shall also resolved Xiang's comment in other thread that the FDT is read multiple times when multiple
> harts call cold_boot_allowed(). I believe the fw_platform_init() in fw_base.S is only called once from initial boot hart.
> I don't think fdt_get_address() can be called in fw_platform_init() as the scratch area is not initialized yet.
> But I think we can still get the FDT location from one of the arguments passed to fw_platform_init().

Yes, fw_base.S ensures that only one HART calls fw_platform_init().

Regards,
Anup

> >
> > Regards,
> > Anup
> >
> > >
> > > > Regards,
> > > > Anup
> > > >
> > > > > +
> > > > > +       coff = fdt_path_offset(fdt, "/chosen");
> > > > > +       if (-1 < coff) {
> > > > > +               val = fdt_getprop(fdt, coff, "boot-hart", &len);
> > > > > +               if (val && len) {
> > > > > +                       u32 selected_hartid = (u32) fdt32_to_cpu(*val);
> > > > > +                       return (selected_hartid == hartid);
> > > > > +               }
> > > > > +       }
> > > > > +
> > > > > +       return TRUE;
> > > > > +}
> > > > > +
> > > > > +static int starfive_jh7110_early_init(bool cold_boot,
> > > > > +                                  const struct fdt_match *match) {
> > > > > +       if (cold_boot)
> > > > > +               hart_cold_booted = TRUE;
> > > > > +
> > > > > +       return 0;
> > > > > +}
> > > > > +
> > > > > +static const struct fdt_match starfive_jh7110_match[] = {
> > > > > +       { .compatible = "starfive,jh7110" },
> > > > > +       { },
> > > > > +};
> > > > > +
> > > > > +const struct platform_override starfive_jh7110 = {
> > > > > +       .match_table = starfive_jh7110_match,
> > > > > +       .early_init = starfive_jh7110_early_init,
> > > > > +       .cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> > > > > +};
> > > > > diff --git a/platform/generic/starfive/objects.mk
> > > > > b/platform/generic/starfive/objects.mk
> > > > > new file mode 100644
> > > > > index 0000000..0b900fb
> > > > > --- /dev/null
> > > > > +++ b/platform/generic/starfive/objects.mk
> > > > > @@ -0,0 +1,6 @@
> > > > > +#
> > > > > +# SPDX-License-Identifier: BSD-2-Clause #
> > > > > +
> > > > > +carray-platform_override_modules-
> > > > $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > > > > ++= starfive_jh7110
> > > > > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> > > > starfive/jh7110.o
> > > > > --
> > > > > 2.25.1
> > > > >
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From peterlin at andestech.com  Tue Dec 20 14:12:29 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Tue, 20 Dec 2022 22:12:29 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <Y6IzTcaMxw9JjBW3@APC323>

On Mon, Dec 12, 2022 at 09:44:21AM +0000, Lad Prabhakar wrote:
> Add support to configure the PMA regions and create a corresponding
> reserve memory node and propagate it to the higher boot stack.
> 
> &L2 {
>        andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
>                                 (AX45MP_PMACFG_ETYP_NAPOT |
>                                  AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
> };
> 
> PMA regions are passed as part of L2 cache node to OpenSBI, these regions
> are parsed and configured in the OpenSBI.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> Hi All,
> 
> This patch is based on the discussion [0] so sending this as an RFC
> patch so that we get the Linux side of things accepeted first and once its
> finalized I'll send a non RFC patch for this.
> 
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> 
> Cheers,
> Prabhakar
> ---
>  platform/generic/renesas/rzfive/objects.mk   |   1 +
>  platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
>  platform/generic/renesas/rzfive/rzfive-pma.h |  12 +
>  platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
>  4 files changed, 421 insertions(+)
>  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
>  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h
> 
> diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
> index 2e7e37f..d666417 100644
> --- a/platform/generic/renesas/rzfive/objects.mk
> +++ b/platform/generic/renesas/rzfive/objects.mk
> @@ -6,3 +6,4 @@
>  
>  carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
>  platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
> +platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive-pma.o
> diff --git a/platform/generic/renesas/rzfive/rzfive-pma.c b/platform/generic/renesas/rzfive/rzfive-pma.c
> new file mode 100644
> index 0000000..a3c0126
> --- /dev/null
> +++ b/platform/generic/renesas/rzfive/rzfive-pma.c
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + * Copyright (c) 2020 Andes Technology Corporation
> + *
> + * Authors:
> + *      Nick Hu <nickhu at andestech.com>
> + *      Nylon Chen <nylon7 at andestech.com>
> + */
> +
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_error.h>
> +
> +/* Configuration Registers */
> +#define CSR_MMSC_CFG		0xfc2

MMSC_CFG is redefined in rzfive.c.

> +
> +#define PMA_MMSC_CFG		(1 << 30)
> +
> +#define PMAADDR_0		0xBD0
> +#define PMAADDR_1		0xBD1
> +#define PMAADDR_2		0xBD2
> +#define PMAADDR_3		0xBD3
> +#define PMAADDR_4		0xBD4
> +#define PMAADDR_5		0xBD5
> +#define PMAADDR_6		0xBD6
> +#define PMAADDR_7		0xBD7
> +#define PMAADDR_8		0xBD8
> +#define PMAADDR_9		0xBD9
> +#define PMAADDR_10		0xBDA
> +#define PMAADDR_11		0xBDB
> +#define PMAADDR_12		0xBDC
> +#define PMAADDR_13		0xBDD
> +#define PMAADDR_14		0xBDE
> +#define PMAADDR_15		0xBDF
> +
> +/* n = 0 - 3 */
> +#define PMACFG_n(n)		(0xbc0 + (n))
> +
> +static inline unsigned long rzfive_read_pmacfg(unsigned int i)
> +{
> +	unsigned long val = 0;
> +
> +	if (!i)
> +		val = csr_read(PMACFG_n(0));
> +	else if (i == 1)
> +		val = csr_read(PMACFG_n(2));
> +
> +	return val;
> +}
> +
> +static inline void rzfive_write_pmacfg(unsigned int i, unsigned long val)
> +{
> +	if (!i)
> +		csr_write(PMACFG_n(0), val);
> +	else if (i == 1)
> +		csr_write(PMACFG_n(2), val);
> +}
> +
> +static inline void rzfive_write_pmaaddr(unsigned int i, unsigned long val)
> +{

> +	if (i == 0)
> +		csr_write(PMAADDR_0, val);
> +	else if (i == 1)
> +		csr_write(PMAADDR_1, val);
> +	else if (i == 2)
> +		csr_write(PMAADDR_2, val);
> +	else if (i == 3)
> +		csr_write(PMAADDR_3, val);
> +	else if (i == 4)
> +		csr_write(PMAADDR_4, val);
> +	else if (i == 5)
> +		csr_write(PMAADDR_5, val);
> +	else if (i == 6)
> +		csr_write(PMAADDR_6, val);
> +	else if (i == 7)
> +		csr_write(PMAADDR_7, val);
> +	else if (i == 8)
> +		csr_write(PMAADDR_8, val);
> +	else if (i == 9)
> +		csr_write(PMAADDR_9, val);
> +	else if (i == 10)
> +		csr_write(PMAADDR_10, val);
> +	else if (i == 11)
> +		csr_write(PMAADDR_11, val);
> +	else if (i == 12)
> +		csr_write(PMAADDR_12, val);
> +	else if (i == 13)
> +		csr_write(PMAADDR_13, val);
> +	else if (i == 14)
> +		csr_write(PMAADDR_14, val);
> +	else if (i == 15)
> +		csr_write(PMAADDR_15, val);
> +}
> +
> +static inline unsigned long rzfive_read_pmaaddr(unsigned int i)
> +{
> +	unsigned long ret = 0;
> +
> +	if (i == 0)
> +		ret = csr_read(PMAADDR_0);
> +	else if (i == 1)
> +		ret = csr_read(PMAADDR_1);
> +	else if (i == 2)
> +		ret = csr_read(PMAADDR_2);
> +	else if (i == 3)
> +		ret = csr_read(PMAADDR_3);
> +	else if (i == 4)
> +		ret = csr_read(PMAADDR_4);
> +	else if (i == 5)
> +		ret = csr_read(PMAADDR_5);
> +	else if (i == 6)
> +		ret =  csr_read(PMAADDR_6);
            ^
            a space added

> +	else if (i == 7)
> +		ret = csr_read(PMAADDR_7);
> +	else if (i == 8)
> +		ret = csr_read(PMAADDR_8);
> +	else if (i == 9)
> +		ret = csr_read(PMAADDR_9);
> +	else if (i == 10)
> +		ret = csr_read(PMAADDR_10);
> +	else if (i == 11)
> +		ret = csr_read(PMAADDR_11);
> +	else if (i == 12)
> +		ret = csr_read(PMAADDR_12);
> +	else if (i == 13)
> +		ret = csr_read(PMAADDR_13);
> +	else if (i == 14)
> +		ret = csr_read(PMAADDR_14);
> +	else if (i == 15)
> +		ret = csr_read(PMAADDR_15);
> +
> +	return ret;
> +}
> +
> +unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
> +				      int entry_id, u32 flag)
> +{
> +	unsigned long size_tmp, shift = 0, pmacfg_val;
> +	unsigned long mmsc = csr_read(CSR_MMSC_CFG);
> +	unsigned long pa = addr;
> +	char *pmaxcfg;
> +	int power = 0;
> +

The granularity of PMA NAPOT mode is 4KiB, so we should not allow this
case.

if (size < (1 << 12))
  return SBI_EINVAL;

> +	if (flag > 0xff || entry_id > 15)
> +		return SBI_EINVAL;
> +
> +	if ((mmsc & PMA_MMSC_CFG) == 0)
> +		return 0;
             ^
             SBI_ENOTSUPP
Can we rename this field as PPMA_MMCS_CFG, which is the same name
in the datasheet?

> +
> +	size_tmp = size;
> +	if ((pa & (size_tmp - 1)) != 0) {
> +		pa = pa & ~(size_tmp - 1);
> +		size_tmp = size_tmp << 1;

PMA only has NAPOT mode, maybe return SBI_EINVAL here?

> +	}
> +
> +	/* Calculate the NAPOT table for pmaaddr */
> +	size_tmp = size;
> +	while (size_tmp != 0x1) {
> +		size_tmp = size_tmp >> 1;
> +		power++;
> +		if (power > 3)
> +			shift = (shift << 1) | 0x1;
> +	}
> +
> +	pmacfg_val = rzfive_read_pmacfg(entry_id / 8);
> +	pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
> +	*pmaxcfg = 0;
> +	*pmaxcfg = (u8)flag;
> +
> +	rzfive_write_pmacfg(entry_id / 8, pmacfg_val);
> +
> +	pa = pa >> 2;
> +	pa |= shift;
> +	pa = pa & ~(0x1 << (power - 3));
> +

Can we simplify the logic to calculate the value of pmaaddr?

If addr = 0x58000000
   size = 0x08000000

pmaaddr = (addr >> 2) + (size >> 3) - 1 = 0x16ffffff


Best regards,
Peter Lin


From prabhakar.csengg at gmail.com  Tue Dec 20 16:38:49 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Wed, 21 Dec 2022 00:38:49 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <Y6IzTcaMxw9JjBW3@APC323>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <Y6IzTcaMxw9JjBW3@APC323>
Message-ID: <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>

Hi Yu-Chien,

Thank you for the review.

On Tue, Dec 20, 2022 at 2:16 PM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> On Mon, Dec 12, 2022 at 09:44:21AM +0000, Lad Prabhakar wrote:
> > Add support to configure the PMA regions and create a corresponding
> > reserve memory node and propagate it to the higher boot stack.
> >
> > &L2 {
> >        andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
> >                                 (AX45MP_PMACFG_ETYP_NAPOT |
> >                                  AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
> > };
> >
> > PMA regions are passed as part of L2 cache node to OpenSBI, these regions
> > are parsed and configured in the OpenSBI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > Hi All,
> >
> > This patch is based on the discussion [0] so sending this as an RFC
> > patch so that we get the Linux side of things accepeted first and once its
> > finalized I'll send a non RFC patch for this.
> >
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> >
> > Cheers,
> > Prabhakar
> > ---
> >  platform/generic/renesas/rzfive/objects.mk   |   1 +
> >  platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
> >  platform/generic/renesas/rzfive/rzfive-pma.h |  12 +
> >  platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
> >  4 files changed, 421 insertions(+)
> >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
> >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h
> >
> > diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
> > index 2e7e37f..d666417 100644
> > --- a/platform/generic/renesas/rzfive/objects.mk
> > +++ b/platform/generic/renesas/rzfive/objects.mk
> > @@ -6,3 +6,4 @@
> >
> >  carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
> >  platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
> > +platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive-pma.o
> > diff --git a/platform/generic/renesas/rzfive/rzfive-pma.c b/platform/generic/renesas/rzfive/rzfive-pma.c
> > new file mode 100644
> > index 0000000..a3c0126
> > --- /dev/null
> > +++ b/platform/generic/renesas/rzfive/rzfive-pma.c
> > @@ -0,0 +1,181 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + *
> > + * Copyright (c) 2020 Andes Technology Corporation
> > + *
> > + * Authors:
> > + *      Nick Hu <nickhu at andestech.com>
> > + *      Nylon Chen <nylon7 at andestech.com>
> > + */
> > +
> > +#include <sbi/riscv_asm.h>
> > +#include <sbi/riscv_io.h>
> > +#include <sbi/sbi_error.h>
> > +
> > +/* Configuration Registers */
> > +#define CSR_MMSC_CFG         0xfc2
>
> MMSC_CFG is redefined in rzfive.c.
>
I'll move this to header and share the offsets,

> > +
> > +#define PMA_MMSC_CFG         (1 << 30)
> > +
> > +#define PMAADDR_0            0xBD0
> > +#define PMAADDR_1            0xBD1
> > +#define PMAADDR_2            0xBD2
> > +#define PMAADDR_3            0xBD3
> > +#define PMAADDR_4            0xBD4
> > +#define PMAADDR_5            0xBD5
> > +#define PMAADDR_6            0xBD6
> > +#define PMAADDR_7            0xBD7
> > +#define PMAADDR_8            0xBD8
> > +#define PMAADDR_9            0xBD9
> > +#define PMAADDR_10           0xBDA
> > +#define PMAADDR_11           0xBDB
> > +#define PMAADDR_12           0xBDC
> > +#define PMAADDR_13           0xBDD
> > +#define PMAADDR_14           0xBDE
> > +#define PMAADDR_15           0xBDF
> > +
> > +/* n = 0 - 3 */
> > +#define PMACFG_n(n)          (0xbc0 + (n))
> > +
> > +static inline unsigned long rzfive_read_pmacfg(unsigned int i)
> > +{
> > +     unsigned long val = 0;
> > +
> > +     if (!i)
> > +             val = csr_read(PMACFG_n(0));
> > +     else if (i == 1)
> > +             val = csr_read(PMACFG_n(2));
> > +
> > +     return val;
> > +}
> > +
> > +static inline void rzfive_write_pmacfg(unsigned int i, unsigned long val)
> > +{
> > +     if (!i)
> > +             csr_write(PMACFG_n(0), val);
> > +     else if (i == 1)
> > +             csr_write(PMACFG_n(2), val);
> > +}
> > +
> > +static inline void rzfive_write_pmaaddr(unsigned int i, unsigned long val)
> > +{
>
> > +     if (i == 0)
> > +             csr_write(PMAADDR_0, val);
> > +     else if (i == 1)
> > +             csr_write(PMAADDR_1, val);
> > +     else if (i == 2)
> > +             csr_write(PMAADDR_2, val);
> > +     else if (i == 3)
> > +             csr_write(PMAADDR_3, val);
> > +     else if (i == 4)
> > +             csr_write(PMAADDR_4, val);
> > +     else if (i == 5)
> > +             csr_write(PMAADDR_5, val);
> > +     else if (i == 6)
> > +             csr_write(PMAADDR_6, val);
> > +     else if (i == 7)
> > +             csr_write(PMAADDR_7, val);
> > +     else if (i == 8)
> > +             csr_write(PMAADDR_8, val);
> > +     else if (i == 9)
> > +             csr_write(PMAADDR_9, val);
> > +     else if (i == 10)
> > +             csr_write(PMAADDR_10, val);
> > +     else if (i == 11)
> > +             csr_write(PMAADDR_11, val);
> > +     else if (i == 12)
> > +             csr_write(PMAADDR_12, val);
> > +     else if (i == 13)
> > +             csr_write(PMAADDR_13, val);
> > +     else if (i == 14)
> > +             csr_write(PMAADDR_14, val);
> > +     else if (i == 15)
> > +             csr_write(PMAADDR_15, val);
> > +}
> > +
> > +static inline unsigned long rzfive_read_pmaaddr(unsigned int i)
> > +{
> > +     unsigned long ret = 0;
> > +
> > +     if (i == 0)
> > +             ret = csr_read(PMAADDR_0);
> > +     else if (i == 1)
> > +             ret = csr_read(PMAADDR_1);
> > +     else if (i == 2)
> > +             ret = csr_read(PMAADDR_2);
> > +     else if (i == 3)
> > +             ret = csr_read(PMAADDR_3);
> > +     else if (i == 4)
> > +             ret = csr_read(PMAADDR_4);
> > +     else if (i == 5)
> > +             ret = csr_read(PMAADDR_5);
> > +     else if (i == 6)
> > +             ret =  csr_read(PMAADDR_6);
>             ^
>             a space added
>
I will drop that.

> > +     else if (i == 7)
> > +             ret = csr_read(PMAADDR_7);
> > +     else if (i == 8)
> > +             ret = csr_read(PMAADDR_8);
> > +     else if (i == 9)
> > +             ret = csr_read(PMAADDR_9);
> > +     else if (i == 10)
> > +             ret = csr_read(PMAADDR_10);
> > +     else if (i == 11)
> > +             ret = csr_read(PMAADDR_11);
> > +     else if (i == 12)
> > +             ret = csr_read(PMAADDR_12);
> > +     else if (i == 13)
> > +             ret = csr_read(PMAADDR_13);
> > +     else if (i == 14)
> > +             ret = csr_read(PMAADDR_14);
> > +     else if (i == 15)
> > +             ret = csr_read(PMAADDR_15);
> > +
> > +     return ret;
> > +}
> > +
> > +unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
> > +                                   int entry_id, u32 flag)
> > +{
> > +     unsigned long size_tmp, shift = 0, pmacfg_val;
> > +     unsigned long mmsc = csr_read(CSR_MMSC_CFG);
> > +     unsigned long pa = addr;
> > +     char *pmaxcfg;
> > +     int power = 0;
> > +
>
> The granularity of PMA NAPOT mode is 4KiB, so we should not allow this
> case.
>
> if (size < (1 << 12))
>   return SBI_EINVAL;
>
The manual I am referring to says "The minimal size of NAPOT regions
must be 8 bytes."

> > +     if (flag > 0xff || entry_id > 15)
> > +             return SBI_EINVAL;
> > +
> > +     if ((mmsc & PMA_MMSC_CFG) == 0)
> > +             return 0;
>              ^
>              SBI_ENOTSUPP
> Can we rename this field as PPMA_MMCS_CFG, which is the same name
> in the datasheet?
>
Sure will do.

> > +
> > +     size_tmp = size;
> > +     if ((pa & (size_tmp - 1)) != 0) {
> > +             pa = pa & ~(size_tmp - 1);
> > +             size_tmp = size_tmp << 1;
>
> PMA only has NAPOT mode, maybe return SBI_EINVAL here?
>
Agreed.

> > +     }
> > +
> > +     /* Calculate the NAPOT table for pmaaddr */
> > +     size_tmp = size;
> > +     while (size_tmp != 0x1) {
> > +             size_tmp = size_tmp >> 1;
> > +             power++;
> > +             if (power > 3)
> > +                     shift = (shift << 1) | 0x1;
> > +     }
> > +
> > +     pmacfg_val = rzfive_read_pmacfg(entry_id / 8);
> > +     pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
> > +     *pmaxcfg = 0;
> > +     *pmaxcfg = (u8)flag;
> > +
> > +     rzfive_write_pmacfg(entry_id / 8, pmacfg_val);
> > +
> > +     pa = pa >> 2;
> > +     pa |= shift;
> > +     pa = pa & ~(0x1 << (power - 3));
> > +
>
> Can we simplify the logic to calculate the value of pmaaddr?
>
> If addr = 0x58000000
>    size = 0x08000000
>
> pmaaddr = (addr >> 2) + (size >> 3) - 1 = 0x16ffffff
>
Ok I'll simply as above.

Cheers,
Prabhakar


From bmeng.cn at gmail.com  Tue Dec 20 17:23:21 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 09:23:21 +0800
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Message-ID: <CAEUhbmW5WmNSPNNe4UWq6o7ZtOgT=9N5f2=F6L+ScLSzW_K8dQ@mail.gmail.com>

On Mon, Dec 12, 2022 at 5:44 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
>
> Add support to configure the PMA regions and create a corresponding
> reserve memory node and propagate it to the higher boot stack.
>
> &L2 {
>        andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
>                                 (AX45MP_PMACFG_ETYP_NAPOT |
>                                  AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
> };
>
> PMA regions are passed as part of L2 cache node to OpenSBI, these regions
> are parsed and configured in the OpenSBI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> ---
> Hi All,
>
> This patch is based on the discussion [0] so sending this as an RFC
> patch so that we get the Linux side of things accepeted first and once its
> finalized I'll send a non RFC patch for this.
>
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
>
> Cheers,
> Prabhakar
> ---
>  platform/generic/renesas/rzfive/objects.mk   |   1 +
>  platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
>  platform/generic/renesas/rzfive/rzfive-pma.h |  12 +

I feel we should name this to something like ax45mp-pma instead of
rzfive-pma, as this is at the core configuration level not SoC's, no?

>  platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
>  4 files changed, 421 insertions(+)
>  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
>  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h
>
> diff --git a/platform/generic/renesas/rzfive/objects.mk b/platform/generic/renesas/rzfive/objects.mk
> index 2e7e37f..d666417 100644
> --- a/platform/generic/renesas/rzfive/objects.mk
> +++ b/platform/generic/renesas/rzfive/objects.mk
> @@ -6,3 +6,4 @@
>
>  carray-platform_override_modules-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas_rzfive
>  platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive.o
> +platform-objs-$(CONFIG_PLATFORM_RENESAS_RZFIVE) += renesas/rzfive/rzfive-pma.o
> diff --git a/platform/generic/renesas/rzfive/rzfive-pma.c b/platform/generic/renesas/rzfive/rzfive-pma.c
> new file mode 100644
> index 0000000..a3c0126
> --- /dev/null
> +++ b/platform/generic/renesas/rzfive/rzfive-pma.c
> @@ -0,0 +1,181 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + *
> + * Copyright (c) 2020 Andes Technology Corporation
> + *
> + * Authors:
> + *      Nick Hu <nickhu at andestech.com>
> + *      Nylon Chen <nylon7 at andestech.com>
> + */
> +
> +#include <sbi/riscv_asm.h>
> +#include <sbi/riscv_io.h>
> +#include <sbi/sbi_error.h>
> +
> +/* Configuration Registers */
> +#define CSR_MMSC_CFG           0xfc2
> +
> +#define PMA_MMSC_CFG           (1 << 30)
> +
> +#define PMAADDR_0              0xBD0
> +#define PMAADDR_1              0xBD1
> +#define PMAADDR_2              0xBD2
> +#define PMAADDR_3              0xBD3
> +#define PMAADDR_4              0xBD4
> +#define PMAADDR_5              0xBD5
> +#define PMAADDR_6              0xBD6
> +#define PMAADDR_7              0xBD7
> +#define PMAADDR_8              0xBD8
> +#define PMAADDR_9              0xBD9
> +#define PMAADDR_10             0xBDA
> +#define PMAADDR_11             0xBDB
> +#define PMAADDR_12             0xBDC
> +#define PMAADDR_13             0xBDD
> +#define PMAADDR_14             0xBDE
> +#define PMAADDR_15             0xBDF
> +
> +/* n = 0 - 3 */
> +#define PMACFG_n(n)            (0xbc0 + (n))
> +
> +static inline unsigned long rzfive_read_pmacfg(unsigned int i)
> +{
> +       unsigned long val = 0;
> +
> +       if (!i)
> +               val = csr_read(PMACFG_n(0));
> +       else if (i == 1)
> +               val = csr_read(PMACFG_n(2));
> +
> +       return val;
> +}
> +
> +static inline void rzfive_write_pmacfg(unsigned int i, unsigned long val)
> +{
> +       if (!i)
> +               csr_write(PMACFG_n(0), val);
> +       else if (i == 1)
> +               csr_write(PMACFG_n(2), val);
> +}
> +
> +static inline void rzfive_write_pmaaddr(unsigned int i, unsigned long val)
> +{
> +       if (i == 0)
> +               csr_write(PMAADDR_0, val);
> +       else if (i == 1)
> +               csr_write(PMAADDR_1, val);
> +       else if (i == 2)
> +               csr_write(PMAADDR_2, val);
> +       else if (i == 3)
> +               csr_write(PMAADDR_3, val);
> +       else if (i == 4)
> +               csr_write(PMAADDR_4, val);
> +       else if (i == 5)
> +               csr_write(PMAADDR_5, val);
> +       else if (i == 6)
> +               csr_write(PMAADDR_6, val);
> +       else if (i == 7)
> +               csr_write(PMAADDR_7, val);
> +       else if (i == 8)
> +               csr_write(PMAADDR_8, val);
> +       else if (i == 9)
> +               csr_write(PMAADDR_9, val);
> +       else if (i == 10)
> +               csr_write(PMAADDR_10, val);
> +       else if (i == 11)
> +               csr_write(PMAADDR_11, val);
> +       else if (i == 12)
> +               csr_write(PMAADDR_12, val);
> +       else if (i == 13)
> +               csr_write(PMAADDR_13, val);
> +       else if (i == 14)
> +               csr_write(PMAADDR_14, val);
> +       else if (i == 15)
> +               csr_write(PMAADDR_15, val);
> +}
> +
> +static inline unsigned long rzfive_read_pmaaddr(unsigned int i)
> +{
> +       unsigned long ret = 0;
> +
> +       if (i == 0)
> +               ret = csr_read(PMAADDR_0);
> +       else if (i == 1)
> +               ret = csr_read(PMAADDR_1);
> +       else if (i == 2)
> +               ret = csr_read(PMAADDR_2);
> +       else if (i == 3)
> +               ret = csr_read(PMAADDR_3);
> +       else if (i == 4)
> +               ret = csr_read(PMAADDR_4);
> +       else if (i == 5)
> +               ret = csr_read(PMAADDR_5);
> +       else if (i == 6)
> +               ret =  csr_read(PMAADDR_6);
> +       else if (i == 7)
> +               ret = csr_read(PMAADDR_7);
> +       else if (i == 8)
> +               ret = csr_read(PMAADDR_8);
> +       else if (i == 9)
> +               ret = csr_read(PMAADDR_9);
> +       else if (i == 10)
> +               ret = csr_read(PMAADDR_10);
> +       else if (i == 11)
> +               ret = csr_read(PMAADDR_11);
> +       else if (i == 12)
> +               ret = csr_read(PMAADDR_12);
> +       else if (i == 13)
> +               ret = csr_read(PMAADDR_13);
> +       else if (i == 14)
> +               ret = csr_read(PMAADDR_14);
> +       else if (i == 15)
> +               ret = csr_read(PMAADDR_15);
> +
> +       return ret;
> +}
> +
> +unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
> +                                     int entry_id, u32 flag)
> +{
> +       unsigned long size_tmp, shift = 0, pmacfg_val;
> +       unsigned long mmsc = csr_read(CSR_MMSC_CFG);
> +       unsigned long pa = addr;
> +       char *pmaxcfg;
> +       int power = 0;
> +
> +       if (flag > 0xff || entry_id > 15)
> +               return SBI_EINVAL;
> +
> +       if ((mmsc & PMA_MMSC_CFG) == 0)
> +               return 0;
> +
> +       size_tmp = size;
> +       if ((pa & (size_tmp - 1)) != 0) {
> +               pa = pa & ~(size_tmp - 1);
> +               size_tmp = size_tmp << 1;
> +       }
> +
> +       /* Calculate the NAPOT table for pmaaddr */
> +       size_tmp = size;
> +       while (size_tmp != 0x1) {
> +               size_tmp = size_tmp >> 1;
> +               power++;
> +               if (power > 3)
> +                       shift = (shift << 1) | 0x1;
> +       }
> +
> +       pmacfg_val = rzfive_read_pmacfg(entry_id / 8);
> +       pmaxcfg = (char *)&pmacfg_val + (entry_id % 8);
> +       *pmaxcfg = 0;
> +       *pmaxcfg = (u8)flag;
> +
> +       rzfive_write_pmacfg(entry_id / 8, pmacfg_val);
> +
> +       pa = pa >> 2;
> +       pa |= shift;
> +       pa = pa & ~(0x1 << (power - 3));
> +
> +       rzfive_write_pmaaddr(entry_id, pa);
> +
> +       return rzfive_read_pmaaddr(entry_id) == pa ? pa : SBI_EINVAL;
> +}
> diff --git a/platform/generic/renesas/rzfive/rzfive-pma.h b/platform/generic/renesas/rzfive/rzfive-pma.h
> new file mode 100644
> index 0000000..0ae3b79
> --- /dev/null
> +++ b/platform/generic/renesas/rzfive/rzfive-pma.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#ifndef _RZFIVE_PMA_H_
> +#define _RZFIVE_PMA_H_
> +
> +unsigned long rzfive_setup_pma_region(unsigned long pa, unsigned long size,
> +                                     int entry_id, u32 flag);
> +
> +#endif /* _RZFIVE_PMA_H_ */
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> index ca182e3..356df07 100644
> --- a/platform/generic/renesas/rzfive/rzfive.c
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -4,9 +4,234 @@
>   *
>   */
>
> +#include <libfdt.h>
>  #include <platform_override.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_console.h>
>  #include <sbi_utils/fdt/fdt_helper.h>
>
> +#include "rzfive-pma.h"
> +
> +/* AX45MP registers */
> +#define AX45MP_CSR_MISA_CFG                    0x301
> +#define AX45MP_CSR_MICM_CFG                    0xfc0
> +#define AX45MP_CSR_MDCM_CFG                    0xfc1
> +#define AX45MP_CSR_MMSC_CFG                    0xfc2
> +#define AX45MP_CSR_MCACHE_CTL                  0x7ca
> +
> +/* AX45MP register bit offsets and masks */
> +#define AX45MP_MISA_20_OFFSET                  20
> +#define AX45MP_MISA_20_MASK                    (0x1 << AX45MP_MISA_20_OFFSET)
> +
> +#define AX45MP_MICM_CFG_ISZ_OFFSET             6
> +#define AX45MP_MICM_CFG_ISZ_MASK               (0x7  << AX45MP_MICM_CFG_ISZ_OFFSET)
> +
> +#define AX45MP_MDCM_CFG_DSZ_OFFSET             6
> +#define AX45MP_MDCM_CFG_DSZ_MASK               (0x7  << AX45MP_MDCM_CFG_DSZ_OFFSET)
> +
> +#define AX45MP_MMSC_CFG_CCTLCSR_OFFSET         16
> +#define AX45MP_MMSC_CFG_CCTLCSR_MASK           (0x1 << AX45MP_MMSC_CFG_CCTLCSR_OFFSET)
> +#define AX45MP_MMSC_IOCP_OFFSET                        47
> +#define AX45MP_MMSC_IOCP_MASK                  (0x1ULL << AX45MP_MMSC_IOCP_OFFSET)
> +
> +#define AX45MP_MCACHE_CTL_CCTL_SUEN_OFFSET     8
> +#define AX45MP_MCACHE_CTL_CCTL_SUEN_MASK       (0x1 << AX45MP_MCACHE_CTL_CCTL_SUEN_OFFSET)
> +
> +#define AX45MP_MAX_PMA_REGIONS                 16
> +
> +enum rzfive_sbi_ext_fid {
> +       RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND = 0,
> +};
> +
> +static bool rzfive_cpu_cache_controlable(void)
> +{
> +       return (((csr_read(AX45MP_CSR_MICM_CFG) & AX45MP_MICM_CFG_ISZ_MASK) ||
> +                (csr_read(AX45MP_CSR_MDCM_CFG) & AX45MP_MDCM_CFG_DSZ_MASK)) &&
> +               (csr_read(AX45MP_CSR_MISA_CFG) & AX45MP_MISA_20_MASK) &&
> +               (csr_read(AX45MP_CSR_MMSC_CFG) & AX45MP_MMSC_CFG_CCTLCSR_MASK) &&
> +               (csr_read(AX45MP_CSR_MCACHE_CTL) & AX45MP_MCACHE_CTL_CCTL_SUEN_MASK));
> +}
> +
> +static bool rzfive_cpu_iocp_disabled(void)
> +{
> +       return (csr_read(AX45MP_CSR_MMSC_CFG) & AX45MP_MMSC_IOCP_MASK) ? false : true;
> +}
> +
> +static bool rzfive_apply_iocp_sw_workaround(void)
> +{
> +       return rzfive_cpu_cache_controlable() & rzfive_cpu_iocp_disabled();
> +}
> +
> +static int fdt_resv_memory_update_node(void *fdt, unsigned long addr,
> +                                      unsigned long size, int index,
> +                                      int parent)
> +{
> +       int na = fdt_address_cells(fdt, 0);
> +       int ns = fdt_size_cells(fdt, 0);
> +       fdt32_t addr_high, addr_low;
> +       fdt32_t size_high, size_low;
> +       int subnode, err;
> +       fdt32_t reg[4];
> +       fdt32_t *val;
> +       char name[32];
> +
> +       addr_high = (u64)addr >> 32;
> +       addr_low = addr;
> +       size_high = (u64)size >> 32;
> +       size_low = size;
> +
> +       if (na > 1 && addr_high)
> +               sbi_snprintf(name, sizeof(name),
> +                            "pma_resv%d@%x,%x", index,
> +                            addr_high, addr_low);
> +       else
> +               sbi_snprintf(name, sizeof(name),
> +                            "pma_resv%d@%x", index,
> +                            addr_low);
> +
> +       subnode = fdt_add_subnode(fdt, parent, name);
> +       if (subnode < 0)
> +               return subnode;
> +
> +       err = fdt_setprop_string(fdt, subnode, "compatible", "shared-dma-pool");
> +       if (err < 0)
> +               return err;
> +
> +       err = fdt_setprop_empty(fdt, subnode, "no-map");
> +       if (err < 0)
> +               return err;
> +
> +       /*
> +        * Linux allows single linux,dma-default region so lets mark
> +        * the first pma region as linux,dma-default
> +        */
> +       if (!index) {
> +               err = fdt_setprop_empty(fdt, subnode, "linux,dma-default");
> +               if (err < 0)
> +                       return err;
> +       }
> +
> +       /* encode the <reg> property value */
> +       val = reg;
> +       if (na > 1)
> +               *val++ = cpu_to_fdt32(addr_high);
> +       *val++ = cpu_to_fdt32(addr_low);
> +       if (ns > 1)
> +               *val++ = cpu_to_fdt32(size_high);
> +       *val++ = cpu_to_fdt32(size_low);
> +
> +       err = fdt_setprop(fdt, subnode, "reg", reg,
> +                         (na + ns) * sizeof(fdt32_t));
> +       if (err < 0)
> +               return err;
> +
> +       return 0;
> +}
> +
> +static int fdt_reserved_memory_fixup(void *fdt, unsigned long addr,
> +                                    unsigned long size, int entry)
> +{
> +       int na = fdt_address_cells(fdt, 0);
> +       int ns = fdt_size_cells(fdt, 0);
> +       int err, parent;
> +
> +       /* try to locate the reserved memory node */
> +       parent = fdt_path_offset(fdt, "/reserved-memory");
> +       if (parent < 0) {
> +               /* if such node does not exist, create one */
> +               parent = fdt_add_subnode(fdt, 0, "reserved-memory");
> +               if (parent < 0)
> +                       return parent;
> +
> +               err = fdt_setprop_empty(fdt, parent, "ranges");
> +               if (err < 0)
> +                       return err;
> +
> +               err = fdt_setprop_u32(fdt, parent, "#size-cells", ns);
> +               if (err < 0)
> +                       return err;
> +
> +               err = fdt_setprop_u32(fdt, parent, "#address-cells", na);
> +               if (err < 0)
> +                       return err;
> +       }
> +
> +       return fdt_resv_memory_update_node(fdt, addr, size, entry, parent);
> +}
> +
> +static int rzfive_configure_pma_regions(void)
> +{
> +       void *fdt = fdt_get_address();
> +       unsigned long start[16], size[16];
> +       unsigned long pma_addr;
> +       unsigned int i, j;
> +       int cells_count;
> +       u32 flags[16];
> +       int l2c_off;
> +       u32 *cells;
> +       int ret;
> +
> +       l2c_off = fdt_node_offset_by_compatible(fdt, 0, "v5l2cache");
> +       if (l2c_off < 0)
> +               return 0;
> +
> +       cells = (u32 *)fdt_getprop(fdt, l2c_off,
> +                                  "andestech,pma-regions", &cells_count);
> +       if (!cells)
> +               return 0;
> +
> +       cells_count = cells_count / sizeof(u32);
> +       if (!cells_count)
> +               return 0;
> +
> +       if (cells_count % 5 || (cells_count / 5) > AX45MP_MAX_PMA_REGIONS)
> +               return SBI_EINVAL;
> +
> +       for (i = 0, j = 0; i < cells_count; i += 5, j++) {
> +               start[j] = ((u64)fdt32_to_cpu(cells[i]) << 32) | fdt32_to_cpu(cells[i + 1]);
> +               size[j] = ((u64)fdt32_to_cpu(cells[i + 2]) << 32) | fdt32_to_cpu(cells[i + 3]);
> +               flags[j] = fdt32_to_cpu(cells[i + 4]);
> +               pma_addr = rzfive_setup_pma_region(start[j], size[j], j, flags[j]);
> +               if (pma_addr == SBI_EINVAL)
> +                       return SBI_EINVAL;
> +       }
> +
> +       ret = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + (64 * j));
> +       if (ret < 0)
> +               return ret;
> +
> +       for (i = 0; i < j; i++) {
> +               ret = fdt_reserved_memory_fixup(fdt, start[i], size[i], i);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +static int rzf_final_init(bool cold_boot, const struct fdt_match *match)
> +{
> +       return rzfive_configure_pma_regions();
> +}
> +
> +static int rzfive_vendor_ext_provider(long extid, long funcid,
> +                                     const struct sbi_trap_regs *regs,
> +                                     unsigned long *out_value,
> +                                     struct sbi_trap_info *out_trap,
> +                                     const struct fdt_match *match)
> +{
> +       switch (funcid) {
> +       case RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND:
> +               *out_value = rzfive_apply_iocp_sw_workaround();
> +               break;
> +
> +       default:
> +               break;
> +       }
> +
> +       return 0;
> +}
> +
>  static const struct fdt_match renesas_rzfive_match[] = {
>         { .compatible = "renesas,r9a07g043f01" },
>         { /* sentinel */ }
> @@ -14,4 +239,6 @@ static const struct fdt_match renesas_rzfive_match[] = {
>
>  const struct platform_override renesas_rzfive = {
>         .match_table = renesas_rzfive_match,
> +       .final_init = rzf_final_init,
> +       .vendor_ext_provider = rzfive_vendor_ext_provider,
>  };

Regards,
Bin


From peterlin at andestech.com  Wed Dec 21 06:22:32 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Wed, 21 Dec 2022 14:22:32 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <CAEUhbmW5WmNSPNNe4UWq6o7ZtOgT=9N5f2=F6L+ScLSzW_K8dQ@mail.gmail.com>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmW5WmNSPNNe4UWq6o7ZtOgT=9N5f2=F6L+ScLSzW_K8dQ@mail.gmail.com>
Message-ID: <Y6MWqO71cISuLEOk@APC323>

On Wed, Dec 21, 2022 at 09:23:21AM +0800, Bin Meng wrote:
> On Mon, Dec 12, 2022 at 5:44 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
> >
> > Add support to configure the PMA regions and create a corresponding
> > reserve memory node and propagate it to the higher boot stack.
> >
> > &L2 {
> >        andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
> >                                 (AX45MP_PMACFG_ETYP_NAPOT |
> >                                  AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
> > };
> >
> > PMA regions are passed as part of L2 cache node to OpenSBI, these regions
> > are parsed and configured in the OpenSBI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > ---
> > Hi All,
> >
> > This patch is based on the discussion [0] so sending this as an RFC
> > patch so that we get the Linux side of things accepeted first and once its
> > finalized I'll send a non RFC patch for this.
> >
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> >
> > Cheers,
> > Prabhakar
> > ---
> >  platform/generic/renesas/rzfive/objects.mk   |   1 +
> >  platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
> >  platform/generic/renesas/rzfive/rzfive-pma.h |  12 +
> 
> I feel we should name this to something like ax45mp-pma instead of
> rzfive-pma, as this is at the core configuration level not SoC's, no?

Agreed, Andes PMA CSRs also exist in A45MP (RV32) so it's better if we
call it andes45-pma.c and andes45_{read|write}_pma{cfg|addr} as function
name.

Any suggestion to add these functions which will be shared between the
platforms?

> 
> >  platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
> >  4 files changed, 421 insertions(+)
> >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
> >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h
> >

Best regards,
Peter Lin


From peterlin at andestech.com  Wed Dec 21 07:15:20 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Wed, 21 Dec 2022 15:15:20 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <Y6IzTcaMxw9JjBW3@APC323>
 <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>
Message-ID: <Y6MjCN7UD1PqL9pL@APC323>

Hi Prabhakar,

> > > +unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
> > > +                                   int entry_id, u32 flag)
> > > +{
> > > +     unsigned long size_tmp, shift = 0, pmacfg_val;
> > > +     unsigned long mmsc = csr_read(CSR_MMSC_CFG);
> > > +     unsigned long pa = addr;
> > > +     char *pmaxcfg;
> > > +     int power = 0;
> > > +
> >
> > The granularity of PMA NAPOT mode is 4KiB, so we should not allow this
> > case.
> >
> > if (size < (1 << 12))
> >   return SBI_EINVAL;
> >
> The manual I am referring to says "The minimal size of NAPOT regions
> must be 8 bytes."

I checked the section "16.17.1 PMA Configuration Registers" [1],
it says "The granularity is 4K bytes.".

Besides, here is my observation:
Assume desired base: 0x58000000
               size: 0x00000400

(gdb) p/x $pmacfg0
$10 = {0xf, pma0cfg = {0xf, etyp = 0x3, mtyp = 0x3}, [...]
(gdb) p/x (0x58000000 >> 2) + (0x400 >> 3) - 1
$6 = 0x1600007f
(gdb) p/x $pmaaddr0=0x1600007fl
$8 = 0x1600007f
(gdb) p/x $pmaaddr0
$9 = 0x160001ff
(gdb) pma_to_addr 0x160001ff
translate pmaaddr 0x160001ff
==========================================
power:  12
base:?? 0x1000
region: 0x58000000 ~ 0x58001000

[1] http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf

[...]
> >
> > Can we simplify the logic to calculate the value of pmaaddr?
> >
> > If addr = 0x58000000
> >    size = 0x08000000
> >
> > pmaaddr = (addr >> 2) + (size >> 3) - 1 = 0x16ffffff
> >
> Ok I'll simply as above.
> 
> Cheers,
> Prabhakar

Best regards,
Peter Lin


From bmeng.cn at gmail.com  Wed Dec 21 01:30:00 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 17:30:00 +0800
Subject: [PATCH v3 3/6] lib: sbi: Add sbi_domain_check_addr_range() function
In-Reply-To: <20221124132906.257732-4-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com> <20221124132906.257732-4-apatel@ventanamicro.com>
Message-ID: <CAEUhbmUdpvHRgjMyGLu0Gu1wT+gSqLB2SK1_3XSa6UQi7j1tDw@mail.gmail.com>

On Thu, Nov 24, 2022 at 9:32 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add sbi_domain_check_addr_range() helper function to check
> whether a given address range is accessible under a particular
> domain.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_domain.h | 15 +++++++++
>  lib/sbi/sbi_domain.c     | 69 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 84 insertions(+)
>
> diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> index 5553d21..4afcc37 100644
> --- a/include/sbi/sbi_domain.h
> +++ b/include/sbi/sbi_domain.h
> @@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
>                            unsigned long addr, unsigned long mode,
>                            unsigned long access_flags);
>
> +/**
> + * Check whether we can access specified address range for given mode and
> + * memory region flags under a domain
> + * @param dom pointer to domain
> + * @param addr the start of the address range to be checked
> + * @param size the size of the address range to be checked
> + * @param mode the privilege mode of access
> + * @param access_flags bitmask of domain access types (enum sbi_domain_access)
> + * @return TRUE if access allowed otherwise FALSE
> + */
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +                                unsigned long addr, unsigned long size,
> +                                unsigned long mode,
> +                                unsigned long access_flags);
> +
>  /** Dump domain details on the console */
>  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
>
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index f24a8e5..11a547c 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -195,6 +195,44 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
>         return FALSE;
>  }
>
> +static const struct sbi_domain_memregion *find_region(
> +                                               const struct sbi_domain *dom,
> +                                               unsigned long addr)
> +{
> +       unsigned long rstart, rend;
> +       struct sbi_domain_memregion *reg;
> +
> +       sbi_domain_for_each_memregion(dom, reg) {
> +               rstart = reg->base;
> +               rend = (reg->order < __riscv_xlen) ?
> +                       rstart + ((1UL << reg->order) - 1) : -1UL;
> +               if (rstart <= addr && addr <= rend)

addr < rend?

> +                       return reg;
> +       }
> +
> +       return NULL;
> +}
> +
> +static const struct sbi_domain_memregion *find_next_subset_region(
> +                               const struct sbi_domain *dom,
> +                               const struct sbi_domain_memregion *reg,
> +                               unsigned long addr)
> +{
> +       struct sbi_domain_memregion *sreg, *ret = NULL;
> +
> +       sbi_domain_for_each_memregion(dom, sreg) {
> +               if (sreg == reg || (sreg->base <= addr) ||
> +                   !is_region_subset(sreg, reg))
> +                       continue;
> +
> +               if (!ret || (sreg->base < ret->base) ||
> +                   ((sreg->base == ret->base) && (sreg->order < ret->order)))
> +                       ret = sreg;
> +       }
> +
> +       return ret;
> +}
> +
>  static int sanitize_domain(const struct sbi_platform *plat,
>                            struct sbi_domain *dom)
>  {
> @@ -303,6 +341,37 @@ static int sanitize_domain(const struct sbi_platform *plat,
>         return 0;
>  }
>
> +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> +                                unsigned long addr, unsigned long size,
> +                                unsigned long mode,
> +                                unsigned long access_flags)
> +{
> +       unsigned long max = addr + size;
> +       const struct sbi_domain_memregion *reg, *sreg;
> +
> +       if (!dom)
> +               return FALSE;
> +
> +       while (addr < max) {
> +               reg = find_region(dom, addr);
> +               if (!reg)
> +                       return FALSE;
> +
> +               if (!sbi_domain_check_addr(dom, addr, mode, access_flags))
> +                       return FALSE;
> +
> +               sreg = find_next_subset_region(dom, reg, addr);
> +               if (sreg)
> +                       addr = sreg->base;
> +               else if (reg->order < __riscv_xlen)
> +                       addr = reg->base + (1UL << reg->order);
> +               else
> +                       break;
> +       }
> +
> +       return TRUE;
> +}
> +
>  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
>  {
>         u32 i, k;

Regards,
Bin


From bmeng.cn at gmail.com  Wed Dec 21 02:17:14 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 18:17:14 +0800
Subject: [PATCH v3 3/6] lib: sbi: Add sbi_domain_check_addr_range() function
In-Reply-To: <CAEUhbmUdpvHRgjMyGLu0Gu1wT+gSqLB2SK1_3XSa6UQi7j1tDw@mail.gmail.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com>
 <20221124132906.257732-4-apatel@ventanamicro.com> <CAEUhbmUdpvHRgjMyGLu0Gu1wT+gSqLB2SK1_3XSa6UQi7j1tDw@mail.gmail.com>
Message-ID: <CAEUhbmWC_q3HbAs0-Q3B5c-gUH9ORzhc0w2ZnbbpFY8EH0J7hg@mail.gmail.com>

On Wed, Dec 21, 2022 at 5:30 PM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Thu, Nov 24, 2022 at 9:32 PM Anup Patel <apatel at ventanamicro.com> wrote:
> >
> > We add sbi_domain_check_addr_range() helper function to check
> > whether a given address range is accessible under a particular
> > domain.
> >
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> >  include/sbi/sbi_domain.h | 15 +++++++++
> >  lib/sbi/sbi_domain.c     | 69 ++++++++++++++++++++++++++++++++++++++++
> >  2 files changed, 84 insertions(+)
> >
> > diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> > index 5553d21..4afcc37 100644
> > --- a/include/sbi/sbi_domain.h
> > +++ b/include/sbi/sbi_domain.h
> > @@ -154,6 +154,21 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
> >                            unsigned long addr, unsigned long mode,
> >                            unsigned long access_flags);
> >
> > +/**
> > + * Check whether we can access specified address range for given mode and
> > + * memory region flags under a domain
> > + * @param dom pointer to domain
> > + * @param addr the start of the address range to be checked
> > + * @param size the size of the address range to be checked
> > + * @param mode the privilege mode of access
> > + * @param access_flags bitmask of domain access types (enum sbi_domain_access)
> > + * @return TRUE if access allowed otherwise FALSE
> > + */
> > +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> > +                                unsigned long addr, unsigned long size,
> > +                                unsigned long mode,
> > +                                unsigned long access_flags);
> > +
> >  /** Dump domain details on the console */
> >  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
> >
> > diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> > index f24a8e5..11a547c 100644
> > --- a/lib/sbi/sbi_domain.c
> > +++ b/lib/sbi/sbi_domain.c
> > @@ -195,6 +195,44 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
> >         return FALSE;
> >  }
> >
> > +static const struct sbi_domain_memregion *find_region(
> > +                                               const struct sbi_domain *dom,
> > +                                               unsigned long addr)
> > +{
> > +       unsigned long rstart, rend;
> > +       struct sbi_domain_memregion *reg;
> > +
> > +       sbi_domain_for_each_memregion(dom, reg) {
> > +               rstart = reg->base;
> > +               rend = (reg->order < __riscv_xlen) ?
> > +                       rstart + ((1UL << reg->order) - 1) : -1UL;
> > +               if (rstart <= addr && addr <= rend)
>
> addr < rend?

Never mind. Looks good.

>
> > +                       return reg;
> > +       }
> > +
> > +       return NULL;
> > +}
> > +
> > +static const struct sbi_domain_memregion *find_next_subset_region(
> > +                               const struct sbi_domain *dom,
> > +                               const struct sbi_domain_memregion *reg,
> > +                               unsigned long addr)
> > +{
> > +       struct sbi_domain_memregion *sreg, *ret = NULL;
> > +
> > +       sbi_domain_for_each_memregion(dom, sreg) {
> > +               if (sreg == reg || (sreg->base <= addr) ||
> > +                   !is_region_subset(sreg, reg))
> > +                       continue;
> > +
> > +               if (!ret || (sreg->base < ret->base) ||
> > +                   ((sreg->base == ret->base) && (sreg->order < ret->order)))
> > +                       ret = sreg;
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> >  static int sanitize_domain(const struct sbi_platform *plat,
> >                            struct sbi_domain *dom)
> >  {
> > @@ -303,6 +341,37 @@ static int sanitize_domain(const struct sbi_platform *plat,
> >         return 0;
> >  }
> >
> > +bool sbi_domain_check_addr_range(const struct sbi_domain *dom,
> > +                                unsigned long addr, unsigned long size,
> > +                                unsigned long mode,
> > +                                unsigned long access_flags)
> > +{
> > +       unsigned long max = addr + size;
> > +       const struct sbi_domain_memregion *reg, *sreg;
> > +
> > +       if (!dom)
> > +               return FALSE;
> > +
> > +       while (addr < max) {
> > +               reg = find_region(dom, addr);
> > +               if (!reg)
> > +                       return FALSE;
> > +
> > +               if (!sbi_domain_check_addr(dom, addr, mode, access_flags))
> > +                       return FALSE;
> > +
> > +               sreg = find_next_subset_region(dom, reg, addr);
> > +               if (sreg)
> > +                       addr = sreg->base;
> > +               else if (reg->order < __riscv_xlen)
> > +                       addr = reg->base + (1UL << reg->order);
> > +               else
> > +                       break;
> > +       }
> > +
> > +       return TRUE;
> > +}
> > +
> >  void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
> >  {
> >         u32 i, k;
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Dec 21 02:21:17 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 18:21:17 +0800
Subject: [PATCH v3 4/6] lib: sbi: Implement SBI debug console extension
In-Reply-To: <20221124132906.257732-5-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com> <20221124132906.257732-5-apatel@ventanamicro.com>
Message-ID: <CAEUhbmVgaQ-FcstNB1BC3xYdn8_8L=Ni30sfs_+M_N6cKvYT_A@mail.gmail.com>

On Thu, Nov 24, 2022 at 9:32 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We implement SBI debug console extension as one of the replacement
> SBI extensions. This extension is only available when OpenSBI platform
> provides a console device to generic library.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/sbi/Kconfig          |  4 +++
>  lib/sbi/objects.mk       |  3 ++
>  lib/sbi/sbi_ecall_dbcn.c | 62 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 69 insertions(+)
>  create mode 100644 lib/sbi/sbi_ecall_dbcn.c
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Dec 21 02:24:50 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 18:24:50 +0800
Subject: [PATCH v3 6/6] lib: utils/serial: Implement console_puts() for semihosting
In-Reply-To: <20221124132906.257732-7-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com> <20221124132906.257732-7-apatel@ventanamicro.com>
Message-ID: <CAEUhbmX_cnB1V1z63QAeY=iQm+9T-CNHnimAULX9NCM0KWJPGw@mail.gmail.com>

On Thu, Nov 24, 2022 at 9:33 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We implement console_puts() for semihosting serial driver to speed-up
> semihosting based prints.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  lib/utils/serial/semihosting.c | 33 +++++++++++++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Dec 21 02:23:16 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 18:23:16 +0800
Subject: [PATCH v3 5/6] lib: sbi: Add console_puts() callback in the
 console device
In-Reply-To: <20221124132906.257732-6-apatel@ventanamicro.com>
References: <20221124132906.257732-1-apatel@ventanamicro.com> <20221124132906.257732-6-apatel@ventanamicro.com>
Message-ID: <CAEUhbmXR1b7uJTge7KnsOLZfrfu7LO7U7w-FtKhWiADaKvM99g@mail.gmail.com>

On Thu, Nov 24, 2022 at 9:33 PM Anup Patel <apatel at ventanamicro.com> wrote:
>
> We add console_puts() callback in the console device which allows
> console drivers (such as semihosting) to implement a specialized
> way to output character string.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_console.h |  3 +++
>  lib/sbi/sbi_console.c     | 19 ++++++++++++++-----
>  2 files changed, 17 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng at tinylab.org  Wed Dec 21 03:38:06 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Wed, 21 Dec 2022 19:38:06 +0800
Subject: [PATCH] treewide: Replace TRUE/FALSE with true/false
Message-ID: <20221221113806.1450323-1-bmeng@tinylab.org>

C language standard uses true/false for the boolean type.
Let's switch to that for better language compatibility.

Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 include/sbi/sbi_domain.h           |  4 +--
 include/sbi/sbi_list.h             |  2 +-
 include/sbi/sbi_platform.h         | 18 +++++------
 include/sbi/sbi_types.h            |  6 ++--
 lib/sbi/sbi_console.c              |  4 +--
 lib/sbi/sbi_domain.c               | 44 ++++++++++++-------------
 lib/sbi/sbi_ecall.c                |  4 +--
 lib/sbi/sbi_ecall_hsm.c            |  2 +-
 lib/sbi/sbi_emulate_csr.c          | 10 +++---
 lib/sbi/sbi_fifo.c                 |  8 ++---
 lib/sbi/sbi_init.c                 | 52 +++++++++++++++---------------
 lib/sbi/sbi_ipi.c                  |  2 +-
 lib/sbi/sbi_pmu.c                  | 14 ++++----
 lib/sbi/sbi_system.c               |  2 +-
 lib/sbi/sbi_trap.c                 |  8 ++---
 lib/utils/fdt/fdt_domain.c         |  4 +--
 lib/utils/reset/fdt_reset_gpio.c   | 12 +++----
 platform/fpga/ariane/platform.c    |  2 +-
 platform/fpga/openpiton/platform.c |  2 +-
 platform/generic/sifive/fu740.c    |  2 +-
 platform/kendryte/k210/platform.c  |  2 +-
 platform/nuclei/ux600/platform.c   |  2 +-
 platform/template/platform.c       |  2 +-
 23 files changed, 103 insertions(+), 105 deletions(-)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..f0d9289 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -113,7 +113,7 @@ extern struct sbi_domain *domidx_to_domain_table[];
  * Check whether given HART is assigned to specified domain
  * @param dom pointer to domain
  * @param hartid the HART ID
- * @return TRUE if HART is assigned to domain otherwise FALSE
+ * @return true if HART is assigned to domain otherwise false
  */
 bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid);
 
@@ -148,7 +148,7 @@ void sbi_domain_memregion_init(unsigned long addr,
  * @param addr the address to be checked
  * @param mode the privilege mode of access
  * @param access_flags bitmask of domain access types (enum sbi_domain_access)
- * @return TRUE if access allowed otherwise FALSE
+ * @return true if access allowed otherwise false
  */
 bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
diff --git a/include/sbi/sbi_list.h b/include/sbi/sbi_list.h
index b1178df..fe735df 100644
--- a/include/sbi/sbi_list.h
+++ b/include/sbi/sbi_list.h
@@ -47,7 +47,7 @@ static inline void __sbi_list_add(struct sbi_dlist *new,
  * Checks if the list is empty or not.
  * @param head List head
  *
- * Retruns TRUE if list is empty, FALSE otherwise.
+ * Returns true if list is empty, false otherwise.
  */
 static inline bool sbi_list_empty(struct sbi_dlist *head)
 {
diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..010e9ce 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -344,16 +344,16 @@ static inline u32 sbi_platform_hart_stack_size(const struct sbi_platform *plat)
  * @param plat pointer to struct sbi_platform
  * @param hartid HART ID
  *
- * @return TRUE if HART is invalid and FALSE otherwise
+ * @return true if HART is invalid and false otherwise
  */
 static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 					     u32 hartid)
 {
 	if (!plat)
-		return TRUE;
+		return true;
 	if (plat->hart_count <= sbi_platform_hart_index(plat, hartid))
-		return TRUE;
-	return FALSE;
+		return true;
+	return false;
 }
 
 /**
@@ -377,7 +377,7 @@ static inline int sbi_platform_nascent_init(const struct sbi_platform *plat)
  * Early initialization for current HART
  *
  * @param plat pointer to struct sbi_platform
- * @param cold_boot whether cold boot (TRUE) or warm_boot (FALSE)
+ * @param cold_boot whether cold boot (true) or warm_boot (false)
  *
  * @return 0 on success and negative error code on failure
  */
@@ -393,7 +393,7 @@ static inline int sbi_platform_early_init(const struct sbi_platform *plat,
  * Final initialization for current HART
  *
  * @param plat pointer to struct sbi_platform
- * @param cold_boot whether cold boot (TRUE) or warm_boot (FALSE)
+ * @param cold_boot whether cold boot (true) or warm_boot (false)
  *
  * @return 0 on success and negative error code on failure
  */
@@ -538,7 +538,7 @@ static inline int sbi_platform_console_init(const struct sbi_platform *plat)
  * Initialize the platform interrupt controller for current HART
  *
  * @param plat pointer to struct sbi_platform
- * @param cold_boot whether cold boot (TRUE) or warm_boot (FALSE)
+ * @param cold_boot whether cold boot (true) or warm_boot (false)
  *
  * @return 0 on success and negative error code on failure
  */
@@ -565,7 +565,7 @@ static inline void sbi_platform_irqchip_exit(const struct sbi_platform *plat)
  * Initialize the platform IPI support for current HART
  *
  * @param plat pointer to struct sbi_platform
- * @param cold_boot whether cold boot (TRUE) or warm_boot (FALSE)
+ * @param cold_boot whether cold boot (true) or warm_boot (false)
  *
  * @return 0 on success and negative error code on failure
  */
@@ -592,7 +592,7 @@ static inline void sbi_platform_ipi_exit(const struct sbi_platform *plat)
  * Initialize the platform timer for current HART
  *
  * @param plat pointer to struct sbi_platform
- * @param cold_boot whether cold boot (TRUE) or warm_boot (FALSE)
+ * @param cold_boot whether cold boot (true) or warm_boot (false)
  *
  * @return 0 on success and negative error code on failure
  */
diff --git a/include/sbi/sbi_types.h b/include/sbi/sbi_types.h
index 7fb1af7..75cdddd 100644
--- a/include/sbi/sbi_types.h
+++ b/include/sbi/sbi_types.h
@@ -54,10 +54,8 @@ typedef unsigned long		virtual_size_t;
 typedef unsigned long		physical_addr_t;
 typedef unsigned long		physical_size_t;
 
-#define TRUE			1
-#define FALSE			0
-#define true			TRUE
-#define false			FALSE
+#define true			1
+#define false			0
 
 #define NULL			((void *)0)
 
diff --git a/lib/sbi/sbi_console.c b/lib/sbi/sbi_console.c
index cfef2f8..bb6e1ef 100644
--- a/lib/sbi/sbi_console.c
+++ b/lib/sbi/sbi_console.c
@@ -20,9 +20,9 @@ bool sbi_isprintable(char c)
 {
 	if (((31 < c) && (c < 127)) || (c == '\f') || (c == '\r') ||
 	    (c == '\n') || (c == '\t')) {
-		return TRUE;
+		return true;
 	}
-	return FALSE;
+	return false;
 }
 
 int sbi_getc(void)
diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3205595..19e2029 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -33,7 +33,7 @@ struct sbi_domain root = {
 	.name = "root",
 	.possible_harts = &root_hmask,
 	.regions = root_memregs,
-	.system_reset_allowed = TRUE,
+	.system_reset_allowed = true,
 };
 
 bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
@@ -41,7 +41,7 @@ bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
 	if (dom)
 		return sbi_hartmask_test_hart(hartid, &dom->assigned_harts);
 
-	return FALSE;
+	return false;
 }
 
 ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
@@ -105,12 +105,12 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 			   unsigned long addr, unsigned long mode,
 			   unsigned long access_flags)
 {
-	bool rmmio, mmio = FALSE;
+	bool rmmio, mmio = false;
 	struct sbi_domain_memregion *reg;
 	unsigned long rstart, rend, rflags, rwx = 0;
 
 	if (!dom)
-		return FALSE;
+		return false;
 
 	if (access_flags & SBI_DOMAIN_READ)
 		rwx |= SBI_DOMAIN_MEMREGION_READABLE;
@@ -119,7 +119,7 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 	if (access_flags & SBI_DOMAIN_EXECUTE)
 		rwx |= SBI_DOMAIN_MEMREGION_EXECUTABLE;
 	if (access_flags & SBI_DOMAIN_MMIO)
-		mmio = TRUE;
+		mmio = true;
 
 	sbi_domain_for_each_memregion(dom, reg) {
 		rflags = reg->flags;
@@ -130,29 +130,29 @@ bool sbi_domain_check_addr(const struct sbi_domain *dom,
 		rend = (reg->order < __riscv_xlen) ?
 			rstart + ((1UL << reg->order) - 1) : -1UL;
 		if (rstart <= addr && addr <= rend) {
-			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? TRUE : FALSE;
+			rmmio = (rflags & SBI_DOMAIN_MEMREGION_MMIO) ? true : false;
 			if (mmio != rmmio)
-				return FALSE;
-			return ((rflags & rwx) == rwx) ? TRUE : FALSE;
+				return false;
+			return ((rflags & rwx) == rwx) ? true : false;
 		}
 	}
 
-	return (mode == PRV_M) ? TRUE : FALSE;
+	return (mode == PRV_M) ? true : false;
 }
 
 /* Check if region complies with constraints */
 static bool is_region_valid(const struct sbi_domain_memregion *reg)
 {
 	if (reg->order < 3 || __riscv_xlen < reg->order)
-		return FALSE;
+		return false;
 
 	if (reg->order == __riscv_xlen && reg->base != 0)
-		return FALSE;
+		return false;
 
 	if (reg->order < __riscv_xlen && (reg->base & (BIT(reg->order) - 1)))
-		return FALSE;
+		return false;
 
-	return TRUE;
+	return true;
 }
 
 /** Check if regionA is sub-region of regionB */
@@ -168,9 +168,9 @@ static bool is_region_subset(const struct sbi_domain_memregion *regA,
 	    (regA_start < regB_end) &&
 	    (regB_start < regA_end) &&
 	    (regA_end <= regB_end))
-		return TRUE;
+		return true;
 
-	return FALSE;
+	return false;
 }
 
 /** Check if regionA conflicts regionB */
@@ -179,9 +179,9 @@ static bool is_region_conflict(const struct sbi_domain_memregion *regA,
 {
 	if ((is_region_subset(regA, regB) || is_region_subset(regB, regA)) &&
 	    regA->flags == regB->flags)
-		return TRUE;
+		return true;
 
-	return FALSE;
+	return false;
 }
 
 /** Check if regionA should be placed before regionB */
@@ -189,13 +189,13 @@ static bool is_region_before(const struct sbi_domain_memregion *regA,
 			     const struct sbi_domain_memregion *regB)
 {
 	if (regA->order < regB->order)
-		return TRUE;
+		return true;
 
 	if ((regA->order == regB->order) &&
 	    (regA->base < regB->base))
-		return TRUE;
+		return true;
 
-	return FALSE;
+	return false;
 }
 
 static int sanitize_domain(const struct sbi_platform *plat,
@@ -237,12 +237,12 @@ static int sanitize_domain(const struct sbi_platform *plat,
 
 	/* Count memory regions and check presence of firmware region */
 	count = 0;
-	have_fw_reg = FALSE;
+	have_fw_reg = false;
 	sbi_domain_for_each_memregion(dom, reg) {
 		if (reg->order == root_fw_region.order &&
 		    reg->base == root_fw_region.base &&
 		    reg->flags == root_fw_region.flags)
-			have_fw_reg = TRUE;
+			have_fw_reg = true;
 		count++;
 	}
 	if (!have_fw_reg) {
diff --git a/lib/sbi/sbi_ecall.c b/lib/sbi/sbi_ecall.c
index 25dd78c..27ce5d4 100644
--- a/lib/sbi/sbi_ecall.c
+++ b/lib/sbi/sbi_ecall.c
@@ -78,7 +78,7 @@ int sbi_ecall_register_extension(struct sbi_ecall_extension *ext)
 
 void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext)
 {
-	bool found = FALSE;
+	bool found = false;
 	struct sbi_ecall_extension *t;
 
 	if (!ext)
@@ -86,7 +86,7 @@ void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext)
 
 	sbi_list_for_each_entry(t, &ecall_exts_list, head) {
 		if (t == ext) {
-			found = TRUE;
+			found = true;
 			break;
 		}
 	}
diff --git a/lib/sbi/sbi_ecall_hsm.c b/lib/sbi/sbi_ecall_hsm.c
index a339abf..703a824 100644
--- a/lib/sbi/sbi_ecall_hsm.c
+++ b/lib/sbi/sbi_ecall_hsm.c
@@ -33,7 +33,7 @@ static int sbi_ecall_hsm_handler(unsigned long extid, unsigned long funcid,
 					 regs->a0, regs->a1, smode, regs->a2);
 		break;
 	case SBI_EXT_HSM_HART_STOP:
-		ret = sbi_hsm_hart_stop(scratch, TRUE);
+		ret = sbi_hsm_hart_stop(scratch, true);
 		break;
 	case SBI_EXT_HSM_HART_GET_STATUS:
 		ret = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(),
diff --git a/lib/sbi/sbi_emulate_csr.c b/lib/sbi/sbi_emulate_csr.c
index aec9d3c..64bebd8 100644
--- a/lib/sbi/sbi_emulate_csr.c
+++ b/lib/sbi/sbi_emulate_csr.c
@@ -39,7 +39,7 @@ static bool hpm_allowed(int hpm_num, ulong prev_mode, bool virt)
 			cen = 0;
 	}
 
-	return ((cen >> hpm_num) & 1) ? TRUE : FALSE;
+	return ((cen >> hpm_num) & 1) ? true : false;
 }
 
 int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
@@ -49,9 +49,9 @@ int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
 	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
 	ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
 #if __riscv_xlen == 32
-	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
+	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? true : false;
 #else
-	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
+	bool virt = (regs->mstatus & MSTATUS_MPV) ? true : false;
 #endif
 
 	switch (csr_num) {
@@ -164,9 +164,9 @@ int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
 	int ret = 0;
 	ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
 #if __riscv_xlen == 32
-	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
+	bool virt = (regs->mstatusH & MSTATUSH_MPV) ? true : false;
 #else
-	bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
+	bool virt = (regs->mstatus & MSTATUS_MPV) ? true : false;
 #endif
 
 	switch (csr_num) {
diff --git a/lib/sbi/sbi_fifo.c b/lib/sbi/sbi_fifo.c
index 68d6039..72c6d39 100644
--- a/lib/sbi/sbi_fifo.c
+++ b/lib/sbi/sbi_fifo.c
@@ -26,7 +26,7 @@ void sbi_fifo_init(struct sbi_fifo *fifo, void *queue_mem, u16 entries,
 /* Note: must be called with fifo->qlock held */
 static inline bool __sbi_fifo_is_full(struct sbi_fifo *fifo)
 {
-	return (fifo->avail == fifo->num_entries) ? TRUE : FALSE;
+	return (fifo->avail == fifo->num_entries) ? true : false;
 }
 
 u16 sbi_fifo_avail(struct sbi_fifo *fifo)
@@ -75,7 +75,7 @@ static inline void  __sbi_fifo_enqueue(struct sbi_fifo *fifo, void *data)
 /* Note: must be called with fifo->qlock held */
 static inline bool __sbi_fifo_is_empty(struct sbi_fifo *fifo)
 {
-	return (fifo->avail == 0) ? TRUE : FALSE;
+	return (fifo->avail == 0) ? true : false;
 }
 
 int sbi_fifo_is_empty(struct sbi_fifo *fifo)
@@ -105,13 +105,13 @@ static inline void __sbi_fifo_reset(struct sbi_fifo *fifo)
 bool sbi_fifo_reset(struct sbi_fifo *fifo)
 {
 	if (!fifo)
-		return FALSE;
+		return false;
 
 	spin_lock(&fifo->qlock);
 	__sbi_fifo_reset(fifo);
 	spin_unlock(&fifo->qlock);
 
-	return TRUE;
+	return true;
 }
 
 /**
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..ded3da0 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -255,15 +255,15 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (!init_count_offset)
 		sbi_hart_hang();
 
-	rc = sbi_hsm_init(scratch, hartid, TRUE);
+	rc = sbi_hsm_init(scratch, hartid, true);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_platform_early_init(plat, TRUE);
+	rc = sbi_platform_early_init(plat, true);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_hart_init(scratch, TRUE);
+	rc = sbi_hart_init(scratch, true);
 	if (rc)
 		sbi_hart_hang();
 
@@ -271,32 +271,32 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_pmu_init(scratch, TRUE);
+	rc = sbi_pmu_init(scratch, true);
 	if (rc)
 		sbi_hart_hang();
 
 	sbi_boot_print_banner(scratch);
 
-	rc = sbi_irqchip_init(scratch, TRUE);
+	rc = sbi_irqchip_init(scratch, true);
 	if (rc) {
 		sbi_printf("%s: irqchip init failed (error %d)\n",
 			   __func__, rc);
 		sbi_hart_hang();
 	}
 
-	rc = sbi_ipi_init(scratch, TRUE);
+	rc = sbi_ipi_init(scratch, true);
 	if (rc) {
 		sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
 	}
 
-	rc = sbi_tlb_init(scratch, TRUE);
+	rc = sbi_tlb_init(scratch, true);
 	if (rc) {
 		sbi_printf("%s: tlb init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
 	}
 
-	rc = sbi_timer_init(scratch, TRUE);
+	rc = sbi_timer_init(scratch, true);
 	if (rc) {
 		sbi_printf("%s: timer init failed (error %d)\n", __func__, rc);
 		sbi_hart_hang();
@@ -332,7 +332,7 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	 * Note: Platform final initialization should be last so that
 	 * it sees correct domain assignment and PMP configuration.
 	 */
-	rc = sbi_platform_final_init(plat, TRUE);
+	rc = sbi_platform_final_init(plat, true);
 	if (rc) {
 		sbi_printf("%s: platform final init failed (error %d)\n",
 			   __func__, rc);
@@ -352,7 +352,7 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 
 	sbi_hsm_prepare_next_jump(scratch, hartid);
 	sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
-			     scratch->next_mode, FALSE);
+			     scratch->next_mode, false);
 }
 
 static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
@@ -364,35 +364,35 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
 	if (!init_count_offset)
 		sbi_hart_hang();
 
-	rc = sbi_hsm_init(scratch, hartid, FALSE);
+	rc = sbi_hsm_init(scratch, hartid, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_platform_early_init(plat, FALSE);
+	rc = sbi_platform_early_init(plat, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_hart_init(scratch, FALSE);
+	rc = sbi_hart_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_pmu_init(scratch, FALSE);
+	rc = sbi_pmu_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_irqchip_init(scratch, FALSE);
+	rc = sbi_irqchip_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_ipi_init(scratch, FALSE);
+	rc = sbi_ipi_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_tlb_init(scratch, FALSE);
+	rc = sbi_tlb_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_timer_init(scratch, FALSE);
+	rc = sbi_timer_init(scratch, false);
 	if (rc)
 		sbi_hart_hang();
 
@@ -400,7 +400,7 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid)
 	if (rc)
 		sbi_hart_hang();
 
-	rc = sbi_platform_final_init(plat, FALSE);
+	rc = sbi_platform_final_init(plat, false);
 	if (rc)
 		sbi_hart_hang();
 
@@ -444,7 +444,7 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
 
 	sbi_hart_switch_mode(hartid, scratch->next_arg1,
 			     scratch->next_addr,
-			     scratch->next_mode, FALSE);
+			     scratch->next_mode, false);
 }
 
 static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
@@ -463,8 +463,8 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
  */
 void __noreturn sbi_init(struct sbi_scratch *scratch)
 {
-	bool next_mode_supported	= FALSE;
-	bool coldboot			= FALSE;
+	bool next_mode_supported	= false;
+	bool coldboot			= false;
 	u32 hartid			= current_hartid();
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
@@ -474,15 +474,15 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 
 	switch (scratch->next_mode) {
 	case PRV_M:
-		next_mode_supported = TRUE;
+		next_mode_supported = true;
 		break;
 	case PRV_S:
 		if (misa_extension('S'))
-			next_mode_supported = TRUE;
+			next_mode_supported = true;
 		break;
 	case PRV_U:
 		if (misa_extension('U'))
-			next_mode_supported = TRUE;
+			next_mode_supported = true;
 		break;
 	default:
 		sbi_hart_hang();
@@ -499,7 +499,7 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 */
 
 	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+		coldboot = true;
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
diff --git a/lib/sbi/sbi_ipi.c b/lib/sbi/sbi_ipi.c
index 7aafbbd..1bcc2e4 100644
--- a/lib/sbi/sbi_ipi.c
+++ b/lib/sbi/sbi_ipi.c
@@ -163,7 +163,7 @@ void sbi_ipi_clear_smode(void)
 
 static void sbi_ipi_process_halt(struct sbi_scratch *scratch)
 {
-	sbi_hsm_hart_stop(scratch, TRUE);
+	sbi_hsm_hart_stop(scratch, true);
 }
 
 static struct sbi_ipi_event_ops ipi_halt_ops = {
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 91d9ccc..154dbda 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -85,7 +85,7 @@ static uint32_t total_ctrs;
  * @param evtA Pointer to the existing hw event structure
  * @param evtB Pointer to the new hw event structure
  *
- * Return FALSE if the range doesn't overlap, TRUE otherwise
+ * Return false if the range doesn't overlap, true otherwise
  */
 static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
 				    struct sbi_pmu_hw_event *evtB)
@@ -93,17 +93,17 @@ static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA,
 	/* check if the range of events overlap with a previous entry */
 	if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) ||
 	   ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx)))
-		return FALSE;
-	return TRUE;
+		return false;
+	return true;
 }
 
 static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt,
 				     uint64_t select_val, uint64_t select_mask)
 {
 	if ((evt->select == select_val) && (evt->select_mask == select_mask))
-		return TRUE;
+		return true;
 
-	return FALSE;
+	return false;
 }
 
 static int pmu_event_validate(unsigned long event_idx)
@@ -384,14 +384,14 @@ int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask,
 	int event_idx_type;
 	uint32_t event_code;
 	int ret = SBI_EINVAL;
-	bool bUpdate = FALSE;
+	bool bUpdate = false;
 	int i, cidx;
 
 	if ((cbase + sbi_fls(cmask)) >= total_ctrs)
 		return ret;
 
 	if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE)
-		bUpdate = TRUE;
+		bUpdate = true;
 
 	for_each_set_bit(i, &cmask, total_ctrs) {
 		cidx = i + cbase;
diff --git a/lib/sbi/sbi_system.c b/lib/sbi/sbi_system.c
index 9cea3c0..f37c811 100644
--- a/lib/sbi/sbi_system.c
+++ b/lib/sbi/sbi_system.c
@@ -79,7 +79,7 @@ void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
 	}
 
 	/* Stop current HART */
-	sbi_hsm_hart_stop(scratch, FALSE);
+	sbi_hsm_hart_stop(scratch, false);
 
 	/* Platform specific reset if domain allowed system reset */
 	if (dom->system_reset_allowed) {
diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
index c875c90..025cf61 100644
--- a/lib/sbi/sbi_trap.c
+++ b/lib/sbi/sbi_trap.c
@@ -88,12 +88,12 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 {
 	ulong hstatus, vsstatus, prev_mode;
 #if __riscv_xlen == 32
-	bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
+	bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? true : false;
 #else
-	bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
+	bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? true : false;
 #endif
 	/* By default, we redirect to HS-mode */
-	bool next_virt = FALSE;
+	bool next_virt = false;
 
 	/* Sanity check on previous mode */
 	prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
@@ -106,7 +106,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 	if (misa_extension('H') && prev_virt) {
 		if ((trap->cause < __riscv_xlen) &&
 		    (csr_read(CSR_HEDELEG) & BIT(trap->cause))) {
-			next_virt = TRUE;
+			next_virt = true;
 		}
 	}
 
diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c
index 0568603..35462a2 100644
--- a/lib/utils/fdt/fdt_domain.c
+++ b/lib/utils/fdt/fdt_domain.c
@@ -401,9 +401,9 @@ static int __fdt_parse_domain(void *fdt, int domain_offset, void *opaque)
 	/* Read "system-reset-allowed" DT property */
 	if (fdt_get_property(fdt, domain_offset,
 			     "system-reset-allowed", NULL))
-		dom->system_reset_allowed = TRUE;
+		dom->system_reset_allowed = true;
 	else
-		dom->system_reset_allowed = FALSE;
+		dom->system_reset_allowed = false;
 
 	/* Find /cpus DT node */
 	cpus_offset = fdt_path_offset(fdt, "/cpus");
diff --git a/lib/utils/reset/fdt_reset_gpio.c b/lib/utils/reset/fdt_reset_gpio.c
index bd2c622..6a908dd 100644
--- a/lib/utils/reset/fdt_reset_gpio.c
+++ b/lib/utils/reset/fdt_reset_gpio.c
@@ -77,7 +77,7 @@ static void gpio_reset_exec(struct gpio_reset *reset)
 
 static int gpio_system_poweroff_check(u32 type, u32 reason)
 {
-	if (gpio_reset_get(FALSE, type))
+	if (gpio_reset_get(false, type))
 		return 128;
 
 	return 0;
@@ -85,7 +85,7 @@ static int gpio_system_poweroff_check(u32 type, u32 reason)
 
 static void gpio_system_poweroff(u32 type, u32 reason)
 {
-	gpio_reset_exec(gpio_reset_get(FALSE, type));
+	gpio_reset_exec(gpio_reset_get(false, type));
 }
 
 static struct sbi_system_reset_device gpio_poweroff = {
@@ -96,7 +96,7 @@ static struct sbi_system_reset_device gpio_poweroff = {
 
 static int gpio_system_restart_check(u32 type, u32 reason)
 {
-	if (gpio_reset_get(TRUE, type))
+	if (gpio_reset_get(true, type))
 		return 128;
 
 	return 0;
@@ -104,7 +104,7 @@ static int gpio_system_restart_check(u32 type, u32 reason)
 
 static void gpio_system_restart(u32 type, u32 reason)
 {
-	gpio_reset_exec(gpio_reset_get(TRUE, type));
+	gpio_reset_exec(gpio_reset_get(true, type));
 }
 
 static struct sbi_system_reset_device gpio_restart = {
@@ -149,7 +149,7 @@ static int gpio_reset_init(void *fdt, int nodeoff,
 }
 
 static const struct fdt_match gpio_poweroff_match[] = {
-	{ .compatible = "gpio-poweroff", .data = (const void *)FALSE },
+	{ .compatible = "gpio-poweroff", .data = (const void *)false },
 	{ },
 };
 
@@ -159,7 +159,7 @@ struct fdt_reset fdt_poweroff_gpio = {
 };
 
 static const struct fdt_match gpio_reset_match[] = {
-	{ .compatible = "gpio-restart", .data = (const void *)TRUE },
+	{ .compatible = "gpio-restart", .data = (const void *)true },
 	{ },
 };
 
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c
index 56a666b..1e341c2 100644
--- a/platform/fpga/ariane/platform.c
+++ b/platform/fpga/ariane/platform.c
@@ -56,7 +56,7 @@ static struct aclint_mtimer_data mtimer = {
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
 	.hart_count = ARIANE_HART_COUNT,
-	.has_64bit_mmio = TRUE,
+	.has_64bit_mmio = true,
 };
 
 /*
diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
index 5ff7d20..57ae698 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/fpga/openpiton/platform.c
@@ -60,7 +60,7 @@ static struct aclint_mtimer_data mtimer = {
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
 	.hart_count = OPENPITON_DEFAULT_HART_COUNT,
-	.has_64bit_mmio = TRUE,
+	.has_64bit_mmio = true,
 };
 
 /*
diff --git a/platform/generic/sifive/fu740.c b/platform/generic/sifive/fu740.c
index f595c04..fe71ce6 100644
--- a/platform/generic/sifive/fu740.c
+++ b/platform/generic/sifive/fu740.c
@@ -205,7 +205,7 @@ static int da9063_reset_init(void *fdt, int nodeoff,
 }
 
 static const struct fdt_match da9063_reset_match[] = {
-	{ .compatible = "dlg,da9063", .data = (void *)TRUE },
+	{ .compatible = "dlg,da9063", .data = (void *)true },
 	{ },
 };
 
diff --git a/platform/kendryte/k210/platform.c b/platform/kendryte/k210/platform.c
index ef848c7..7eb9015 100644
--- a/platform/kendryte/k210/platform.c
+++ b/platform/kendryte/k210/platform.c
@@ -52,7 +52,7 @@ static struct aclint_mtimer_data mtimer = {
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
 	.hart_count = K210_HART_COUNT,
-	.has_64bit_mmio = TRUE,
+	.has_64bit_mmio = true,
 };
 
 static u32 k210_get_clk_freq(void)
diff --git a/platform/nuclei/ux600/platform.c b/platform/nuclei/ux600/platform.c
index 2b02734..4eccff1 100644
--- a/platform/nuclei/ux600/platform.c
+++ b/platform/nuclei/ux600/platform.c
@@ -83,7 +83,7 @@ static struct aclint_mtimer_data mtimer = {
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
 	.hart_count = UX600_HART_COUNT,
-	.has_64bit_mmio = TRUE,
+	.has_64bit_mmio = true,
 };
 
 static u32 measure_cpu_freq(u32 n)
diff --git a/platform/template/platform.c b/platform/template/platform.c
index f3802da..8adc431 100644
--- a/platform/template/platform.c
+++ b/platform/template/platform.c
@@ -53,7 +53,7 @@ static struct aclint_mtimer_data mtimer = {
 	.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
 	.first_hartid = 0,
 	.hart_count = PLATFORM_HART_COUNT,
-	.has_64bit_mmio = TRUE,
+	.has_64bit_mmio = true,
 };
 
 /*
-- 
2.34.1



From bmeng.cn at gmail.com  Wed Dec 21 05:32:53 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 21:32:53 +0800
Subject: [PATCH v4 2/3] platform: generic: Allow platform_override to
 select cold boot HART
In-Reply-To: <20221220034102.150151-3-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com> <20221220034102.150151-3-weiliang.lim@starfivetech.com>
Message-ID: <CAEUhbmW30_pRyiePwxVKkQqyrV9zXLgy2sdMD_iYhsRWoTRygw@mail.gmail.com>

On Tue, Dec 20, 2022 at 11:48 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> From: Anup Patel <apatel at ventanamicro.com>
>
> We add a generic platform override callback to allow platform specific
> selection of cold boot HART.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  platform/generic/include/platform_override.h | 1 +
>  platform/generic/platform.c                  | 9 +++++++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index 7f1558d..21354e9 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -18,6 +18,7 @@ struct platform_override {
>         const struct fdt_match *match_table;
>         u64 (*features)(const struct fdt_match *match);
>         u64 (*tlbr_flush_limit)(const struct fdt_match *match);
> +       bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
>         int (*early_init)(bool cold_boot, const struct fdt_match *match);
>         int (*final_init)(bool cold_boot, const struct fdt_match *match);
>         void (*early_exit)(const struct fdt_match *match);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index bfe15f0..16aa4f3 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -122,6 +122,14 @@ fail:
>                 wfi();
>  }
>
> +static bool generic_cold_boot_allowed(u32 hartid)
> +{
> +       if (generic_plat && generic_plat->cold_boot_allowed)
> +               return generic_plat->cold_boot_allowed(
> +                                               hartid, generic_plat_match);
> +       return TRUE;

s/TRUE/true

> +}
> +
>  static int generic_nascent_init(void)
>  {
>         if (platform_has_mlevel_imsic)
> @@ -261,6 +269,7 @@ static int generic_console_init(void)
>  }
>
>  const struct sbi_platform_operations platform_ops = {
> +       .cold_boot_allowed      = generic_cold_boot_allowed,
>         .nascent_init           = generic_nascent_init,
>         .early_init             = generic_early_init,
>         .final_init             = generic_final_init,
> --
> 2.25.1
>

Otherwise,
Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Dec 21 05:32:04 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 21:32:04 +0800
Subject: [PATCH v4 1/3] lib: sbi: Allow platform to influence cold boot
 HART selection
In-Reply-To: <20221220034102.150151-2-weiliang.lim@starfivetech.com>
References: <20221220034102.150151-1-weiliang.lim@starfivetech.com> <20221220034102.150151-2-weiliang.lim@starfivetech.com>
Message-ID: <CAEUhbmWbMcZS9wKQqDyhVoHUUTkvpH=8aLwHnQfD2Y+3orog0g@mail.gmail.com>

On Tue, Dec 20, 2022 at 11:48 AM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> From: Anup Patel <apatel at ventanamicro.com>
>
> We add an optional cold_boot_allowed() platform callback which allows
> platform support to decide which HARTs can do cold boot initialization.
>
> If this platform callback is not available then any HART can do cold
> boot initialization.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
>  lib/sbi/sbi_init.c         |  7 +++++--
>  2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 722f27a..566eee3 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -65,6 +65,9 @@ enum sbi_platform_features {
>
>  /** Platform functions */
>  struct sbi_platform_operations {
> +       /* Check if specified HART is allowed to do cold boot */
> +       bool (*cold_boot_allowed)(u32 hartid);
> +
>         /* Platform nascent initialization */
>         int (*nascent_init)(void);
>
> @@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
>         return FALSE;
>  }
>
> +/**
> + * Check whether given HART is allowed to do cold boot
> + *
> + * @param plat pointer to struct sbi_platform
> + * @param hartid HART ID
> + *
> + * @return TRUE if HART is allowed to do cold boot and FALSE otherwise

s/TRUE/true/g
s/FALSE/false/g

> + */
> +static inline bool sbi_platform_cold_boot_allowed(
> +                                       const struct sbi_platform *plat,
> +                                       u32 hartid)
> +{
> +       if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
> +               return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
> +       return TRUE;
> +}
> +
>  /**
>   * Nascent (very early) initialization for current HART
>   *
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..d4902d9 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
>          * HARTs which satisfy above condition.
>          */
>
> -       if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> -               coldboot = TRUE;
> +       if (sbi_platform_cold_boot_allowed(plat, hartid)) {
> +               if (next_mode_supported &&
> +                   atomic_xchg(&coldboot_lottery, 1) == 0)
> +                       coldboot = TRUE;
> +       }
>
>         /*
>          * Do platform specific nascent (very early) initialization so
> --
> 2.25.1

Otherwise,
Reviewed-by: Bin Meng <bmeng at tinylab.org>


From bmeng.cn at gmail.com  Wed Dec 21 05:43:24 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 21:43:24 +0800
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi
 state reflect back in status
In-Reply-To: <20221212030804.927309-3-debug@rivosinc.com>
References: <20221212030804.927309-1-debug@rivosinc.com> <20221212030804.927309-3-debug@rivosinc.com>
Message-ID: <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com>

On Mon, Dec 12, 2022 at 11:10 AM Deepak Gupta <debug at rivosinc.com> wrote:
>
> This patch adds support for zsslpcfi detection in sbi_hart.c
> If zsslpcfi is detected, this turns on menvcfg.CFI
>
> zsslpcfi records status of cfi state in xstatus csr. Missing landing pad
> sets MPELP in mstatus. When SBI is redirecting back to S/VS/HS, SPELP is
> set in sstatus/vsstatus.
>
> Signed-off-by: Deepak Gupta <debug at rivosinc.com>
> ---
>  include/sbi/riscv_encoding.h |  2 ++
>  lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
>  lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
>  3 files changed, 41 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 1fb520f..d7886e7 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -32,6 +32,8 @@
>  #define MSTATUS_TVM                    _UL(0x00100000)
>  #define MSTATUS_TW                     _UL(0x00200000)
>  #define MSTATUS_TSR                    _UL(0x00400000)
> +#define MSTATUS_SPELP                  _UL(0x10000000)
> +#define MSTATUS_MPELP                  _UL(0x20000000)
>  #define MSTATUS32_SD                   _UL(0x80000000)
>  #if __riscv_xlen == 64
>  #define MSTATUS_UXL                    _ULL(0x0000000300000000)
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 5447c52..6beae2d 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -157,6 +157,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
>  #endif
>                 }
>
> +               if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSLPCFI)) {
> +#if __riscv_xlen == 32
> +                       unsigned long menvcfgh_val;
> +                       menvcfgh_val = csr_read(CSR_MENVCFGH);
> +                       menvcfgh_val |= ENVCFGH_CFI;
> +                       csr_write(CSR_MENVCFGH, menvcfgh_val);
> +#else
> +                       menvcfg_val |= ENVCFG_CFI;
> +#endif
> +               }
>                 csr_write(CSR_MENVCFG, menvcfg_val);
>         }
>
> @@ -555,6 +565,7 @@ static int hart_detect_features(struct sbi_scratch *scratch)
>                 sbi_scratch_offset_ptr(scratch, hart_features_offset);
>         unsigned long val, oldval;
>         int rc;
> +       int ssp_exist, lplr_exist;

Use bool

>
>         /* If hart features already detected then do nothing */
>         if (hfeatures->detected)
> @@ -693,6 +704,16 @@ __mhpm_skip:
>                                         SBI_HART_EXT_SMSTATEEN, true);
>         }
>
> +       if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
> +               val = csr_read_allowed(CSR_SSP, (unsigned long)&trap);
> +               ssp_exist = trap.cause?0:1;

need space around ? and :

use true/false instead of 1/0

> +               val = csr_read_allowed(CSR_LPLR, (unsigned long)&trap);
> +               lplr_exist = trap.cause?0:1;
> +               if (lplr_exist & ssp_exist)
> +                       __sbi_hart_update_extension(hfeatures,
> +                                       SBI_HART_EXT_SSLPCFI, true);
> +       }
> +
>         /* Let platform populate extensions */
>         rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
>                                           hfeatures);
> diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
> index c875c90..a700041 100644
> --- a/lib/sbi/sbi_trap.c
> +++ b/lib/sbi/sbi_trap.c
> @@ -87,6 +87,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>                       struct sbi_trap_info *trap)
>  {
>         ulong hstatus, vsstatus, prev_mode;
> +       bool elp = FALSE;

s/FALSE/false

>  #if __riscv_xlen == 32
>         bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
>  #else
> @@ -100,6 +101,13 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>         if (prev_mode != PRV_S && prev_mode != PRV_U)
>                 return SBI_ENOTSUPP;
>
> +       /* If extension has support for CFI, clear MPELP because redirecting to VS or (H)S */
> +       if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSLPCFI)) {
> +               elp = (regs->mstatus & MSTATUS_MPELP)? TRUE: FALSE;
> +               /* Since redirecting, clear mpelp unconditionally */
> +               regs->mstatus &= ~MSTATUS_MPELP;
> +       }
> +
>         /* If exceptions came from VS/VU-mode, redirect to VS-mode if
>          * delegated in hedeleg
>          */
> @@ -153,6 +161,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>                 /* Get VS-mode SSTATUS CSR */
>                 vsstatus = csr_read(CSR_VSSTATUS);
>
> +               /*if elp was set, set it back in vsstatus */

need space after /*

> +               if (elp) {
> +                       vsstatus |= MSTATUS_SPELP;
> +               }
> +
>                 /* Set SPP for VS-mode */
>                 vsstatus &= ~SSTATUS_SPP;
>                 if (prev_mode == PRV_S)
> @@ -193,6 +206,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
>
>                 /* Clear SIE for S-mode */
>                 regs->mstatus &= ~MSTATUS_SIE;
> +
> +               /* if elp was set, set it back in mstatus */
> +               if (elp) {
> +                       regs->mstatus |= MSTATUS_SPELP;
> +               }
>         }
>

Regards,
Bin


From bmeng.cn at gmail.com  Wed Dec 21 05:39:51 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 21:39:51 +0800
Subject: [PATCH Zisslpcfi 1/2] include: adding support for zsslpcfi encodings
In-Reply-To: <20221212030804.927309-2-debug@rivosinc.com>
References: <20221212030804.927309-1-debug@rivosinc.com> <20221212030804.927309-2-debug@rivosinc.com>
Message-ID: <CAEUhbmXam4R3af9njRYYAXOFw8PYeYOXCRfjKfcbae=su-87dw@mail.gmail.com>

On Mon, Dec 12, 2022 at 11:10 AM Deepak Gupta <debug at rivosinc.com> wrote:
>
> zsslpcfi extension (see links) introduces b60 (CFI) in menvcfg CSR to

The extension name is Zisslpcfi (capital Z)

> enable shadow stack and landing pad for machine and lesser privileged
> modes. Additionally extension introduces new bits in xstatus for cfi
> state.
>
> Links:https://github.com/riscv/riscv-cfi

nits: need a space after :

s/Links/Link

>
> Signed-off-by: Deepak Gupta <debug at rivosinc.com>
> ---
>  include/sbi/riscv_encoding.h | 4 ++++
>  include/sbi/sbi_hart.h       | 2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index b0f08c8..1fb520f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -210,9 +210,11 @@
>  #if __riscv_xlen > 32
>  #define ENVCFG_STCE                    (_ULL(1) << 63)
>  #define ENVCFG_PBMTE                   (_ULL(1) << 62)
> +#define ENVCFG_CFI                     (_ULL(1) << 60)
>  #else
>  #define ENVCFGH_STCE                   (_UL(1) << 31)
>  #define ENVCFGH_PBMTE                  (_UL(1) << 30)
> +#define ENVCFGH_CFI                    (_UL(1) << 28)
>  #endif
>  #define ENVCFG_CBZE                    (_UL(1) << 7)
>  #define ENVCFG_CBCFE                   (_UL(1) << 6)
> @@ -229,6 +231,8 @@
>  #define CSR_USTATUS                    0x000
>  #define CSR_UIE                                0x004
>  #define CSR_UTVEC                      0x005
> +#define CSR_LPLR                       0x006
> +#define CSR_SSP                                0x020
>
>  /* User Trap Handling (N-extension) */
>  #define CSR_USCRATCH                   0x040
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 95b40e7..d25227d 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -36,6 +36,8 @@ enum sbi_hart_extensions {
>         SBI_HART_EXT_SMSTATEEN,
>         /** HART has Sstc extension */
>         SBI_HART_EXT_SSTC,
> +       /** HART has sslpcfi extension */

Zisslpcfi

> +       SBI_HART_EXT_SSLPCFI,

SBI_HART_EXT_ZISSLPCFI

>
>         /** Maximum index of Hart extension */
>         SBI_HART_EXT_MAX,
> --

Regards,
Bin


From conor at kernel.org  Wed Dec 21 05:59:40 2022
From: conor at kernel.org (Conor Dooley)
Date: Wed, 21 Dec 2022 13:59:40 +0000
Subject: [PATCH v1] docs: pmu: fix binding example
Message-ID: <20221221135939.266377-1-conor@kernel.org>

From: Conor Dooley <conor.dooley at microchip.com>

The first PMU binding example does not terminate properties with a ;,
which is invalid. Noticed while converting the binding to yaml.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
 docs/pmu_support.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 1db36fc..1a16bad 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -70,17 +70,17 @@ via platform hooks rather than the device tree.
 ```
 pmu {
 	compatible 			= "riscv,pmu";
-	riscv,event-to-mhpmevent 		= <0x0000B  0x0000 0x0001>,
+	riscv,event-to-mhpmevent 		= <0x0000B  0x0000 0x0001>;
 	riscv,event-to-mhpmcounters 	= <0x00001 0x00001 0x00000001>,
 						  <0x00002 0x00002 0x00000004>,
 						  <0x00003 0x0000A 0x00000ff8>,
-						  <0x10000 0x10033 0x000ff000>,
+						  <0x10000 0x10033 0x000ff000>;
 					/* For event ID 0x0002 */
 	riscv,raw-event-to-mhpmcounters = <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
 					/* For event ID 0-4 */
 					<0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
 					/* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
-					<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>,
+					<0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
 };
 ```
 
-- 
2.38.1



From schwab at suse.de  Wed Dec 21 05:59:54 2022
From: schwab at suse.de (Andreas Schwab)
Date: Wed, 21 Dec 2022 14:59:54 +0100
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi
 state reflect back in status
In-Reply-To: <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com>
	(Bin Meng's message of "Wed, 21 Dec 2022 21:43:24 +0800")
References: <20221212030804.927309-1-debug@rivosinc.com>
	<20221212030804.927309-3-debug@rivosinc.com>
	<CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com>
Message-ID: <mvmwn6kn9gl.fsf@suse.de>

On Dez 21 2022, Bin Meng wrote:

>> @@ -693,6 +704,16 @@ __mhpm_skip:
>>                                         SBI_HART_EXT_SMSTATEEN, true);
>>         }
>>
>> +       if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
>> +               val = csr_read_allowed(CSR_SSP, (unsigned long)&trap);
>> +               ssp_exist = trap.cause?0:1;

                   ssp_exist = trap.cause == 0;

-- 
Andreas Schwab, SUSE Labs, schwab at suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."


From atishp at atishpatra.org  Wed Dec 21 07:02:41 2022
From: atishp at atishpatra.org (Atish Patra)
Date: Wed, 21 Dec 2022 07:02:41 -0800
Subject: Upcoming OpenSBI v1.2 release
In-Reply-To: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>
References: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>
Message-ID: <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>

On Fri, Dec 16, 2022 at 9:42 PM Anup Patel <anup at brainfault.org> wrote:
>
> Hi All,
>
> We are close to the OpenSBI v1.2 release. I plan to complete this
> release before the end of next week (i.e. 24th December 2022).
>
> Next week, I won't be merging patches unless it's a critical fix.
> Also, I request everyone to test the latest OpenSBI on their RISC-V
> platforms.
>

Explicitly adding some folks for help in testing. We don't have access
to all the boards.
It would be great if folks can test the latest head commit b848d87 on
the boards they have and send a Tested by tag.

> Thanks & Regards,
> Anup
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi



-- 
Regards,
Atish


From ben.dooks at codethink.co.uk  Wed Dec 21 07:05:07 2022
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Wed, 21 Dec 2022 15:05:07 +0000
Subject: [PATCH] treewide: Replace TRUE/FALSE with true/false
In-Reply-To: <20221221113806.1450323-1-bmeng@tinylab.org>
References: <20221221113806.1450323-1-bmeng@tinylab.org>
Message-ID: <b8716804-8e2b-cbd3-c6b9-74d1529e92e7@codethink.co.uk>

On 21/12/2022 11:38, Bin Meng wrote:
> C language standard uses true/false for the boolean type.
> Let's switch to that for better language compatibility.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>

snip

> diff --git a/include/sbi/sbi_types.h b/include/sbi/sbi_types.h
> index 7fb1af7..75cdddd 100644
> --- a/include/sbi/sbi_types.h
> +++ b/include/sbi/sbi_types.h
> @@ -54,10 +54,8 @@ typedef unsigned long		virtual_size_t;
>   typedef unsigned long		physical_addr_t;
>   typedef unsigned long		physical_size_t;
>   
> -#define TRUE			1
> -#define FALSE			0
> -#define true			TRUE
> -#define false			FALSE
> +#define true			1
> +#define false			0
>   

I assume we can't use the <stdbool.h> ?



-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html



From bmeng at tinylab.org  Wed Dec 21 07:31:44 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Wed, 21 Dec 2022 15:31:44 +0000
Subject: [PATCH] treewide: Replace TRUE/FALSE with true/false
In-Reply-To: <b8716804-8e2b-cbd3-c6b9-74d1529e92e7@codethink.co.uk>
References: <20221221113806.1450323-1-bmeng@tinylab.org>
 <b8716804-8e2b-cbd3-c6b9-74d1529e92e7@codethink.co.uk>
Message-ID: <em0d571ad2-e509-497e-a061-623da606451c@a9022134.com>

On 2022/12/21 23:05:07, "Ben Dooks" <ben.dooks at codethink.co.uk> wrote:

>On 21/12/2022 11:38, Bin Meng wrote:
>>C language standard uses true/false for the boolean type.
>>Let's switch to that for better language compatibility.
>>
>>Signed-off-by: Bin Meng <bmeng at tinylab.org>
>
>snip
>
>>diff --git a/include/sbi/sbi_types.h b/include/sbi/sbi_types.h
>>index 7fb1af7..75cdddd 100644
>>--- a/include/sbi/sbi_types.h
>>+++ b/include/sbi/sbi_types.h
>>@@ -54,10 +54,8 @@ typedef unsigned long		virtual_size_t;
>>   typedef unsigned long		physical_addr_t;
>>   typedef unsigned long		physical_size_t;
>>   -#define TRUE			1
>>-#define FALSE			0
>>-#define true			TRUE
>>-#define false			FALSE
>>+#define true			1
>>+#define false			0
>>
>
>I assume we can't use the <stdbool.h> ?
>

Yes, as we are using -nostdinc and -nostdlib.

Regards,
Bin


From bmeng.cn at gmail.com  Wed Dec 21 07:33:40 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Wed, 21 Dec 2022 23:33:40 +0800
Subject: [PATCH v1] docs: pmu: fix binding example
In-Reply-To: <20221221135939.266377-1-conor@kernel.org>
References: <20221221135939.266377-1-conor@kernel.org>
Message-ID: <CAEUhbmWXo3Xoz2AxnNeEXZSn21Sg=7eu7z65qtp+ZYh9vc1GSQ@mail.gmail.com>

On Wed, Dec 21, 2022 at 10:14 PM Conor Dooley <conor at kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley at microchip.com>
>
> The first PMU binding example does not terminate properties with a ;,
> which is invalid. Noticed while converting the binding to yaml.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  docs/pmu_support.md | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng at tinylab.org>


From prabhakar.csengg at gmail.com  Wed Dec 21 10:04:34 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Wed, 21 Dec 2022 18:04:34 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <Y6MWqO71cISuLEOk@APC323>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <CAEUhbmW5WmNSPNNe4UWq6o7ZtOgT=9N5f2=F6L+ScLSzW_K8dQ@mail.gmail.com> <Y6MWqO71cISuLEOk@APC323>
Message-ID: <CA+V-a8vB2u2yjYno=Y_jAAjYg3gC1qCrrg7X6gQjAD1gbkr=_g@mail.gmail.com>

Hi Yu-Chien,

On Wed, Dec 21, 2022 at 6:26 AM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> On Wed, Dec 21, 2022 at 09:23:21AM +0800, Bin Meng wrote:
> > On Mon, Dec 12, 2022 at 5:44 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj at bp.renesas.com> wrote:
> > >
> > > Add support to configure the PMA regions and create a corresponding
> > > reserve memory node and propagate it to the higher boot stack.
> > >
> > > &L2 {
> > >        andestech,pma-regions = <0x0 0x58000000 0x0 0x08000000
> > >                                 (AX45MP_PMACFG_ETYP_NAPOT |
> > >                                  AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF)>;
> > > };
> > >
> > > PMA regions are passed as part of L2 cache node to OpenSBI, these regions
> > > are parsed and configured in the OpenSBI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > ---
> > > Hi All,
> > >
> > > This patch is based on the discussion [0] so sending this as an RFC
> > > patch so that we get the Linux side of things accepeted first and once its
> > > finalized I'll send a non RFC patch for this.
> > >
> > > [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20221124172207.153718-8-prabhakar.mahadev-lad.rj at bp.renesas.com/
> > >
> > > Cheers,
> > > Prabhakar
> > > ---
> > >  platform/generic/renesas/rzfive/objects.mk   |   1 +
> > >  platform/generic/renesas/rzfive/rzfive-pma.c | 181 +++++++++++++++
> > >  platform/generic/renesas/rzfive/rzfive-pma.h |  12 +
> >
> > I feel we should name this to something like ax45mp-pma instead of
> > rzfive-pma, as this is at the core configuration level not SoC's, no?
>
> Agreed, Andes PMA CSRs also exist in A45MP (RV32) so it's better if we
> call it andes45-pma.c and andes45_{read|write}_pma{cfg|addr} as function
> name.
>
Ok, I will rename it.

Cheers,
Prabhakar

> Any suggestion to add these functions which will be shared between the
> platforms?
>
> >
> > >  platform/generic/renesas/rzfive/rzfive.c     | 227 +++++++++++++++++++
> > >  4 files changed, 421 insertions(+)
> > >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.c
> > >  create mode 100644 platform/generic/renesas/rzfive/rzfive-pma.h
> > >
>
> Best regards,
> Peter Lin


From prabhakar.csengg at gmail.com  Wed Dec 21 10:19:12 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Wed, 21 Dec 2022 18:19:12 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <Y6MjCN7UD1PqL9pL@APC323>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <Y6IzTcaMxw9JjBW3@APC323> <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>
 <Y6MjCN7UD1PqL9pL@APC323>
Message-ID: <CA+V-a8staavOP=bpnxZw=ZjXFH-XQB7HQLKOF6fY39iFu8Wq0w@mail.gmail.com>

Hi Yu-Chien,

For the next version I'm thinking of having an array in OpenSBI itself
for the PMA regions to be configured instead of passing it from u-boot
and then passing the required region to the upper boot stack. Hope
that's OK with you.

On Wed, Dec 21, 2022 at 7:18 AM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> Hi Prabhakar,
>
> > > > +unsigned long rzfive_setup_pma_region(unsigned long addr, unsigned long size,
> > > > +                                   int entry_id, u32 flag)
> > > > +{
> > > > +     unsigned long size_tmp, shift = 0, pmacfg_val;
> > > > +     unsigned long mmsc = csr_read(CSR_MMSC_CFG);
> > > > +     unsigned long pa = addr;
> > > > +     char *pmaxcfg;
> > > > +     int power = 0;
> > > > +
> > >
> > > The granularity of PMA NAPOT mode is 4KiB, so we should not allow this
> > > case.
> > >
> > > if (size < (1 << 12))
> > >   return SBI_EINVAL;
> > >
> > The manual I am referring to says "The minimal size of NAPOT regions
> > must be 8 bytes."
>
> I checked the section "16.17.1 PMA Configuration Registers" [1],
> it says "The granularity is 4K bytes.".
>
> Besides, here is my observation:
> Assume desired base: 0x58000000
>                size: 0x00000400
>
> (gdb) p/x $pmacfg0
> $10 = {0xf, pma0cfg = {0xf, etyp = 0x3, mtyp = 0x3}, [...]
> (gdb) p/x (0x58000000 >> 2) + (0x400 >> 3) - 1
> $6 = 0x1600007f
> (gdb) p/x $pmaaddr0=0x1600007fl
> $8 = 0x1600007f
> (gdb) p/x $pmaaddr0
> $9 = 0x160001ff
> (gdb) pma_to_addr 0x160001ff
> translate pmaaddr 0x160001ff
> ==========================================
> power:  12
> base:   0x1000
> region: 0x58000000 ~ 0x58001000
>
> [1] http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>
Thanks for the pointer.

Cheers,
Prabhakar


From debug at rivosinc.com  Wed Dec 21 10:41:30 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 10:41:30 -0800
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi
 state reflect back in status
In-Reply-To: <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com>
References: <20221212030804.927309-1-debug@rivosinc.com> <20221212030804.927309-3-debug@rivosinc.com>
 <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com>
Message-ID: <CAKC1njT7f_UWDB_gOWYt9o6R39U-89-vDgpStndyPq4y3uo_sA@mail.gmail.com>

On Wed, Dec 21, 2022 at 5:43 AM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> > @@ -87,6 +87,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
> >                       struct sbi_trap_info *trap)
> >  {
> >         ulong hstatus, vsstatus, prev_mode;
> > +       bool elp = FALSE;
>
> s/FALSE/false

I followed whatever rest of the code is following. In the same function

"
int sbi_trap_redirect(struct sbi_trap_regs *regs,
                      struct sbi_trap_info *trap)
{
        ulong hstatus, vsstatus, prev_mode;
        bool elp = FALSE;
#if __riscv_xlen == 32
        bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
#else
        bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
#endif
        /* By default, we redirect to HS-mode */
        bool next_virt = FALSE;
"
I can change it to false but it'll look ugly because at other places
we're using upper case FALSE.
Let me know what needs to be done.

>
> >  #if __riscv_xlen == 32
> >         bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
> >  #else
> > @@ -100,6 +101,13 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
> >         if (prev_mode != PRV_S && prev_mode != PRV_U)
> >                 return SBI_ENOTSUPP;
> >
> > +       /* If extension has support for CFI, clear MPELP because redirecting to VS or (H)S */
> > +       if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_SSLPCFI)) {
> > +               elp = (regs->mstatus & MSTATUS_MPELP)? TRUE: FALSE;
> > +               /* Since redirecting, clear mpelp unconditionally */
> > +               regs->mstatus &= ~MSTATUS_MPELP;
> > +       }
> > +
> >         /* If exceptions came from VS/VU-mode, redirect to VS-mode if
> >          * delegated in hedeleg
> >          */
> > @@ -153,6 +161,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
> >                 /* Get VS-mode SSTATUS CSR */
> >                 vsstatus = csr_read(CSR_VSSTATUS);
> >
> > +               /*if elp was set, set it back in vsstatus */
>
> need space after /*
>
> > +               if (elp) {
> > +                       vsstatus |= MSTATUS_SPELP;
> > +               }
> > +
> >                 /* Set SPP for VS-mode */
> >                 vsstatus &= ~SSTATUS_SPP;
> >                 if (prev_mode == PRV_S)
> > @@ -193,6 +206,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
> >
> >                 /* Clear SIE for S-mode */
> >                 regs->mstatus &= ~MSTATUS_SIE;
> > +
> > +               /* if elp was set, set it back in mstatus */
> > +               if (elp) {
> > +                       regs->mstatus |= MSTATUS_SPELP;
> > +               }
> >         }
> >
>
> Regards,
> Bin


From debug at rivosinc.com  Wed Dec 21 11:55:33 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 11:55:33 -0800
Subject: [PATCH v2 Zisslpcfi 0/2] Support for zisslpcfi in opensbi
Message-ID: <20221221195535.2136015-1-debug@rivosinc.com>

Zisslpcfi [1] extension extends risc-v architecture to mitigate against
control-flow integrity attacks (ROP/JOP/COP).

Zisslpcfi uses bits (b23-b29) in (m/s/vs) status CSR for enabling cfi in
lesser privileged mode and record cfi state. One such state is expected
landing pad (ELP). If forward cfi is enabled, indirect call/jmp updates
hart's ELP state (1bit) to true. ELP state is cleared only by a landing
pad instruction else trap is delivered with ELP state recorded in sstatus
CSR.

This two patch series adds following changes to opensbi
    - Adds support in opensbi to detect zisslpcfi
    - trap redirection updates ELP state accordingly

Qemu implementation for Zisslpcfi can be checked out on github [2]
Strawman linux kernel enabling (still very early) can be checked out on github [3]

[1] - https://github.com/riscv/riscv-cfi
[2] - https://github.com/deepak0414/qemu/tree/gh_Zisslpcfi-0.1
[3] - https://github.com/deepak0414/linux-riscv-cfi/tree/Zisslpcfi-0.1_v6.1-rc2

Deepak Gupta (2):
  include: adding support for Zisslpcfi encodings
  lib: sbi: Zisslpcfi detection and elp cfi state reflect back in status

 include/sbi/riscv_encoding.h |  6 ++++++
 include/sbi/sbi_hart.h       |  2 ++
 lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
 lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
 4 files changed, 47 insertions(+)

-- 
2.25.1



From debug at rivosinc.com  Wed Dec 21 11:55:34 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 11:55:34 -0800
Subject: [PATCH v2 Zisslpcfi 1/2] include: adding support for Zisslpcfi encodings
In-Reply-To: <20221221195535.2136015-1-debug@rivosinc.com>
References: <20221221195535.2136015-1-debug@rivosinc.com>
Message-ID: <20221221195535.2136015-2-debug@rivosinc.com>

Zisslpcfi extension (see link) introduces b60 (CFI) in menvcfg CSR to
enable shadow stack and landing pad for machine and lesser privileged
modes. Additionally extension introduces new bits in xstatus for cfi
state.

Link: https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug at rivosinc.com>

---
changelog
v1 --> v2:
 - updated with correct name for extension "Zisslpcfi"
---
 include/sbi/riscv_encoding.h | 4 ++++
 include/sbi/sbi_hart.h       | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index b0f08c8..1fb520f 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -210,9 +210,11 @@
 #if __riscv_xlen > 32
 #define ENVCFG_STCE			(_ULL(1) << 63)
 #define ENVCFG_PBMTE			(_ULL(1) << 62)
+#define ENVCFG_CFI			(_ULL(1) << 60)
 #else
 #define ENVCFGH_STCE			(_UL(1) << 31)
 #define ENVCFGH_PBMTE			(_UL(1) << 30)
+#define ENVCFGH_CFI			(_UL(1) << 28)
 #endif
 #define ENVCFG_CBZE			(_UL(1) << 7)
 #define ENVCFG_CBCFE			(_UL(1) << 6)
@@ -229,6 +231,8 @@
 #define CSR_USTATUS			0x000
 #define CSR_UIE				0x004
 #define CSR_UTVEC			0x005
+#define CSR_LPLR			0x006
+#define CSR_SSP				0x020
 
 /* User Trap Handling (N-extension) */
 #define CSR_USCRATCH			0x040
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 95b40e7..d25227d 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -36,6 +36,8 @@ enum sbi_hart_extensions {
 	SBI_HART_EXT_SMSTATEEN,
 	/** HART has Sstc extension */
 	SBI_HART_EXT_SSTC,
+	/** HART has sslpcfi extension */
+	SBI_HART_EXT_SSLPCFI,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
-- 
2.25.1



From debug at rivosinc.com  Wed Dec 21 11:55:35 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 11:55:35 -0800
Subject: [PATCH v2 Zisslpcfi 2/2] lib: sbi: Zisslpcfi detection and elp cfi state reflect back in status
In-Reply-To: <20221221195535.2136015-1-debug@rivosinc.com>
References: <20221221195535.2136015-1-debug@rivosinc.com>
Message-ID: <20221221195535.2136015-3-debug@rivosinc.com>

This patch adds support for Zisslpcfi detection in sbi_hart.c
If Zisslpcfi is detected, this turns on menvcfg.CFI

Zisslpcfi records status of cfi state in xstatus csr. Missing landing pad
sets MPELP in mstatus. When SBI is redirecting back to S/VS/HS, SPELP is
set in sstatus/vsstatus.

Signed-off-by: Deepak Gupta <debug at rivosinc.com>

---
changelog
v1 --> v2:
 - instead of using "int" for lplr_exist/ssp_exist use "bool"
 - use smaller case true/false
 - updates to use correct extension name "Zisslpcfi"
---
 include/sbi/riscv_encoding.h |  2 ++
 include/sbi/sbi_hart.h       |  2 +-
 lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
 lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
 4 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 1fb520f..d7886e7 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -32,6 +32,8 @@
 #define MSTATUS_TVM			_UL(0x00100000)
 #define MSTATUS_TW			_UL(0x00200000)
 #define MSTATUS_TSR			_UL(0x00400000)
+#define MSTATUS_SPELP     		_UL(0x10000000)
+#define MSTATUS_MPELP     		_UL(0x20000000)
 #define MSTATUS32_SD			_UL(0x80000000)
 #if __riscv_xlen == 64
 #define MSTATUS_UXL			_ULL(0x0000000300000000)
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index d25227d..5060262 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -37,7 +37,7 @@ enum sbi_hart_extensions {
 	/** HART has Sstc extension */
 	SBI_HART_EXT_SSTC,
 	/** HART has sslpcfi extension */
-	SBI_HART_EXT_SSLPCFI,
+	SBI_HART_EXT_ZISSLPCFI,
 
 	/** Maximum index of Hart extension */
 	SBI_HART_EXT_MAX,
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5447c52..c287538 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -157,6 +157,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
 		}
 
+		if (sbi_hart_has_extension(scratch, SBI_HART_EXT_ZISSLPCFI)) {
+#if __riscv_xlen == 32
+			unsigned long menvcfgh_val;
+			menvcfgh_val = csr_read(CSR_MENVCFGH);
+			menvcfgh_val |= ENVCFGH_CFI;
+			csr_write(CSR_MENVCFGH, menvcfgh_val);
+#else
+			menvcfg_val |= ENVCFG_CFI;
+#endif
+		}
 		csr_write(CSR_MENVCFG, menvcfg_val);
 	}
 
@@ -555,6 +565,7 @@ static int hart_detect_features(struct sbi_scratch *scratch)
 		sbi_scratch_offset_ptr(scratch, hart_features_offset);
 	unsigned long val, oldval;
 	int rc;
+	bool ssp_exist, lplr_exist;
 
 	/* If hart features already detected then do nothing */
 	if (hfeatures->detected)
@@ -693,6 +704,16 @@ __mhpm_skip:
 					SBI_HART_EXT_SMSTATEEN, true);
 	}
 
+	if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
+		val = csr_read_allowed(CSR_SSP, (unsigned long)&trap);
+		ssp_exist = trap.cause == 0;
+		val = csr_read_allowed(CSR_LPLR, (unsigned long)&trap);
+		lplr_exist = trap.cause == 0;
+		if (lplr_exist & ssp_exist)
+			__sbi_hart_update_extension(hfeatures,
+					SBI_HART_EXT_ZISSLPCFI, true);
+	}
+
 	/* Let platform populate extensions */
 	rc = sbi_platform_extensions_init(sbi_platform_thishart_ptr(),
 					  hfeatures);
diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c
index c875c90..743c740 100644
--- a/lib/sbi/sbi_trap.c
+++ b/lib/sbi/sbi_trap.c
@@ -87,6 +87,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		      struct sbi_trap_info *trap)
 {
 	ulong hstatus, vsstatus, prev_mode;
+	bool elp = false;
 #if __riscv_xlen == 32
 	bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
 #else
@@ -100,6 +101,13 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 	if (prev_mode != PRV_S && prev_mode != PRV_U)
 		return SBI_ENOTSUPP;
 
+	/* If extension has support for CFI, clear MPELP because redirecting to VS or (H)S */
+	if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(), SBI_HART_EXT_ZISSLPCFI)) {
+		elp = (regs->mstatus & MSTATUS_MPELP)? true: false;
+		/* Since redirecting, clear mpelp unconditionally */
+		regs->mstatus &= ~MSTATUS_MPELP;
+	}
+
 	/* If exceptions came from VS/VU-mode, redirect to VS-mode if
 	 * delegated in hedeleg
 	 */
@@ -153,6 +161,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 		/* Get VS-mode SSTATUS CSR */
 		vsstatus = csr_read(CSR_VSSTATUS);
 
+		/*if elp was set, set it back in vsstatus */
+		if (elp) {
+			vsstatus |= MSTATUS_SPELP;
+		}
+
 		/* Set SPP for VS-mode */
 		vsstatus &= ~SSTATUS_SPP;
 		if (prev_mode == PRV_S)
@@ -193,6 +206,11 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 
 		/* Clear SIE for S-mode */
 		regs->mstatus &= ~MSTATUS_SIE;
+
+		/* if elp was set, set it back in mstatus */
+		if (elp) {
+			regs->mstatus |= MSTATUS_SPELP;
+		}
 	}
 
 	return 0;
-- 
2.25.1



From debug at rivosinc.com  Wed Dec 21 12:01:24 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 12:01:24 -0800
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi
 state reflect back in status
In-Reply-To: <mvmwn6kn9gl.fsf@suse.de>
References: <20221212030804.927309-1-debug@rivosinc.com> <20221212030804.927309-3-debug@rivosinc.com>
 <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com> <mvmwn6kn9gl.fsf@suse.de>
Message-ID: <CAKC1njQB_QQAA5q6LpKk=PY3pf4Vp897BGREP063fHyxKOXChA@mail.gmail.com>

Thanks Andreas and Bin for your review comments.
Sent out v2 version of the patch.

-Deepak

On Wed, Dec 21, 2022 at 5:59 AM Andreas Schwab <schwab at suse.de> wrote:
>
> On Dez 21 2022, Bin Meng wrote:
>
> >> @@ -693,6 +704,16 @@ __mhpm_skip:
> >>                                         SBI_HART_EXT_SMSTATEEN, true);
> >>         }
> >>
> >> +       if (hfeatures->priv_version >= SBI_HART_PRIV_VER_1_12) {
> >> +               val = csr_read_allowed(CSR_SSP, (unsigned long)&trap);
> >> +               ssp_exist = trap.cause?0:1;
>
>                    ssp_exist = trap.cause == 0;
>
> --
> Andreas Schwab, SUSE Labs, schwab at suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."


From debug at rivosinc.com  Wed Dec 21 15:38:39 2022
From: debug at rivosinc.com (Deepak Gupta)
Date: Wed, 21 Dec 2022 15:38:39 -0800
Subject: [PATCH v2 Zisslpcfi 0/2] Support for zisslpcfi in opensbi
In-Reply-To: <20221221195535.2136015-1-debug@rivosinc.com>
References: <20221221195535.2136015-1-debug@rivosinc.com>
Message-ID: <CAKC1njQWJ43mk5bkkccL58F9MHDcZj8QNZVvpVmDj6nAChcyJw@mail.gmail.com>

Please don't bother with your time and ignore this patch series.
Something went wrong on my setup and patches didn't come out as expected.

I'll send a new version.
Apologies.

-Deepak

On Wed, Dec 21, 2022 at 11:55 AM Deepak Gupta <debug at rivosinc.com> wrote:
>
> Zisslpcfi [1] extension extends risc-v architecture to mitigate against
> control-flow integrity attacks (ROP/JOP/COP).
>
> Zisslpcfi uses bits (b23-b29) in (m/s/vs) status CSR for enabling cfi in
> lesser privileged mode and record cfi state. One such state is expected
> landing pad (ELP). If forward cfi is enabled, indirect call/jmp updates
> hart's ELP state (1bit) to true. ELP state is cleared only by a landing
> pad instruction else trap is delivered with ELP state recorded in sstatus
> CSR.
>
> This two patch series adds following changes to opensbi
>     - Adds support in opensbi to detect zisslpcfi
>     - trap redirection updates ELP state accordingly
>
> Qemu implementation for Zisslpcfi can be checked out on github [2]
> Strawman linux kernel enabling (still very early) can be checked out on github [3]
>
> [1] - https://github.com/riscv/riscv-cfi
> [2] - https://github.com/deepak0414/qemu/tree/gh_Zisslpcfi-0.1
> [3] - https://github.com/deepak0414/linux-riscv-cfi/tree/Zisslpcfi-0.1_v6.1-rc2
>
> Deepak Gupta (2):
>   include: adding support for Zisslpcfi encodings
>   lib: sbi: Zisslpcfi detection and elp cfi state reflect back in status
>
>  include/sbi/riscv_encoding.h |  6 ++++++
>  include/sbi/sbi_hart.h       |  2 ++
>  lib/sbi/sbi_hart.c           | 21 +++++++++++++++++++++
>  lib/sbi/sbi_trap.c           | 18 ++++++++++++++++++
>  4 files changed, 47 insertions(+)
>
> --
> 2.25.1
>


From bmeng.cn at gmail.com  Wed Dec 21 17:29:55 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Thu, 22 Dec 2022 09:29:55 +0800
Subject: [PATCH Zisslpcfi 2/2] lib: sbi: zsslpcfi detection and elp cfi
 state reflect back in status
In-Reply-To: <CAKC1njT7f_UWDB_gOWYt9o6R39U-89-vDgpStndyPq4y3uo_sA@mail.gmail.com>
References: <20221212030804.927309-1-debug@rivosinc.com> <20221212030804.927309-3-debug@rivosinc.com>
 <CAEUhbmVbzA5UhFnV+Z_eDVBd1BizjyYjrzoJ7ymT4c=Vx6FjiQ@mail.gmail.com> <CAKC1njT7f_UWDB_gOWYt9o6R39U-89-vDgpStndyPq4y3uo_sA@mail.gmail.com>
Message-ID: <CAEUhbmU_VSxOZimny4A8Ym3ELo_5EZpKD=jaYwnPGQm_Rcqwog@mail.gmail.com>

On Thu, Dec 22, 2022 at 2:41 AM Deepak Gupta <debug at rivosinc.com> wrote:
>
> On Wed, Dec 21, 2022 at 5:43 AM Bin Meng <bmeng.cn at gmail.com> wrote:
> >
> > > @@ -87,6 +87,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
> > >                       struct sbi_trap_info *trap)
> > >  {
> > >         ulong hstatus, vsstatus, prev_mode;
> > > +       bool elp = FALSE;
> >
> > s/FALSE/false
>
> I followed whatever rest of the code is following. In the same function
>
> "
> int sbi_trap_redirect(struct sbi_trap_regs *regs,
>                       struct sbi_trap_info *trap)
> {
>         ulong hstatus, vsstatus, prev_mode;
>         bool elp = FALSE;
> #if __riscv_xlen == 32
>         bool prev_virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
> #else
>         bool prev_virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
> #endif
>         /* By default, we redirect to HS-mode */
>         bool next_virt = FALSE;
> "
> I can change it to false but it'll look ugly because at other places
> we're using upper case FALSE.
> Let me know what needs to be done.
>

No need to worry about other places, as I already sent one patch to
change all other places.

Regards,
Bin


From peterlin at andestech.com  Wed Dec 21 18:04:03 2022
From: peterlin at andestech.com (Yu Chien Peter Lin)
Date: Thu, 22 Dec 2022 10:04:03 +0800
Subject: [PATCH] lib: utils/serial: Simplify semihosting_getc() function
Message-ID: <20221222020403.23209-1-peterlin@andestech.com>

Simply pass the character returned by semihosting_trap(SYSREADC, NULL)
on success, or -1 on failure. This also fixes issue [1] of comparison
of constant -1 with char type.

[1] https://github.com/riscv-software-src/opensbi/issues/269

Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
---
 lib/utils/serial/semihosting.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/lib/utils/serial/semihosting.c b/lib/utils/serial/semihosting.c
index 5012fa1..cd15f91 100644
--- a/lib/utils/serial/semihosting.c
+++ b/lib/utils/serial/semihosting.c
@@ -151,15 +151,11 @@ static void semihosting_putc(char ch)
 static int semihosting_getc(void)
 {
 	char ch = 0;
-	int ret;
 
-	if (semihosting_infd < 0)  {
-		ch = semihosting_trap(SYSREADC, NULL);
-		ret = ch > -1 ? ch : -1;
-	} else
-		ret = semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
-
-	return ret;
+	if (semihosting_infd < 0)
+		return semihosting_trap(SYSREADC, NULL);
+	else
+		return semihosting_read(semihosting_infd, &ch, 1) > 0 ? ch : -1;
 }
 
 static struct sbi_console_device semihosting_console = {
-- 
2.34.1



From weiliang.lim at starfivetech.com  Thu Dec 22 00:44:40 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 22 Dec 2022 16:44:40 +0800
Subject: [PATCH v5 0/4] generic/starfive: Enable Starfive JH7110 platform preferred cold boot HART implementation
Message-ID: <20221222084444.224301-1-weiliang.lim@starfivetech.com>

This is patchset to enable Starfive JH7110 platform preferred cold boot HART implementation.
User has the option to specify preferred cold boot HART in the device tree. If unspecified, the existing lottery mechanism will be used.

Anup Patel (2):
  lib: sbi: Allow platform to influence cold boot HART selection
  platform: generic: Allow platform_override to select cold boot HART

Wei Liang Lim (2):
  platform: generic: Allow platform_override to perform firmware init
  generic/starfive: Add Starfive JH7110 platform implementation

 include/sbi/sbi_platform.h                   | 20 +++++++++
 lib/sbi/sbi_init.c                           |  7 ++-
 platform/generic/Kconfig                     |  4 ++
 platform/generic/configs/defconfig           |  1 +
 platform/generic/include/platform_override.h |  2 +
 platform/generic/platform.c                  | 12 +++++
 platform/generic/starfive/jh7110.c           | 47 ++++++++++++++++++++
 platform/generic/starfive/objects.mk         |  6 +++
 8 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 00:44:41 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 22 Dec 2022 16:44:41 +0800
Subject: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
Message-ID: <20221222084444.224301-2-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..566eee3 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return TRUE if HART is allowed to do cold boot and FALSE otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return TRUE;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d4902d9 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = TRUE;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 00:44:42 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 22 Dec 2022 16:44:42 +0800
Subject: [PATCH v5 2/4] platform: generic: Allow platform_override to select cold boot HART
In-Reply-To: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
Message-ID: <20221222084444.224301-3-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..16aa4f3 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return TRUE;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 00:44:43 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 22 Dec 2022 16:44:43 +0800
Subject: [PATCH v5 3/4] platform: generic: Allow platform_override to perform firmware init
In-Reply-To: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
Message-ID: <20221222084444.224301-4-weiliang.lim@starfivetech.com>

We add a generic platform override callback to allow platform specific firmware init.

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 21354e9..a59b06a 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -26,6 +26,7 @@ struct platform_override {
 	int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
 	int (*extensions_init)(const struct fdt_match *match,
 			       struct sbi_hart_features *hfeatures);
+	void (*fw_init)(void *fdt, const struct fdt_match *match);
 	int (*vendor_ext_check)(long extid, const struct fdt_match *match);
 	int (*vendor_ext_provider)(long extid, long funcid,
 				   const struct sbi_trap_regs *regs,
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 16aa4f3..1cb1750 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -85,6 +85,9 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
 
 	fw_platform_lookup_special(fdt, root_offset);
 
+	if (generic_plat && generic_plat->fw_init)
+		generic_plat->fw_init(fdt, generic_plat_match);
+
 	model = fdt_getprop(fdt, root_offset, "model", &len);
 	if (model)
 		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 00:44:44 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 22 Dec 2022 16:44:44 +0800
Subject: [PATCH v5 4/4] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
Message-ID: <20221222084444.224301-5-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 +++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 47 ++++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 ++++
 4 files changed, 58 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 62c7a2d..47c10e5 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 47fca95..4b0842e 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..9b25fea
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <libfdt.h>
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static u32 selected_hartid = -1;
+
+static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	if (selected_hartid != -1)
+		return (selected_hartid == hartid);
+
+	return TRUE;
+}
+
+static void starfive_jh7110_fw_init(void *fdt, const struct fdt_match *match)
+{
+	const fdt32_t *val;
+	int len, coff;
+
+	coff = fdt_path_offset(fdt, "/chosen");
+	if (-1 < coff) {
+		val = fdt_getprop(fdt, coff, "boot-hart-id", &len);
+		if (val && len)
+			selected_hartid = (u32) fdt32_to_cpu(*val);
+	}
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
+	.fw_init = starfive_jh7110_fw_init,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From bmeng.cn at gmail.com  Thu Dec 22 01:22:06 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Thu, 22 Dec 2022 17:22:06 +0800
Subject: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot
 HART selection
In-Reply-To: <20221222084444.224301-2-weiliang.lim@starfivetech.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com> <20221222084444.224301-2-weiliang.lim@starfivetech.com>
Message-ID: <CAEUhbmVhBo=3hDqFXcbyEs-TpRLQhHAjpiL5hrpO2RYKXA+BCw@mail.gmail.com>

On Thu, Dec 22, 2022 at 4:48 PM Wei Liang Lim
<weiliang.lim at starfivetech.com> wrote:
>
> From: Anup Patel <apatel at ventanamicro.com>
>
> We add an optional cold_boot_allowed() platform callback which allows
> platform support to decide which HARTs can do cold boot initialization.
>
> If this platform callback is not available then any HART can do cold
> boot initialization.
>
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> ---
>  include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
>  lib/sbi/sbi_init.c         |  7 +++++--
>  2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> index 722f27a..566eee3 100644
> --- a/include/sbi/sbi_platform.h
> +++ b/include/sbi/sbi_platform.h
> @@ -65,6 +65,9 @@ enum sbi_platform_features {
>
>  /** Platform functions */
>  struct sbi_platform_operations {
> +       /* Check if specified HART is allowed to do cold boot */
> +       bool (*cold_boot_allowed)(u32 hartid);
> +
>         /* Platform nascent initialization */
>         int (*nascent_init)(void);
>
> @@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
>         return FALSE;
>  }
>
> +/**
> + * Check whether given HART is allowed to do cold boot
> + *
> + * @param plat pointer to struct sbi_platform
> + * @param hartid HART ID
> + *
> + * @return TRUE if HART is allowed to do cold boot and FALSE otherwise

Previous comments were not addressed.

s/TRUE/true/g
s/FALSE/false/g

Please also include a changelog when you send a new version.

The tags (RB, TB, etc) should be carried forward if there are no
significant changes.

> + */
> +static inline bool sbi_platform_cold_boot_allowed(
> +                                       const struct sbi_platform *plat,
> +                                       u32 hartid)
> +{
> +       if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
> +               return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
> +       return TRUE;
> +}
> +
>  /**
>   * Nascent (very early) initialization for current HART
>   *
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..d4902d9 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
>          * HARTs which satisfy above condition.
>          */
>
> -       if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> -               coldboot = TRUE;
> +       if (sbi_platform_cold_boot_allowed(plat, hartid)) {
> +               if (next_mode_supported &&
> +                   atomic_xchg(&coldboot_lottery, 1) == 0)
> +                       coldboot = TRUE;
> +       }
>
>         /*
>          * Do platform specific nascent (very early) initialization so
> --

Regards,
Bin


From Conor.Dooley at microchip.com  Thu Dec 22 02:49:25 2022
From: Conor.Dooley at microchip.com (Conor.Dooley at microchip.com)
Date: Thu, 22 Dec 2022 10:49:25 +0000
Subject: Upcoming OpenSBI v1.2 release
In-Reply-To: <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>
References: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>
 <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>
Message-ID: <efd224b6-47c4-4f55-b247-5e6156c3d451@microchip.com>

Hey,

On 21/12/2022 15:02, Atish Patra wrote:
> On Fri, Dec 16, 2022 at 9:42 PM Anup Patel <anup at brainfault.org> wrote:
>>
>> Hi All,
>>
>> We are close to the OpenSBI v1.2 release. I plan to complete this
>> release before the end of next week (i.e. 24th December 2022).
>>
>> Next week, I won't be merging patches unless it's a critical fix.
>> Also, I request everyone to test the latest OpenSBI on their RISC-V
>> platforms.
>>
> 
> Explicitly adding some folks for help in testing. We don't have access
> to all the boards.

In terms of PolarFire SoC, neither good nor bad news? Since OpenSBI is
just one part of the HSS [0] it's non-trivial to do an upgrade & any
meaningful testing - so probably not a runner in advance of Christmas.

We are incredibly tight on space in eNVM for the HSS as things stand,
so it is likely that we will not move to later versions of OpenSBI
than (maybe) v1.1 & stick to cherry-picking fixes.
The last time the HSS bumped its OpenSBI version, the change in size
of OpenSBI needed some working around IIRC.

I'll try to give my boards from other vendors a go, but I doubt I'll
have anything useful done before the 24th.

Apologies for not being more helpful,
Conor.

0 - https://github.com/polarfire-soc/hart-software-services/tree/master/thirdparty/opensbi

> It would be great if folks can test the latest head commit b848d87 on
> the boards they have and send a Tested by tag.
> 
>> Thanks & Regards,
>> Anup
>>
>> --
>> opensbi mailing list
>> opensbi at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/opensbi
> 
> 
> 
> --
> Regards,
> Atish


From weiliang.lim at starfivetech.com  Thu Dec 22 02:49:43 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Thu, 22 Dec 2022 10:49:43 +0000
Subject: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot
 HART selection
In-Reply-To: <CAEUhbmVhBo=3hDqFXcbyEs-TpRLQhHAjpiL5hrpO2RYKXA+BCw@mail.gmail.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
 <20221222084444.224301-2-weiliang.lim@starfivetech.com>
 <CAEUhbmVhBo=3hDqFXcbyEs-TpRLQhHAjpiL5hrpO2RYKXA+BCw@mail.gmail.com>
Message-ID: <d9655dc839054d54a6db2a625b966192@EXMBX163.cuchost.com>



> -----Original Message-----
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Thursday, December 22, 2022 5:22 PM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> Cc: opensbi at lists.infradead.org; apatel at ventanamicro.com; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot
> HART selection
> 
> On Thu, Dec 22, 2022 at 4:48 PM Wei Liang Lim
> <weiliang.lim at starfivetech.com> wrote:
> >
> > From: Anup Patel <apatel at ventanamicro.com>
> >
> > We add an optional cold_boot_allowed() platform callback which allows
> > platform support to decide which HARTs can do cold boot initialization.
> >
> > If this platform callback is not available then any HART can do cold
> > boot initialization.
> >
> > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > ---
> >  include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
> >  lib/sbi/sbi_init.c         |  7 +++++--
> >  2 files changed, 25 insertions(+), 2 deletions(-)
> >
> > diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> > index 722f27a..566eee3 100644
> > --- a/include/sbi/sbi_platform.h
> > +++ b/include/sbi/sbi_platform.h
> > @@ -65,6 +65,9 @@ enum sbi_platform_features {
> >
> >  /** Platform functions */
> >  struct sbi_platform_operations {
> > +       /* Check if specified HART is allowed to do cold boot */
> > +       bool (*cold_boot_allowed)(u32 hartid);
> > +
> >         /* Platform nascent initialization */
> >         int (*nascent_init)(void);
> >
> > @@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const
> struct sbi_platform *plat,
> >         return FALSE;
> >  }
> >
> > +/**
> > + * Check whether given HART is allowed to do cold boot
> > + *
> > + * @param plat pointer to struct sbi_platform
> > + * @param hartid HART ID
> > + *
> > + * @return TRUE if HART is allowed to do cold boot and FALSE
> > +otherwise
> 
> Previous comments were not addressed.
> 
> s/TRUE/true/g
> s/FALSE/false/g

Should this changes applied to this patch alone or all the patches?

> 
> Please also include a changelog when you send a new version.
> 
> The tags (RB, TB, etc) should be carried forward if there are no significant
> changes.
> 
> > + */
> > +static inline bool sbi_platform_cold_boot_allowed(
> > +                                       const struct sbi_platform *plat,
> > +                                       u32 hartid) {
> > +       if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
> > +               return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
> > +       return TRUE;
> > +}
> > +
> >  /**
> >   * Nascent (very early) initialization for current HART
> >   *
> > diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index
> > a8500e5..d4902d9 100644
> > --- a/lib/sbi/sbi_init.c
> > +++ b/lib/sbi/sbi_init.c
> > @@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch
> *scratch)
> >          * HARTs which satisfy above condition.
> >          */
> >
> > -       if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
> > -               coldboot = TRUE;
> > +       if (sbi_platform_cold_boot_allowed(plat, hartid)) {
> > +               if (next_mode_supported &&
> > +                   atomic_xchg(&coldboot_lottery, 1) == 0)
> > +                       coldboot = TRUE;
> > +       }
> >
> >         /*
> >          * Do platform specific nascent (very early) initialization so
> > --
> 
> Regards,
> Bin

From bmeng.cn at gmail.com  Thu Dec 22 03:32:11 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Thu, 22 Dec 2022 19:32:11 +0800
Subject: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot
 HART selection
In-Reply-To: <d9655dc839054d54a6db2a625b966192@EXMBX163.cuchost.com>
References: <20221222084444.224301-1-weiliang.lim@starfivetech.com>
 <20221222084444.224301-2-weiliang.lim@starfivetech.com> <CAEUhbmVhBo=3hDqFXcbyEs-TpRLQhHAjpiL5hrpO2RYKXA+BCw@mail.gmail.com>
 <d9655dc839054d54a6db2a625b966192@EXMBX163.cuchost.com>
Message-ID: <CAEUhbmVOEB3tiakQuz6PoB8E9fKogrd8C6jZ-mAymWWbW3MX6A@mail.gmail.com>

On Thu, Dec 22, 2022 at 6:49 PM WeiLiang Lim
<weiliang.lim at starfivetech.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn at gmail.com>
> > Sent: Thursday, December 22, 2022 5:22 PM
> > To: WeiLiang Lim <weiliang.lim at starfivetech.com>
> > Cc: opensbi at lists.infradead.org; apatel at ventanamicro.com; Cheehong Ang
> > <cheehong.ang at starfivetech.com>; JunLiang Tan
> > <junliang.tan at starfivetech.com>
> > Subject: Re: [PATCH v5 1/4] lib: sbi: Allow platform to influence cold boot
> > HART selection
> >
> > On Thu, Dec 22, 2022 at 4:48 PM Wei Liang Lim
> > <weiliang.lim at starfivetech.com> wrote:
> > >
> > > From: Anup Patel <apatel at ventanamicro.com>
> > >
> > > We add an optional cold_boot_allowed() platform callback which allows
> > > platform support to decide which HARTs can do cold boot initialization.
> > >
> > > If this platform callback is not available then any HART can do cold
> > > boot initialization.
> > >
> > > Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> > > ---
> > >  include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
> > >  lib/sbi/sbi_init.c         |  7 +++++--
> > >  2 files changed, 25 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
> > > index 722f27a..566eee3 100644
> > > --- a/include/sbi/sbi_platform.h
> > > +++ b/include/sbi/sbi_platform.h
> > > @@ -65,6 +65,9 @@ enum sbi_platform_features {
> > >
> > >  /** Platform functions */
> > >  struct sbi_platform_operations {
> > > +       /* Check if specified HART is allowed to do cold boot */
> > > +       bool (*cold_boot_allowed)(u32 hartid);
> > > +
> > >         /* Platform nascent initialization */
> > >         int (*nascent_init)(void);
> > >
> > > @@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const
> > struct sbi_platform *plat,
> > >         return FALSE;
> > >  }
> > >
> > > +/**
> > > + * Check whether given HART is allowed to do cold boot
> > > + *
> > > + * @param plat pointer to struct sbi_platform
> > > + * @param hartid HART ID
> > > + *
> > > + * @return TRUE if HART is allowed to do cold boot and FALSE
> > > +otherwise
> >
> > Previous comments were not addressed.
> >
> > s/TRUE/true/g
> > s/FALSE/false/g
>
> Should this changes applied to this patch alone or all the patches?
>

On all patches in this series, please.

Regards,
Bin


From peterlin at andestech.com  Thu Dec 22 12:16:01 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Thu, 22 Dec 2022 20:16:01 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <CA+V-a8staavOP=bpnxZw=ZjXFH-XQB7HQLKOF6fY39iFu8Wq0w@mail.gmail.com>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <Y6IzTcaMxw9JjBW3@APC323>
 <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>
 <Y6MjCN7UD1PqL9pL@APC323>
 <CA+V-a8staavOP=bpnxZw=ZjXFH-XQB7HQLKOF6fY39iFu8Wq0w@mail.gmail.com>
Message-ID: <Y6S6uRzAupUkCFP2@APC323>

Hi Prabhakar,

On Wed, Dec 21, 2022 at 06:19:12PM +0000, Lad, Prabhakar wrote:
> Hi Yu-Chien,
> 
> For the next version I'm thinking of having an array in OpenSBI itself
> for the PMA regions to be configured instead of passing it from u-boot
> and then passing the required region to the upper boot stack. Hope
> that's OK with you.

I'll help to test with our platform.

Thanks,
Peter Lin


From prabhakar.csengg at gmail.com  Thu Dec 22 09:52:17 2022
From: prabhakar.csengg at gmail.com (Lad, Prabhakar)
Date: Thu, 22 Dec 2022 17:52:17 +0000
Subject: [RFC PATCH] platform: generic: renesas: Add support to configure
 the PMA
In-Reply-To: <Y6S6uRzAupUkCFP2@APC323>
References: <20221212094421.14556-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <Y6IzTcaMxw9JjBW3@APC323> <CA+V-a8t8G3AawnRNxi373Gp6W15hp9FmHYCCuSANVnyT7wqmXQ@mail.gmail.com>
 <Y6MjCN7UD1PqL9pL@APC323> <CA+V-a8staavOP=bpnxZw=ZjXFH-XQB7HQLKOF6fY39iFu8Wq0w@mail.gmail.com>
 <Y6S6uRzAupUkCFP2@APC323>
Message-ID: <CA+V-a8sXSO3xyREjgM=UUc+BsQFwrEgeRMeGC2g+MshNTqs-Ng@mail.gmail.com>

Hi Yu-Chien,

On Thu, Dec 22, 2022 at 12:19 PM Yu-Chien Peter Lin
<peterlin at andestech.com> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 06:19:12PM +0000, Lad, Prabhakar wrote:
> > Hi Yu-Chien,
> >
> > For the next version I'm thinking of having an array in OpenSBI itself
> > for the PMA regions to be configured instead of passing it from u-boot
> > and then passing the required region to the upper boot stack. Hope
> > that's OK with you.
>
> I'll help to test with our platform.
>
Thanks, that would be great.

While you are testing that, maybe you also want to test the PMA
patches too on your platform ;)

Cheers,
Prabhakar


From conor at kernel.org  Thu Dec 22 11:39:14 2022
From: conor at kernel.org (Conor Dooley)
Date: Thu, 22 Dec 2022 19:39:14 +0000
Subject: [PATCH v1] docs: pmu: update a reference to a deprecated property name
Message-ID: <20221222193913.223114-1-conor@kernel.org>

From: Conor Dooley <conor.dooley at microchip.com>

event-to-mhpmevent was deprecated and replaced by
riscv,event-to-mhpmevent, but a reference remains to the old name.
Replace it with the new one.

Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
 docs/pmu_support.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 1a16bad..9c79636 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -46,7 +46,7 @@ a table format where each row represents a certain range of events and
 corresponding counters. The first column represents starting of the pmu event id
 and 2nd column represents the end of the pmu event id. The third column
 represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
-event-to-mhpmevent is present. Otherwise, it can be omitted. This property
+riscv,event-to-mhpmevent is present. Otherwise, it can be omitted. This property
 shouldn't encode any raw event.
 
 * **riscv,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
-- 
2.38.1



From atishp at rivosinc.com  Thu Dec 22 11:41:33 2022
From: atishp at rivosinc.com (Atish Kumar Patra)
Date: Thu, 22 Dec 2022 11:41:33 -0800
Subject: [PATCH v1] docs: pmu: update a reference to a deprecated property name
In-Reply-To: <20221222193913.223114-1-conor@kernel.org>
References: <20221222193913.223114-1-conor@kernel.org>
Message-ID: <CAHBxVyH5eiopj6n2dBuj6SY8U6V7ohjyQ__NntQyO9WvByS_xQ@mail.gmail.com>

On Thu, Dec 22, 2022 at 11:39 AM Conor Dooley <conor at kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley at microchip.com>
>
> event-to-mhpmevent was deprecated and replaced by
> riscv,event-to-mhpmevent, but a reference remains to the old name.
> Replace it with the new one.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  docs/pmu_support.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 1a16bad..9c79636 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -46,7 +46,7 @@ a table format where each row represents a certain range of events and
>  corresponding counters. The first column represents starting of the pmu event id
>  and 2nd column represents the end of the pmu event id. The third column
>  represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
> -event-to-mhpmevent is present. Otherwise, it can be omitted. This property
> +riscv,event-to-mhpmevent is present. Otherwise, it can be omitted. This property
>  shouldn't encode any raw event.
>


Reviewed-by: Atish Patra <atishp at rivosinc.com>

>  * **riscv,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
> --
> 2.38.1
>


From atishp at rivosinc.com  Thu Dec 22 11:55:29 2022
From: atishp at rivosinc.com (Atish Kumar Patra)
Date: Thu, 22 Dec 2022 11:55:29 -0800
Subject: [PATCH v1] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <Y6SuyiYC/oLB2VzL@spud>
References: <20221221141548.274408-1-conor@kernel.org> <20221222180627.GA1748427-robh@kernel.org>
 <Y6SuyiYC/oLB2VzL@spud>
Message-ID: <CAHBxVyEZJeH6H00Jdcm2_=z-D2kYxVTgagYhmLoyJ2CPqcFbgg@mail.gmail.com>

On Thu, Dec 22, 2022 at 11:24 AM Conor Dooley <conor at kernel.org> wrote:
>
> Hey Rob,
>
> On Thu, Dec 22, 2022 at 12:06:27PM -0600, Rob Herring wrote:
> > On Wed, Dec 21, 2022 at 02:15:49PM +0000, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley at microchip.com>
> > >
> > > The SBI PMU extension requires a firmware to be aware of the event to
> > > counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> > > DeviceTree to describe the PMU mappings. This binding is currently
> > > described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> > > since v7.2.0.
> > >
> > > Import the binding for use while validating dtb dumps from QEMU and
> > > upcoming hardware (eg JH7110 SoC) that will make use of the event
> > > mapping.
> > >
> > > Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> > > Co-developed-by: Atish Patra <atishp at rivosinc.com>
> > > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> > > ---
> > > I asked Rob on IRC about these bindings a few weeks ago & he said he
> > > would be willing to take them. I have modified wording slightly in the
> > > descriptions, but have mostly left things as close to the OpenSBI
> > > documentation as possible.
> >
> > Please CC the perf maintainers. Might be crickets, but so they at least
> > have a chance to see it.
>
> Yah, I was kinda unsure who to CC. It does list them as being
> specifically ARM so I probably made the wrong choice about inclusion.
> I've added them now.
>
> > > I'm not super sure about what I've done with the properties being
> > > correct type wise, I went digging in bindings and am sorta using the
> > > first thing that "fit".
> > >
> > > Since you wrote the md doc Atish, I put your co-developed-by. OpenSBI
> > > is BSD-2-Clause licensed so I am also unsure as to what license I can
> > > use for this binding since that's where I took it from.
> > > ---
> > >  .../devicetree/bindings/perf/riscv,pmu.yaml   | 158 ++++++++++++++++++
> > >  1 file changed, 158 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > > new file mode 100644
> > > index 000000000000..d65f937680af
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > > @@ -0,0 +1,158 @@
> > > +# SPDX-License-Identifier: BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: RISC-V SBI PMU events
> > > +
> > > +maintainers:
> > > +  - Atish Patra <atishp at rivosinc.com>
> > > +
> > > +description: |
> > > +  SBI PMU extension supports allow supervisor software to configure, start &
> > > +  stop any performance counter at anytime. Thus, a user can leverage full
> > > +  capability of performance analysis tools such as perf if the SBI PMU
> > > +  extension is enabled. The OpenSBI implementation makes the following
> > > +  assumptions about the hardware platform:
> > > +    MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, the SBI
> > > +    PMU extension will not be enabled.
> > > +

This is no longer true since OpenSBI commit b28f070. We should remove
this from OpenSBI docs as well.

> > > +    The platform must provide information about PMU event to counter mapping
> > > +    via device tree or platform specific hooks. Otherwise, the SBI PMU
> > > +    extension will not be enabled.
> > > +
> > > +    The platforms should provide information about the PMU event selector
> > > +    values that should be encoded in the expected value of MHPMEVENTx while
> > > +    configuring MHPMCOUNTERx for that specific event. This can be done via a
> > > +    device tree or platform specific hooks. The exact value to be written to
> > > +    the MHPMEVENTx is completely dependent on the platform. The generic
> > > +    platform writes the zero-extended event_idx as the expected value for
> > > +    hardware cache/generic events as suggested by the SBI specification.
> > > +

But the larger question is these are OpenSBI implementation specific
assumptions. Should it be included in
the DT binding ?

> > > +properties:
> > > +  compatible:
> > > +    const: riscv,pmu
> > > +
> > > +  riscv,event-to-mhpmevent:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > +    description:
> > > +      Represents an ONE-to-ONE mapping between a PMU event and the event
> > > +      selector value that platform expects to be written to the MHPMEVENTx CSR
> > > +      for that event.
> > > +      The mapping is encoded in an array format where each row represents an
> >
> > s/array/matrix/
> >
> > > +      event. The first element represents the event idx while the second &
> > > +      third elements represent the event selector value that should be encoded
> > > +      in the expected value to be written in MHPMEVENTx.
> > > +      This property shouldn't encode any raw hardware event.
> > > +    minItems: 1
> > > +    maxItems: 255
>
> I copied these 255s from dt-schema somewhere as a sane max.
> Atish, is there a cap here or should we allow as many as someone likes?
> The md binding doesn't mention any limits - is it in the SBI spec?
> The strongest wording I saw there was "limited" & event idx is 20 bits
> wide as per the spec [0]. Does that make 2^20 the hard limit here?
>

This is for hardware & cache events. The total number of events
defined there are 52 (10 HW + 42 Cache) events.
So 255 is a sane max that provides enough room for expansion in future
if required.

> 0 - https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#11-performance-monitoring-unit-extension-eid-0x504d55-pmu
>
> > > +    items:
> > > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> >
> > Huh? A property can only have 1 type. I wonder what the tools do with
> > this...
>
> I suppose I left this over (by accident) from when I had it arranged
> slightly differently. I guess I never actually noticed as the tools
> don't appear to complain. Now dropped :)
>
> > > +      maxItems: 3
> >
> > Better to do:
> >
> >          items:
> >            - description: what's in the 1st word
> >            - description: what's in the 2nd word
> >            - description: what's in the 3rd word
> >
> > And rework the overall description to not say the same thing.
>
> Yah, good idea. I'll do that for the next version.
>
> > > +  riscv,event-to-mhpmcounters:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > +    description:
> > > +      Represents a MANY-to-MANY mapping between a range of events and all the
> > > +      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
> > > +      of events. The information is encoded in an array format where each
> > > +      row represents a certain range of events and corresponding counters.
> > > +      The first element represents starting of the pmu event id and 2nd column
> > > +      represents the end of the pmu event id. The third element represent a
> > > +      bitmap of all the MHPMCOUNTERx.
> > > +      This property is mandatory if event-to-mhpmevent is present. Otherwise,
> > > +      it can be omitted.
> >
> > No need to state this in freeform text, use 'dependencies'.
>
> Oh! I didn't know that that existed. I was going to go and do some sort
> of required properties dance but perhaps that's not needed now (at least
> to the same extent).
>
> > > +      This property shouldn't encode any raw event.
> > > +    minItems: 1
> > > +    maxItems: 255
> > > +    items:
> > > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > > +      maxItems: 3
> > > +
> > > +  riscv,raw-event-to-mhpmcounters:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > +    description:
> > > +      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
> > > +      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
> > > +      that raw event.
> > > +      The encoding of the raw events are platform specific. The information is
> > > +      encoded in an array format where each row represents the specific raw
> > > +      event(s). The first element is a 64-bit match value where the invariant
> > > +      bits of range of events are set. The second element is a 64-bit mask that
> > > +      will have all the variant bits of the range of events cleared. All other
> > > +      bits should be set in the mask. The third element is a 32-bit value to
> > > +      represent bitmap of all MHPMCOUNTERx that can monitor these set of
> > > +      event(s). If a platform directly encodes each raw PMU event as a unique
> > > +      ID, the value of select_mask must be 0xffffffff_ffffffff.
> > > +    minItems: 1
> > > +    maxItems: 255
> > > +    items:
> > > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > > +      maxItems: 5
> > > +
> > > +required:
> > > +  - compatible
> >
> > I assume at least one of the other properties must be present?
>
> Atish: (and +CC the OpenSBI list)
> Which properties are actually needed here? Or are any? The md binding
> in the OpenSBI sources doesn't seem to require anything other than the
> compatible?
>

That's true. Opensbi allows the platform to define functions
to provide the mapping. Now that's an OpenSBI implementation thing.
Other implementations may choose to use it differently.


> Thanks Rob,
> Conor.
>


From atishp at rivosinc.com  Thu Dec 22 12:38:50 2022
From: atishp at rivosinc.com (Atish Patra)
Date: Thu, 22 Dec 2022 12:38:50 -0800
Subject: [PATCH] docs: pmu: Update the pmu doc with removal of mcountinhbit restriction
Message-ID: <20221222203850.2592975-1-atishp@rivosinc.com>

Since commit b28f070, it is possible for platforms to run perf monitoring
even if mcountinhibit is not supported. Sampling still won't be possible
though as it requires sscofpmf extension.

Update the docs to remove the restriction.

Signed-off-by: Atish Patra <atishp at rivosinc.com>
---
 docs/pmu_support.md | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 1db36fc..c74ef5f 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -6,9 +6,6 @@ capability of performance analysis tools such as perf if SBI PMU extension is
 enabled. The OpenSBI implementation makes the following assumptions about the
 hardware platform.
 
- * MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, SBI PMU
-extension will not be enabled.
-
  * The platform must provide information about PMU event to counter mapping
 via device tree or platform specific hooks. Otherwise, SBI PMU extension will
 not be enabled.
-- 
2.25.1



From atishp at rivosinc.com  Thu Dec 22 12:39:31 2022
From: atishp at rivosinc.com (Atish Kumar Patra)
Date: Thu, 22 Dec 2022 12:39:31 -0800
Subject: [PATCH v1] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <Y6S7ENNXQe42ymTz@spud>
References: <20221221141548.274408-1-conor@kernel.org> <20221222180627.GA1748427-robh@kernel.org>
 <Y6SuyiYC/oLB2VzL@spud> <CAHBxVyEZJeH6H00Jdcm2_=z-D2kYxVTgagYhmLoyJ2CPqcFbgg@mail.gmail.com>
 <Y6S7ENNXQe42ymTz@spud>
Message-ID: <CAHBxVyHn7NEYCJTCJYU3Pu4=t7TGssog3ywaxfd1TFXXF9f9+Q@mail.gmail.com>

On Thu, Dec 22, 2022 at 12:16 PM Conor Dooley <conor at kernel.org> wrote:
>
> On Thu, Dec 22, 2022 at 11:55:29AM -0800, Atish Kumar Patra wrote:
> > On Thu, Dec 22, 2022 at 11:24 AM Conor Dooley <conor at kernel.org> wrote:
> > > On Thu, Dec 22, 2022 at 12:06:27PM -0600, Rob Herring wrote:
> > > > On Wed, Dec 21, 2022 at 02:15:49PM +0000, Conor Dooley wrote:
> > > > > From: Conor Dooley <conor.dooley at microchip.com>
> > > > >
> > > > > The SBI PMU extension requires a firmware to be aware of the event to
> > > > > counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> > > > > DeviceTree to describe the PMU mappings. This binding is currently
> > > > > described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> > > > > since v7.2.0.
> > > > >
> > > > > Import the binding for use while validating dtb dumps from QEMU and
> > > > > upcoming hardware (eg JH7110 SoC) that will make use of the event
> > > > > mapping.
> > > > >
> > > > > Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> > > > > Co-developed-by: Atish Patra <atishp at rivosinc.com>
> > > > > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > > > > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> > > > > +description: |
> > > > > +  SBI PMU extension supports allow supervisor software to configure, start &
> > > > > +  stop any performance counter at anytime. Thus, a user can leverage full
> > > > > +  capability of performance analysis tools such as perf if the SBI PMU
> > > > > +  extension is enabled. The OpenSBI implementation makes the following
> > > > > +  assumptions about the hardware platform:
> > > > > +    MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, the SBI
> > > > > +    PMU extension will not be enabled.
> > > > > +
> >
> > This is no longer true since OpenSBI commit b28f070. We should remove
> > this from OpenSBI docs as well.
>
> Since you know the detail of it, I volunteer you for that one ;)
>

Done.

> > > > > +    The platform must provide information about PMU event to counter mapping
> > > > > +    via device tree or platform specific hooks. Otherwise, the SBI PMU
> > > > > +    extension will not be enabled.
> > > > > +
> > > > > +    The platforms should provide information about the PMU event selector
> > > > > +    values that should be encoded in the expected value of MHPMEVENTx while
> > > > > +    configuring MHPMCOUNTERx for that specific event. This can be done via a
> > > > > +    device tree or platform specific hooks. The exact value to be written to
> > > > > +    the MHPMEVENTx is completely dependent on the platform. The generic
> > > > > +    platform writes the zero-extended event_idx as the expected value for
> > > > > +    hardware cache/generic events as suggested by the SBI specification.
> > > > > +
> >
> > But the larger question is these are OpenSBI implementation specific
> > assumptions. Should it be included in
> > the DT binding?
>
> Probably not. I'll drop it for v2.
>
> > > > > +properties:
> > > > > +  compatible:
> > > > > +    const: riscv,pmu
> > > > > +
> > > > > +  riscv,event-to-mhpmevent:
> > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > > > +    description:
> > > > > +      Represents an ONE-to-ONE mapping between a PMU event and the event
> > > > > +      selector value that platform expects to be written to the MHPMEVENTx CSR
> > > > > +      for that event.
> > > > > +      The mapping is encoded in an array format where each row represents an
> > > >
> > > > s/array/matrix/
> > > >
> > > > > +      event. The first element represents the event idx while the second &
> > > > > +      third elements represent the event selector value that should be encoded
> > > > > +      in the expected value to be written in MHPMEVENTx.
> > > > > +      This property shouldn't encode any raw hardware event.
> > > > > +    minItems: 1
> > > > > +    maxItems: 255
> > >
> > > I copied these 255s from dt-schema somewhere as a sane max.
> > > Atish, is there a cap here or should we allow as many as someone likes?
> > > The md binding doesn't mention any limits - is it in the SBI spec?
> > > The strongest wording I saw there was "limited" & event idx is 20 bits
> > > wide as per the spec [0]. Does that make 2^20 the hard limit here?
> > >
> >
> > This is for hardware & cache events. The total number of events
> > defined there are 52 (10 HW + 42 Cache) events.
> > So 255 is a sane max that provides enough room for expansion in future
> > if required.
>
> WFM.
>
> > > > > +  riscv,raw-event-to-mhpmcounters:
> > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > > > +    description:
> > > > > +      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
> > > > > +      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
> > > > > +      that raw event.
> > > > > +      The encoding of the raw events are platform specific. The information is
> > > > > +      encoded in an array format where each row represents the specific raw
> > > > > +      event(s). The first element is a 64-bit match value where the invariant
> > > > > +      bits of range of events are set. The second element is a 64-bit mask that
> > > > > +      will have all the variant bits of the range of events cleared. All other
> > > > > +      bits should be set in the mask. The third element is a 32-bit value to
> > > > > +      represent bitmap of all MHPMCOUNTERx that can monitor these set of
> > > > > +      event(s). If a platform directly encodes each raw PMU event as a unique
> > > > > +      ID, the value of select_mask must be 0xffffffff_ffffffff.
> > > > > +    minItems: 1
> > > > > +    maxItems: 255
> > > > > +    items:
> > > > > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > +      maxItems: 5
> > > > > +
> > > > > +required:
> > > > > +  - compatible
> > > >
> > > > I assume at least one of the other properties must be present?
> > >
> > > Atish: (and +CC the OpenSBI list)
> > > Which properties are actually needed here? Or are any? The md binding
> > > in the OpenSBI sources doesn't seem to require anything other than the
> > > compatible?
> > >
> >
> > That's true. Opensbi allows the platform to define functions
> > to provide the mapping. Now that's an OpenSBI implementation thing.
> > Other implementations may choose to use it differently.
>
> In the case where the platform can define functions, the "bare" node
> with just the compatible is still required though in that case, right?
>

Yup.

> Thanks,
> Conor.
>


From weiliang.lim at starfivetech.com  Thu Dec 22 23:07:40 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 23 Dec 2022 15:07:40 +0800
Subject: [PATCH v6 3/4] platform: generic: Allow platform_override to perform firmware init
In-Reply-To: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
Message-ID: <20221223070741.236271-4-weiliang.lim@starfivetech.com>

We add a generic platform override callback to allow platform specific firmware init.

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 21354e9..a59b06a 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -26,6 +26,7 @@ struct platform_override {
 	int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
 	int (*extensions_init)(const struct fdt_match *match,
 			       struct sbi_hart_features *hfeatures);
+	void (*fw_init)(void *fdt, const struct fdt_match *match);
 	int (*vendor_ext_check)(long extid, const struct fdt_match *match);
 	int (*vendor_ext_provider)(long extid, long funcid,
 				   const struct sbi_trap_regs *regs,
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 5fb0dc6..a34d3b0 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -85,6 +85,9 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
 
 	fw_platform_lookup_special(fdt, root_offset);
 
+	if (generic_plat && generic_plat->fw_init)
+		generic_plat->fw_init(fdt, generic_plat_match);
+
 	model = fdt_getprop(fdt, root_offset, "model", &len);
 	if (model)
 		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 23:07:37 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 23 Dec 2022 15:07:37 +0800
Subject: [PATCH v6 0/4] generic/starfive: Enable Starfive JH7110 platform preferred cold boot HART implementation
Message-ID: <20221223070741.236271-1-weiliang.lim@starfivetech.com>

This is patchset to enable Starfive JH7110 platform preferred cold boot HART implementation.
User has the option to specify preferred cold boot HART in the device tree. If unspecified, the existing lottery mechanism will be used.

v5->v6:
- Minor changes on TRUE->true, FALSE->false.

v4->v5:
- Move FDT boot hart id reading from cold_boot_allowed() to fw_init()callback function.

v3->v4:
- Add implementation to allow user to specify preferred cold boot HART in the device tree. 
- If unspecified, the existing lottery mechanism will be used.

v3:
- Add Starfive JH7110 implementation.
- Anup's patches to allow platform specific selection of cold boot HART.

v2:
https://patchwork.ozlabs.org/project/opensbi/patch/20221202063845.14938-1-weiliang.lim at starfivetech.com/

v1:
https://patchwork.ozlabs.org/project/opensbi/patch/20221129052119.379830-1-weiliang.lim at starfivetech.com/

Anup Patel (2):
  lib: sbi: Allow platform to influence cold boot HART selection
  platform: generic: Allow platform_override to select cold boot HART

Wei Liang Lim (2):
  platform: generic: Allow platform_override to perform firmware init
  generic/starfive: Add Starfive JH7110 platform implementation

 include/sbi/sbi_platform.h                   | 20 +++++++++
 lib/sbi/sbi_init.c                           |  7 ++-
 platform/generic/Kconfig                     |  4 ++
 platform/generic/configs/defconfig           |  1 +
 platform/generic/include/platform_override.h |  2 +
 platform/generic/platform.c                  | 12 +++++
 platform/generic/starfive/jh7110.c           | 47 ++++++++++++++++++++
 platform/generic/starfive/objects.mk         |  6 +++
 8 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 23:07:41 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 23 Dec 2022 15:07:41 +0800
Subject: [PATCH v6 4/4] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
Message-ID: <20221223070741.236271-5-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 +++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 47 ++++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 ++++
 4 files changed, 58 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 62c7a2d..47c10e5 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 47fca95..4b0842e 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..70a26fe
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <libfdt.h>
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static u32 selected_hartid = -1;
+
+static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	if (selected_hartid != -1)
+		return (selected_hartid == hartid);
+
+	return true;
+}
+
+static void starfive_jh7110_fw_init(void *fdt, const struct fdt_match *match)
+{
+	const fdt32_t *val;
+	int len, coff;
+
+	coff = fdt_path_offset(fdt, "/chosen");
+	if (-1 < coff) {
+		val = fdt_getprop(fdt, coff, "boot-hart-id", &len);
+		if (val && len)
+			selected_hartid = (u32) fdt32_to_cpu(*val);
+	}
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
+	.fw_init = starfive_jh7110_fw_init,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 23:07:38 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 23 Dec 2022 15:07:38 +0800
Subject: [PATCH v6 1/4] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
Message-ID: <20221223070741.236271-2-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..bd0d5ca 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return true if HART is allowed to do cold boot and false otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return true;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d45cee6 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = true;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Thu Dec 22 23:07:39 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Fri, 23 Dec 2022 15:07:39 +0800
Subject: [PATCH v6 2/4] platform: generic: Allow platform_override to select cold boot HART
In-Reply-To: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
Message-ID: <20221223070741.236271-3-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..5fb0dc6 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return true;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From ben.dooks at codethink.co.uk  Fri Dec 23 01:01:51 2022
From: ben.dooks at codethink.co.uk (Ben Dooks)
Date: Fri, 23 Dec 2022 09:01:51 +0000
Subject: Upcoming OpenSBI v1.2 release
In-Reply-To: <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>
References: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>
 <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>
Message-ID: <222bec58-2e07-2505-583b-89b8f9274b80@codethink.co.uk>

On 21/12/2022 15:02, Atish Patra wrote:
> On Fri, Dec 16, 2022 at 9:42 PM Anup Patel <anup at brainfault.org> wrote:
>>
>> Hi All,
>>
>> We are close to the OpenSBI v1.2 release. I plan to complete this
>> release before the end of next week (i.e. 24th December 2022).
>>
>> Next week, I won't be merging patches unless it's a critical fix.
>> Also, I request everyone to test the latest OpenSBI on their RISC-V
>> platforms.

Unfortunately I've been too busy post RISCV summit, but will try and
get testing done once we're back at work early January 2023.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html



From anup at brainfault.org  Fri Dec 23 21:38:32 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 24 Dec 2022 11:08:32 +0530
Subject: [PATCH v1] docs: pmu: fix binding example
In-Reply-To: <20221221135939.266377-1-conor@kernel.org>
References: <20221221135939.266377-1-conor@kernel.org>
Message-ID: <CAAhSdy0GD3TVB6rO-gLqFkgHCjBsTaEN_YMGdMjoF4j4pW0=KA@mail.gmail.com>

On Wed, Dec 21, 2022 at 7:42 PM Conor Dooley <conor at kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley at microchip.com>
>
> The first PMU binding example does not terminate properties with a ;,
> which is invalid. Noticed while converting the binding to yaml.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/pmu_support.md | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 1db36fc..1a16bad 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -70,17 +70,17 @@ via platform hooks rather than the device tree.
>  ```
>  pmu {
>         compatible                      = "riscv,pmu";
> -       riscv,event-to-mhpmevent                = <0x0000B  0x0000 0x0001>,
> +       riscv,event-to-mhpmevent                = <0x0000B  0x0000 0x0001>;
>         riscv,event-to-mhpmcounters     = <0x00001 0x00001 0x00000001>,
>                                                   <0x00002 0x00002 0x00000004>,
>                                                   <0x00003 0x0000A 0x00000ff8>,
> -                                                 <0x10000 0x10033 0x000ff000>,
> +                                                 <0x10000 0x10033 0x000ff000>;
>                                         /* For event ID 0x0002 */
>         riscv,raw-event-to-mhpmcounters = <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
>                                         /* For event ID 0-4 */
>                                         <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
>                                         /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
> -                                       <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>,
> +                                       <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
>  };
>  ```
>
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Fri Dec 23 21:39:24 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 24 Dec 2022 11:09:24 +0530
Subject: [PATCH] docs: pmu: Update the pmu doc with removal of
 mcountinhbit restriction
In-Reply-To: <20221222203850.2592975-1-atishp@rivosinc.com>
References: <20221222203850.2592975-1-atishp@rivosinc.com>
Message-ID: <CAAhSdy0+XYH7ci27j1h=mO4cYA7bC38Q_bz7=Nq5oPiBUce6ng@mail.gmail.com>

On Fri, Dec 23, 2022 at 2:08 AM Atish Patra <atishp at rivosinc.com> wrote:
>
> Since commit b28f070, it is possible for platforms to run perf monitoring
> even if mcountinhibit is not supported. Sampling still won't be possible
> though as it requires sscofpmf extension.
>
> Update the docs to remove the restriction.
>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/pmu_support.md | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 1db36fc..c74ef5f 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -6,9 +6,6 @@ capability of performance analysis tools such as perf if SBI PMU extension is
>  enabled. The OpenSBI implementation makes the following assumptions about the
>  hardware platform.
>
> - * MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, SBI PMU
> -extension will not be enabled.
> -
>   * The platform must provide information about PMU event to counter mapping
>  via device tree or platform specific hooks. Otherwise, SBI PMU extension will
>  not be enabled.
> --
> 2.25.1
>


From anup at brainfault.org  Fri Dec 23 21:39:00 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 24 Dec 2022 11:09:00 +0530
Subject: [PATCH v1] docs: pmu: update a reference to a deprecated property name
In-Reply-To: <20221222193913.223114-1-conor@kernel.org>
References: <20221222193913.223114-1-conor@kernel.org>
Message-ID: <CAAhSdy0brgKcXRnzAZom6yu_KUMmPbtF3bBhVzTH6VzTuq=nYg@mail.gmail.com>

On Fri, Dec 23, 2022 at 1:17 AM Conor Dooley <conor at kernel.org> wrote:
>
> From: Conor Dooley <conor.dooley at microchip.com>
>
> event-to-mhpmevent was deprecated and replaced by
> riscv,event-to-mhpmevent, but a reference remains to the old name.
> Replace it with the new one.
>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  docs/pmu_support.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 1a16bad..9c79636 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -46,7 +46,7 @@ a table format where each row represents a certain range of events and
>  corresponding counters. The first column represents starting of the pmu event id
>  and 2nd column represents the end of the pmu event id. The third column
>  represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if
> -event-to-mhpmevent is present. Otherwise, it can be omitted. This property
> +riscv,event-to-mhpmevent is present. Otherwise, it can be omitted. This property
>  shouldn't encode any raw event.
>
>  * **riscv,raw-event-to-mhpmcounters**(Optional) - It represents an ONE-to-MANY
> --
> 2.38.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi


From anup at brainfault.org  Sat Dec 24 02:10:19 2022
From: anup at brainfault.org (Anup Patel)
Date: Sat, 24 Dec 2022 15:40:19 +0530
Subject: OpenSBI v1.2 Released
Message-ID: <CAAhSdy26PFCbY1tJm-0-urbXeFZcpOOdhwotaykfTU5CmJbkHA@mail.gmail.com>

Hi All,

The OpenSBI v1.2 is now available on GitHub at:
https://github.com/riscv-software-src/opensbi/releases

This release has:
* Menuconfig support using Kconfiglib v14.1.0
* RISC-V AIA v1.0.0 support
* Cadence UART driver
* Platform specific PMU device operations
* Trap handling improvements for platforms with H-extension
* Semihosting support
* T-HEAD C9XX PMU and CLINT support
* FDT based drivers for Andes AE350 platform
* Andes AE350 platform improvements
* Allow enabling/disabling of SBI extensions via Kconfig
* Renesas SCIF serial driver
* Renesas RZ/Five platform support

Overall, this release mainly adds Kconfig support, new drivers
and new platforms along with other improvements.

Many thanks to everyone who has contributed to this release.

Best Regards,
Anup Patel


From conor at kernel.org  Thu Dec 22 11:23:54 2022
From: conor at kernel.org (Conor Dooley)
Date: Thu, 22 Dec 2022 19:23:54 +0000
Subject: [PATCH v1] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <20221222180627.GA1748427-robh@kernel.org>
References: <20221221141548.274408-1-conor@kernel.org>
 <20221222180627.GA1748427-robh@kernel.org>
Message-ID: <Y6SuyiYC/oLB2VzL@spud>

Hey Rob,

On Thu, Dec 22, 2022 at 12:06:27PM -0600, Rob Herring wrote:
> On Wed, Dec 21, 2022 at 02:15:49PM +0000, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley at microchip.com>
> > 
> > The SBI PMU extension requires a firmware to be aware of the event to
> > counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> > DeviceTree to describe the PMU mappings. This binding is currently
> > described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> > since v7.2.0.
> > 
> > Import the binding for use while validating dtb dumps from QEMU and
> > upcoming hardware (eg JH7110 SoC) that will make use of the event
> > mapping.
> > 
> > Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> > Co-developed-by: Atish Patra <atishp at rivosinc.com>
> > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> > ---
> > I asked Rob on IRC about these bindings a few weeks ago & he said he
> > would be willing to take them. I have modified wording slightly in the
> > descriptions, but have mostly left things as close to the OpenSBI
> > documentation as possible.
> 
> Please CC the perf maintainers. Might be crickets, but so they at least 
> have a chance to see it.

Yah, I was kinda unsure who to CC. It does list them as being
specifically ARM so I probably made the wrong choice about inclusion.
I've added them now.

> > I'm not super sure about what I've done with the properties being
> > correct type wise, I went digging in bindings and am sorta using the
> > first thing that "fit".
> > 
> > Since you wrote the md doc Atish, I put your co-developed-by. OpenSBI
> > is BSD-2-Clause licensed so I am also unsure as to what license I can
> > use for this binding since that's where I took it from.
> > ---
> >  .../devicetree/bindings/perf/riscv,pmu.yaml   | 158 ++++++++++++++++++
> >  1 file changed, 158 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > new file mode 100644
> > index 000000000000..d65f937680af
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> > @@ -0,0 +1,158 @@
> > +# SPDX-License-Identifier: BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V SBI PMU events
> > +
> > +maintainers:
> > +  - Atish Patra <atishp at rivosinc.com>
> > +
> > +description: |
> > +  SBI PMU extension supports allow supervisor software to configure, start &
> > +  stop any performance counter at anytime. Thus, a user can leverage full
> > +  capability of performance analysis tools such as perf if the SBI PMU
> > +  extension is enabled. The OpenSBI implementation makes the following
> > +  assumptions about the hardware platform:
> > +    MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, the SBI
> > +    PMU extension will not be enabled.
> > +
> > +    The platform must provide information about PMU event to counter mapping
> > +    via device tree or platform specific hooks. Otherwise, the SBI PMU
> > +    extension will not be enabled.
> > +
> > +    The platforms should provide information about the PMU event selector
> > +    values that should be encoded in the expected value of MHPMEVENTx while
> > +    configuring MHPMCOUNTERx for that specific event. This can be done via a
> > +    device tree or platform specific hooks. The exact value to be written to
> > +    the MHPMEVENTx is completely dependent on the platform. The generic
> > +    platform writes the zero-extended event_idx as the expected value for
> > +    hardware cache/generic events as suggested by the SBI specification.
> > +
> > +properties:
> > +  compatible:
> > +    const: riscv,pmu
> > +
> > +  riscv,event-to-mhpmevent:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +    description:
> > +      Represents an ONE-to-ONE mapping between a PMU event and the event
> > +      selector value that platform expects to be written to the MHPMEVENTx CSR
> > +      for that event.
> > +      The mapping is encoded in an array format where each row represents an
> 
> s/array/matrix/
> 
> > +      event. The first element represents the event idx while the second &
> > +      third elements represent the event selector value that should be encoded
> > +      in the expected value to be written in MHPMEVENTx.
> > +      This property shouldn't encode any raw hardware event.
> > +    minItems: 1
> > +    maxItems: 255

I copied these 255s from dt-schema somewhere as a sane max.
Atish, is there a cap here or should we allow as many as someone likes?
The md binding doesn't mention any limits - is it in the SBI spec?
The strongest wording I saw there was "limited" & event idx is 20 bits
wide as per the spec [0]. Does that make 2^20 the hard limit here?

0 - https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc#11-performance-monitoring-unit-extension-eid-0x504d55-pmu

> > +    items:
> > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> 
> Huh? A property can only have 1 type. I wonder what the tools do with 
> this...

I suppose I left this over (by accident) from when I had it arranged
slightly differently. I guess I never actually noticed as the tools
don't appear to complain. Now dropped :)

> > +      maxItems: 3
> 
> Better to do:
> 
>          items:
>            - description: what's in the 1st word
>            - description: what's in the 2nd word
>            - description: what's in the 3rd word
> 
> And rework the overall description to not say the same thing.

Yah, good idea. I'll do that for the next version.

> > +  riscv,event-to-mhpmcounters:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +    description:
> > +      Represents a MANY-to-MANY mapping between a range of events and all the
> > +      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
> > +      of events. The information is encoded in an array format where each
> > +      row represents a certain range of events and corresponding counters.
> > +      The first element represents starting of the pmu event id and 2nd column
> > +      represents the end of the pmu event id. The third element represent a
> > +      bitmap of all the MHPMCOUNTERx.
> > +      This property is mandatory if event-to-mhpmevent is present. Otherwise,
> > +      it can be omitted.
> 
> No need to state this in freeform text, use 'dependencies'.

Oh! I didn't know that that existed. I was going to go and do some sort
of required properties dance but perhaps that's not needed now (at least
to the same extent).

> > +      This property shouldn't encode any raw event.
> > +    minItems: 1
> > +    maxItems: 255
> > +    items:
> > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > +      maxItems: 3
> > +
> > +  riscv,raw-event-to-mhpmcounters:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +    description:
> > +      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
> > +      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
> > +      that raw event.
> > +      The encoding of the raw events are platform specific. The information is
> > +      encoded in an array format where each row represents the specific raw
> > +      event(s). The first element is a 64-bit match value where the invariant
> > +      bits of range of events are set. The second element is a 64-bit mask that
> > +      will have all the variant bits of the range of events cleared. All other
> > +      bits should be set in the mask. The third element is a 32-bit value to
> > +      represent bitmap of all MHPMCOUNTERx that can monitor these set of
> > +      event(s). If a platform directly encodes each raw PMU event as a unique
> > +      ID, the value of select_mask must be 0xffffffff_ffffffff.
> > +    minItems: 1
> > +    maxItems: 255
> > +    items:
> > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > +      maxItems: 5
> > +
> > +required:
> > +  - compatible
> 
> I assume at least one of the other properties must be present?

Atish: (and +CC the OpenSBI list)
Which properties are actually needed here? Or are any? The md binding
in the OpenSBI sources doesn't seem to require anything other than the
compatible?

Thanks Rob,
Conor.

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From conor at kernel.org  Thu Dec 22 12:16:16 2022
From: conor at kernel.org (Conor Dooley)
Date: Thu, 22 Dec 2022 20:16:16 +0000
Subject: [PATCH v1] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <CAHBxVyEZJeH6H00Jdcm2_=z-D2kYxVTgagYhmLoyJ2CPqcFbgg@mail.gmail.com>
References: <20221221141548.274408-1-conor@kernel.org>
 <20221222180627.GA1748427-robh@kernel.org>
 <Y6SuyiYC/oLB2VzL@spud>
 <CAHBxVyEZJeH6H00Jdcm2_=z-D2kYxVTgagYhmLoyJ2CPqcFbgg@mail.gmail.com>
Message-ID: <Y6S7ENNXQe42ymTz@spud>

On Thu, Dec 22, 2022 at 11:55:29AM -0800, Atish Kumar Patra wrote:
> On Thu, Dec 22, 2022 at 11:24 AM Conor Dooley <conor at kernel.org> wrote:
> > On Thu, Dec 22, 2022 at 12:06:27PM -0600, Rob Herring wrote:
> > > On Wed, Dec 21, 2022 at 02:15:49PM +0000, Conor Dooley wrote:
> > > > From: Conor Dooley <conor.dooley at microchip.com>
> > > >
> > > > The SBI PMU extension requires a firmware to be aware of the event to
> > > > counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> > > > DeviceTree to describe the PMU mappings. This binding is currently
> > > > described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> > > > since v7.2.0.
> > > >
> > > > Import the binding for use while validating dtb dumps from QEMU and
> > > > upcoming hardware (eg JH7110 SoC) that will make use of the event
> > > > mapping.
> > > >
> > > > Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> > > > Co-developed-by: Atish Patra <atishp at rivosinc.com>
> > > > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > > > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> > > > +description: |
> > > > +  SBI PMU extension supports allow supervisor software to configure, start &
> > > > +  stop any performance counter at anytime. Thus, a user can leverage full
> > > > +  capability of performance analysis tools such as perf if the SBI PMU
> > > > +  extension is enabled. The OpenSBI implementation makes the following
> > > > +  assumptions about the hardware platform:
> > > > +    MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, the SBI
> > > > +    PMU extension will not be enabled.
> > > > +
> 
> This is no longer true since OpenSBI commit b28f070. We should remove
> this from OpenSBI docs as well.

Since you know the detail of it, I volunteer you for that one ;)

> > > > +    The platform must provide information about PMU event to counter mapping
> > > > +    via device tree or platform specific hooks. Otherwise, the SBI PMU
> > > > +    extension will not be enabled.
> > > > +
> > > > +    The platforms should provide information about the PMU event selector
> > > > +    values that should be encoded in the expected value of MHPMEVENTx while
> > > > +    configuring MHPMCOUNTERx for that specific event. This can be done via a
> > > > +    device tree or platform specific hooks. The exact value to be written to
> > > > +    the MHPMEVENTx is completely dependent on the platform. The generic
> > > > +    platform writes the zero-extended event_idx as the expected value for
> > > > +    hardware cache/generic events as suggested by the SBI specification.
> > > > +
> 
> But the larger question is these are OpenSBI implementation specific
> assumptions. Should it be included in
> the DT binding?

Probably not. I'll drop it for v2.

> > > > +properties:
> > > > +  compatible:
> > > > +    const: riscv,pmu
> > > > +
> > > > +  riscv,event-to-mhpmevent:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > > +    description:
> > > > +      Represents an ONE-to-ONE mapping between a PMU event and the event
> > > > +      selector value that platform expects to be written to the MHPMEVENTx CSR
> > > > +      for that event.
> > > > +      The mapping is encoded in an array format where each row represents an
> > >
> > > s/array/matrix/
> > >
> > > > +      event. The first element represents the event idx while the second &
> > > > +      third elements represent the event selector value that should be encoded
> > > > +      in the expected value to be written in MHPMEVENTx.
> > > > +      This property shouldn't encode any raw hardware event.
> > > > +    minItems: 1
> > > > +    maxItems: 255
> >
> > I copied these 255s from dt-schema somewhere as a sane max.
> > Atish, is there a cap here or should we allow as many as someone likes?
> > The md binding doesn't mention any limits - is it in the SBI spec?
> > The strongest wording I saw there was "limited" & event idx is 20 bits
> > wide as per the spec [0]. Does that make 2^20 the hard limit here?
> >
> 
> This is for hardware & cache events. The total number of events
> defined there are 52 (10 HW + 42 Cache) events.
> So 255 is a sane max that provides enough room for expansion in future
> if required.

WFM.

> > > > +  riscv,raw-event-to-mhpmcounters:
> > > > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > > > +    description:
> > > > +      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
> > > > +      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
> > > > +      that raw event.
> > > > +      The encoding of the raw events are platform specific. The information is
> > > > +      encoded in an array format where each row represents the specific raw
> > > > +      event(s). The first element is a 64-bit match value where the invariant
> > > > +      bits of range of events are set. The second element is a 64-bit mask that
> > > > +      will have all the variant bits of the range of events cleared. All other
> > > > +      bits should be set in the mask. The third element is a 32-bit value to
> > > > +      represent bitmap of all MHPMCOUNTERx that can monitor these set of
> > > > +      event(s). If a platform directly encodes each raw PMU event as a unique
> > > > +      ID, the value of select_mask must be 0xffffffff_ffffffff.
> > > > +    minItems: 1
> > > > +    maxItems: 255
> > > > +    items:
> > > > +      $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > +      maxItems: 5
> > > > +
> > > > +required:
> > > > +  - compatible
> > >
> > > I assume at least one of the other properties must be present?
> >
> > Atish: (and +CC the OpenSBI list)
> > Which properties are actually needed here? Or are any? The md binding
> > in the OpenSBI sources doesn't seem to require anything other than the
> > compatible?
> >
> 
> That's true. Opensbi allows the platform to define functions
> to provide the mapping. Now that's an OpenSBI implementation thing.
> Other implementations may choose to use it differently.

In the case where the platform can define functions, the "bare" node
with just the compatible is still required though in that case, right?

Thanks,
Conor.

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From rpathak at ventanamicro.com  Sat Dec 24 19:22:11 2022
From: rpathak at ventanamicro.com (Rahul Pathak)
Date: Sun, 25 Dec 2022 08:52:11 +0530
Subject: [PATCH] Makefile: Remove -N ldflag to prevent linker RWX warning
Message-ID: <20221225032211.1370467-1-rpathak@ventanamicro.com>

-N option coalesce all sections into single LOAD segment which causes
data and other sections to have executable permission causing warning
with new binutils ld 2.39.
New ld emits warning when any segment have all three permissions RWX.

ld.bfd: warning: test.elf has a LOAD segment with RWX permissions
ld.bfd: warning: fw_dynamic.elf has a LOAD segment with RWX permissions
ld.bfd: warning: fw_jump.elf has a LOAD segment with RWX permissions
ld.bfd: warning: fw_payload.elf has a LOAD segment with RWX permissions

This option was added in below commit -
commit: eeab92f2423e ("Makefile: Convert to a more standard format")

Removing -N option allows to have text and rodata into one LOAD
segment and other sections into separate LOAD segment which prevents
RWX permissions on single LOAD segment. Here X == E

Current
 LOAD           0x0000000000000120 0x0000000080000000 0x0000000080000000
                 0x000000000001d4d0 0x0000000000032ed8  RWE    0x10

-N removed
  LOAD           0x0000000000001000 0x0000000080000000 0x0000000080000000
                 0x00000000000198cc 0x00000000000198cc  R E    0x1000
  LOAD           0x000000000001b000 0x000000008001a000 0x000000008001a000
                 0x00000000000034d0 0x0000000000018ed8  RW     0x1000

Signed-off-by: Rahul Pathak <rpathak at ventanamicro.com>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 92203c5a2ac0..b742d6dbc5e5 100644
--- a/Makefile
+++ b/Makefile
@@ -369,7 +369,7 @@ ASFLAGS		+=	$(firmware-asflags-y)
 ARFLAGS		=	rcs
 
 ELFFLAGS	+=	$(USE_LD_FLAG)
-ELFFLAGS	+=	-Wl,--build-id=none -Wl,-N
+ELFFLAGS	+=	-Wl,--build-id=none
 ELFFLAGS	+=	$(platform-ldflags-y)
 ELFFLAGS	+=	$(firmware-ldflags-y)
 
-- 
2.34.1



From bmeng at tinylab.org  Sun Dec 25 19:36:03 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Mon, 26 Dec 2022 11:36:03 +0800
Subject: [PATCH] lib: utils/sys: Allow custom HTIF base address for RV32
Message-ID: <20221226033603.1860569-1-bmeng@tinylab.org>

commit 6dde43584f18 ("lib: utils/sys: Extend HTIF library to allow custom base address")
forgot to update do_tohost_fromhost() codes for RV32, which still
accesses the HTIF registers using the ELF symbol address directly.

Fixes: 6dde43584f18 ("lib: utils/sys: Extend HTIF library to allow custom base address")
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 lib/utils/sys/htif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/utils/sys/htif.c b/lib/utils/sys/htif.c
index d7cbeaf..b4e6321 100644
--- a/lib/utils/sys/htif.c
+++ b/lib/utils/sys/htif.c
@@ -135,11 +135,11 @@ static void do_tohost_fromhost(uint64_t dev, uint64_t cmd, uint64_t data)
 	__set_tohost(HTIF_DEV_SYSTEM, cmd, data);
 
 	while (1) {
-		uint64_t fh = fromhost;
+		uint64_t fh = __read_fromhost();
 		if (fh) {
 			if (FROMHOST_DEV(fh) == HTIF_DEV_SYSTEM &&
 			    FROMHOST_CMD(fh) == cmd) {
-				fromhost = 0;
+				__write_fromhost(0);
 				break;
 			}
 			__check_fromhost();
-- 
2.34.1



From marouene.boubakri at nxp.com  Mon Dec 26 10:25:22 2022
From: marouene.boubakri at nxp.com (Marouene Boubakri)
Date: Mon, 26 Dec 2022 18:25:22 +0000
Subject: BUG: OpenSBI crashes when passing custom DTB on Qemu
Message-ID: <AS1PR04MB9455ACCE24963065CDC19D47FCEC9@AS1PR04MB9455.eurprd04.prod.outlook.com>

Hi,

Is the OpenSBI community looking to the Github repository sometime ?
I opened an issue [1] and would be great if someone looks at this.

[1] https://github.com/riscv-software-src/opensbi/issues/281

Thanks
Maro




From bmeng.cn at gmail.com  Mon Dec 26 23:49:33 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 15:49:33 +0800
Subject: BUG: OpenSBI crashes when passing custom DTB on Qemu
In-Reply-To: <AS1PR04MB9455ACCE24963065CDC19D47FCEC9@AS1PR04MB9455.eurprd04.prod.outlook.com>
References: <AS1PR04MB9455ACCE24963065CDC19D47FCEC9@AS1PR04MB9455.eurprd04.prod.outlook.com>
Message-ID: <CAEUhbmX3JXdv1=ek0yugEHnVP-h84rgHUj1f5PAa4YBvBSXBdw@mail.gmail.com>

On Tue, Dec 27, 2022 at 2:27 AM Marouene Boubakri
<marouene.boubakri at nxp.com> wrote:
>
> Hi,
>
> Is the OpenSBI community looking to the Github repository sometime ?
> I opened an issue [1] and would be great if someone looks at this.
>
> [1] https://github.com/riscv-software-src/opensbi/issues/281
>

Yes, it's monitored, and I asked for a clarification already.

Regards,
Bin


From marouene.boubakri at nxp.com  Tue Dec 27 00:24:36 2022
From: marouene.boubakri at nxp.com (Marouene Boubakri)
Date: Tue, 27 Dec 2022 08:24:36 +0000
Subject: [EXT] Re: BUG: OpenSBI crashes when passing custom DTB on Qemu
In-Reply-To: <CAEUhbmX3JXdv1=ek0yugEHnVP-h84rgHUj1f5PAa4YBvBSXBdw@mail.gmail.com>
References: <AS1PR04MB9455ACCE24963065CDC19D47FCEC9@AS1PR04MB9455.eurprd04.prod.outlook.com>
 <CAEUhbmX3JXdv1=ek0yugEHnVP-h84rgHUj1f5PAa4YBvBSXBdw@mail.gmail.com>
Message-ID: <AS1PR04MB9455E9128C9AD28B6812C550FCED9@AS1PR04MB9455.eurprd04.prod.outlook.com>

I updated the issue on Github
Here is the DTS:

/dts-v1/;

/ {
        #address-cells = <0x02>;
        #size-cells = <0x02>;
        compatible = "riscv-virtio";
        model = "riscv-virtio,qemu";

        /*fw-cfg at 10100000 {
                dma-coherent;
                reg = <0x00 0x10100000 0x00 0x18>;
                compatible = "qemu,fw-cfg-mmio";
        };*/

        flash at 20000000 {
                bank-width = <0x04>;
                reg = <0x00 0x20000000 0x00 0x2000000 0x00 0x22000000 0x00 0x2000000>;
                compatible = "cfi-flash";
        };

        chosen {
                bootargs = "root=/dev/vda rw console=ttyS0 earlycon";
                stdout-path = "/soc/uart at 10000000";
				
				opensbi-domains {
					compatible = "opensbi,domain,config";

					mumem: mumem {
						compatible = "opensbi,domain,memregion";
						base = <0x0 0x50000000>;
						order = <10>;
					};

					tmem: tmem {
						compatible = "opensbi,domain,memregion";
						base = <0x0 0x80100000>;
						order = <20>;
					};

					tuart: tuart {
						compatible = "opensbi,domain,memregion";
						base = <0x0 0x10000000>;
						order = <12>;
						mmio;
						devices = <&uart0>;
					};

					allmem: allmem {
						compatible = "opensbi,domain,memregion";
						base = <0x0 0x0>;
						order = <64>;
					};

					tdomain: trusted-domain {
						compatible = "opensbi,domain,instance";
						possible-harts = <&cpu0>;
						/* dev: access to all for now */
						regions = <&tmem 0x7>, <&tuart 0x7>, <&allmem 0x7>, <&mumem 0x7>;
						boot-hart = <&cpu0>;
						next-arg1 = <0x0 0x0>;
						next-addr = <0x0 0x80100000>;
						next-mode = <0x1>;
						system-reset-allowed;
					};

					udomain: untrusted-domain {
						compatible = "opensbi,domain,instance";
						possible-harts = <&cpu1 &cpu2 &cpu3>;
						/* dev: access to all for now */
						regions = <&tmem 0x0>, <&tuart 0x7>, <&allmem 0x7>, <&mumem 0x7>;
					};
				};				
        };

        memory at 80000000 {
                device_type = "memory";
                reg = <0x00 0x80000000 0x00 0x10000000>;
        };
	
        cpus {
                #address-cells = <0x01>;
                #size-cells = <0x00>;
                timebase-frequency = <0x989680>;

                cpu0: cpu at 0 {
                        phandle = <0x07>;
                        device_type = "cpu";
                        reg = <0x00>;
                        status = "okay";
                        compatible = "riscv";
                        riscv,isa = "rv64imafdcsu";
			opensbi-domain = <&tdomain>;
                        mmu-type = "riscv,sv39";

                        interrupt-controller {
                                #interrupt-cells = <0x01>;
                                interrupt-controller;
                                compatible = "riscv,cpu-intc";
                                phandle = <0x08>;
                        };
                };

                cpu1:cpu at 1 {
                        phandle = <0x05>;
                        device_type = "cpu";
                        reg = <0x01>;
                        status = "okay";
                        compatible = "riscv";
                        riscv,isa = "rv64imafdcsu";
			opensbi-domain = <&udomain>;
                        mmu-type = "riscv,sv39";

                        interrupt-controller {
                                #interrupt-cells = <0x01>;
                                interrupt-controller;
                                compatible = "riscv,cpu-intc";
                                phandle = <0x06>;
                        };
                };

                cpu2:cpu at 2 {
                        phandle = <0x03>;
                        device_type = "cpu";
                        reg = <0x02>;
                        status = "okay";
                        compatible = "riscv";
                        riscv,isa = "rv64imafdcsu";
			opensbi-domain = <&udomain>;
                        mmu-type = "riscv,sv39";

                        interrupt-controller {
                                #interrupt-cells = <0x01>;
                                interrupt-controller;
                                compatible = "riscv,cpu-intc";
                                phandle = <0x04>;
                        };
                };

                cpu3:cpu at 3 {
                        phandle = <0x01>;
                        device_type = "cpu";
                        reg = <0x03>;
                        status = "okay";
                        compatible = "riscv";
                        riscv,isa = "rv64imafdcsu";
			opensbi-domain = <&udomain>;
                        mmu-type = "riscv,sv39";

                        interrupt-controller {
                                #interrupt-cells = <0x01>;
                                interrupt-controller;
                                compatible = "riscv,cpu-intc";
                                phandle = <0x02>;
                        };
                };

                cpu-map {

                        cluster0 {

                                /*core0 {
                                        cpu = <0x07>;
                                };*/

                                core1 {
                                        cpu = <0x05>;
                                };

                                core2 {
                                        cpu = <0x03>;
                                };

                                core3 {
                                        cpu = <0x01>;
                                };
                        };
                };
        };

        soc {
                #address-cells = <0x02>;
                #size-cells = <0x02>;
                compatible = "simple-bus";
                ranges;

                rtc at 101000 {
                        interrupts = <0x0b>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x101000 0x00 0x1000>;
                        compatible = "google,goldfish-rtc";
                };

                uart0:uart at 10000000 {
                        interrupts = <0x0a>;
                        interrupt-parent = <0x09>;
                        clock-frequency = "\08@";
                        reg = <0x00 0x10000000 0x00 0x100>;
                        compatible = "ns16550a";
                };

                poweroff {
                        value = <0x5555>;
                        offset = <0x00>;
                        regmap = <0x0a>;
                        compatible = "syscon-poweroff";
                };

                reboot {
                        value = <0x7777>;
                        offset = <0x00>;
                        regmap = <0x0a>;
                        compatible = "syscon-reboot";
                };

                test at 100000 {
                        phandle = <0x0a>;
                        reg = <0x00 0x100000 0x00 0x1000>;
                        compatible = "sifive,test1\0sifive,test0\0syscon";
                };

                pci at 30000000 {
                        interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
                        interrupt-map = <0x00 0x00 0x00 0x01 0x09 0x20 0x00 0x00 0x00 0x02 0x09 0x21 0x00 0x00 0x00 0x03 0x09 0x22 0x00 0x00 0x00 0x04 0x09 0x23 0x800 0x00 0x00 0x01 0x09 0x21 0x800 0x00 0x00 0x02 0x09 0x22 0x800 0x00 0x00 0x03 0x09 0x23 0x800 0x00 0x00 0x04 0x09 0x20 0x1000 0x00 0x00 0x01 0x09 0x22 0x1000 0x00 0x00 0x02 0x09 0x23 0x1000 0x00 0x00 0x03 0x09 0x20 0x1000 0x00 0x00 0x04 0x09 0x21 0x1800 0x00 0x00 0x01 0x09 0x23 0x1800 0x00 0x00 0x02 0x09 0x20 0x1800 0x00 0x00 0x03 0x09 0x21 0x1800 0x00 0x00 0x04 0x09 0x22>;
                        ranges = <0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000 0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
                        reg = <0x00 0x30000000 0x00 0x10000000>;
                        dma-coherent;
                        bus-range = <0x00 0xff>;
                        linux,pci-domain = <0x00>;
                        device_type = "pci";
                        compatible = "pci-host-ecam-generic";
                        #size-cells = <0x02>;
                        #interrupt-cells = <0x01>;
                        #address-cells = <0x03>;
                };

                virtio_mmio at 10008000 {
                        interrupts = <0x08>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10008000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10007000 {
                        interrupts = <0x07>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10007000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10006000 {
                        interrupts = <0x06>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10006000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10005000 {
                        interrupts = <0x05>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10005000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10004000 {
                        interrupts = <0x04>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10004000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10003000 {
                        interrupts = <0x03>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10003000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10002000 {
                        interrupts = <0x02>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10002000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                virtio_mmio at 10001000 {
                        interrupts = <0x01>;
                        interrupt-parent = <0x09>;
                        reg = <0x00 0x10001000 0x00 0x1000>;
                        compatible = "virtio,mmio";
                };

                plic at c000000 {
                        phandle = <0x09>;
                        riscv,ndev = <0x35>;
                        reg = <0x00 0xc000000 0x00 0x210000>;
                        interrupts-extended = <0x08 0x0b 0x08 0x09 0x06 0x0b 0x06 0x09 0x04 0x0b 0x04 0x09 0x02 0x0b 0x02 0x09>;
                        interrupt-controller;
                        compatible = "sifive,plic-1.0.0\0riscv,plic0";
                        #interrupt-cells = <0x01>;
                        #address-cells = <0x00>;
                };

                clint at 2000000 {
                        interrupts-extended = <0x08 0x03 0x08 0x07 0x06 0x03 0x06 0x07 0x04 0x03 0x04 0x07 0x02 0x03 0x02 0x07>;
                        reg = <0x00 0x2000000 0x00 0x10000>;
                        compatible = "sifive,clint0\0riscv,clint0";
                };
        };

		firmware {
			optee {
				compatible = "riscv,optee-td";
				method = "rpmsg";
			};
		};
	
};

-----Original Message-----
From: Bin Meng <bmeng.cn at gmail.com> 
Sent: Tuesday, December 27, 2022 8:50 AM
To: Marouene Boubakri <marouene.boubakri at nxp.com>
Cc: opensbi at lists.infradead.org
Subject: [EXT] Re: BUG: OpenSBI crashes when passing custom DTB on Qemu

Caution: EXT Email

On Tue, Dec 27, 2022 at 2:27 AM Marouene Boubakri <marouene.boubakri at nxp.com> wrote:
>
> Hi,
>
> Is the OpenSBI community looking to the Github repository sometime ?
> I opened an issue [1] and would be great if someone looks at this.
>
> [1] 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> ub.com%2Friscv-software-src%2Fopensbi%2Fissues%2F281&data=05%7C01%7Cma
> rouene.boubakri%40nxp.com%7C7cdd0a33c2224e4342a208dae7deec3b%7C686ea1d
> 3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638077241876898208%7CUnknown%7CTWF
> pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M
> n0%3D%7C3000%7C%7C%7C&sdata=40WuGPVNGHBxpElw7XR9rmjuCX8kucy2Ho0RA%2FH9
> kGw%3D&reserved=0
>

Yes, it's monitored, and I asked for a clarification already.

Regards,
Bin


From heinrich.schuchardt at canonical.com  Tue Dec 27 02:54:21 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Tue, 27 Dec 2022 11:54:21 +0100
Subject: [PATCH v2 2/5] libs: utils/irqchip: plic: Ensure no out-of-bound
 access in priority save/restore helpers
In-Reply-To: <20221204051503.439727-2-bmeng@tinylab.org>
References: <20221204051503.439727-1-bmeng@tinylab.org>
 <20221204051503.439727-2-bmeng@tinylab.org>
Message-ID: <70ccdcc7-613b-6a56-dc33-3b22ef5d0474@canonical.com>



On 12/4/22 06:15, Bin Meng wrote:
> Currently the priority save/restore helpers writes/reads the provided
> array using an index whose maximum value is determined by PLIC, which
> potentially may disagree with the caller to these helpers.
> 
> Add a parameter to ask the caller to provide the size limit of the
> array to ensure no out-of-bound access happens.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---
> 
> Changes in v2:
> - new patch: libs: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers
> 
>   include/sbi_utils/irqchip/fdt_irqchip_plic.h |  4 ++--
>   include/sbi_utils/irqchip/plic.h             |  5 +++--
>   lib/utils/irqchip/fdt_irqchip_plic.c         | 12 ++++++++----
>   lib/utils/irqchip/plic.c                     |  9 +++++----
>   platform/generic/allwinner/sun20i-d1.c       |  4 ++--
>   5 files changed, 20 insertions(+), 14 deletions(-)
> 
> diff --git a/include/sbi_utils/irqchip/fdt_irqchip_plic.h b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> index 98d4de5..5f3f54d 100644
> --- a/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> +++ b/include/sbi_utils/irqchip/fdt_irqchip_plic.h
> @@ -9,9 +9,9 @@
>   
>   #include <sbi/sbi_types.h>
>   
> -void fdt_plic_priority_save(u8 *priority);
> +void fdt_plic_priority_save(u8 *priority, u32 num);
>   
> -void fdt_plic_priority_restore(const u8 *priority);
> +void fdt_plic_priority_restore(const u8 *priority, u32 num);
>   
>   void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold);
>   
> diff --git a/include/sbi_utils/irqchip/plic.h b/include/sbi_utils/irqchip/plic.h
> index 48c24f0..38704a1 100644
> --- a/include/sbi_utils/irqchip/plic.h
> +++ b/include/sbi_utils/irqchip/plic.h
> @@ -18,9 +18,10 @@ struct plic_data {
>   };
>   
>   /* So far, priorities on all consumers of these functions fit in 8 bits. */
> -void plic_priority_save(const struct plic_data *plic, u8 *priority);
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num);
>   
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority);
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +			   u32 num);
>   
>   void plic_context_save(const struct plic_data *plic, int context_id,
>   		       u32 *enable, u32 *threshold);
> diff --git a/lib/utils/irqchip/fdt_irqchip_plic.c b/lib/utils/irqchip/fdt_irqchip_plic.c
> index a6e185c..87fb9bd 100644
> --- a/lib/utils/irqchip/fdt_irqchip_plic.c
> +++ b/lib/utils/irqchip/fdt_irqchip_plic.c
> @@ -24,18 +24,22 @@ static struct plic_data plic[PLIC_MAX_NR];
>   static struct plic_data *plic_hartid2data[SBI_HARTMASK_MAX_BITS];
>   static int plic_hartid2context[SBI_HARTMASK_MAX_BITS][2];
>   
> -void fdt_plic_priority_save(u8 *priority)
> +void fdt_plic_priority_save(u8 *priority, u32 num)
>   {
>   	struct plic_data *plic = plic_hartid2data[current_hartid()];
>   
> -	plic_priority_save(plic, priority);
> +	if (num > plic->num_src + 1)
> +		num = plic->num_src + 1;
> +	plic_priority_save(plic, priority, num);
>   }
>   
> -void fdt_plic_priority_restore(const u8 *priority)
> +void fdt_plic_priority_restore(const u8 *priority, u32 num)
>   {
>   	struct plic_data *plic = plic_hartid2data[current_hartid()];
>   
> -	plic_priority_restore(plic, priority);
> +	if (num > plic->num_src + 1)
> +		num = plic->num_src + 1;
> +	plic_priority_restore(plic, priority, num);
>   }
>   
>   void fdt_plic_context_save(bool smode, u32 *enable, u32 *threshold)
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index 4df9020..c5c1879 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -36,15 +36,16 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>   	writel(val, plic_priority);
>   }
>   
> -void plic_priority_save(const struct plic_data *plic, u8 *priority)
> +void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>   {
> -	for (u32 i = 1; i <= plic->num_src; i++)
> +	for (u32 i = 1; i <= num; i++)
>   		priority[i] = plic_get_priority(plic, i);
>   }
>   
> -void plic_priority_restore(const struct plic_data *plic, const u8 *priority)
> +void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
> +			   u32 num)
>   {
> -	for (u32 i = 1; i <= plic->num_src; i++)
> +	for (u32 i = 1; i <= num; i++)
>   		plic_set_priority(plic, i, priority[i]);
>   }
>   
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 707313b..46d336f 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -79,13 +79,13 @@ static u32 plic_threshold;
>   static void sun20i_d1_plic_save(void)
>   {
>   	fdt_plic_context_save(true, plic_sie, &plic_threshold);
> -	fdt_plic_priority_save(plic_priority);
> +	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);

This ends up calling plic_priority_save() which will access 
plic_priority at indexes 1 to PLIC_SOURCES. So you are overrunning the 
plic_priority array size.

Coverity 1530252 Out-of-bounds access


>   }
>   
>   static void sun20i_d1_plic_restore(void)
>   {
>   	thead_plic_restore();
> -	fdt_plic_priority_restore(plic_priority);
> +	fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);

This ends up calling plic_priority_restore() which will access 
plic_priority at indexes 1 to PLIC_SOURCES. So you are overrunning the 
plic_priority array size.

Coverity 1530251 Out-of-bounds access

Best regards

Heinrich

>   	fdt_plic_context_restore(true, plic_sie, plic_threshold);
>   }
>   


From heinrich.schuchardt at canonical.com  Tue Dec 27 03:01:29 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Tue, 27 Dec 2022 12:01:29 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
Message-ID: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>

plic_priority_save() and plic_priority_restore() access indexes 1 to num of
the passed array. Avoid a buffer overrun by increasing the used array size
by one.

Addresses-Coverity-ID: 1530251 ("Out-of-bounds access")
Addresses-Coverity-ID: 1530252 ("Out-of-bounds access")
Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 platform/generic/allwinner/sun20i-d1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 1da9e5b..9891ad0 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -72,7 +72,7 @@ static void sun20i_d1_csr_restore(void)
 #define PLIC_SOURCES			176
 #define PLIC_IE_WORDS			((PLIC_SOURCES + 31) / 32)
 
-static u8 plic_priority[PLIC_SOURCES];
+static u8 plic_priority[PLIC_SOURCES + 1];
 static u32 plic_sie[PLIC_IE_WORDS];
 static u32 plic_threshold;
 
-- 
2.37.2



From bmeng.cn at gmail.com  Tue Dec 27 03:46:11 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 19:46:11 +0800
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
Message-ID: <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>

On Tue, Dec 27, 2022 at 7:03 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> plic_priority_save() and plic_priority_restore() access indexes 1 to num of
> the passed array. Avoid a buffer overrun by increasing the used array size
> by one.
>
> Addresses-Coverity-ID: 1530251 ("Out-of-bounds access")
> Addresses-Coverity-ID: 1530252 ("Out-of-bounds access")

Where is the Coverity for OpenSBI project hosted?

> Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers")
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> ---
>  platform/generic/allwinner/sun20i-d1.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> index 1da9e5b..9891ad0 100644
> --- a/platform/generic/allwinner/sun20i-d1.c
> +++ b/platform/generic/allwinner/sun20i-d1.c
> @@ -72,7 +72,7 @@ static void sun20i_d1_csr_restore(void)
>  #define PLIC_SOURCES                   176
>  #define PLIC_IE_WORDS                  ((PLIC_SOURCES + 31) / 32)
>
> -static u8 plic_priority[PLIC_SOURCES];
> +static u8 plic_priority[PLIC_SOURCES + 1];

This change could fix the Coverity, but IMHO we should not change this
value. PLIC_SOURCES should be 176.

You probably are using a buggy DTB that contains a wrong "riscv,ndev",
which I pointed out in the linux-riscv ML.

>  static u32 plic_sie[PLIC_IE_WORDS];
>  static u32 plic_threshold;
>

My original patch [1] contains a size check against "riscv,ndev" in
the DTB. But somehow that size check got dropped when the patch was
applied.

[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221211065424.806478-2-bmeng at tinylab.org/

Regards,
Bin


From heinrich.schuchardt at canonical.com  Tue Dec 27 04:01:18 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Tue, 27 Dec 2022 13:01:18 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
Message-ID: <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>



On 12/27/22 12:46, Bin Meng wrote:
> On Tue, Dec 27, 2022 at 7:03 PM Heinrich Schuchardt
> <heinrich.schuchardt at canonical.com> wrote:
>>
>> plic_priority_save() and plic_priority_restore() access indexes 1 to num of
>> the passed array. Avoid a buffer overrun by increasing the used array size
>> by one.
>>
>> Addresses-Coverity-ID: 1530251 ("Out-of-bounds access")
>> Addresses-Coverity-ID: 1530252 ("Out-of-bounds access")
> 
> Where is the Coverity for OpenSBI project hosted?

https://scan.coverity.com

> 
>> Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers")
>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
>> ---
>>   platform/generic/allwinner/sun20i-d1.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
>> index 1da9e5b..9891ad0 100644
>> --- a/platform/generic/allwinner/sun20i-d1.c
>> +++ b/platform/generic/allwinner/sun20i-d1.c
>> @@ -72,7 +72,7 @@ static void sun20i_d1_csr_restore(void)
>>   #define PLIC_SOURCES                   176
>>   #define PLIC_IE_WORDS                  ((PLIC_SOURCES + 31) / 32)
>>
>> -static u8 plic_priority[PLIC_SOURCES];
>> +static u8 plic_priority[PLIC_SOURCES + 1];
> 
> This change could fix the Coverity, but IMHO we should not change this
> value. PLIC_SOURCES should be 176.
> 
> You probably are using a buggy DTB that contains a wrong "riscv,ndev",
> which I pointed out in the linux-riscv ML.

The problem does not depend on any device-tree. PLIC_SOURCES is a 
constant that your code uses in

platform/generic/allwinner/sun20i-d1.c:82: 
fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
platform/generic/allwinner/sun20i-d1.c:88: 
fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);

I wonder why plic_priority_save() and plic_priority_restore() start 
indexing at 1 and not at 0. This might deserve a code comment.
> 
>>   static u32 plic_sie[PLIC_IE_WORDS];
>>   static u32 plic_threshold;
>>
> 
> My original patch [1] contains a size check against "riscv,ndev" in
> the DTB. But somehow that size check got dropped when the patch was
> applied.
> 
> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221211065424.806478-2-bmeng at tinylab.org/

"riscv,ndev" isn't used anywhere in your patch. Just the constant 
PLIC_SOURCES.

Best regards

Heinrich

> 
> Regards,
> Bin


From schwab at linux-m68k.org  Tue Dec 27 04:05:22 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 13:05:22 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	(Heinrich Schuchardt's message of "Tue, 27 Dec 2022 12:01:29 +0100")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
Message-ID: <87h6xhdpbx.fsf@igel.home>

The actual bug is in plic_priority_save/restore.

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index d633514..901ffaa 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -39,14 +39,14 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
 {
 	for (u32 i = 1; i <= num; i++)
-		priority[i] = plic_get_priority(plic, i);
+		priority[i - 1] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
 			   u32 num)
 {
 	for (u32 i = 1; i <= num; i++)
-		plic_set_priority(plic, i, priority[i]);
+		plic_set_priority(plic, i, priority[i - 1]);
 }
 
 static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid)

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From bmeng.cn at gmail.com  Tue Dec 27 04:07:40 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 20:07:40 +0800
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com> <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
Message-ID: <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>

On Tue, Dec 27, 2022 at 8:01 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
>
>
> On 12/27/22 12:46, Bin Meng wrote:
> > On Tue, Dec 27, 2022 at 7:03 PM Heinrich Schuchardt
> > <heinrich.schuchardt at canonical.com> wrote:
> >>
> >> plic_priority_save() and plic_priority_restore() access indexes 1 to num of
> >> the passed array. Avoid a buffer overrun by increasing the used array size
> >> by one.
> >>
> >> Addresses-Coverity-ID: 1530251 ("Out-of-bounds access")
> >> Addresses-Coverity-ID: 1530252 ("Out-of-bounds access")
> >
> > Where is the Coverity for OpenSBI project hosted?
>
> https://scan.coverity.com
>
> >
> >> Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers")
> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
> >> ---
> >>   platform/generic/allwinner/sun20i-d1.c | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
> >> index 1da9e5b..9891ad0 100644
> >> --- a/platform/generic/allwinner/sun20i-d1.c
> >> +++ b/platform/generic/allwinner/sun20i-d1.c
> >> @@ -72,7 +72,7 @@ static void sun20i_d1_csr_restore(void)
> >>   #define PLIC_SOURCES                   176
> >>   #define PLIC_IE_WORDS                  ((PLIC_SOURCES + 31) / 32)
> >>
> >> -static u8 plic_priority[PLIC_SOURCES];
> >> +static u8 plic_priority[PLIC_SOURCES + 1];
> >
> > This change could fix the Coverity, but IMHO we should not change this
> > value. PLIC_SOURCES should be 176.
> >
> > You probably are using a buggy DTB that contains a wrong "riscv,ndev",
> > which I pointed out in the linux-riscv ML.
>
> The problem does not depend on any device-tree. PLIC_SOURCES is a
> constant that your code uses in
>
> platform/generic/allwinner/sun20i-d1.c:82:
> fdt_plic_priority_save(plic_priority, PLIC_SOURCES);
> platform/generic/allwinner/sun20i-d1.c:88:
> fdt_plic_priority_restore(plic_priority, PLIC_SOURCES);
>
> I wonder why plic_priority_save() and plic_priority_restore() start
> indexing at 1 and not at 0. This might deserve a code comment.

Please see the link I provided. In my original patch with the size
check, this Coverity issue won't happen.

> >
> >>   static u32 plic_sie[PLIC_IE_WORDS];
> >>   static u32 plic_threshold;
> >>
> >
> > My original patch [1] contains a size check against "riscv,ndev" in
> > the DTB. But somehow that size check got dropped when the patch was
> > applied.
> >
> > [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221211065424.806478-2-bmeng at tinylab.org/
>
> "riscv,ndev" isn't used anywhere in your patch. Just the constant
> PLIC_SOURCES.
>

Changing the array size to PLIC_SOURCES + 1 does not make sense. The
PLIC_SOURCES should be 176 which is correct as it includes source 0 on
the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
will create a buffer overrun.

[1] https://lore.kernel.org/linux-riscv/20221128133421.58614-1-bmeng at tinylab.org/

Regards,
Bin


From heinrich.schuchardt at canonical.com  Tue Dec 27 04:28:41 2022
From: heinrich.schuchardt at canonical.com (Heinrich Schuchardt)
Date: Tue, 27 Dec 2022 13:28:41 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <87h6xhdpbx.fsf@igel.home>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <87h6xhdpbx.fsf@igel.home>
Message-ID: <e869a6e2-458a-df92-6662-bf4fd3ff68a9@canonical.com>

On 12/27/22 13:05, Andreas Schwab wrote:
> The actual bug is in plic_priority_save/restore.


The problem really starts at include/sbi_utils/irqchip/plic.h where 
there is no comment at all describing the usage of the function and its 
parameters. So we don't know what the different authors of these 
functions intended to use index 0 for.

It would be great if we could move the project to follow the kernel 
documentation style (https://docs.kernel.org/doc-guide/kernel-doc.html)


> 
> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index d633514..901ffaa 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -39,14 +39,14 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>   void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>   {
>   	for (u32 i = 1; i <= num; i++)

In patch 34da6638 ("lib: utils/irqchip: plic: Fix the off-by-one error 
in priority save/restore helpers") Bin wrote

Interrupt source 0 is reserved. Hence the irq should start from 1.

Why was the the upper limit changed?

-       for (u32 i = 0; i < plic->num_src; i++)
+       for (u32 i = 1; i <= plic->num_src; i++)

Best regards

Heinrich

> -		priority[i] = plic_get_priority(plic, i);
> +		priority[i - 1] = plic_get_priority(plic, i);
>   }
>   
>   void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
>   			   u32 num)
>   {
>   	for (u32 i = 1; i <= num; i++)
> -		plic_set_priority(plic, i, priority[i]);
> +		plic_set_priority(plic, i, priority[i - 1]);
>   }
>   
>   static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid)
> 


From bmeng.cn at gmail.com  Tue Dec 27 04:41:42 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 20:41:42 +0800
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <e869a6e2-458a-df92-6662-bf4fd3ff68a9@canonical.com>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <87h6xhdpbx.fsf@igel.home> <e869a6e2-458a-df92-6662-bf4fd3ff68a9@canonical.com>
Message-ID: <CAEUhbmXqNLnpP=726bvY0h8GUehGCqQZkESM_RHd-voc7QQRoA@mail.gmail.com>

On Tue, Dec 27, 2022 at 8:30 PM Heinrich Schuchardt
<heinrich.schuchardt at canonical.com> wrote:
>
> On 12/27/22 13:05, Andreas Schwab wrote:
> > The actual bug is in plic_priority_save/restore.
>
>
> The problem really starts at include/sbi_utils/irqchip/plic.h where
> there is no comment at all describing the usage of the function and its
> parameters. So we don't know what the different authors of these
> functions intended to use index 0 for.
>
> It would be great if we could move the project to follow the kernel
> documentation style (https://docs.kernel.org/doc-guide/kernel-doc.html)
>
>
> >
> > diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> > index d633514..901ffaa 100644
> > --- a/lib/utils/irqchip/plic.c
> > +++ b/lib/utils/irqchip/plic.c
> > @@ -39,14 +39,14 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
> >   void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
> >   {
> >       for (u32 i = 1; i <= num; i++)
>
> In patch 34da6638 ("lib: utils/irqchip: plic: Fix the off-by-one error
> in priority save/restore helpers") Bin wrote
>
> Interrupt source 0 is reserved. Hence the irq should start from 1.
>
> Why was the the upper limit changed?
>

Both lower and upper limits are changed because the irq number range
is really [1, plic->num_src].

Previously the author had a wrong understanding of the irq number
hence that's what the patch 34da6638 tried to fix.

Regards,
Bin


From schwab at linux-m68k.org  Tue Dec 27 05:03:54 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 14:03:54 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	(Bin Meng's message of "Tue, 27 Dec 2022 20:07:40 +0800")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
Message-ID: <87cz85dmmd.fsf@igel.home>

On Dez 27 2022, Bin Meng wrote:

> Changing the array size to PLIC_SOURCES + 1 does not make sense. The
> PLIC_SOURCES should be 176 which is correct as it includes source 0 on
> the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
> will create a buffer overrun.

The range check will always allow that overrrun.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From bmeng.cn at gmail.com  Tue Dec 27 05:13:11 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 21:13:11 +0800
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <87cz85dmmd.fsf@igel.home>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
 <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com> <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
 <87cz85dmmd.fsf@igel.home>
Message-ID: <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>

On Tue, Dec 27, 2022 at 9:04 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>
> On Dez 27 2022, Bin Meng wrote:
>
> > Changing the array size to PLIC_SOURCES + 1 does not make sense. The
> > PLIC_SOURCES should be 176 which is correct as it includes source 0 on
> > the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
> > will create a buffer overrun.
>
> The range check will always allow that overrrun.
>

Well, with a correct dtb it doesn't.

Strictly speaking, your proposed fix allows that overrun too, if the
given num is an arbitrary larger value than the size of the priority
array.

Regards,
Bin


From schwab at linux-m68k.org  Tue Dec 27 05:36:26 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 14:36:26 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
	(Bin Meng's message of "Tue, 27 Dec 2022 21:13:11 +0800")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	<87cz85dmmd.fsf@igel.home>
	<CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
Message-ID: <878ritdl45.fsf@igel.home>

On Dez 27 2022, Bin Meng wrote:

> On Tue, Dec 27, 2022 at 9:04 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>>
>> On Dez 27 2022, Bin Meng wrote:
>>
>> > Changing the array size to PLIC_SOURCES + 1 does not make sense. The
>> > PLIC_SOURCES should be 176 which is correct as it includes source 0 on
>> > the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
>> > will create a buffer overrun.
>>
>> The range check will always allow that overrrun.
>>
>
> Well, with a correct dtb it doesn't.

You cannot argue with the dtb, since this is externally controlled.

> Strictly speaking, your proposed fix allows that overrun too

How?

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From bmeng.cn at gmail.com  Tue Dec 27 05:49:07 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Tue, 27 Dec 2022 21:49:07 +0800
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <878ritdl45.fsf@igel.home>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
 <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com> <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
 <87cz85dmmd.fsf@igel.home> <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
 <878ritdl45.fsf@igel.home>
Message-ID: <CAEUhbmWx9=YYZQ1SW_a9rkLraJ-R4ABStdMASUARVkBAx0mYUA@mail.gmail.com>

On Tue, Dec 27, 2022 at 9:36 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>
> On Dez 27 2022, Bin Meng wrote:
>
> > On Tue, Dec 27, 2022 at 9:04 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
> >>
> >> On Dez 27 2022, Bin Meng wrote:
> >>
> >> > Changing the array size to PLIC_SOURCES + 1 does not make sense. The
> >> > PLIC_SOURCES should be 176 which is correct as it includes source 0 on
> >> > the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
> >> > will create a buffer overrun.
> >>
> >> The range check will always allow that overrrun.
> >>
> >
> > Well, with a correct dtb it doesn't.
>
> You cannot argue with the dtb, since this is externally controlled.
>
> > Strictly speaking, your proposed fix allows that overrun too
>
> How?
>

Passing num = 200 to plic_priority_save/restore.

You can argue my example is a misuse of the API, but I can argue a
wrong dtb should not be in the first place too.

Regards,
Bin


From schwab at linux-m68k.org  Tue Dec 27 06:06:00 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 15:06:00 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <CAEUhbmWx9=YYZQ1SW_a9rkLraJ-R4ABStdMASUARVkBAx0mYUA@mail.gmail.com>
	(Bin Meng's message of "Tue, 27 Dec 2022 21:49:07 +0800")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	<87cz85dmmd.fsf@igel.home>
	<CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
	<878ritdl45.fsf@igel.home>
	<CAEUhbmWx9=YYZQ1SW_a9rkLraJ-R4ABStdMASUARVkBAx0mYUA@mail.gmail.com>
Message-ID: <874jthdjqv.fsf@igel.home>

On Dez 27 2022, Bin Meng wrote:

> Passing num = 200 to plic_priority_save/restore.
>
> You can argue my example is a misuse of the API,

It is a bug just like the bug in plic_priority_save/restore.

> but I can argue a wrong dtb should not be in the first place too.

The dtb is an external resource.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From samuel at sholland.org  Tue Dec 27 09:06:24 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 11:06:24 -0600
Subject: Upcoming OpenSBI v1.2 release
In-Reply-To: <efd224b6-47c4-4f55-b247-5e6156c3d451@microchip.com>
References: <CAAhSdy1MTYZcN0cbwPoM41RTWPwLuhbNvprKqhcXfJiNE8Jamw@mail.gmail.com>
 <CAOnJCUK=XOfNtp6aTveqSdHYwUtNbbrnqn53z06fKU_i6ufTbA@mail.gmail.com>
 <efd224b6-47c4-4f55-b247-5e6156c3d451@microchip.com>
Message-ID: <af3a653f-1a20-38ad-b8d9-3b6b1a0e66c4@sholland.org>

On 12/22/22 04:49, Conor.Dooley at microchip.com wrote:
> Hey,
> 
> On 21/12/2022 15:02, Atish Patra wrote:
>> On Fri, Dec 16, 2022 at 9:42 PM Anup Patel <anup at brainfault.org> wrote:
>>>
>>> Hi All,
>>>
>>> We are close to the OpenSBI v1.2 release. I plan to complete this
>>> release before the end of next week (i.e. 24th December 2022).
>>>
>>> Next week, I won't be merging patches unless it's a critical fix.
>>> Also, I request everyone to test the latest OpenSBI on their RISC-V
>>> platforms.
>>>
>>
>> Explicitly adding some folks for help in testing. We don't have access
>> to all the boards.
> 
> In terms of PolarFire SoC, neither good nor bad news? Since OpenSBI is
> just one part of the HSS [0] it's non-trivial to do an upgrade & any
> meaningful testing - so probably not a runner in advance of Christmas.
> 
> We are incredibly tight on space in eNVM for the HSS as things stand,
> so it is likely that we will not move to later versions of OpenSBI
> than (maybe) v1.1 & stick to cherry-picking fixes.
> The last time the HSS bumped its OpenSBI version, the change in size
> of OpenSBI needed some working around IIRC.

Adding Kconfig was quite helpful here. Now that there is an
officially-supported way to disable unused FDT drivers, my OpenSBI
builds for D1 are comfortably back under 256 KiB.

> I'll try to give my boards from other vendors a go, but I doubt I'll
> have anything useful done before the 24th.
> 
> Apologies for not being more helpful,
> Conor.
> 
> 0 - https://github.com/polarfire-soc/hart-software-services/tree/master/thirdparty/opensbi
> 
>> It would be great if folks can test the latest head commit b848d87 on
>> the boards they have and send a Tested by tag.

While I still have concerns about the PLIC series that was merged at the
last minute with multiple outstanding concerns, the v1.2 release still
boots and hart suspend still works, so:

Tested-by: Samuel Holland <samuel at sholland.org> # D1

Regards,
Samuel



From dbarboza at ventanamicro.com  Tue Dec 27 09:25:24 2022
From: dbarboza at ventanamicro.com (Daniel Henrique Barboza)
Date: Tue, 27 Dec 2022 14:25:24 -0300
Subject: [PATCH] lib: utils/sys: Allow custom HTIF base address for RV32
In-Reply-To: <20221226033603.1860569-1-bmeng@tinylab.org>
References: <20221226033603.1860569-1-bmeng@tinylab.org>
Message-ID: <ddf50096-ee91-b0af-9a03-496159e264bf@ventanamicro.com>



On 12/26/22 00:36, Bin Meng wrote:
> commit 6dde43584f18 ("lib: utils/sys: Extend HTIF library to allow custom base address")
> forgot to update do_tohost_fromhost() codes for RV32, which still
> accesses the HTIF registers using the ELF symbol address directly.
>
> Fixes: 6dde43584f18 ("lib: utils/sys: Extend HTIF library to allow custom base address")
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---

With this patch, "qemu-system-riscv32 -M spike -bios fw_payload.bin -nographic"
now displays OpenSBI output in the terminal


Tested-by: Daniel Henrique Barboza <dbarboza at ventanamicro.com>

>
>   lib/utils/sys/htif.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/utils/sys/htif.c b/lib/utils/sys/htif.c
> index d7cbeaf..b4e6321 100644
> --- a/lib/utils/sys/htif.c
> +++ b/lib/utils/sys/htif.c
> @@ -135,11 +135,11 @@ static void do_tohost_fromhost(uint64_t dev, uint64_t cmd, uint64_t data)
>   	__set_tohost(HTIF_DEV_SYSTEM, cmd, data);
>   
>   	while (1) {
> -		uint64_t fh = fromhost;
> +		uint64_t fh = __read_fromhost();
>   		if (fh) {
>   			if (FROMHOST_DEV(fh) == HTIF_DEV_SYSTEM &&
>   			    FROMHOST_CMD(fh) == cmd) {
> -				fromhost = 0;
> +				__write_fromhost(0);
>   				break;
>   			}
>   			__check_fromhost();



From samuel at sholland.org  Tue Dec 27 10:22:22 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 12:22:22 -0600
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
 <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
 <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
 <87cz85dmmd.fsf@igel.home>
 <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
Message-ID: <da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>

On 12/27/22 07:13, Bin Meng wrote:
> On Tue, Dec 27, 2022 at 9:04 PM Andreas Schwab <schwab at linux-m68k.org> wrote:
>>
>> On Dez 27 2022, Bin Meng wrote:
>>
>>> Changing the array size to PLIC_SOURCES + 1 does not make sense. The
>>> PLIC_SOURCES should be 176 which is correct as it includes source 0 on
>>> the Allwinner SoC. The "riscv,ndev" [1] should not be 176 otherwise it
>>> will create a buffer overrun.
>>
>> The range check will always allow that overrrun.
>>
> 
> Well, with a correct dtb it doesn't.

No, the bug has nothing at all to do with the DTB. The bug is purely in
the C code.

> Strictly speaking, your proposed fix allows that overrun too, if the
> given num is an arbitrary larger value than the size of the priority
> array.

This is already what you are doing! You have:

	static u8 plic_priority[PLIC_SOURCES];

and

	fdt_plic_priority_save(plic_priority, PLIC_SOURCES);

The combination of those two lines is necessarily incorrect. Because you
dereference priority[num], the number of elements in the array *must* be
greater than num.

Since the range of external interrupt sources is [1, 175], the
definitions need to be:

#define PLIC_SOURCES                    175
#define PLIC_IE_WORDS                   ((PLIC_SOURCES / 32) + 1)

static u8 plic_priority[1 + PLIC_SOURCES];

Anything else is either wrong or wasting space.

Regards,
Samuel



From schwab at linux-m68k.org  Tue Dec 27 10:39:25 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 19:39:25 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org> (Samuel
	Holland's message of "Tue, 27 Dec 2022 12:22:22 -0600")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	<87cz85dmmd.fsf@igel.home>
	<CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
	<da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>
Message-ID: <87v8lwd736.fsf@igel.home>

On Dez 27 2022, Samuel Holland wrote:

> Anything else is either wrong or wasting space.

Not wasting space:

diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
index d633514..901ffaa 100644
--- a/lib/utils/irqchip/plic.c
+++ b/lib/utils/irqchip/plic.c
@@ -39,14 +39,14 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
 void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
 {
 	for (u32 i = 1; i <= num; i++)
-		priority[i] = plic_get_priority(plic, i);
+		priority[i - 1] = plic_get_priority(plic, i);
 }
 
 void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
 			   u32 num)
 {
 	for (u32 i = 1; i <= num; i++)
-		plic_set_priority(plic, i, priority[i]);
+		plic_set_priority(plic, i, priority[i - 1]);
 }
 
 static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid)

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From samuel at sholland.org  Tue Dec 27 10:44:44 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 12:44:44 -0600
Subject: [PATCH] platform: generic: allwinner: Fix PLIC array bounds
Message-ID: <20221227184444.61331-1-samuel@sholland.org>

The two referenced commits passed incorrect bounds to the PLIC save/
restore functions, causing out-of-bounds memory access. The functions
expect "num" to be the 1-based number of interrupt sources, equivalent
to the "riscv,ndev" devicetree property. Thus, "num" must be strictly
smaller than the 0-based size of the array storing the register values.

However, the referenced commits incorrectly passed in the unmodified
size of the array as "num". Fix this by reducing PLIC_SOURCES (matching
"riscv,ndev" on this platform), while keeping the same array sizes.

Addresses-Coverity-ID: 1530251 ("Out-of-bounds access")
Addresses-Coverity-ID: 1530252 ("Out-of-bounds access")
Fixes: 8509e46ca63a ("lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers")
Fixes: 9a2eeb4aaeac ("lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers")
Signed-off-by: Samuel Holland <samuel at sholland.org>
---

 platform/generic/allwinner/sun20i-d1.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 1da9e5b..e2b76a3 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -69,10 +69,10 @@ static void sun20i_d1_csr_restore(void)
  * PLIC
  */
 
-#define PLIC_SOURCES			176
-#define PLIC_IE_WORDS			((PLIC_SOURCES + 31) / 32)
+#define PLIC_SOURCES			175
+#define PLIC_IE_WORDS			(PLIC_SOURCES / 32 + 1)
 
-static u8 plic_priority[PLIC_SOURCES];
+static u8 plic_priority[1 + PLIC_SOURCES];
 static u32 plic_sie[PLIC_IE_WORDS];
 static u32 plic_threshold;
 
-- 
2.37.4



From samuel at sholland.org  Tue Dec 27 10:49:12 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 12:49:12 -0600
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <87v8lwd736.fsf@igel.home>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
 <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
 <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
 <87cz85dmmd.fsf@igel.home>
 <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
 <da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>
 <87v8lwd736.fsf@igel.home>
Message-ID: <af4ef9bb-8c83-6c73-6e68-8c46b3b96892@sholland.org>

On 12/27/22 12:39, Andreas Schwab wrote:
> On Dez 27 2022, Samuel Holland wrote:
> 
>> Anything else is either wrong or wasting space.
> 
> Not wasting space:

I am aware. However, this sort of change is not feasible for
plic_context_save()/plic_context_restore(). It would severely complicate
those functions with extra bit manipulation (thus wasting even more
space in code size). So I am happy to pay one byte here for consistency
between the two sets of functions.

Regards,
Samuel

> diff --git a/lib/utils/irqchip/plic.c b/lib/utils/irqchip/plic.c
> index d633514..901ffaa 100644
> --- a/lib/utils/irqchip/plic.c
> +++ b/lib/utils/irqchip/plic.c
> @@ -39,14 +39,14 @@ static void plic_set_priority(const struct plic_data *plic, u32 source, u32 val)
>  void plic_priority_save(const struct plic_data *plic, u8 *priority, u32 num)
>  {
>  	for (u32 i = 1; i <= num; i++)
> -		priority[i] = plic_get_priority(plic, i);
> +		priority[i - 1] = plic_get_priority(plic, i);
>  }
>  
>  void plic_priority_restore(const struct plic_data *plic, const u8 *priority,
>  			   u32 num)
>  {
>  	for (u32 i = 1; i <= num; i++)
> -		plic_set_priority(plic, i, priority[i]);
> +		plic_set_priority(plic, i, priority[i - 1]);
>  }
>  
>  static u32 plic_get_thresh(const struct plic_data *plic, u32 cntxid)
> 



From schwab at linux-m68k.org  Tue Dec 27 10:52:22 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 19:52:22 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <af4ef9bb-8c83-6c73-6e68-8c46b3b96892@sholland.org> (Samuel
	Holland's message of "Tue, 27 Dec 2022 12:49:12 -0600")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	<87cz85dmmd.fsf@igel.home>
	<CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
	<da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>
	<87v8lwd736.fsf@igel.home>
	<af4ef9bb-8c83-6c73-6e68-8c46b3b96892@sholland.org>
Message-ID: <87r0wkd6hl.fsf@igel.home>

On Dez 27 2022, Samuel Holland wrote:

> I am aware. However, this sort of change is not feasible for
> plic_context_save()/plic_context_restore(). It would severely complicate
> those functions with extra bit manipulation (thus wasting even more
> space in code size).

If your compiler is so dumb you have a much bigger problem.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From schwab at linux-m68k.org  Tue Dec 27 10:53:45 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 19:53:45 +0100
Subject: [PATCH] platform: generic: allwinner: Fix PLIC array bounds
In-Reply-To: <20221227184444.61331-1-samuel@sholland.org> (Samuel Holland's
	message of "Tue, 27 Dec 2022 12:44:44 -0600")
References: <20221227184444.61331-1-samuel@sholland.org>
Message-ID: <87mt78d6fa.fsf@igel.home>

On Dez 27 2022, Samuel Holland wrote:

> -static u8 plic_priority[PLIC_SOURCES];
> +static u8 plic_priority[1 + PLIC_SOURCES];

This is unnecessarily wasting space.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From samuel at sholland.org  Tue Dec 27 11:12:05 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 13:12:05 -0600
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <87r0wkd6hl.fsf@igel.home>
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
 <CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
 <374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
 <CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
 <87cz85dmmd.fsf@igel.home>
 <CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
 <da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>
 <87v8lwd736.fsf@igel.home>
 <af4ef9bb-8c83-6c73-6e68-8c46b3b96892@sholland.org>
 <87r0wkd6hl.fsf@igel.home>
Message-ID: <6e6e3302-ce90-f851-807f-d236499dbf83@sholland.org>

On 12/27/22 12:52, Andreas Schwab wrote:
> On Dez 27 2022, Samuel Holland wrote:
> 
>> I am aware. However, this sort of change is not feasible for
>> plic_context_save()/plic_context_restore(). It would severely complicate
>> those functions with extra bit manipulation (thus wasting even more
>> space in code size).
> 
> If your compiler is so dumb you have a much bigger problem.

I'm disappointed that I even have to explain this...

"This sort of change" to avoid using space for IRQ 0, thus saving one
*bit* in the array used by plic_context_save(), would require combining
two registers into one array element with shifts:

	enable[i] = plic_get_ie(plic, context_id, i) >> 1 |
	            plic_get_ie(plic, context_id, i + 1) << 31;

and doing the opposite transformation in plic_context_restore(). The
compiler is not going to optimize that out.

If you really care about shaving off bytes, there is plenty of
low-hanging fruit elsewhere in OpenSBI. This bikeshed really does not
need painting.

Regards,
Samuel



From schwab at linux-m68k.org  Tue Dec 27 11:31:38 2022
From: schwab at linux-m68k.org (Andreas Schwab)
Date: Tue, 27 Dec 2022 20:31:38 +0100
Subject: [PATCH 1/1] platform: generic: allwinner: avoid buffer overrun
In-Reply-To: <6e6e3302-ce90-f851-807f-d236499dbf83@sholland.org> (Samuel
	Holland's message of "Tue, 27 Dec 2022 13:12:05 -0600")
References: <20221227110129.145976-1-heinrich.schuchardt@canonical.com>
	<CAEUhbmX9u1Fpy-ZQP=Gyp=-jwc5OzRM7XziCkydLcsQqYBivKg@mail.gmail.com>
	<374eb91d-e580-3583-accf-0d0e3a3687ea@canonical.com>
	<CAEUhbmUbaAYp-dcEYF845XX66ZGFLPkNuJMp2xpkpPLNZ3o4MQ@mail.gmail.com>
	<87cz85dmmd.fsf@igel.home>
	<CAEUhbmXcQiGH6WQ3pN_C+mv_qRn0mF2Pb2vq_dxeXxMsygNwdw@mail.gmail.com>
	<da726834-79af-8e40-c39e-a6dd4c421ea4@sholland.org>
	<87v8lwd736.fsf@igel.home>
	<af4ef9bb-8c83-6c73-6e68-8c46b3b96892@sholland.org>
	<87r0wkd6hl.fsf@igel.home>
	<6e6e3302-ce90-f851-807f-d236499dbf83@sholland.org>
Message-ID: <87ilhwd4o5.fsf@igel.home>

On Dez 27 2022, Samuel Holland wrote:

> "This sort of change" to avoid using space for IRQ 0, thus saving one
> *bit* in the array

??? *byte*

> used by plic_context_save(),

??? plic_priority_save/restore

> 	enable[i] = plic_get_ie(plic, context_id, i) >> 1 |
> 	            plic_get_ie(plic, context_id, i + 1) << 31;

??? Nothing at all changes here.

-- 
Andreas Schwab, schwab at linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."


From conor at kernel.org  Tue Dec 27 11:40:57 2022
From: conor at kernel.org (Conor Dooley)
Date: Tue, 27 Dec 2022 19:40:57 +0000
Subject: [PATCH v2] dt-bindings: riscv: add SBI PMU event mappings
Message-ID: <20221227194056.3891216-1-conor@kernel.org>

From: Conor Dooley <conor.dooley at microchip.com>

The SBI PMU extension requires a firmware to be aware of the event to
counter/mhpmevent mappings supported by the hardware. OpenSBI may use
DeviceTree to describe the PMU mappings. This binding is currently
described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
since v7.2.0.

Import the binding for use while validating dtb dumps from QEMU and
upcoming hardware (eg JH7110 SoC) that will make use of the event
mapping.

Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit Extension
Co-developed-by: Atish Patra <atishp at rivosinc.com>
Signed-off-by: Atish Patra <atishp at rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
---
Changes in v2:
- use the schema mechanism for dependancies between properties
- +CC perf maintainers...
- move the matrix element descriptions into regular item descriptions
  rather than doing so freeform in the property description
- drop some description text that no longer applies since changes were
  made to the SBI spec
- drop mention of the "generic platform" which is OpenSBI specific
- drop the min/max items from the matrices, they don't appear to be
  needed?
---
 .../devicetree/bindings/perf/riscv,pmu.yaml   | 154 ++++++++++++++++++
 1 file changed, 154 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml

diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
new file mode 100644
index 000000000000..b50b69ed4599
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V SBI PMU events
+
+maintainers:
+  - Atish Patra <atishp at rivosinc.com>
+
+description: |
+  SBI PMU extension supports allow supervisor software to configure, start &
+  stop any performance counter at anytime. Thus, a user can leverage full
+  capability of performance analysis tools such as perf if the SBI PMU
+  extension is enabled. The OpenSBI implementation makes the following
+  assumptions about the hardware platform:
+
+    The platform must provide information about PMU event to counter mapping
+    via device tree or platform specific hooks. Otherwise, the SBI PMU
+    extension will not be enabled.
+
+    The platforms should provide information about the PMU event selector
+    values that should be encoded in the expected value of MHPMEVENTx while
+    configuring MHPMCOUNTERx for that specific event. This can be done via a
+    device tree or platform specific hooks. The exact value to be written to
+    the MHPMEVENTx is completely dependent on the platform.
+
+    For information on the SBI spec see:
+      https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
+
+properties:
+  compatible:
+    const: riscv,pmu
+
+  riscv,event-to-mhpmevent:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    description:
+      Represents an ONE-to-ONE mapping between a PMU event and the event
+      selector value that platform expects to be written to the MHPMEVENTx CSR
+      for that event.
+      The mapping is encoded in an matrix format where each element represents
+      an event.
+      This property shouldn't encode any raw hardware event.
+    items:
+      - description: event idx
+      - description: upper 32 bits of the event selector value for MHPMEVENTx
+      - description: lower 32 bits of the event selector value for MHPMEVENTx
+
+  riscv,event-to-mhpmcounters:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    description:
+      Represents a MANY-to-MANY mapping between a range of events and all the
+      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
+      of events. The information is encoded in an matrix format where each
+      element represents a certain range of events and corresponding counters.
+      This property shouldn't encode any raw event.
+    items:
+      - description: upper 32 bits of the pmu event id
+      - description: lower 32 bits of the pmu event id
+      - description: bitmap of MHPMCOUNTERx for this event
+
+  riscv,raw-event-to-mhpmcounters:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    description:
+      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
+      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
+      that raw event.
+      The encoding of the raw events are platform specific. The information is
+      encoded in a matrix format where each element represents the specific raw
+      event(s).
+      If a platform directly encodes each raw PMU event as a unique ID, the
+      value of variant must be 0xffffffff_ffffffff.
+    items:
+      - description:
+          upper 32 invariant bits for the range of events
+      - description:
+          lower 32 invariant bits for the range of events
+      - description:
+          upper 32 bits of the variant bit mask for the range of events
+      - description:
+          lower 32 bits of the variant bit mask for the range of events
+      - description:
+          bitmap of all MHPMCOUNTERx that can monitor the range of events
+
+dependencies:
+  "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
+  "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ]
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    pmu {
+        compatible = "riscv,pmu";
+        riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
+        riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
+                                      <0x00002 0x00002 0x00000004>,
+                                      <0x00003 0x0000A 0x00000ff8>,
+                                      <0x10000 0x10033 0x000ff000>;
+        riscv,raw-event-to-mhpmcounters =
+            /* For event ID 0x0002 */
+            <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
+            /* For event ID 0-4 */
+            <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
+            /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
+            <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
+    };
+
+  - |
+    /*
+     * For HiFive Unmatched board the encodings can be found here
+     * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
+     * This example also binds standard SBI PMU hardware id's to U74 PMU event
+     * codes, U74 uses a bitfield for events encoding, so several U74 events
+     * can be bound to single perf id.
+     * See SBI PMU hardware id's in OpenSBI's include/sbi/sbi_ecall_interface.h
+     */
+    pmu {
+          compatible = "riscv,pmu";
+          riscv,event-to-mhpmevent =
+              /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
+              <0x00003 0x00000000 0x1801>,
+              /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
+              <0x00004 0x00000000 0x0302>,
+              /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
+              <0x00005 0x00000000 0x4000>,
+              /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
+              <0x00006 0x00000000 0x6001>,
+              /* L1D_READ_MISS -> Data cache miss or MMIO access */
+              <0x10001 0x00000000 0x0202>,
+              /* L1D_WRITE_ACCESS -> Data cache write-back */
+              <0x10002 0x00000000 0x0402>,
+              /* L1I_READ_ACCESS -> Instruction cache miss */
+              <0x10009 0x00000000 0x0102>,
+              /* LL_READ_MISS -> UTLB miss */
+              <0x10011 0x00000000 0x2002>,
+              /* DTLB_READ_MISS -> Data TLB miss */
+              <0x10019 0x00000000 0x1002>,
+              /* ITLB_READ_MISS-> Instruction TLB miss */
+              <0x10021 0x00000000 0x0802>;
+          riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
+                                        <0x10001 0x10002 0x18>,
+                                        <0x10009 0x10009 0x18>,
+                                        <0x10011 0x10011 0x18>,
+                                        <0x10019 0x10019 0x18>,
+                                        <0x10021 0x10021 0x18>;
+          riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
+                                            <0x0 0x1 0xffffffff 0xfff800ff 0x18>,
+                                            <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
+    };
-- 
2.38.1



From samuel at sholland.org  Tue Dec 27 12:05:01 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 14:05:01 -0600
Subject: [PATCH v2] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <20221227194056.3891216-1-conor@kernel.org>
References: <20221227194056.3891216-1-conor@kernel.org>
Message-ID: <8bbe4e7b-ae35-ab68-bb0b-72c201ea1256@sholland.org>

Hi Conor,

On 12/27/22 13:40, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> The SBI PMU extension requires a firmware to be aware of the event to
> counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> DeviceTree to describe the PMU mappings. This binding is currently
> described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> since v7.2.0.
> 
> Import the binding for use while validating dtb dumps from QEMU and
> upcoming hardware (eg JH7110 SoC) that will make use of the event
> mapping.
> 
> Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit Extension
> Co-developed-by: Atish Patra <atishp at rivosinc.com>
> Signed-off-by: Atish Patra <atishp at rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> Changes in v2:
> - use the schema mechanism for dependancies between properties
> - +CC perf maintainers...
> - move the matrix element descriptions into regular item descriptions
>   rather than doing so freeform in the property description
> - drop some description text that no longer applies since changes were
>   made to the SBI spec
> - drop mention of the "generic platform" which is OpenSBI specific
> - drop the min/max items from the matrices, they don't appear to be
>   needed?
> ---
>  .../devicetree/bindings/perf/riscv,pmu.yaml   | 154 ++++++++++++++++++
>  1 file changed, 154 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> new file mode 100644
> index 000000000000..b50b69ed4599
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V SBI PMU events
> +
> +maintainers:
> +  - Atish Patra <atishp at rivosinc.com>
> +
> +description: |
> +  SBI PMU extension supports allow supervisor software to configure, start &
> +  stop any performance counter at anytime. Thus, a user can leverage full
> +  capability of performance analysis tools such as perf if the SBI PMU
> +  extension is enabled. The OpenSBI implementation makes the following
> +  assumptions about the hardware platform:
> +
> +    The platform must provide information about PMU event to counter mapping
> +    via device tree or platform specific hooks. Otherwise, the SBI PMU
> +    extension will not be enabled.
> +
> +    The platforms should provide information about the PMU event selector
> +    values that should be encoded in the expected value of MHPMEVENTx while
> +    configuring MHPMCOUNTERx for that specific event. This can be done via a
> +    device tree or platform specific hooks. The exact value to be written to
> +    the MHPMEVENTx is completely dependent on the platform.
> +
> +    For information on the SBI spec see:
> +      https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
> +
> +properties:
> +  compatible:
> +    const: riscv,pmu
> +
> +  riscv,event-to-mhpmevent:
> +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +    description:
> +      Represents an ONE-to-ONE mapping between a PMU event and the event
> +      selector value that platform expects to be written to the MHPMEVENTx CSR
> +      for that event.
> +      The mapping is encoded in an matrix format where each element represents
> +      an event.
> +      This property shouldn't encode any raw hardware event.
> +    items:
> +      - description: event idx

It might be good to clarify that this refers specifically to "event_idx"
from the SBI specification.

> +      - description: upper 32 bits of the event selector value for MHPMEVENTx
> +      - description: lower 32 bits of the event selector value for MHPMEVENTx

Since you are describing the the columns of the matrix here, I believe
these entries need to go under two levels of "items:". The same applies
for the other properties.

> +
> +  riscv,event-to-mhpmcounters:
> +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +    description:
> +      Represents a MANY-to-MANY mapping between a range of events and all the
> +      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
> +      of events. The information is encoded in an matrix format where each
> +      element represents a certain range of events and corresponding counters.
> +      This property shouldn't encode any raw event.
> +    items:
> +      - description: upper 32 bits of the pmu event id
> +      - description: lower 32 bits of the pmu event id

These two cells represent the start and end of a range of 32-bit values
(again the "event_idx" from the SBI specification), not 32-bit
components of a 64-bit value.

Regards,
Samuel

> +      - description: bitmap of MHPMCOUNTERx for this event
> +
> +  riscv,raw-event-to-mhpmcounters:
> +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> +    description:
> +      Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s)
> +      and all the MHPMCOUNTERx in a bitmap format that can be used to monitor
> +      that raw event.
> +      The encoding of the raw events are platform specific. The information is
> +      encoded in a matrix format where each element represents the specific raw
> +      event(s).
> +      If a platform directly encodes each raw PMU event as a unique ID, the
> +      value of variant must be 0xffffffff_ffffffff.
> +    items:
> +      - description:
> +          upper 32 invariant bits for the range of events
> +      - description:
> +          lower 32 invariant bits for the range of events
> +      - description:
> +          upper 32 bits of the variant bit mask for the range of events
> +      - description:
> +          lower 32 bits of the variant bit mask for the range of events
> +      - description:
> +          bitmap of all MHPMCOUNTERx that can monitor the range of events
> +
> +dependencies:
> +  "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
> +  "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ]
> +
> +required:
> +  - compatible
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    pmu {
> +        compatible = "riscv,pmu";
> +        riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
> +        riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
> +                                      <0x00002 0x00002 0x00000004>,
> +                                      <0x00003 0x0000A 0x00000ff8>,
> +                                      <0x10000 0x10033 0x000ff000>;
> +        riscv,raw-event-to-mhpmcounters =
> +            /* For event ID 0x0002 */
> +            <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
> +            /* For event ID 0-4 */
> +            <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
> +            /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */
> +            <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>;
> +    };
> +
> +  - |
> +    /*
> +     * For HiFive Unmatched board the encodings can be found here
> +     * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
> +     * This example also binds standard SBI PMU hardware id's to U74 PMU event
> +     * codes, U74 uses a bitfield for events encoding, so several U74 events
> +     * can be bound to single perf id.
> +     * See SBI PMU hardware id's in OpenSBI's include/sbi/sbi_ecall_interface.h
> +     */
> +    pmu {
> +          compatible = "riscv,pmu";
> +          riscv,event-to-mhpmevent =
> +              /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
> +              <0x00003 0x00000000 0x1801>,
> +              /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */
> +              <0x00004 0x00000000 0x0302>,
> +              /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
> +              <0x00005 0x00000000 0x4000>,
> +              /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */
> +              <0x00006 0x00000000 0x6001>,
> +              /* L1D_READ_MISS -> Data cache miss or MMIO access */
> +              <0x10001 0x00000000 0x0202>,
> +              /* L1D_WRITE_ACCESS -> Data cache write-back */
> +              <0x10002 0x00000000 0x0402>,
> +              /* L1I_READ_ACCESS -> Instruction cache miss */
> +              <0x10009 0x00000000 0x0102>,
> +              /* LL_READ_MISS -> UTLB miss */
> +              <0x10011 0x00000000 0x2002>,
> +              /* DTLB_READ_MISS -> Data TLB miss */
> +              <0x10019 0x00000000 0x1002>,
> +              /* ITLB_READ_MISS-> Instruction TLB miss */
> +              <0x10021 0x00000000 0x0802>;
> +          riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>,
> +                                        <0x10001 0x10002 0x18>,
> +                                        <0x10009 0x10009 0x18>,
> +                                        <0x10011 0x10011 0x18>,
> +                                        <0x10019 0x10019 0x18>,
> +                                        <0x10021 0x10021 0x18>;
> +          riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>,
> +                                            <0x0 0x1 0xffffffff 0xfff800ff 0x18>,
> +                                            <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
> +    };



From samuel at sholland.org  Tue Dec 27 12:13:44 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 14:13:44 -0600
Subject: [PATCH] Makefile: Remove -N ldflag to prevent linker RWX warning
In-Reply-To: <20221225032211.1370467-1-rpathak@ventanamicro.com>
References: <20221225032211.1370467-1-rpathak@ventanamicro.com>
Message-ID: <f0c6670a-27f7-5412-65f9-56f39b67fe16@sholland.org>

On 12/24/22 21:22, Rahul Pathak wrote:
> -N option coalesce all sections into single LOAD segment which causes
> data and other sections to have executable permission causing warning
> with new binutils ld 2.39.
> New ld emits warning when any segment have all three permissions RWX.
> 
> ld.bfd: warning: test.elf has a LOAD segment with RWX permissions
> ld.bfd: warning: fw_dynamic.elf has a LOAD segment with RWX permissions
> ld.bfd: warning: fw_jump.elf has a LOAD segment with RWX permissions
> ld.bfd: warning: fw_payload.elf has a LOAD segment with RWX permissions
> 
> This option was added in below commit -
> commit: eeab92f2423e ("Makefile: Convert to a more standard format")
> 
> Removing -N option allows to have text and rodata into one LOAD
> segment and other sections into separate LOAD segment which prevents
> RWX permissions on single LOAD segment. Here X == E
> 
> Current
>  LOAD           0x0000000000000120 0x0000000080000000 0x0000000080000000
>                  0x000000000001d4d0 0x0000000000032ed8  RWE    0x10
> 
> -N removed
>   LOAD           0x0000000000001000 0x0000000080000000 0x0000000080000000
>                  0x00000000000198cc 0x00000000000198cc  R E    0x1000
>   LOAD           0x000000000001b000 0x000000008001a000 0x000000008001a000
>                  0x00000000000034d0 0x0000000000018ed8  RW     0x1000
> 
> Signed-off-by: Rahul Pathak <rpathak at ventanamicro.com>
> ---
>  Makefile | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

fw_dynamic.bin still works for me on D1 with this change, so:

Tested-by: Samuel Holland <samuel at sholland.org>



From conor at kernel.org  Tue Dec 27 12:17:59 2022
From: conor at kernel.org (Conor Dooley)
Date: Tue, 27 Dec 2022 20:17:59 +0000
Subject: [PATCH v2] dt-bindings: riscv: add SBI PMU event mappings
In-Reply-To: <8bbe4e7b-ae35-ab68-bb0b-72c201ea1256@sholland.org>
References: <20221227194056.3891216-1-conor@kernel.org>
 <8bbe4e7b-ae35-ab68-bb0b-72c201ea1256@sholland.org>
Message-ID: <Y6tS959TaY2EBAdn@spud>

On Tue, Dec 27, 2022 at 02:05:01PM -0600, Samuel Holland wrote:
> Hi Conor,
> 
> On 12/27/22 13:40, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley at microchip.com>
> > 
> > The SBI PMU extension requires a firmware to be aware of the event to
> > counter/mhpmevent mappings supported by the hardware. OpenSBI may use
> > DeviceTree to describe the PMU mappings. This binding is currently
> > described in markdown in OpenSBI (since v1.0 in Dec 2021) & used by QEMU
> > since v7.2.0.
> > 
> > Import the binding for use while validating dtb dumps from QEMU and
> > upcoming hardware (eg JH7110 SoC) that will make use of the event
> > mapping.
> > 
> > Link: https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md
> > Link: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc # Performance Monitoring Unit Extension
> > Co-developed-by: Atish Patra <atishp at rivosinc.com>
> > Signed-off-by: Atish Patra <atishp at rivosinc.com>
> > Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> > ---
> > Changes in v2:
> > - use the schema mechanism for dependancies between properties
> > - +CC perf maintainers...
> > - move the matrix element descriptions into regular item descriptions
> >   rather than doing so freeform in the property description
> > - drop some description text that no longer applies since changes were
> >   made to the SBI spec
> > - drop mention of the "generic platform" which is OpenSBI specific
> > - drop the min/max items from the matrices, they don't appear to be
> >   needed?

> > +  riscv,event-to-mhpmevent:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +    description:
> > +      Represents an ONE-to-ONE mapping between a PMU event and the event
> > +      selector value that platform expects to be written to the MHPMEVENTx CSR
> > +      for that event.
> > +      The mapping is encoded in an matrix format where each element represents
> > +      an event.
> > +      This property shouldn't encode any raw hardware event.
> > +    items:
> > +      - description: event idx
> 
> It might be good to clarify that this refers specifically to "event_idx"
> from the SBI specification.
> 
> > +      - description: upper 32 bits of the event selector value for MHPMEVENTx
> > +      - description: lower 32 bits of the event selector value for MHPMEVENTx
> 
> Since you are describing the the columns of the matrix here, I believe
> these entries need to go under two levels of "items:". The same applies
> for the other properties.
> 
> > +
> > +  riscv,event-to-mhpmcounters:
> > +    $ref: /schemas/types.yaml#/definitions/uint32-matrix
> > +    description:
> > +      Represents a MANY-to-MANY mapping between a range of events and all the
> > +      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
> > +      of events. The information is encoded in an matrix format where each
> > +      element represents a certain range of events and corresponding counters.
> > +      This property shouldn't encode any raw event.
> > +    items:
> > +      - description: upper 32 bits of the pmu event id
> > +      - description: lower 32 bits of the pmu event id
> 
> These two cells represent the start and end of a range of 32-bit values
> (again the "event_idx" from the SBI specification), not 32-bit
> components of a 64-bit value.

I think this one is me struggling to understand the markdown description
of the binding. Thanks for explaining!

I'll sort the lot out for v3 in a few days.

Thanks,
Conor.

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From samuel at sholland.org  Tue Dec 27 18:22:51 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 20:22:51 -0600
Subject: [PATCH v6 4/4] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <20221223070741.236271-5-weiliang.lim@starfivetech.com>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
 <20221223070741.236271-5-weiliang.lim@starfivetech.com>
Message-ID: <e98acfe6-3fef-f7cd-fb58-001ace86bbf4@sholland.org>

On 12/23/22 01:07, Wei Liang Lim wrote:
> Add Starfive JH7110 platform implementation
> 
> Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> ---
>  platform/generic/Kconfig             |  4 +++
>  platform/generic/configs/defconfig   |  1 +
>  platform/generic/starfive/jh7110.c   | 47 ++++++++++++++++++++++++++++
>  platform/generic/starfive/objects.mk |  6 ++++
>  4 files changed, 58 insertions(+)
>  create mode 100644 platform/generic/starfive/jh7110.c
>  create mode 100644 platform/generic/starfive/objects.mk
> 
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 62c7a2d..47c10e5 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
>  	depends on FDT_RESET && FDT_I2C
>  	default n
>  
> +config PLATFORM_STARFIVE_JH7110
> +	bool "StarFive JH7110 support"
> +	default n
> +
>  endif
> diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
> index 47fca95..4b0842e 100644
> --- a/platform/generic/configs/defconfig
> +++ b/platform/generic/configs/defconfig
> @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
>  CONFIG_PLATFORM_RENESAS_RZFIVE=y
>  CONFIG_PLATFORM_SIFIVE_FU540=y
>  CONFIG_PLATFORM_SIFIVE_FU740=y
> +CONFIG_PLATFORM_STARFIVE_JH7110=y
>  CONFIG_FDT_GPIO=y
>  CONFIG_FDT_GPIO_SIFIVE=y
>  CONFIG_FDT_I2C=y
> diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
> new file mode 100644
> index 0000000..70a26fe
> --- /dev/null
> +++ b/platform/generic/starfive/jh7110.c
> @@ -0,0 +1,47 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2022 StarFive
> + *
> + * Authors:
> + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> + */
> +
> +#include <libfdt.h>
> +#include <platform_override.h>
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +static u32 selected_hartid = -1;
> +
> +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> +				   const struct fdt_match *match)
> +{
> +	if (selected_hartid != -1)
> +		return (selected_hartid == hartid);
> +
> +	return true;
> +}
> +
> +static void starfive_jh7110_fw_init(void *fdt, const struct fdt_match *match)
> +{
> +	const fdt32_t *val;
> +	int len, coff;
> +
> +	coff = fdt_path_offset(fdt, "/chosen");
> +	if (-1 < coff) {
> +		val = fdt_getprop(fdt, coff, "boot-hart-id", &len);

This looks like a brand new property. Please document it:

https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/chosen.yaml

> +		if (val && len)

This should probably check "len >= 4" (or sizeof equivalent).

Regards,
Samuel

> +			selected_hartid = (u32) fdt32_to_cpu(*val);
> +	}
> +}
> +
> +static const struct fdt_match starfive_jh7110_match[] = {
> +	{ .compatible = "starfive,jh7110" },
> +	{ },
> +};
> +
> +const struct platform_override starfive_jh7110 = {
> +	.match_table = starfive_jh7110_match,
> +	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> +	.fw_init = starfive_jh7110_fw_init,
> +};
> diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
> new file mode 100644
> index 0000000..0b900fb
> --- /dev/null
> +++ b/platform/generic/starfive/objects.mk
> @@ -0,0 +1,6 @@
> +#
> +# SPDX-License-Identifier: BSD-2-Clause
> +#
> +
> +carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
> +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o



From samuel at sholland.org  Tue Dec 27 18:58:27 2022
From: samuel at sholland.org (Samuel Holland)
Date: Tue, 27 Dec 2022 20:58:27 -0600
Subject: [PATCH] treewide: Replace TRUE/FALSE with true/false
In-Reply-To: <20221221113806.1450323-1-bmeng@tinylab.org>
References: <20221221113806.1450323-1-bmeng@tinylab.org>
Message-ID: <dee4771b-eaed-8c6a-03e3-e37e3b790add@sholland.org>

On 12/21/22 05:38, Bin Meng wrote:
> C language standard uses true/false for the boolean type.
> Let's switch to that for better language compatibility.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---
> 
>  include/sbi/sbi_domain.h           |  4 +--
>  include/sbi/sbi_list.h             |  2 +-
>  include/sbi/sbi_platform.h         | 18 +++++------
>  include/sbi/sbi_types.h            |  6 ++--
>  lib/sbi/sbi_console.c              |  4 +--
>  lib/sbi/sbi_domain.c               | 44 ++++++++++++-------------
>  lib/sbi/sbi_ecall.c                |  4 +--
>  lib/sbi/sbi_ecall_hsm.c            |  2 +-
>  lib/sbi/sbi_emulate_csr.c          | 10 +++---
>  lib/sbi/sbi_fifo.c                 |  8 ++---
>  lib/sbi/sbi_init.c                 | 52 +++++++++++++++---------------
>  lib/sbi/sbi_ipi.c                  |  2 +-
>  lib/sbi/sbi_pmu.c                  | 14 ++++----
>  lib/sbi/sbi_system.c               |  2 +-
>  lib/sbi/sbi_trap.c                 |  8 ++---
>  lib/utils/fdt/fdt_domain.c         |  4 +--
>  lib/utils/reset/fdt_reset_gpio.c   | 12 +++----
>  platform/fpga/ariane/platform.c    |  2 +-
>  platform/fpga/openpiton/platform.c |  2 +-
>  platform/generic/sifive/fu740.c    |  2 +-
>  platform/kendryte/k210/platform.c  |  2 +-
>  platform/nuclei/ux600/platform.c   |  2 +-
>  platform/template/platform.c       |  2 +-
>  23 files changed, 103 insertions(+), 105 deletions(-)

Verified the generated firmware binaries are identical.

Reviewed-by: Samuel Holland <samuel at sholland.org>
Tested-by: Samuel Holland <samuel at sholland.org>



From samuel at sholland.org  Wed Dec 28 11:11:24 2022
From: samuel at sholland.org (Samuel Holland)
Date: Wed, 28 Dec 2022 13:11:24 -0600
Subject: [PATCH 2/2] platform: generic: allwinner: Advertise nonretentive suspend
In-Reply-To: <20221228191125.37584-1-samuel@sholland.org>
References: <20221228191125.37584-1-samuel@sholland.org>
Message-ID: <20221228191125.37584-2-samuel@sholland.org>

Add D1's nonretentive suspend state to the devicetree so S-mode software
knows about it and can use it.

Latency and power measurements were taken on an Allwinner Nezha board:
 - Entry latency was measured from the beginning of sbi_ecall_handler()
   to before the call to wfi() in sun20i_d1_hart_suspend().
 - Exit latency was measured from the beginning of sbi_init() to before
   the call to sbi_hart_switch_mode() in init_warmboot().
 - There was a 17.5 mW benefit from non-retentive suspend compared to
   WFI, with a 170 mW cost during the 107 us entry/exit period. This
   provides a break-even point around 1040 us. Residency includes entry
   latency, so round this up to 1100 us.
 - The hardware power sequence latency (after the WFI) is assumed to be
   negligible, so set the wakeup latency to the exit latency.

Signed-off-by: Samuel Holland <samuel at sholland.org>
---

 platform/generic/allwinner/sun20i-d1.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/platform/generic/allwinner/sun20i-d1.c b/platform/generic/allwinner/sun20i-d1.c
index 1da9e5b..8ca556e 100644
--- a/platform/generic/allwinner/sun20i-d1.c
+++ b/platform/generic/allwinner/sun20i-d1.c
@@ -12,6 +12,7 @@
 #include <sbi/sbi_error.h>
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_pmu.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 #include <sbi_utils/irqchip/fdt_irqchip_plic.h>
 
@@ -202,6 +203,24 @@ static int sun20i_d1_final_init(bool cold_boot, const struct fdt_match *match)
 	return 0;
 }
 
+static const struct sbi_cpu_idle_state sun20i_d1_cpu_idle_states[] = {
+	{
+		.name			= "cpu-nonretentive",
+		.suspend_param		= SBI_HSM_SUSPEND_NON_RET_DEFAULT,
+		.local_timer_stop	= true,
+		.entry_latency_us	= 40,
+		.exit_latency_us	= 67,
+		.min_residency_us	= 1100,
+		.wakeup_latency_us	= 67,
+	},
+	{ }
+};
+
+static int sun20i_d1_fdt_fixup(void *fdt, const struct fdt_match *match)
+{
+	return fdt_add_cpu_idle_states(fdt, sun20i_d1_cpu_idle_states);
+}
+
 static void thead_c9xx_pmu_ctr_enable_irq(uint32_t ctr_idx)
 {
 	unsigned long mip_val;
@@ -265,5 +284,6 @@ static const struct fdt_match sun20i_d1_match[] = {
 const struct platform_override sun20i_d1 = {
 	.match_table	= sun20i_d1_match,
 	.final_init	= sun20i_d1_final_init,
+	.fdt_fixup	= sun20i_d1_fdt_fixup,
 	.extensions_init = sun20i_d1_extensions_init,
 };
-- 
2.37.4



From samuel at sholland.org  Wed Dec 28 11:11:23 2022
From: samuel at sholland.org (Samuel Holland)
Date: Wed, 28 Dec 2022 13:11:23 -0600
Subject: [PATCH 1/2] lib: utils: Add fdt_add_cpu_idle_states() helper function
Message-ID: <20221228191125.37584-1-samuel@sholland.org>

Since the availability and latency properties of CPU idle states depend
on the specific SBI HSM implementation, it is appropriate that the idle
states are added to the devicetree at runtime by that implementation.

This helper function adds a platform-provided array of idle states to
the devicetree, following the SBI idle state binding. It makes some
assumptions for simplicity, but these could be relaxed if needed.

Signed-off-by: Samuel Holland <samuel at sholland.org>
---

 include/sbi_utils/fdt/fdt_fixup.h | 23 +++++++++
 lib/utils/fdt/fdt_fixup.c         | 80 +++++++++++++++++++++++++++++++
 2 files changed, 103 insertions(+)

diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
index fb076ba..cab3f0f 100644
--- a/include/sbi_utils/fdt/fdt_fixup.h
+++ b/include/sbi_utils/fdt/fdt_fixup.h
@@ -9,6 +9,29 @@
 #ifndef __FDT_FIXUP_H__
 #define __FDT_FIXUP_H__
 
+struct sbi_cpu_idle_state {
+	const char *name;
+	uint32_t suspend_param;
+	bool local_timer_stop;
+	uint32_t entry_latency_us;
+	uint32_t exit_latency_us;
+	uint32_t min_residency_us;
+	uint32_t wakeup_latency_us;
+};
+
+/**
+ * Add CPU idle states to cpu nodes in the DT
+ *
+ * Add information about CPU idle states to the devicetree. This function
+ * assumes that CPU idle states are not already present in the devicetree, and
+ * that all CPU states are equally applicable to all CPUs.
+ *
+ * @param fdt: device tree blob
+ * @param states: array of idle state descriptions, ending with empty element
+ * @return zero on success and -ve on failure
+ */
+int fdt_add_cpu_idle_states(void *dtb, const struct sbi_cpu_idle_state *state);
+
 /**
  * Fix up the CPU node in the device tree
  *
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index 41f6cbb..d9aa0b2 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -18,6 +18,86 @@
 #include <sbi_utils/fdt/fdt_pmu.h>
 #include <sbi_utils/fdt/fdt_helper.h>
 
+int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
+{
+	int cpu_node, cpus_node, err, idle_states_node;
+	uint32_t count, phandle;
+
+	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
+	if (err < 0)
+		return err;
+
+	err = fdt_find_max_phandle(fdt, &phandle);
+	phandle++;
+	if (err < 0)
+		return err;
+
+	cpus_node = fdt_path_offset(fdt, "/cpus");
+	if (cpus_node < 0)
+		return cpus_node;
+
+	/* Create the idle-states node and its child nodes. */
+	idle_states_node = fdt_add_subnode(fdt, cpus_node, "idle-states");
+	if (idle_states_node < 0)
+		return idle_states_node;
+
+	for (count = 0; state->name; count++, phandle++, state++) {
+		int idle_state_node;
+
+		idle_state_node = fdt_add_subnode(fdt, idle_states_node,
+						  state->name);
+		if (idle_state_node < 0)
+			return idle_state_node;
+
+		fdt_setprop_string(fdt, idle_state_node, "compatible",
+				   "riscv,idle-state");
+		fdt_setprop_u32(fdt, idle_state_node,
+				"riscv,sbi-suspend-param",
+				state->suspend_param);
+		if (state->local_timer_stop)
+			fdt_setprop_empty(fdt, idle_state_node,
+					  "local-timer-stop");
+		fdt_setprop_u32(fdt, idle_state_node, "entry-latency-us",
+				state->entry_latency_us);
+		fdt_setprop_u32(fdt, idle_state_node, "exit-latency-us",
+				state->exit_latency_us);
+		fdt_setprop_u32(fdt, idle_state_node, "min-residency-us",
+				state->min_residency_us);
+		if (state->wakeup_latency_us)
+			fdt_setprop_u32(fdt, idle_state_node,
+					"wakeup-latency-us",
+					state->wakeup_latency_us);
+		fdt_setprop_u32(fdt, idle_state_node, "phandle", phandle);
+	}
+
+	if (count == 0)
+		return 0;
+
+	/* Link each cpu node to the idle state nodes. */
+	fdt_for_each_subnode(cpu_node, fdt, cpus_node) {
+		const char *device_type;
+		fdt32_t *value;
+
+		/* Only process child nodes with device_type = "cpu". */
+		device_type = fdt_getprop(fdt, cpu_node, "device_type", NULL);
+		if (!device_type || strcmp(device_type, "cpu"))
+			continue;
+
+		/* Allocate space for the list of phandles. */
+		err = fdt_setprop_placeholder(fdt, cpu_node, "cpu-idle-states",
+					      count * sizeof(phandle),
+					      (void **)&value);
+		if (err < 0)
+			return err;
+
+		/* Fill in the phandles of the idle state nodes. */
+		for (uint32_t i = 0; i < count; ++i)
+			value[i] = cpu_to_fdt32(phandle - count + i);
+	}
+
+	return 0;
+}
+
 void fdt_cpu_fixup(void *fdt)
 {
 	struct sbi_domain *dom = sbi_domain_thishart_ptr();
-- 
2.37.4



From marouene.boubakri at nxp.com  Wed Dec 28 14:22:48 2022
From: marouene.boubakri at nxp.com (Marouene Boubakri)
Date: Wed, 28 Dec 2022 22:22:48 +0000
Subject: Rethink PMPs assignment #283
Message-ID: <AS1PR04MB94555484A6BE32C8F3E5C4B2FCF29@AS1PR04MB9455.eurprd04.prod.outlook.com>

Hi,

My use case is simple, I'm configuring 2 domains, called trusted and untrusted. The trusted memory region starts at 0x82000000 while the untrusted region starts at 0x80200000. The regions does not overlap.
For this use case few PMP entries are needed (considering PMP to protect OpenSBI etc).

This should work fine in platform with 16 PMP entries, however this is not the case. I noticed that running the SW in trusted domain triggers an Illegal Instruction, by debugging it turned out that, OpenSBI writes to non-existing PMP register. Its address is 0x3c0. This is pmpaddr16. However my platform has only 16 PMP entries.

By looking at the code https://github.com/riscv-software-src/opensbi/blob/master/lib/sbi/sbi_hart.c#L315-L318 The PMP is selected by shifting the desired address.

I guess this should be re-considered. 

Link to the Issue on Github. https://github.com/riscv-software-src/opensbi/issues/283

Thanks
Maro



From weiliang.lim at starfivetech.com  Wed Dec 28 18:53:22 2022
From: weiliang.lim at starfivetech.com (WeiLiang Lim)
Date: Thu, 29 Dec 2022 02:53:22 +0000
Subject: [PATCH v6 4/4] generic/starfive: Add Starfive JH7110 platform
 implementation
In-Reply-To: <e98acfe6-3fef-f7cd-fb58-001ace86bbf4@sholland.org>
References: <20221223070741.236271-1-weiliang.lim@starfivetech.com>
 <20221223070741.236271-5-weiliang.lim@starfivetech.com>
 <e98acfe6-3fef-f7cd-fb58-001ace86bbf4@sholland.org>
Message-ID: <59761d9c87f24e33adb03bdfd9889e5e@EXMBX163.cuchost.com>



> -----Original Message-----
> From: Samuel Holland <samuel at sholland.org>
> Sent: Wednesday, December 28, 2022 10:23 AM
> To: WeiLiang Lim <weiliang.lim at starfivetech.com>;
> opensbi at lists.infradead.org
> Cc: apatel at ventanamicro.com; Cheehong Ang
> <cheehong.ang at starfivetech.com>; JunLiang Tan
> <junliang.tan at starfivetech.com>
> Subject: Re: [PATCH v6 4/4] generic/starfive: Add Starfive JH7110 platform
> implementation
> 
> On 12/23/22 01:07, Wei Liang Lim wrote:
> > Add Starfive JH7110 platform implementation
> >
> > Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
> > Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
> > Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
> > ---
> >  platform/generic/Kconfig             |  4 +++
> >  platform/generic/configs/defconfig   |  1 +
> >  platform/generic/starfive/jh7110.c   | 47 ++++++++++++++++++++++++++++
> >  platform/generic/starfive/objects.mk |  6 ++++
> >  4 files changed, 58 insertions(+)
> >  create mode 100644 platform/generic/starfive/jh7110.c
> >  create mode 100644 platform/generic/starfive/objects.mk
> >
> > diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig index
> > 62c7a2d..47c10e5 100644
> > --- a/platform/generic/Kconfig
> > +++ b/platform/generic/Kconfig
> > @@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
> >  	depends on FDT_RESET && FDT_I2C
> >  	default n
> >
> > +config PLATFORM_STARFIVE_JH7110
> > +	bool "StarFive JH7110 support"
> > +	default n
> > +
> >  endif
> > diff --git a/platform/generic/configs/defconfig
> > b/platform/generic/configs/defconfig
> > index 47fca95..4b0842e 100644
> > --- a/platform/generic/configs/defconfig
> > +++ b/platform/generic/configs/defconfig
> > @@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
> > CONFIG_PLATFORM_RENESAS_RZFIVE=y
> CONFIG_PLATFORM_SIFIVE_FU540=y
> > CONFIG_PLATFORM_SIFIVE_FU740=y
> > +CONFIG_PLATFORM_STARFIVE_JH7110=y
> >  CONFIG_FDT_GPIO=y
> >  CONFIG_FDT_GPIO_SIFIVE=y
> >  CONFIG_FDT_I2C=y
> > diff --git a/platform/generic/starfive/jh7110.c
> > b/platform/generic/starfive/jh7110.c
> > new file mode 100644
> > index 0000000..70a26fe
> > --- /dev/null
> > +++ b/platform/generic/starfive/jh7110.c
> > @@ -0,0 +1,47 @@
> > +/*
> > + * SPDX-License-Identifier: BSD-2-Clause
> > + *
> > + * Copyright (c) 2022 StarFive
> > + *
> > + * Authors:
> > + *   Wei Liang Lim <weiliang.lim at starfivetech.com>
> > + */
> > +
> > +#include <libfdt.h>
> > +#include <platform_override.h>
> > +#include <sbi_utils/fdt/fdt_helper.h>
> > +
> > +static u32 selected_hartid = -1;
> > +
> > +static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
> > +				   const struct fdt_match *match) {
> > +	if (selected_hartid != -1)
> > +		return (selected_hartid == hartid);
> > +
> > +	return true;
> > +}
> > +
> > +static void starfive_jh7110_fw_init(void *fdt, const struct fdt_match
> > +*match) {
> > +	const fdt32_t *val;
> > +	int len, coff;
> > +
> > +	coff = fdt_path_offset(fdt, "/chosen");
> > +	if (-1 < coff) {
> > +		val = fdt_getprop(fdt, coff, "boot-hart-id", &len);
> 
> This looks like a brand new property. Please document it:
> 
> https://github.com/devicetree-org/dt-
> schema/blob/main/dtschema/schemas/chosen.yaml

Will do.

> 
> > +		if (val && len)
> 
> This should probably check "len >= 4" (or sizeof equivalent).
> 
> Regards,
> Samuel
> 
> > +			selected_hartid = (u32) fdt32_to_cpu(*val);
> > +	}
> > +}
> > +
> > +static const struct fdt_match starfive_jh7110_match[] = {
> > +	{ .compatible = "starfive,jh7110" },
> > +	{ },
> > +};
> > +
> > +const struct platform_override starfive_jh7110 = {
> > +	.match_table = starfive_jh7110_match,
> > +	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
> > +	.fw_init = starfive_jh7110_fw_init,
> > +};
> > diff --git a/platform/generic/starfive/objects.mk
> > b/platform/generic/starfive/objects.mk
> > new file mode 100644
> > index 0000000..0b900fb
> > --- /dev/null
> > +++ b/platform/generic/starfive/objects.mk
> > @@ -0,0 +1,6 @@
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause #
> > +
> > +carray-platform_override_modules-
> $(CONFIG_PLATFORM_STARFIVE_JH7110)
> > ++= starfive_jh7110
> > +platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) +=
> starfive/jh7110.o


From weiliang.lim at starfivetech.com  Wed Dec 28 18:56:17 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 29 Dec 2022 10:56:17 +0800
Subject: [PATCH v7 3/4] platform: generic: Allow platform_override to perform firmware init
In-Reply-To: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
References: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
Message-ID: <20221229025618.29555-4-weiliang.lim@starfivetech.com>

We add a generic platform override callback to allow platform specific firmware init.

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 21354e9..a59b06a 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -26,6 +26,7 @@ struct platform_override {
 	int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
 	int (*extensions_init)(const struct fdt_match *match,
 			       struct sbi_hart_features *hfeatures);
+	void (*fw_init)(void *fdt, const struct fdt_match *match);
 	int (*vendor_ext_check)(long extid, const struct fdt_match *match);
 	int (*vendor_ext_provider)(long extid, long funcid,
 				   const struct sbi_trap_regs *regs,
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 5fb0dc6..a34d3b0 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -85,6 +85,9 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
 
 	fw_platform_lookup_special(fdt, root_offset);
 
+	if (generic_plat && generic_plat->fw_init)
+		generic_plat->fw_init(fdt, generic_plat_match);
+
 	model = fdt_getprop(fdt, root_offset, "model", &len);
 	if (model)
 		sbi_strncpy(platform.name, model, sizeof(platform.name) - 1);
-- 
2.25.1



From weiliang.lim at starfivetech.com  Wed Dec 28 18:56:14 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 29 Dec 2022 10:56:14 +0800
Subject: [PATCH v7 0/4] generic/starfive: Enable Starfive JH7110 platform preferred cold boot HART implementation
Message-ID: <20221229025618.29555-1-weiliang.lim@starfivetech.com>

This is patchset to enable Starfive JH7110 platform preferred cold boot HART implementation.
User has the option to specify preferred cold boot HART in the device tree. If unspecified, the existing lottery mechanism will be used.

v6->v7:
- Changing if (val && len) -> if (val && len >= sizeof(fdt32_t)) in /platform/generic/starfive/jh7110.c

v5->v6:
- Minor changes on TRUE->true, FALSE->false.

v4->v5:
- Move FDT boot hart id reading from cold_boot_allowed() to fw_init()callback function.

v3->v4:
- Add implementation to allow user to specify preferred cold boot HART in the device tree. 
- If unspecified, the existing lottery mechanism will be used.

v3:
- Add Starfive JH7110 implementation.
- Anup's patches to allow platform specific selection of cold boot HART.

v2:
https://patchwork.ozlabs.org/project/opensbi/patch/20221202063845.14938-1-weiliang.lim at starfivetech.com/

v1:
https://patchwork.ozlabs.org/project/opensbi/patch/20221129052119.379830-1-weiliang.lim at starfivetech.com/

Anup Patel (2):
  lib: sbi: Allow platform to influence cold boot HART selection
  platform: generic: Allow platform_override to select cold boot HART

Wei Liang Lim (2):
  platform: generic: Allow platform_override to perform firmware init
  generic/starfive: Add Starfive JH7110 platform implementation

 include/sbi/sbi_platform.h                   | 20 +++++++++
 lib/sbi/sbi_init.c                           |  7 ++-
 platform/generic/Kconfig                     |  4 ++
 platform/generic/configs/defconfig           |  1 +
 platform/generic/include/platform_override.h |  2 +
 platform/generic/platform.c                  | 12 +++++
 platform/generic/starfive/jh7110.c           | 47 ++++++++++++++++++++
 platform/generic/starfive/objects.mk         |  6 +++
 8 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

-- 
2.25.1



From weiliang.lim at starfivetech.com  Wed Dec 28 18:56:16 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 29 Dec 2022 10:56:16 +0800
Subject: [PATCH v7 2/4] platform: generic: Allow platform_override to select cold boot HART
In-Reply-To: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
References: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
Message-ID: <20221229025618.29555-3-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add a generic platform override callback to allow platform specific
selection of cold boot HART.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 platform/generic/include/platform_override.h | 1 +
 platform/generic/platform.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index 7f1558d..21354e9 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -18,6 +18,7 @@ struct platform_override {
 	const struct fdt_match *match_table;
 	u64 (*features)(const struct fdt_match *match);
 	u64 (*tlbr_flush_limit)(const struct fdt_match *match);
+	bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
 	int (*early_init)(bool cold_boot, const struct fdt_match *match);
 	int (*final_init)(bool cold_boot, const struct fdt_match *match);
 	void (*early_exit)(const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index bfe15f0..5fb0dc6 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -122,6 +122,14 @@ fail:
 		wfi();
 }
 
+static bool generic_cold_boot_allowed(u32 hartid)
+{
+	if (generic_plat && generic_plat->cold_boot_allowed)
+		return generic_plat->cold_boot_allowed(
+						hartid, generic_plat_match);
+	return true;
+}
+
 static int generic_nascent_init(void)
 {
 	if (platform_has_mlevel_imsic)
@@ -261,6 +269,7 @@ static int generic_console_init(void)
 }
 
 const struct sbi_platform_operations platform_ops = {
+	.cold_boot_allowed	= generic_cold_boot_allowed,
 	.nascent_init		= generic_nascent_init,
 	.early_init		= generic_early_init,
 	.final_init		= generic_final_init,
-- 
2.25.1



From weiliang.lim at starfivetech.com  Wed Dec 28 18:56:15 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 29 Dec 2022 10:56:15 +0800
Subject: [PATCH v7 1/4] lib: sbi: Allow platform to influence cold boot HART selection
In-Reply-To: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
References: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
Message-ID: <20221229025618.29555-2-weiliang.lim@starfivetech.com>

From: Anup Patel <apatel at ventanamicro.com>

We add an optional cold_boot_allowed() platform callback which allows
platform support to decide which HARTs can do cold boot initialization.

If this platform callback is not available then any HART can do cold
boot initialization.

Signed-off-by: Anup Patel <apatel at ventanamicro.com>
---
 include/sbi/sbi_platform.h | 20 ++++++++++++++++++++
 lib/sbi/sbi_init.c         |  7 +++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h
index 722f27a..bd0d5ca 100644
--- a/include/sbi/sbi_platform.h
+++ b/include/sbi/sbi_platform.h
@@ -65,6 +65,9 @@ enum sbi_platform_features {
 
 /** Platform functions */
 struct sbi_platform_operations {
+	/* Check if specified HART is allowed to do cold boot */
+	bool (*cold_boot_allowed)(u32 hartid);
+
 	/* Platform nascent initialization */
 	int (*nascent_init)(void);
 
@@ -356,6 +359,23 @@ static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
 	return FALSE;
 }
 
+/**
+ * Check whether given HART is allowed to do cold boot
+ *
+ * @param plat pointer to struct sbi_platform
+ * @param hartid HART ID
+ *
+ * @return true if HART is allowed to do cold boot and false otherwise
+ */
+static inline bool sbi_platform_cold_boot_allowed(
+					const struct sbi_platform *plat,
+					u32 hartid)
+{
+	if (plat && sbi_platform_ops(plat)->cold_boot_allowed)
+		return sbi_platform_ops(plat)->cold_boot_allowed(hartid);
+	return true;
+}
+
 /**
  * Nascent (very early) initialization for current HART
  *
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..d45cee6 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -498,8 +498,11 @@ void __noreturn sbi_init(struct sbi_scratch *scratch)
 	 * HARTs which satisfy above condition.
 	 */
 
-	if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
-		coldboot = TRUE;
+	if (sbi_platform_cold_boot_allowed(plat, hartid)) {
+		if (next_mode_supported &&
+		    atomic_xchg(&coldboot_lottery, 1) == 0)
+			coldboot = true;
+	}
 
 	/*
 	 * Do platform specific nascent (very early) initialization so
-- 
2.25.1



From weiliang.lim at starfivetech.com  Wed Dec 28 18:56:18 2022
From: weiliang.lim at starfivetech.com (Wei Liang Lim)
Date: Thu, 29 Dec 2022 10:56:18 +0800
Subject: [PATCH v7 4/4] generic/starfive: Add Starfive JH7110 platform implementation
In-Reply-To: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
References: <20221229025618.29555-1-weiliang.lim@starfivetech.com>
Message-ID: <20221229025618.29555-5-weiliang.lim@starfivetech.com>

Add Starfive JH7110 platform implementation

Signed-off-by: Wei Liang Lim <weiliang.lim at starfivetech.com>
Reviewed-by: Chee Hong Ang <cheehong.ang at starfivetech.com>
Reviewed-by: Jun Liang Tan <junliang.tan at starfivetech.com>
---
 platform/generic/Kconfig             |  4 +++
 platform/generic/configs/defconfig   |  1 +
 platform/generic/starfive/jh7110.c   | 47 ++++++++++++++++++++++++++++
 platform/generic/starfive/objects.mk |  6 ++++
 4 files changed, 58 insertions(+)
 create mode 100644 platform/generic/starfive/jh7110.c
 create mode 100644 platform/generic/starfive/objects.mk

diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 62c7a2d..47c10e5 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -45,4 +45,8 @@ config PLATFORM_SIFIVE_FU740
 	depends on FDT_RESET && FDT_I2C
 	default n
 
+config PLATFORM_STARFIVE_JH7110
+	bool "StarFive JH7110 support"
+	default n
+
 endif
diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig
index 47fca95..4b0842e 100644
--- a/platform/generic/configs/defconfig
+++ b/platform/generic/configs/defconfig
@@ -3,6 +3,7 @@ CONFIG_PLATFORM_ANDES_AE350=y
 CONFIG_PLATFORM_RENESAS_RZFIVE=y
 CONFIG_PLATFORM_SIFIVE_FU540=y
 CONFIG_PLATFORM_SIFIVE_FU740=y
+CONFIG_PLATFORM_STARFIVE_JH7110=y
 CONFIG_FDT_GPIO=y
 CONFIG_FDT_GPIO_SIFIVE=y
 CONFIG_FDT_I2C=y
diff --git a/platform/generic/starfive/jh7110.c b/platform/generic/starfive/jh7110.c
new file mode 100644
index 0000000..0eb60b2
--- /dev/null
+++ b/platform/generic/starfive/jh7110.c
@@ -0,0 +1,47 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 StarFive
+ *
+ * Authors:
+ *   Wei Liang Lim <weiliang.lim at starfivetech.com>
+ */
+
+#include <libfdt.h>
+#include <platform_override.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+static u32 selected_hartid = -1;
+
+static bool starfive_jh7110_cold_boot_allowed(u32 hartid,
+				   const struct fdt_match *match)
+{
+	if (selected_hartid != -1)
+		return (selected_hartid == hartid);
+
+	return true;
+}
+
+static void starfive_jh7110_fw_init(void *fdt, const struct fdt_match *match)
+{
+	const fdt32_t *val;
+	int len, coff;
+
+	coff = fdt_path_offset(fdt, "/chosen");
+	if (-1 < coff) {
+		val = fdt_getprop(fdt, coff, "boot-hart-id", &len);
+		if (val && len >= sizeof(fdt32_t))
+			selected_hartid = (u32) fdt32_to_cpu(*val);
+	}
+}
+
+static const struct fdt_match starfive_jh7110_match[] = {
+	{ .compatible = "starfive,jh7110" },
+	{ },
+};
+
+const struct platform_override starfive_jh7110 = {
+	.match_table = starfive_jh7110_match,
+	.cold_boot_allowed = starfive_jh7110_cold_boot_allowed,
+	.fw_init = starfive_jh7110_fw_init,
+};
diff --git a/platform/generic/starfive/objects.mk b/platform/generic/starfive/objects.mk
new file mode 100644
index 0000000..0b900fb
--- /dev/null
+++ b/platform/generic/starfive/objects.mk
@@ -0,0 +1,6 @@
+#
+# SPDX-License-Identifier: BSD-2-Clause
+#
+
+carray-platform_override_modules-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive_jh7110
+platform-objs-$(CONFIG_PLATFORM_STARFIVE_JH7110) += starfive/jh7110.o
-- 
2.25.1



From peterlin at andestech.com  Thu Dec 29 04:33:04 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Thu, 29 Dec 2022 12:33:04 +0000
Subject: [PATCH 1/2] lib: utils: Add fdt_add_cpu_idle_states() helper
 function
In-Reply-To: <20221228191125.37584-1-samuel@sholland.org>
References: <20221228191125.37584-1-samuel@sholland.org>
Message-ID: <Y62JAIU/VBM/jpV+@APC323>

Hi Samuel,

On Wed, Dec 28, 2022 at 01:11:23PM -0600, Samuel Holland wrote:
> Since the availability and latency properties of CPU idle states depend
> on the specific SBI HSM implementation, it is appropriate that the idle
> states are added to the devicetree at runtime by that implementation.
> 
> This helper function adds a platform-provided array of idle states to
> the devicetree, following the SBI idle state binding. It makes some
> assumptions for simplicity, but these could be relaxed if needed.
> 
> Signed-off-by: Samuel Holland <samuel at sholland.org>
> ---
> 
>  include/sbi_utils/fdt/fdt_fixup.h | 23 +++++++++
>  lib/utils/fdt/fdt_fixup.c         | 80 +++++++++++++++++++++++++++++++
>  2 files changed, 103 insertions(+)
> 
> diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
> index fb076ba..cab3f0f 100644
> --- a/include/sbi_utils/fdt/fdt_fixup.h
> +++ b/include/sbi_utils/fdt/fdt_fixup.h
> @@ -9,6 +9,29 @@
>  #ifndef __FDT_FIXUP_H__
>  #define __FDT_FIXUP_H__
>  
> +struct sbi_cpu_idle_state {
> +	const char *name;
> +	uint32_t suspend_param;
> +	bool local_timer_stop;
> +	uint32_t entry_latency_us;
> +	uint32_t exit_latency_us;
> +	uint32_t min_residency_us;
> +	uint32_t wakeup_latency_us;
> +};
> +
> +/**
> + * Add CPU idle states to cpu nodes in the DT
> + *
> + * Add information about CPU idle states to the devicetree. This function
> + * assumes that CPU idle states are not already present in the devicetree, and
> + * that all CPU states are equally applicable to all CPUs.
> + *
> + * @param fdt: device tree blob
> + * @param states: array of idle state descriptions, ending with empty element
> + * @return zero on success and -ve on failure
> + */
> +int fdt_add_cpu_idle_states(void *dtb, const struct sbi_cpu_idle_state *state);
> +
>  /**
>   * Fix up the CPU node in the device tree
>   *
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index 41f6cbb..d9aa0b2 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -18,6 +18,86 @@
>  #include <sbi_utils/fdt/fdt_pmu.h>
>  #include <sbi_utils/fdt/fdt_helper.h>
>  
> +int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
> +{
> +	int cpu_node, cpus_node, err, idle_states_node;
> +	uint32_t count, phandle;
> +
> +	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
> +	if (err < 0)
> +		return err;
> +
> +	err = fdt_find_max_phandle(fdt, &phandle);
> +	phandle++;
> +	if (err < 0)
> +		return err;
> +
> +	cpus_node = fdt_path_offset(fdt, "/cpus");
> +	if (cpus_node < 0)
> +		return cpus_node;
> +
> +	/* Create the idle-states node and its child nodes. */
> +	idle_states_node = fdt_add_subnode(fdt, cpus_node, "idle-states");
> +	if (idle_states_node < 0)
> +		return idle_states_node;

It breaks platform final init when the ?idle-states? already exists:

   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

init_coldboot: platform final init failed (error -2)

The error code comes from fdt_add_subnode_namelen():
https://github.com/riscv-software-src/opensbi/blob/v1.2/lib/utils/libfdt/fdt_rw.c#L347

should it return 0 here?

Best regards,
Peter Lin


From samuel at sholland.org  Wed Dec 28 21:40:23 2022
From: samuel at sholland.org (Samuel Holland)
Date: Wed, 28 Dec 2022 23:40:23 -0600
Subject: [PATCH 1/2] lib: utils: Add fdt_add_cpu_idle_states() helper
 function
In-Reply-To: <Y62JAIU/VBM/jpV+@APC323>
References: <20221228191125.37584-1-samuel@sholland.org>
 <Y62JAIU/VBM/jpV+@APC323>
Message-ID: <6f14e6af-058c-58d1-bd56-af68814b8463@sholland.org>

On 12/29/22 06:33, Yu-Chien Peter Lin wrote:
> Hi Samuel,
> 
> On Wed, Dec 28, 2022 at 01:11:23PM -0600, Samuel Holland wrote:
>> Since the availability and latency properties of CPU idle states depend
>> on the specific SBI HSM implementation, it is appropriate that the idle
>> states are added to the devicetree at runtime by that implementation.
>>
>> This helper function adds a platform-provided array of idle states to
>> the devicetree, following the SBI idle state binding. It makes some
>> assumptions for simplicity, but these could be relaxed if needed.
>>
>> Signed-off-by: Samuel Holland <samuel at sholland.org>
>> ---
>>
>>  include/sbi_utils/fdt/fdt_fixup.h | 23 +++++++++
>>  lib/utils/fdt/fdt_fixup.c         | 80 +++++++++++++++++++++++++++++++
>>  2 files changed, 103 insertions(+)
>>
>> diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
>> index fb076ba..cab3f0f 100644
>> --- a/include/sbi_utils/fdt/fdt_fixup.h
>> +++ b/include/sbi_utils/fdt/fdt_fixup.h
>> @@ -9,6 +9,29 @@
>>  #ifndef __FDT_FIXUP_H__
>>  #define __FDT_FIXUP_H__
>>  
>> +struct sbi_cpu_idle_state {
>> +	const char *name;
>> +	uint32_t suspend_param;
>> +	bool local_timer_stop;
>> +	uint32_t entry_latency_us;
>> +	uint32_t exit_latency_us;
>> +	uint32_t min_residency_us;
>> +	uint32_t wakeup_latency_us;
>> +};
>> +
>> +/**
>> + * Add CPU idle states to cpu nodes in the DT
>> + *
>> + * Add information about CPU idle states to the devicetree. This function
>> + * assumes that CPU idle states are not already present in the devicetree, and
>> + * that all CPU states are equally applicable to all CPUs.
>> + *
>> + * @param fdt: device tree blob
>> + * @param states: array of idle state descriptions, ending with empty element
>> + * @return zero on success and -ve on failure
>> + */
>> +int fdt_add_cpu_idle_states(void *dtb, const struct sbi_cpu_idle_state *state);
>> +
>>  /**
>>   * Fix up the CPU node in the device tree
>>   *
>> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
>> index 41f6cbb..d9aa0b2 100644
>> --- a/lib/utils/fdt/fdt_fixup.c
>> +++ b/lib/utils/fdt/fdt_fixup.c
>> @@ -18,6 +18,86 @@
>>  #include <sbi_utils/fdt/fdt_pmu.h>
>>  #include <sbi_utils/fdt/fdt_helper.h>
>>  
>> +int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
>> +{
>> +	int cpu_node, cpus_node, err, idle_states_node;
>> +	uint32_t count, phandle;
>> +
>> +	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
>> +	if (err < 0)
>> +		return err;
>> +
>> +	err = fdt_find_max_phandle(fdt, &phandle);
>> +	phandle++;
>> +	if (err < 0)
>> +		return err;
>> +
>> +	cpus_node = fdt_path_offset(fdt, "/cpus");
>> +	if (cpus_node < 0)
>> +		return cpus_node;
>> +
>> +	/* Create the idle-states node and its child nodes. */
>> +	idle_states_node = fdt_add_subnode(fdt, cpus_node, "idle-states");
>> +	if (idle_states_node < 0)
>> +		return idle_states_node;
> 
> It breaks platform final init when the ?idle-states? already exists:

Right, that is a documented limitation. I would expect there to be a
single source of idle state information -- wherever the HSM
implementation is. So my suggestion would be to remove idle-states from
the static devicetree if you plan to use this function. If that is not
desired, could you explain your scenario in a bit more detail?

Regards,
Samuel



From peterlin at andestech.com  Thu Dec 29 07:42:35 2022
From: peterlin at andestech.com (Yu-Chien Peter Lin)
Date: Thu, 29 Dec 2022 15:42:35 +0000
Subject: [PATCH 1/2] lib: utils: Add fdt_add_cpu_idle_states() helper
 function
In-Reply-To: <6f14e6af-058c-58d1-bd56-af68814b8463@sholland.org>
References: <20221228191125.37584-1-samuel@sholland.org>
 <Y62JAIU/VBM/jpV+@APC323>
 <6f14e6af-058c-58d1-bd56-af68814b8463@sholland.org>
Message-ID: <Y621a6aG8R56X7Zx@APC323>

On Wed, Dec 28, 2022 at 11:40:23PM -0600, Samuel Holland wrote:
> On 12/29/22 06:33, Yu-Chien Peter Lin wrote:
> > Hi Samuel,
> > 
> > On Wed, Dec 28, 2022 at 01:11:23PM -0600, Samuel Holland wrote:
> >> Since the availability and latency properties of CPU idle states depend
> >> on the specific SBI HSM implementation, it is appropriate that the idle
> >> states are added to the devicetree at runtime by that implementation.
> >>
> >> This helper function adds a platform-provided array of idle states to
> >> the devicetree, following the SBI idle state binding. It makes some
> >> assumptions for simplicity, but these could be relaxed if needed.
> >>
> >> Signed-off-by: Samuel Holland <samuel at sholland.org>
> >> ---
> >>
> >>  include/sbi_utils/fdt/fdt_fixup.h | 23 +++++++++
> >>  lib/utils/fdt/fdt_fixup.c         | 80 +++++++++++++++++++++++++++++++
> >>  2 files changed, 103 insertions(+)
> >>
> >> diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
> >> index fb076ba..cab3f0f 100644
> >> --- a/include/sbi_utils/fdt/fdt_fixup.h
> >> +++ b/include/sbi_utils/fdt/fdt_fixup.h
> >> @@ -9,6 +9,29 @@
> >>  #ifndef __FDT_FIXUP_H__
> >>  #define __FDT_FIXUP_H__
> >>  
> >> +struct sbi_cpu_idle_state {
> >> +	const char *name;
> >> +	uint32_t suspend_param;
> >> +	bool local_timer_stop;
> >> +	uint32_t entry_latency_us;
> >> +	uint32_t exit_latency_us;
> >> +	uint32_t min_residency_us;
> >> +	uint32_t wakeup_latency_us;
> >> +};
> >> +
> >> +/**
> >> + * Add CPU idle states to cpu nodes in the DT
> >> + *
> >> + * Add information about CPU idle states to the devicetree. This function
> >> + * assumes that CPU idle states are not already present in the devicetree, and
> >> + * that all CPU states are equally applicable to all CPUs.
> >> + *
> >> + * @param fdt: device tree blob
> >> + * @param states: array of idle state descriptions, ending with empty element
> >> + * @return zero on success and -ve on failure
> >> + */
> >> +int fdt_add_cpu_idle_states(void *dtb, const struct sbi_cpu_idle_state *state);
> >> +
> >>  /**
> >>   * Fix up the CPU node in the device tree
> >>   *
> >> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> >> index 41f6cbb..d9aa0b2 100644
> >> --- a/lib/utils/fdt/fdt_fixup.c
> >> +++ b/lib/utils/fdt/fdt_fixup.c
> >> @@ -18,6 +18,86 @@
> >>  #include <sbi_utils/fdt/fdt_pmu.h>
> >>  #include <sbi_utils/fdt/fdt_helper.h>
> >>  
> >> +int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
> >> +{
> >> +	int cpu_node, cpus_node, err, idle_states_node;
> >> +	uint32_t count, phandle;
> >> +
> >> +	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
> >> +	if (err < 0)
> >> +		return err;
> >> +
> >> +	err = fdt_find_max_phandle(fdt, &phandle);
> >> +	phandle++;
> >> +	if (err < 0)
> >> +		return err;
> >> +
> >> +	cpus_node = fdt_path_offset(fdt, "/cpus");
> >> +	if (cpus_node < 0)
> >> +		return cpus_node;
> >> +
> >> +	/* Create the idle-states node and its child nodes. */
> >> +	idle_states_node = fdt_add_subnode(fdt, cpus_node, "idle-states");
> >> +	if (idle_states_node < 0)
> >> +		return idle_states_node;
> > 
> > It breaks platform final init when the ?idle-states? already exists:
> 
> Right, that is a documented limitation. I would expect there to be a
> single source of idle state information -- wherever the HSM
> implementation is. So my suggestion would be to remove idle-states from
> the static devicetree if you plan to use this function. If that is not
> desired, could you explain your scenario in a bit more detail?

Understood, then I have no more questions.

Thanks,
Peter Lin

> 
> Regards,
> Samuel
> 


From hchauhan at ventanamicro.com  Thu Dec 29 11:11:11 2022
From: hchauhan at ventanamicro.com (Himanshu Chauhan)
Date: Fri, 30 Dec 2022 00:41:11 +0530
Subject: [PATCH] lib: sbi: Check pmp index for overflow before programming
Message-ID: <20221229191111.29041-1-hchauhan@ventanamicro.com>

Check the current pmp index if it overflows the number of
pmp entries present. If so, skip the programming but
print debug information about the region, domain and
the last index of pmp programmed.

Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 5447c52..2782c0d 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -313,9 +313,17 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
 			pmp_flags |= PMP_L;
 
 		pmp_addr =  reg->base >> PMP_SHIFT;
-		if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
+		if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
+			if (pmp_idx+1 >= pmp_count) {
+				sbi_printf("Cannot program pmp region: 0x%lx (order: 0x%lx) for domain %s.\n",
+					   reg->base, reg->order, dom->name);
+				sbi_printf("Reason: No free PMP entry left. "
+					   "Number of PMP entries: %d Last PMP Index written: %d\n",
+					   pmp_count, pmp_idx);
+				break;
+			}
 			pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
-		else {
+		} else {
 			sbi_printf("Can not configure pmp for domain %s", dom->name);
 			sbi_printf(" because memory region address %lx or size %lx is not in range\n",
 				    reg->base, reg->order);
-- 
2.39.0



From bmeng at tinylab.org  Thu Dec 29 20:26:11 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Fri, 30 Dec 2022 12:26:11 +0800
Subject: [PATCH] lib: sbi_domain: Avoid overwriting coldboot hart's scratch->arg1
Message-ID: <20221230042611.1966361-1-bmeng@tinylab.org>

In sbi_domain_finalize(), when locating the coldboot hart's domain,
the coldboot hart's scratch->arg1 will be overwritten by the domain
configuration. scratch->arg1 holds the FDT address of the coldboot
hart, and in later boot process OpenSBI codes still read the FDT
here and there, which leads to a crash.

To fix this, we save the next booting stage arg1 for the coldboot
domain instance for the caller to use later.

Resolves: https://github.com/riscv-software-src/opensbi/issues/281
Fixes: b1678af210dc ("lib: sbi: Add initial domain support")
Reported-by: Marouene Boubakri <marouene.boubakri at nxp.com>
Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 include/sbi/sbi_domain.h |  3 ++-
 lib/sbi/sbi_domain.c     | 15 +++++++++++++--
 lib/sbi/sbi_init.c       |  7 ++++++-
 3 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
index 5553d21..0370d48 100644
--- a/include/sbi/sbi_domain.h
+++ b/include/sbi/sbi_domain.h
@@ -195,7 +195,8 @@ int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
 			   unsigned long align, unsigned long region_flags);
 
 /** Finalize domain tables and startup non-root domains */
-int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid);
+int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid,
+			bool *coldboot_domain, unsigned long *next_arg1);
 
 /** Initialize domains */
 int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid);
diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
index 3205595..bdef99f 100644
--- a/lib/sbi/sbi_domain.c
+++ b/lib/sbi/sbi_domain.c
@@ -552,12 +552,14 @@ int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
 	return 0;
 }
 
-int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
+int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid,
+			bool *coldboot_domain, unsigned long *next_arg1)
 {
 	int rc;
 	u32 i, dhart;
 	struct sbi_domain *dom;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	*coldboot_domain = false;
 
 	/* Initialize and populate domains for the platform */
 	rc = sbi_platform_domains_init(plat);
@@ -589,7 +591,16 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
 		if (dhart == cold_hartid) {
 			scratch->next_addr = dom->next_addr;
 			scratch->next_mode = dom->next_mode;
-			scratch->next_arg1 = dom->next_arg1;
+			/*
+			 * We cannot overwrite the scratch->next_arg1 here
+			 * as it holds the FDT address for the coldboot hart.
+			 *
+			 * Instead, we save the next booting stage arg1 for
+			 * the coldboot domain instance for the caller to
+			 * use later.
+			 */
+			*coldboot_domain = true;
+			*next_arg1 = dom->next_arg1;
 		} else {
 			rc = sbi_hsm_hart_start(scratch, NULL, dhart,
 						dom->next_addr,
diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
index a8500e5..85d211b 100644
--- a/lib/sbi/sbi_init.c
+++ b/lib/sbi/sbi_init.c
@@ -240,6 +240,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	int rc;
 	unsigned long *init_count;
 	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
+	bool coldboot_domain;
+	unsigned long next_arg1;
 
 	/* Note: This has to be first thing in coldboot init sequence */
 	rc = sbi_scratch_init(scratch);
@@ -314,7 +316,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	 * Note: Finalize domains before HART PMP configuration so
 	 * that we use correct domain for configuring PMP.
 	 */
-	rc = sbi_domain_finalize(scratch, hartid);
+	rc = sbi_domain_finalize(scratch, hartid, &coldboot_domain,
+				 &next_arg1);
 	if (rc) {
 		sbi_printf("%s: domain finalize failed (error %d)\n",
 			   __func__, rc);
@@ -351,6 +354,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
 	(*init_count)++;
 
 	sbi_hsm_prepare_next_jump(scratch, hartid);
+	if (coldboot_domain)
+		scratch->next_arg1 = next_arg1;
 	sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
 			     scratch->next_mode, FALSE);
 }
-- 
2.34.1



From bmeng at tinylab.org  Thu Dec 29 21:07:23 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Fri, 30 Dec 2022 13:07:23 +0800
Subject: [PATCH] lib: sbi_hsm: Rename 'priv' argument to 'arg1'
Message-ID: <20221230050723.1966623-1-bmeng@tinylab.org>

'priv' argument of sbi_hsm_hart_start() and sbi_hsm_hart_suspend()
may mislead people to think it stands for 'privilege mode', but it
is not. Change it to 'arg1' to clearly indicate the a1 register.

Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 include/sbi/sbi_hsm.h | 4 ++--
 lib/sbi/sbi_hsm.c     | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/sbi/sbi_hsm.h b/include/sbi/sbi_hsm.h
index d6cc468..c2a728a 100644
--- a/include/sbi/sbi_hsm.h
+++ b/include/sbi/sbi_hsm.h
@@ -59,12 +59,12 @@ void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch);
 
 int sbi_hsm_hart_start(struct sbi_scratch *scratch,
 		       const struct sbi_domain *dom,
-		       u32 hartid, ulong saddr, ulong smode, ulong priv);
+		       u32 hartid, ulong saddr, ulong smode, ulong arg1);
 int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow);
 void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch);
 void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch);
 int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
-			 ulong raddr, ulong rmode, ulong priv);
+			 ulong raddr, ulong rmode, ulong arg1);
 int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid);
 int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
 				    ulong hbase, ulong *out_hmask);
diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
index 836008f..c0a5505 100644
--- a/lib/sbi/sbi_hsm.c
+++ b/lib/sbi/sbi_hsm.c
@@ -248,7 +248,7 @@ fail_exit:
 
 int sbi_hsm_hart_start(struct sbi_scratch *scratch,
 		       const struct sbi_domain *dom,
-		       u32 hartid, ulong saddr, ulong smode, ulong priv)
+		       u32 hartid, ulong saddr, ulong smode, ulong arg1)
 {
 	unsigned long init_count;
 	unsigned int hstate;
@@ -281,7 +281,7 @@ int sbi_hsm_hart_start(struct sbi_scratch *scratch,
 		return SBI_EINVAL;
 
 	init_count = sbi_init_count(hartid);
-	rscratch->next_arg1 = priv;
+	rscratch->next_arg1 = arg1;
 	rscratch->next_addr = saddr;
 	rscratch->next_mode = smode;
 
@@ -402,7 +402,7 @@ void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch)
 }
 
 int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
-			 ulong raddr, ulong rmode, ulong priv)
+			 ulong raddr, ulong rmode, ulong arg1)
 {
 	int oldstate, ret;
 	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
@@ -433,7 +433,7 @@ int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
 	}
 
 	/* Save the resume address and resume mode */
-	scratch->next_arg1 = priv;
+	scratch->next_arg1 = arg1;
 	scratch->next_addr = raddr;
 	scratch->next_mode = rmode;
 
-- 
2.34.1



From bmeng at tinylab.org  Thu Dec 29 21:07:51 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Fri, 30 Dec 2022 13:07:51 +0800
Subject: [PATCH] docs: domain_support: Use capital letter for privilege modes
Message-ID: <20221230050751.1966673-1-bmeng@tinylab.org>

The RISC-V convention for the privilege mode is capital letter, like
'M-mode', instead of 'm-mode'.

Signed-off-by: Bin Meng <bmeng at tinylab.org>
---

 docs/domain_support.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/domain_support.md b/docs/domain_support.md
index 8963b57..c909d4a 100644
--- a/docs/domain_support.md
+++ b/docs/domain_support.md
@@ -161,7 +161,7 @@ The DT properties of a domain instance DT node are as follows:
   and access permissions for the domain instance. Each list entry is a pair
   of DT node phandle and access permissions. The access permissions are
   represented as a 32bit bitmask having bits: **readable** (BIT[0]),
-  **writeable** (BIT[1]), **executable** (BIT[2]), and **m-mode** (BIT[3]).
+  **writeable** (BIT[1]), **executable** (BIT[2]), and **M-mode** (BIT[3]).
 * **boot-hart** (Optional) - The DT node phandle of the HART booting the
   domain instance. If coldboot HART is assigned to the domain instance then
   this DT property is ignored and the coldboot HART is assumed to be the
@@ -180,7 +180,7 @@ The DT properties of a domain instance DT node are as follows:
   is used as default value.
 * **next-mode** (Optional) - The 32 bit next booting stage mode for the
   domain instance. The possible values of this DT property are: **0x1**
-  (s-mode), and **0x0** (u-mode). If this DT property is not available
+  (S-mode), and **0x0** (U-mode). If this DT property is not available
   and coldboot HART is not assigned to the domain instance then **0x1**
   is used as default value. If this DT property is not available and
   coldboot HART is assigned to the domain instance then **next booting
-- 
2.34.1



From samuel at sholland.org  Fri Dec 30 08:26:50 2022
From: samuel at sholland.org (Samuel Holland)
Date: Fri, 30 Dec 2022 10:26:50 -0600
Subject: [PATCH] lib: sbi_domain: Avoid overwriting coldboot hart's
 scratch->arg1
In-Reply-To: <20221230042611.1966361-1-bmeng@tinylab.org>
References: <20221230042611.1966361-1-bmeng@tinylab.org>
Message-ID: <776535ea-e99a-f887-2825-2912aa3b7f30@sholland.org>

Hi Bin,

On 12/29/22 22:26, Bin Meng wrote:
> In sbi_domain_finalize(), when locating the coldboot hart's domain,
> the coldboot hart's scratch->arg1 will be overwritten by the domain
> configuration. scratch->arg1 holds the FDT address of the coldboot
> hart, and in later boot process OpenSBI codes still read the FDT
> here and there, which leads to a crash.

It sounds to me like the bug is in fdt_get_address(), not here. We
should save off the FDT address in some global variable, and not
continue getting it from next_arg1. Then there is no problem updating
next_arg1 from the domain configuration.

Regards,
Samuel

> To fix this, we save the next booting stage arg1 for the coldboot
> domain instance for the caller to use later.
> 
> Resolves: https://github.com/riscv-software-src/opensbi/issues/281
> Fixes: b1678af210dc ("lib: sbi: Add initial domain support")
> Reported-by: Marouene Boubakri <marouene.boubakri at nxp.com>
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---
> 
>  include/sbi/sbi_domain.h |  3 ++-
>  lib/sbi/sbi_domain.c     | 15 +++++++++++++--
>  lib/sbi/sbi_init.c       |  7 ++++++-
>  3 files changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h
> index 5553d21..0370d48 100644
> --- a/include/sbi/sbi_domain.h
> +++ b/include/sbi/sbi_domain.h
> @@ -195,7 +195,8 @@ int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
>  			   unsigned long align, unsigned long region_flags);
>  
>  /** Finalize domain tables and startup non-root domains */
> -int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid);
> +int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid,
> +			bool *coldboot_domain, unsigned long *next_arg1);
>  
>  /** Initialize domains */
>  int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid);
> diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c
> index 3205595..bdef99f 100644
> --- a/lib/sbi/sbi_domain.c
> +++ b/lib/sbi/sbi_domain.c
> @@ -552,12 +552,14 @@ int sbi_domain_root_add_memrange(unsigned long addr, unsigned long size,
>  	return 0;
>  }
>  
> -int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
> +int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid,
> +			bool *coldboot_domain, unsigned long *next_arg1)
>  {
>  	int rc;
>  	u32 i, dhart;
>  	struct sbi_domain *dom;
>  	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
> +	*coldboot_domain = false;
>  
>  	/* Initialize and populate domains for the platform */
>  	rc = sbi_platform_domains_init(plat);
> @@ -589,7 +591,16 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
>  		if (dhart == cold_hartid) {
>  			scratch->next_addr = dom->next_addr;
>  			scratch->next_mode = dom->next_mode;
> -			scratch->next_arg1 = dom->next_arg1;
> +			/*
> +			 * We cannot overwrite the scratch->next_arg1 here
> +			 * as it holds the FDT address for the coldboot hart.
> +			 *
> +			 * Instead, we save the next booting stage arg1 for
> +			 * the coldboot domain instance for the caller to
> +			 * use later.
> +			 */
> +			*coldboot_domain = true;
> +			*next_arg1 = dom->next_arg1;
>  		} else {
>  			rc = sbi_hsm_hart_start(scratch, NULL, dhart,
>  						dom->next_addr,
> diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c
> index a8500e5..85d211b 100644
> --- a/lib/sbi/sbi_init.c
> +++ b/lib/sbi/sbi_init.c
> @@ -240,6 +240,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
>  	int rc;
>  	unsigned long *init_count;
>  	const struct sbi_platform *plat = sbi_platform_ptr(scratch);
> +	bool coldboot_domain;
> +	unsigned long next_arg1;
>  
>  	/* Note: This has to be first thing in coldboot init sequence */
>  	rc = sbi_scratch_init(scratch);
> @@ -314,7 +316,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
>  	 * Note: Finalize domains before HART PMP configuration so
>  	 * that we use correct domain for configuring PMP.
>  	 */
> -	rc = sbi_domain_finalize(scratch, hartid);
> +	rc = sbi_domain_finalize(scratch, hartid, &coldboot_domain,
> +				 &next_arg1);
>  	if (rc) {
>  		sbi_printf("%s: domain finalize failed (error %d)\n",
>  			   __func__, rc);
> @@ -351,6 +354,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
>  	(*init_count)++;
>  
>  	sbi_hsm_prepare_next_jump(scratch, hartid);
> +	if (coldboot_domain)
> +		scratch->next_arg1 = next_arg1;
>  	sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
>  			     scratch->next_mode, FALSE);
>  }



From samuel at sholland.org  Fri Dec 30 08:29:42 2022
From: samuel at sholland.org (Samuel Holland)
Date: Fri, 30 Dec 2022 10:29:42 -0600
Subject: [PATCH] lib: sbi_hsm: Rename 'priv' argument to 'arg1'
In-Reply-To: <20221230050723.1966623-1-bmeng@tinylab.org>
References: <20221230050723.1966623-1-bmeng@tinylab.org>
Message-ID: <b13f4620-c700-fc58-0ef2-9e60486ee4a5@sholland.org>

On 12/29/22 23:07, Bin Meng wrote:
> 'priv' argument of sbi_hsm_hart_start() and sbi_hsm_hart_suspend()
> may mislead people to think it stands for 'privilege mode', but it
> is not. Change it to 'arg1' to clearly indicate the a1 register.
> 
> Signed-off-by: Bin Meng <bmeng at tinylab.org>
> ---
> 
>  include/sbi/sbi_hsm.h | 4 ++--
>  lib/sbi/sbi_hsm.c     | 8 ++++----
>  2 files changed, 6 insertions(+), 6 deletions(-)

Reviewed-by: Samuel Holland <samuel at sholland.org>
Tested-by: Samuel Holland <samuel at sholland.org>

> diff --git a/include/sbi/sbi_hsm.h b/include/sbi/sbi_hsm.h
> index d6cc468..c2a728a 100644
> --- a/include/sbi/sbi_hsm.h
> +++ b/include/sbi/sbi_hsm.h
> @@ -59,12 +59,12 @@ void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch);
>  
>  int sbi_hsm_hart_start(struct sbi_scratch *scratch,
>  		       const struct sbi_domain *dom,
> -		       u32 hartid, ulong saddr, ulong smode, ulong priv);
> +		       u32 hartid, ulong saddr, ulong smode, ulong arg1);
>  int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow);
>  void sbi_hsm_hart_resume_start(struct sbi_scratch *scratch);
>  void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch);
>  int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
> -			 ulong raddr, ulong rmode, ulong priv);
> +			 ulong raddr, ulong rmode, ulong arg1);
>  int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid);
>  int sbi_hsm_hart_interruptible_mask(const struct sbi_domain *dom,
>  				    ulong hbase, ulong *out_hmask);
> diff --git a/lib/sbi/sbi_hsm.c b/lib/sbi/sbi_hsm.c
> index 836008f..c0a5505 100644
> --- a/lib/sbi/sbi_hsm.c
> +++ b/lib/sbi/sbi_hsm.c
> @@ -248,7 +248,7 @@ fail_exit:
>  
>  int sbi_hsm_hart_start(struct sbi_scratch *scratch,
>  		       const struct sbi_domain *dom,
> -		       u32 hartid, ulong saddr, ulong smode, ulong priv)
> +		       u32 hartid, ulong saddr, ulong smode, ulong arg1)
>  {
>  	unsigned long init_count;
>  	unsigned int hstate;
> @@ -281,7 +281,7 @@ int sbi_hsm_hart_start(struct sbi_scratch *scratch,
>  		return SBI_EINVAL;
>  
>  	init_count = sbi_init_count(hartid);
> -	rscratch->next_arg1 = priv;
> +	rscratch->next_arg1 = arg1;
>  	rscratch->next_addr = saddr;
>  	rscratch->next_mode = smode;
>  
> @@ -402,7 +402,7 @@ void sbi_hsm_hart_resume_finish(struct sbi_scratch *scratch)
>  }
>  
>  int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
> -			 ulong raddr, ulong rmode, ulong priv)
> +			 ulong raddr, ulong rmode, ulong arg1)
>  {
>  	int oldstate, ret;
>  	const struct sbi_domain *dom = sbi_domain_thishart_ptr();
> @@ -433,7 +433,7 @@ int sbi_hsm_hart_suspend(struct sbi_scratch *scratch, u32 suspend_type,
>  	}
>  
>  	/* Save the resume address and resume mode */
> -	scratch->next_arg1 = priv;
> +	scratch->next_arg1 = arg1;
>  	scratch->next_addr = raddr;
>  	scratch->next_mode = rmode;
>  



From bmeng at tinylab.org  Fri Dec 30 17:40:38 2022
From: bmeng at tinylab.org (Bin Meng)
Date: Sat, 31 Dec 2022 01:40:38 +0000
Subject: [PATCH] lib: sbi_domain: Avoid overwriting coldboot hart's scratch->arg1
In-Reply-To: <776535ea-e99a-f887-2825-2912aa3b7f30@sholland.org>
References: <20221230042611.1966361-1-bmeng@tinylab.org>
 <776535ea-e99a-f887-2825-2912aa3b7f30@sholland.org>
Message-ID: <em0eee6780-8a4c-4dfc-b8ea-7ea07a83f6b5@a9022134.com>

Hi Samuel,

On Sat, Dec 31, 2022 at 12:38 AM Samuel Holland <samuel at sholland.org> 
wrote:
 >
 > Hi Bin,
 >
 > On 12/29/22 22:26, Bin Meng wrote:
 > > In sbi_domain_finalize(), when locating the coldboot hart's domain,
 > > the coldboot hart's scratch->arg1 will be overwritten by the domain
 > > configuration. scratch->arg1 holds the FDT address of the coldboot
 > > hart, and in later boot process OpenSBI codes still read the FDT
 > > here and there, which leads to a crash.
 >
 > It sounds to me like the bug is in fdt_get_address(), not here. We
 > should save off the FDT address in some global variable, and not
 > continue getting it from next_arg1. Then there is no problem updating
 > next_arg1 from the domain configuration.
 >

Yep, I thought about this and felt that might change a lot of places. I 
will have a try in v2.

Regards,
Bin


From bmeng.cn at gmail.com  Fri Dec 30 18:10:16 2022
From: bmeng.cn at gmail.com (Bin Meng)
Date: Sat, 31 Dec 2022 10:10:16 +0800
Subject: [PATCH] lib: sbi: Check pmp index for overflow before programming
In-Reply-To: <20221229191111.29041-1-hchauhan@ventanamicro.com>
References: <20221229191111.29041-1-hchauhan@ventanamicro.com>
Message-ID: <CAEUhbmWZRJqTNV-2U+SG7P5_JrbGxVJzVP7Z7NeP=6EMc_-6hw@mail.gmail.com>

On Thu, Dec 29, 2022 at 10:51 PM Himanshu Chauhan
<hchauhan at ventanamicro.com> wrote:
>
> Check the current pmp index if it overflows the number of
> pmp entries present. If so, skip the programming but
> print debug information about the region, domain and
> the last index of pmp programmed.
>
> Signed-off-by: Himanshu Chauhan <hchauhan at ventanamicro.com>
> ---
>  lib/sbi/sbi_hart.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 5447c52..2782c0d 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -313,9 +313,17 @@ int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
>                         pmp_flags |= PMP_L;
>
>                 pmp_addr =  reg->base >> PMP_SHIFT;
> -               if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
> +               if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max) {
> +                       if (pmp_idx+1 >= pmp_count) {

This check is meaningless. There is already a check at the beginning
of the loop:

                if (pmp_count <= pmp_idx)
                        break;

> +                               sbi_printf("Cannot program pmp region: 0x%lx (order: 0x%lx) for domain %s.\n",
> +                                          reg->base, reg->order, dom->name);
> +                               sbi_printf("Reason: No free PMP entry left. "
> +                                          "Number of PMP entries: %d Last PMP Index written: %d\n",
> +                                          pmp_count, pmp_idx);
> +                               break;
> +                       }
>                         pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
> -               else {
> +               } else {
>                         sbi_printf("Can not configure pmp for domain %s", dom->name);
>                         sbi_printf(" because memory region address %lx or size %lx is not in range\n",
>                                     reg->base, reg->order);
> --

Regards,
Bin


