[PATCH v2 1/5] include: Add mstatus[h].GVA encodings

[Anup Patel]

On Thu, Aug 4, 2022 at 9:13 PM Vivian Wang <dramforever at live.com> wrote:
>
> The machine mode GVA field is in mstatus for RV64 and mstatush for RV32,
> and is available if the hypervisor extension is available. If an
> exception occurs, we may need to redirect the trap to HS-mode, in which
> case, hstatus.GVA should be set to same as the machine mode GVA bit.
>
> Add MSTATUS_GVA for RV64, MSTATUSH_GVA for RV32, and their SHIFT
> encodings. The SHIFT index is helpful in assembly code, since field
> extraction can be implemented in only one register. In pseudocode:
>
> - For RV32: gva = (mstatus >> MSTATUS_GVA_SHIFT) & 1;
> - For RV64: gva = (mstatush >> MSTATUSH_GVA_SHIFT) & 1;
>
> Signed-off-by: Vivian Wang <dramforever at live.com>
> Reviewed-by: Andrew Jones <ajones at ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/riscv_encoding.h | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 798afb7..8884301 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -38,10 +38,14 @@
>  #define MSTATUS_SXL                    _ULL(0x0000000C00000000)
>  #define MSTATUS_SBE                    _ULL(0x0000001000000000)
>  #define MSTATUS_MBE                    _ULL(0x0000002000000000)
> +#define MSTATUS_GVA                    _ULL(0x0000004000000000)
> +#define MSTATUS_GVA_SHIFT              38
>  #define MSTATUS_MPV                    _ULL(0x0000008000000000)
>  #else
>  #define MSTATUSH_SBE                   _UL(0x00000010)
>  #define MSTATUSH_MBE                   _UL(0x00000020)
> +#define MSTATUSH_GVA                   _UL(0x00000040)
> +#define MSTATUSH_GVA_SHIFT             6
>  #define MSTATUSH_MPV                   _UL(0x00000080)
>  #endif
>  #define MSTATUS32_SD                   _UL(0x80000000)
> --
> 2.37.1
>
>
> --
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