Patch "mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS" has been added to the 4.9-stable tree

[gregkh at linuxfoundation.org]

This is a note to let you know that I've just added the patch titled

    mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS

to the 4.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable at vger.kernel.org> know about it.


>From foo at baz Thu Nov  4 09:33:49 AM CET 2021
From: Florian Fainelli <f.fainelli at gmail.com>
Date: Wed,  3 Nov 2021 13:57:13 -0700
Subject: mm/zsmalloc: Prepare to variable MAX_PHYSMEM_BITS
To: linux-kernel at vger.kernel.org
Cc: stable at vger.kernel.org, Greg Kroah-Hartman <gregkh at linuxfoundation.org>, Sasha Levin <sashal at kernel.org>, "Kirill A. Shutemov" <kirill.shutemov at linux.intel.com>, Nitin Gupta <ngupta at vflare.org>, Minchan Kim <minchan at kernel.org>, Andy Lutomirski <luto at amacapital.net>, Borislav Petkov <bp at suse.de>, Linus Torvalds <torvalds at linux-foundation.org>, Peter Zijlstra <peterz at infradead.org>, Sergey Senozhatsky <sergey.senozhatsky.work at gmail.com>, Thomas Gleixner <tglx at linutronix.de>, linux-mm at kvack.org, Ingo Molnar <mingo at kernel.org>, Florian Fainelli <f.fainelli at gmail.com>, Vineet Gupta <vgupta at synopsys.com>, Russell King <linux at armlinux.org.uk>, Ralf Baechle <ralf at linux-mips.org>, Benjamin Herrenschmidt <benh at kernel.crashing.org>, Paul Mackerras <paulus at samba.org>, Michael Ellerman <mpe at ellerman.id.au>, Ingo Molnar <mingo at redhat.com>, "H. Peter Anvin" <hpa at zytor.com>, x86 at kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)), Arnd Bergmann <arnd at arndb.de>, Thomas Bogendoerfer <tsb
 ogend at alpha.franken.de>, Mike Rapoport <rppt at linux.ibm.com>, Stefan Agner <stefan at agner.ch>, linux-snps-arc at lists.infradead.org (open list:SYNOPSYS ARC ARCHITECTURE), linux-arm-kernel at lists.infradead.org (moderated list:ARM PORT), linux-mips at linux-mips.org (open list:MIPS), linuxppc-dev at lists.ozlabs.org (open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)), linux-arch at vger.kernel.org (open list:GENERIC INCLUDE/ASM HEADER FILES)
Message-ID: <20211103205714.374801-2-f.fainelli at gmail.com>

From: "Kirill A. Shutemov" <kirill.shutemov at linux.intel.com>

commit 02390b87a9459937cdb299e6b34ff33992512ec7 upstream

With boot-time switching between paging mode we will have variable
MAX_PHYSMEM_BITS.

Let's use the maximum variable possible for CONFIG_X86_5LEVEL=y
configuration to define zsmalloc data structures.

The patch introduces MAX_POSSIBLE_PHYSMEM_BITS to cover such case.
It also suits well to handle PAE special case.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov at linux.intel.com>
Reviewed-by: Nitin Gupta <ngupta at vflare.org>
Acked-by: Minchan Kim <minchan at kernel.org>
Cc: Andy Lutomirski <luto at amacapital.net>
Cc: Borislav Petkov <bp at suse.de>
Cc: Linus Torvalds <torvalds at linux-foundation.org>
Cc: Peter Zijlstra <peterz at infradead.org>
Cc: Sergey Senozhatsky <sergey.senozhatsky.work at gmail.com>
Cc: Thomas Gleixner <tglx at linutronix.de>
Cc: linux-mm at kvack.org
Link: http://lkml.kernel.org/r/20180214111656.88514-3-kirill.shutemov@linux.intel.com
Signed-off-by: Ingo Molnar <mingo at kernel.org>
[florian: drop arch/x86/include/asm/pgtable_64_types.h changes since
there is no CONFIG_X86_5LEVEL]
Signed-off-by: Florian Fainelli <f.fainelli at gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh at linuxfoundation.org>
---
 arch/x86/include/asm/pgtable-3level_types.h |    1 +
 mm/zsmalloc.c                               |   13 +++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

--- a/arch/x86/include/asm/pgtable-3level_types.h
+++ b/arch/x86/include/asm/pgtable-3level_types.h
@@ -42,5 +42,6 @@ typedef union {
  */
 #define PTRS_PER_PTE	512
 
+#define MAX_POSSIBLE_PHYSMEM_BITS	36
 
 #endif /* _ASM_X86_PGTABLE_3LEVEL_DEFS_H */
--- a/mm/zsmalloc.c
+++ b/mm/zsmalloc.c
@@ -83,18 +83,19 @@
  * This is made more complicated by various memory models and PAE.
  */
 
-#ifndef MAX_PHYSMEM_BITS
-#ifdef CONFIG_HIGHMEM64G
-#define MAX_PHYSMEM_BITS 36
-#else /* !CONFIG_HIGHMEM64G */
+#ifndef MAX_POSSIBLE_PHYSMEM_BITS
+#ifdef MAX_PHYSMEM_BITS
+#define MAX_POSSIBLE_PHYSMEM_BITS MAX_PHYSMEM_BITS
+#else
 /*
  * If this definition of MAX_PHYSMEM_BITS is used, OBJ_INDEX_BITS will just
  * be PAGE_SHIFT
  */
-#define MAX_PHYSMEM_BITS BITS_PER_LONG
+#define MAX_POSSIBLE_PHYSMEM_BITS BITS_PER_LONG
 #endif
 #endif
-#define _PFN_BITS		(MAX_PHYSMEM_BITS - PAGE_SHIFT)
+
+#define _PFN_BITS		(MAX_POSSIBLE_PHYSMEM_BITS - PAGE_SHIFT)
 
 /*
  * Memory for allocating for handle keeps object position by


Patches currently in stable-queue which might be from f.fainelli at gmail.com are

queue-4.9/mm-zsmalloc-prepare-to-variable-max_physmem_bits.patch
queue-4.9/arch-pgtable-define-max_possible_physmem_bits-where-needed.patch