[PATCH] arcv2: Make sure busy bit is set properly on SLC flushing

[Alexey Brodkin]

Hi Vineet,

On Wed, 2017-03-29 at 16:41 -0700, Vineet Gupta wrote:
> On 03/29/2017 07:15 AM, Alexey Brodkin wrote:
> > 
> > As reported in STAR 9001165532 if data cache gets disabled right before
> > L2 cache invalidation we may read wrong value of L2 cache "busy" bit.
> > So we won't wait before L2 cache gets properly flushed and so some
> > data might not reach DDR at all thus we'll use older values from DDR
> > next time they are accessed.
> > 
> > For now we use a work-around with one extra read from SLC's control
> > register which guarantees next read will return real value of "busy"
> > bit.
> > 
> > Signed-off-by: Alexey Brodkin <abrodkin at synopsys.com>
> 
> Thx Alexey - pushed to for-curr !

Care to add for-stable tag?

-Alexey