[PATCH 3/3 v6] ARC: hsdk: initial port for HSDK board

Eugeniy Paltsev Eugeniy.Paltsev at synopsys.com
Thu Jun 29 09:39:45 PDT 2017


On Wed, 2017-06-28 at 17:50 -0500, Rob Herring wrote:
> > > > +                       #clock-cells = <0>;
> > > > +                       compatible = "fixed-clock";
> > > > +                       clock-frequency = <1000000000>;
> > > > +               };
> > > > +
> > > > +               core_intc: archs-intc at cpu {
> > > 
> > > cpu is not a valid unit-address. How are these interrupt
> > > controllers addressed?
> > 
> > We have per-core INTC so each core communicates to its own INTC and
> > there's no way
> > for any core to talk with INTC of another core.
> > 
> > But then we have the next level INTC which is IDU (Interrupt
> > Distribution Unit)
> > which dispatches "common" IRQs to different upstream per-core INTC,
> > see below its node. 
> 
> Okay, I'd just do "cpu-interrupt-controller" for the node name then. 
> There doesn't seem to be an easy way to use just "interrupt-
> controller" 
> since you have 2 nodes at the same level and no unit-address (i.e. a 
> reg property).
> 

To be more clarify, what is better way do describe such hardware in
device tree?

-------------    -------------  
| cpu core 0|    | cpu core 1|  
-------------    -------------  
| interrupt |    | interrupt |  
| controller|    | controller|  
|     0     |    |     1     |  
-------------    -------------  
      ^                ^
      |                |
             -----------
      |      |
----------------
|   interrupt  |
| distribution |
|     unit     |
----------------
      ^
      |
      |<--other devices interrupt lines

We can't just create a node for each core interrupt controller because
we wouldn't able to specify which one is parent for interrupt
distribution unit:

------------>>>-------------
cpus {
    cpu at 0 { intc at 0 };
    cpu at 1 { intc at 1 };
};

interrupt-distribution-unit {
    interrupt-parent = ????
};
------------>>>-------------

Should we simply create one core interrupt controller node for all cpus
(instead of one per each cpu core), or where is a better option?

-- 
 Eugeniy Paltsev


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