From 8eff278552aaf248161df9af04f8b93f03526bcd Mon Sep 17 00:00:00 2001 From: Gevorg Sahakyan Date: Mon, 31 Jul 2017 17:19:51 +0400 Subject: [PATCH] usb: dwc2: Fix TxFIFO setup issue In host mode reading from DPTXSIZn returning invalid value(0) in dwc2_check_param_tx_fifo_sizes function. Added g_tx_fifo_size array in dwc2_hw_params structure in which stored power on reset valus of DPTXSIZn registers in device mode (forced to device). Updated dwc2_get_hwparams function to write DPTXFSIZn to array. Modyfied dwc2_check_param_tx_fifo_sizes function accordingly. Change-Id: I61d3db753b1bc06f0f2caf40df350a09655f18fd Signed-off-by: Gevorg Sahakyan --- diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 5029dde..3b71b49 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -533,6 +533,7 @@ unsigned utmi_phy_data_width:2; u32 snpsid; u32 dev_ep_dirs; + u32 g_tx_fifo_size[MAX_EPS_CHANNELS]; }; /* Size of control and EP0 buffers */ diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index 701516e..79080a9 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -452,7 +452,6 @@ int fifo; int min; u32 total = 0; - u32 dptxfszn; fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; @@ -467,15 +466,15 @@ } for (fifo = 1; fifo <= fifo_count; fifo++) { - dptxfszn = (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & - FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; if (hsotg->params.g_tx_fifo_size[fifo] < min || - hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { + hsotg->params.g_tx_fifo_size[fifo] > + hsotg->hw_params.g_tx_fifo_size[fifo]) { dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", __func__, fifo, hsotg->params.g_tx_fifo_size[fifo]); - hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; + hsotg->params.g_tx_fifo_size[fifo] = + hsotg->hw_params.g_tx_fifo_size[fifo]; } } } @@ -607,6 +606,7 @@ { struct dwc2_hw_params *hw = &hsotg->hw_params; unsigned int width; + int fifo, fifo_count; u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; u32 grxfsiz; @@ -675,6 +675,12 @@ hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> GRXFSIZ_DEPTH_SHIFT; + fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); + + for (fifo = 1; fifo <= fifo_count; fifo++) { + hw->g_tx_fifo_size[fifo] = (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & + FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; + } return 0; }