[PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information

Stefan Wahren stefan.wahren at i2se.com
Tue Dec 28 08:30:52 PST 2021

Am 21.12.21 um 23:48 schrieb Richard Schleich:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
> Signed-off-by: Richard Schleich <rs at noreya.tech>

Tested-by: Stefan Wahren <stefan.wahren at i2se.com>

I tested the patch with a Raspberry Pi 4 (arm64/defconfig) and here are
some outputs:




Architecture:        aarch64
Byte Order:          Little Endian
CPU(s):              4
On-line CPU(s) list: 0-3
Thread(s) per core:  1
Core(s) per socket:  4
Socket(s):           1
NUMA node(s):        1
Vendor ID:           ARM
Model:               3
Model name:          Cortex-A72
Stepping:            r0p3
CPU max MHz:         1500,0000
CPU min MHz:         600,0000
BogoMIPS:            108.00
L1d cache:           32K
L1i cache:           48K
L2 cache:            1024K
NUMA node0 CPU(s):   0-3
Flags:               fp asimd evtstrm crc32 cpuid

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