[PATCH] irq_bcm2836: Send event when onlining sleeping cores
marc.zyngier at arm.com
Tue May 9 11:14:55 PDT 2017
On 09/05/17 19:08, Eric Anholt wrote:
> Marc Zyngier <marc.zyngier at arm.com> writes:
>> On 09/05/17 17:59, Eric Anholt wrote:
>>> Phil Elwell <phil at raspberrypi.org> writes:
>>>> In order to reduce power consumption and bus traffic, it is sensible
>>>> for secondary cores to enter a low-power idle state when waiting to
>>>> be started. The wfe instruction causes a core to wait until an event
>>>> or interrupt arrives before continuing to the next instruction.
>>>> The sev instruction sends a wakeup event to the other cores, so call
>>>> it from bcm2836_smp_boot_secondary, the function that wakes up the
>>>> waiting cores during booting.
>>>> It is harmless to use this patch without the corresponding change
>>>> adding wfe to the ARMv7/ARMv8-32 stubs, but if the stubs are updated
>>>> and this patch is not applied then the other cores will sleep forever.
>>>> See: https://github.com/raspberrypi/linux/issues/1989
>>>> Signed-off-by: Phil Elwell <phil at raspberrypi.org>
>>>> drivers/irqchip/irq-bcm2836.c | 3 +++
>>>> 1 file changed, 3 insertions(+)
>>>> diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
>>>> index e10597c..6dccdf9 100644
>>>> --- a/drivers/irqchip/irq-bcm2836.c
>>>> +++ b/drivers/irqchip/irq-bcm2836.c
>>>> @@ -248,6 +248,9 @@ static int __init bcm2836_smp_boot_secondary(unsigned int cpu,
>>>> intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
>>>> + dsb(sy); /* Ensure write has completed before waking the other CPUs */
>>>> + sev();
>>>> return 0;
>>> This is also the behavior that the standard arm64 spin-table method has,
>>> which we unfortunately can't quite use.
>> And why is that so? Why do you have to reinvent the wheel (and hide the
>> cloned wheel in an interrupt controller driver)?
>> That doesn't seem right to me.
> The armv8 stubs (firmware-supplied code in the low page that do the
> spinning) do actually implement arm64's spin-table method. It's the
> armv7 stubs that use these registers in the irqchip instead of plain
> addresses in system memory.
Let's put ARMv7 aside for the time being. If your firmware already
implements spin-tables, why don't you simply use that at least on arm64?
Jazz is not dead. It just smells funny...
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