Failed to set clk rate for BCM2835_CLOCK_EMMC
eric at anholt.net
Wed Jan 4 10:05:29 PST 2017
Stefan Wahren <stefan.wahren at i2se.com> writes:
> i'm still playing with sdhci-iproc and i found out that the emmc clock (249799997 Hz) of the host isn't optimal for high speed.
> Here an example debugfs output for a Compute Module:
> clock: 52000000 Hz
> actual clock: 41633332 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 2 (4 bits)
> timing spec: 1 (mmc high-speed)
> signal voltage: 0 (3.30 V)
> driver type: 0 (driver type B)
> The actual clock results from the restriction that the clock divider of the emmc module must be multiple of 2 (249799997 / 6 = 41633332). So if we could adjust the emmc clock to something like 208 MHz we get an nearly optimal clock.
> So tried set the clock rate of BCM2835_CLOCK_EMMC via clk_set_rate() to 208 MHz during driver probe, but it fails:
> [ 1.478953] sdhci-iproc 20300000.sdhci: failed to set host clk: -16
> This seems to be EBUSY.
> Any explanation or solution for this?
Did you try to set the rate while the clock was enabled? We don't allow
that. I've heard that the hw actually can change dividers while
enabled, but the docs said not to iirc.
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