[PATCH v6 10/22] usb: dwc2: host: Properly set the HFIR
dianders at chromium.org
Sun Jan 31 14:19:37 PST 2016
On Sun, Jan 31, 2016 at 1:23 AM, Kever Yang <kever.yang at rock-chips.com> wrote:
> On 01/29/2016 10:20 AM, Douglas Anderson wrote:
>> According to the most up to date version of the dwc2 databook, the FRINT
>> field of the HFIR register should be programmed to:
>> * 125 us * (PHY clock freq for HS) - 1
>> * 1000 us * (PHY clock freq for FS/LS) - 1
> I got 3 version of dwc_otg databook, 2.74a, 2.94a and 3.10a,
> all the doc describe the FrInt as:
Can you check to see if you can get 3.30a (October 2015)?
> * 125 us * (PHY clock freq for HS)
> * 1000 us * (PHY clock freq for FS/LS)
> Maybe John can help to check the design.
Yes, this really needs John or someone at Synopsys.
> There are some feature different in new and old version, but not sure
> if this is one of then.
> The doc says If no value is programmed, the corecalculates the value
> based on the PHY clock specified in the FS/LS PHY Clock select field of
> Host configuration register(HCFG.FLSLPclkSel), does this work?
It seems to. It looks like that's what makes our firmware work. I'm
not 100% sure if there are any downsides to that approach...
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