[PATCH 3/6] spi: bcm2835: fill FIFO before enabling interrupts to
broonie at kernel.org
Mon Mar 30 22:25:19 PDT 2015
On Mon, Mar 30, 2015 at 09:16:21PM -0600, Stephen Warren wrote:
> On 03/29/2015 08:03 AM, Martin Sperl wrote:
> > There have been rare cases where short (<200ns) chip-select switches with
> > native CS have been observed during such operation, this is why this
> > optimization is only enabled for GPIO-CS.
> > + /* fill in fifo if we have gpio-cs
> > + * note that there have been rare events where the native-CS
> > + * flapped for <1us which may change the behaviour
> > + * with gpio-cs this does not happen, so it is implemented
> > + * only for this case
> > + */
> However, I'm not sure why this is in any way related to whether the
> chip-select GPIO is valid. Surely we always want to do this? How does
> the mechanism used to control chip selects influence whether we want to
> pre-fill the FIFO?
I think both the comment and the commit message answer that question -
something triggers spurious chip select changes?
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