[PATCH 3/6] spi: bcm2835: fill FIFO before enabling interrupts to

Mark Brown broonie at kernel.org
Tue Apr 7 09:28:57 PDT 2015

On Tue, Apr 07, 2015 at 09:39:03AM -0600, Stephen Warren wrote:
> On 04/07/2015 12:25 AM, Martin Sperl wrote:

> >As the CS register contains the interrupt flags as well as the
> >control for the native-chip-selects this is impacting the chip select
> >lines in native mode.

> Is the driver simply programming the HW incorrectly then? I would expect the
> driver to do something roughly like:

> * Set up the HW to execute the transaction; everything except enabling IRQs
> and telling the HW to "go"
> * Clear stale IRQ status (perhaps do this right at the start)
> * Enable IRQs
> * Tell the HW to "go"

> ... then not touch any CS-related register for the entire transfer. There
> shouldn't be a need to enable/disable IRQs during the transfer; just leave
> them enabled the entire time, until all bytes have been transferred.

We will need to make sure /CS is kept asserted between transfers in a
message too.
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