[PATCH 3/6] spi: bcm2835: fill FIFO before enabling interrupts to

Martin Sperl kernel at martin.sperl.org
Mon Apr 6 23:43:02 PDT 2015

Now remembering a bit more from what I have observed:
> On 07.04.2015, at 08:25, Martin Sperl <kernel at martin.sperl.org> wrote:
> See also:
> http://www.raspberrypi.org/forums/viewtopic.php?f=44&t=19489&start=125#p451817
> for some observations mostly related to CLEAR_TX/CLEAR_RX that also
> de-assert CS for short periods.

Note that this TX/RX reset with native CS is also inhibiting the use
of DMA for any transfers not a multiple of 4 (DMA transfers data into
the FIFO in words not bytes). Because after those transfers we have
to reset the FIFO or the remaining bytes still in the FIFO will get
shifted out before a subsequent transfer.

So for any DMA enabled driver we need this kind of gpio-cs to avoid
this CS-glitch situation unless we want a "DMA only on multiple of 4"
with native-cs situation...

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