[PATCH] staging: dwc2: set up all module params

Martin Sperl kernel at martin.sperl.org
Tue Nov 26 23:34:12 PST 2013

On 27.11.2013, at 07:47, Gordon Hollingworth wrote:
> In general it should be possible to schedule multiple split
> transactions to a TT but they _must_ be completed on time or the hub
> will drop the transactions on the floor...  Unfortunately because of
> the interrupt latency issues it cannot be guaranteed without the FIQ

Maybe a bit of outside of the box thinking with limited knowledge of
the finer details of USB:
If the "delay" we are allowed to have is "somewhat" deterministic,
then maybe use the ARM DMA to configure the USB registers after a
certain delay.

My experiments with a DMA only pipelined SPI driver shows that it is
* to schedule delays only in DMA (with an accuracy of about 2%)
  (note that this has some impact on available Memory bandwidth)
* to configure VC registers via DMA - I am not sure if this also 
  applies to the USB registers that are coming from an external IP.

That way one could configure a max delay after which the DMA would
schedule the pending USB-transfer itself.
The only thing one would need to make sure is that there is no 
concurrent access to the registers between code and DMA.

Another approach could be looking if we can get that "scheduling"
part of interrupts into the VideoCore CPU, which runs RTOS.
So essentially creating an interrupt engine in RTOS - even if it
would only start a pre-configured DMA transfer.
(but that would mean convincing lots of people to get this into 


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