>From 8478b796642a658982a928179981a94e2557a483 Mon Sep 17 00:00:00 2001 From: Sebastian Fricke Date: Sat, 14 Nov 2020 15:05:34 +0100 Subject: [PATCH v3] arm64:dts: Add OV13850 & RkISP1 to the device tree The OV13850 camera sensor device tree addition to I2C1 was ported from the BSP kernel from friendlyElec. The RkISP1 is part of another unmerged patch series by Helen Koike. (https://patchwork.kernel.org/project/linux-media/patch/20201020193850.1460644-9-helen.koike@collabora.com/) Connect the camera sensor to the ISP directly and set the mipi_dphy_rx0 as the physical layer. Signed-off-by: Sebastian Fricke --- .../boot/dts/rockchip/rk3399-nanopc-t4.dts | 64 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++ 2 files changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts index e0d75617bb7e..1f348a0842db 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts @@ -99,6 +99,29 @@ vpcie3v3-supply = <&vcc3v3_sys>; }; +&i2c1 { + status = "okay"; + ov13850p0: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru 0x89>; + clock-names = "xvclk"; + + reset-gpios = <&gpio2 27 0>; + pwdn-gpios = <&gpio2 28 0>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam0_default_pins &cif_clkout_a>; + pinctrl-1 = <&cam0_default_pins>; + + port { + ucam_out0b: endpoint { + remote-endpoint = <&mipi_in_ucam0b>; + data-lanes = <1 2>; + }; + }; + }; +}; &pinctrl { ir { ir_rx: ir-rx { @@ -106,6 +129,47 @@ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; }; }; + cam_pins { + cif_clkout_a: cif-clkout-a { + rockchip,pins = <2 11 3 &pcfg_pull_none>; + }; + + cif_clkout_a_sleep: cif-clkout-a-sleep { + rockchip,pins = <2 11 0 &pcfg_pull_none>; + }; + + cam0_default_pins: cam0-default-pins { + rockchip,pins = <2 28 0 &pcfg_pull_down>, <2 27 0 &pcfg_pull_none>; + }; + + cam1_default_pins: cam1-default-pins { + rockchip,pins = <0 12 0 &pcfg_pull_down>, <0 8 0 &pcfg_pull_none>; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp0 { + status = "okay"; + resets = <&cru SRST_H_ISP0>, <&cru SRST_ISP0>; + reset-names = "h_isp0", "isp0"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0b: endpoint@0 { + reg = <0>; + remote-endpoint = <&ucam_out0b>; + }; + }; }; &sdhci { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1f8bf0cec5c2..4cb13bfada62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1723,6 +1723,32 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_WRAPPER>; + clock-names = "isp", "aclk", "hclk"; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; -- 2.20.1