[PATCH v5 00/21] drm: starfive: jh7110: Enable display subsystem

[Byron Stanoszek]

On Tue, 29 Sep 2026, Michal Wilczynski wrote:

> This series enables the display subsystem on the StarFive JH7110.
>
> [...]
> - New patch 1 fixes v_HSYNC_POLARITY and v_VSYNC_POLARITY, which have
>  been swapped in inno-hdmi since the driver was merged. The hardware
>  puts HSYNC in bit 2 and VSYNC in bit 3, and the driver had them the
>  other way round. Almost all CEA modes drive both syncs with the same
>  polarity, so the two writes are indistinguishable and the bug only
>  shows on a mode whose polarities differ - a band of black rows at the
>  top of the screen, vsync_end - vsync_start + 1 rows tall. Reported
>  independently by Dominique Belhachemi, Maud Spierings and Byron
>  Stanoszek, and confirmed against the RK3128 TRM by Icenowy Zheng, so
>  this is a Rockchip fix too.
> - Added a 201 MHz entry to the JH7110 pre-PLL table for a 2560x1440
>  mode Byron Stanoszek runs on a Dell U2711. It is derived the same way
>  as the neighbouring entries (fbdiv 134, /16, VCO 3.216 GHz) but I have
>  no sink that asks for it, so it is untested on my hardware.

Hi Michal,

I confirm that the hsync/vsync polarity and 201 MHz mode are both working on my
setup in v5. Tested against 7.3-rc5 with af384d6e0573 and Bo Gan's cache
coherency fixes. Thanks again for your work on this series!

Tested-by: Byron Stanoszek <gandalf at winds.org>

Best regards,
  -Byron