[PATCH 1/2] PCI: dwc: Align register macros with Synopsys documentation

[Bjorn Helgaas]

On Mon, Sep 28, 2026 at 04:50:09PM -0500, Bjorn Helgaas wrote:
> On Sat, Sep 12, 2026 at 12:25:36AM +0800, Hans Zhang wrote:
> > The DWC PCIe register and field macros are inconsistently named and
> > often do not match the Synopsys DesignWare PCIe Controller Reference
> > Manual.  This makes it harder to cross-reference the code with the
> > documentation when debugging or maintaining the driver.
> 
> > +#define  PORT_AFAC_L0S_ELS		24		/* L0s Entrance Latency shift */
> > +#define  PORT_AFAC_L0S_ELM		GENMASK(26, 24)	/* L0s Entrance Latency mask */
> > +#define  PORT_AFAC_L1_ELS		27		/* L1 Entrance Latency shift */
> > +#define  PORT_AFAC_L1_ELM		GENMASK(29, 27)	/* L1 Entrance Latency mask */
> 
> Surely we don't need both the shift and the mask?  Maybe a separate
> patch convert to FIELD_PREP()?

Oops, sorry, didn't notice that Mani had already applied these.  This
could be material for follow-on patches.

> > +#define  GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24		/* Rate Shadow Select shift */
> > +#define  GEN3_CTRL_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)	/* Rate Shadow Select mask */
> 
> Ditto.
> 
> > +#define MSIX_DOORBELL			0x948
> > +#define  MSIX_DOORBELL_PF_SHIFT		24
> 
> Probably would be better to define a mask so we have the position
> *and* the width.
> 
> > @@ -621,15 +621,15 @@ static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
> >  	u32 val;
> >  
> >  	val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
> > -				PCIE_RAS_DES_EVENT_COUNTER_CONTROL);
> > +				RAS_DES_EVENT_COUNTER_CONTROL);
> >  	val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
> >  	val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
> >  	val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
> >  	val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
> 
> Probably a good chance to convert these to FIELD_PREP() etc. as well,
> maybe in a separate patch.