[PATCH v16 4/6] usb: dwc3: rockchip: support PHY reset notifications

[Manivannan Sadhasivam]

On Thu, Sep 24, 2026 at 07:25:40PM +0200, Sebastian Reichel wrote:
> On recent Rockchip platforms (at least RK3588 & RK3576), DWC3 IP is used
> with a USBDP PHY providing USB3 and DP. This PHY needs to be reset when
> the mode changes, which may happen when plugging in different USB-C
> devices.
> 
> If the USBDP PHY resets with the DWC3 IP running, its internal state
> corrupts resulting in the USBDP PHY not being able to lock some PLL
> clocks, which effectively renders USB3 unusable.
> 
> To fix the issue this adds handling for the new PHY framework reset
> notifications, which will assert PHYSOFTRST before the actual PHY
> is disabled and will deassert it once the PHY returns.
> 
> Tested-by: Igor Paunovic <royalnet026 at gmail.com> # Orange Pi 5 Plus
> Acked-by: Thinh Nguyen <Thinh.Nguyen at synopsys.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>  # PHY

- Mani

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