[PATCH v15 09/11] phy: rockchip: usbdp: Avoid xHCI SErrors

[Manivannan Sadhasivam]

On Tue, Sep 15, 2026 at 05:06:12PM +0200, Sebastian Reichel wrote:
> The USBDP PHY provides the PIPE clock to the USB3 controller, which
> means the PHY must be fully running when anything tries to access
> the xHCI registers.
> 
> When switching between USB3-only, USB3 + DP and DP-only mode, the
> PHY must be re-initialized resulting in a short period of the PHY
> being disabled. If the DWC3 driver decides to access the xHCI at
> this point the system will fail with an SError.
> 
> This patch avoids the problems by disabling the USB3 port before
> re-initializing it. This does a couple of things:
> 
> - forces phystatus to 0 from GRF (not from PHY)
> - switches PIPE clock source from PHY to UTMI (safe fallback clock)
> - num_u3_port=0
> 
> The last part will be ignored, as DWC3 already probed, but the
> clock re-routing will avoid the SError. There is a small delay
> afterwards to make sure the mux happened. The datasheet gives
> no hints how long it takes, so delay time is a guess.
> 
> Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
> Tested-by: Igor Paunovic <royalnet026 at gmail.com> # Orange Pi 5 Plus
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani

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