[PATCH v9 1/9] PCI: dw-rockchip: Fix LTSSM set functions

[Sebastian Reichel]

Hi,

On Mon, Nov 09, 2026 at 11:33:29AM -0600, Bjorn Helgaas wrote:
> On Thu, Nov 05, 2026 at 02:33:09PM +0100, Sebastian Reichel wrote:
> > Before the Rockchip PCIe driver has been switched over to the
> > FIELD_PREP_WM16 macro, PCIE_CLIENT_ENABLE_LTSSM and
> > PCIE_CLIENT_DISABLE_LTSSM were setting bits with a mask of 0xc = 0b1100,
> > which means BIT 2 and BIT 3. After the conversion it only sets bit 2,
> > with bit 3 being handled by a separate define named
> > PCIE_CLIENT_LD_RQ_RST_GRT. Apparently the conversion missed to make use
> > of this new macros resulting in the third bit not being set.
> > 
> > Fixes: 30e919570581 ("PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro")
> 
> This commit appeared in v6.18, so this looks like it might be a
> candidate for a stable tag?

IDK if its worth backporting. I mainly did not add the tag, since I
found this by chance while rebasing code around it. For my basic
tests I didn't notice any problems even without the bit. Also nobody
reported anything since v6.18. The bit was originally set since the
driver had been introduced. Maybe Shawn can say if its worth backporting?

Greetings,

-- Sebastian

> 
> > Reviewed-by: Shawn Lin <shawn.lin at rock-chips.com>
> > Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-dw-rockchip.c | 10 ++++++----
> >  1 file changed, 6 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > index bd86e32cc2b1..c35c5583c797 100644
> > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> > @@ -322,14 +322,16 @@ static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,
> >  
> >  static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
> >  {
> > -	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
> > -				 PCIE_CLIENT_GENERAL_CON);
> > +	u32 val = PCIE_CLIENT_ENABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT;
> > +
> > +	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON);
> >  }
> >  
> >  static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
> >  {
> > -	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
> > -				 PCIE_CLIENT_GENERAL_CON);
> > +	u32 val = PCIE_CLIENT_DISABLE_LTSSM | PCIE_CLIENT_LD_RQ_RST_GRT;
> > +
> > +	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_GENERAL_CON);
> >  }
> >  
> >  static bool rockchip_pcie_link_up(struct dw_pcie *pci)
> > 
> > -- 
> > 2.53.0
> > 
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