[PATCH v6 5/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo at pardini.net>

The FriendlyElec NanoPi R6C carries one on-board Realtek RTL8125 NIC
(the LAN port) behind pcie2x1l1.

Describe the PCI function node and attach an ethernet1 alias, so that
U-Boot's fdt_fixup_ethernet() can fill in its MAC address from its
eth1addr environment.

ethernet0 stays mapped to the on-SoC gmac1 (the WAN port). The node
goes in this .dts rather than the shared rk3588s-nanopi-r6.dtsi, since
on the R6C the dtsi's second RTL8125-capable lane is empty compared to
the R6S.

Signed-off-by: Ricardo Pardini <ricardo at pardini.net>
---
 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
index ccc5e4627517..48d87f7923db 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
@@ -7,8 +7,28 @@
 / {
 	model = "FriendlyElec NanoPi R6C";
 	compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
+
+	aliases {
+		ethernet1 = &rtl_eth1;
+	};
 };
 
 &lan2_led {
 	label = "user_led";
 };
+
+&pcie2x1l1 {
+	pcie at 0,0 {
+		reg = <0x300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x31 0x3f>;
+
+		rtl_eth1: ethernet at 0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x310000 0 0 0 0>;
+		};
+	};
+};

-- 
2.47.3