[PATCH v2] gpio: rockchip: restore the bank registers after hibernation

[Igor Velkov]

Hi Heiko,

Please hold v2: Sashiko is right about the debounce clock. On ODROID-M1,
after hybrid sleep with a power cut, a line with debounce saw 0/8 edges
and a control line without debounce 8/8 (one run). dbclk_gpio3 and its
parent dbclk_gpio read enable count 1 with the hardware gate closed;
opening both by hand gave 8/8.

With WoL on, aclk_gmac0 and pclk_gmac0 come back the same way and the
network stays down after restore. So this looks wider than GPIO, and
fixing it per driver looks like the wrong level.

Should the Rockchip clock driver write its gates back after restore, as
at91, tegra210 and ti do through clk_restore_context()? I find no
restore_context in drivers/clk/rockchip.

Igor