[PATCH v2 2/3] PCI: Configure Root Port MPS after scanning its hierarchy

[Manivannan Sadhasivam]

On 2026-10-20 14:28 +0200, Niklas Cassel wrote:
> With the default MPS strategy (PCIE_BUS_DEFAULT), pci_configure_mps()
> only matches each device's Maximum Payload Size (MPS) to its upstream
> bridge.  Root Ports have no upstream bridge, so their MPS stays at
> whatever firmware or the hardware default (128 bytes) left there, and the
> hierarchy below them inherits that value even if the Root Port and all
> devices below it support more.
> 
> Once the hierarchy below a Root Port has been scanned, and before drivers
> are bound, set the Root Port and every device below it to the largest MPS
> they all support, even if that is more than firmware programmed.  Do this
> from pcie_bus_configure_settings(), which the host bridge, ACPI and
> hotplug paths call after scanning, and from pci_rescan_bus() and
> pci_rescan_bus_bridge_resize(), which don't.
> 
> If the hierarchy contains a hotplug bridge other than the Root Port,
> typically a Switch Downstream Port, limit it to 128 bytes instead, like
> pcie_find_smpss() does for PCIE_BUS_SAFE: a device hot-added below such a
> port later can't lower the MPS of a hierarchy in use, but every device
> supports 128 bytes.  This costs throughput where firmware programmed a
> larger MPS for such a hierarchy, in exchange for hot-added devices always
> working.
> 
> An empty slot directly below a Root Port is left alone; it is evaluated
> when a device is hot-added or rescanned there, which also allows raising
> the Root Port again after a device that supported less has been replaced.
> Hierarchies in which a device other than a Switch port may already have
> a driver bound are never changed.  If the MPS of a device can't be set,
> restore the previous MPS of the whole hierarchy rather than leaving it
> with mismatched settings.
> 
> Since PCIE_BUS_DEFAULT can now raise MPS above what firmware programmed,
> apply the Intel 5000/5100 read completion coalescing quirk to it as well.
> 
> The other strategies are unchanged: PCIE_BUS_TUNE_OFF doesn't touch MPS,
> and PCIE_BUS_SAFE, PCIE_BUS_PERFORMANCE and PCIE_BUS_PEER2PEER already
> configure the hierarchy in pcie_bus_configure_settings().
> 
> Suggested-by: Manivannan Sadhasivam <mani at kernel.org>
> Co-developed-by: Hans Zhang <18255117159 at 163.com>
> Signed-off-by: Hans Zhang <18255117159 at 163.com>
> Signed-off-by: Niklas Cassel <cassel at kernel.org>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani