[PATCH v5 1/2] dt-bindings: PCI: rockchip,rk3399-pcie: Add PERST# inactive delay properties

[Krzysztof Kozlowski]

On Wed, Nov 04, 2026 at 09:58:46PM +0000, Enrique Hernández Bello wrote:
> The driver holds PERST# asserted for T_PVPERL (100 ms) before releasing it.
> Endpoints disagree about what they want there: some need longer than the
> default to settle, while others stop answering configuration reads when the
> reset pulse is stretched that far, because PERST# stays asserted for the
> whole wait.
> 
> Describe two properties so a board can state what its endpoint needs, named
> after the ones the Rockchip vendor driver already uses for the dwc-based
> controllers:

Vendor driver does not matter, it is antipattern. Do not mention it here
as reason to do such change.

> 
>   rockchip,perst-inactive-ms      - the delay used at probe
>   rockchip,s2r-perst-inactive-ms  - the delay used when resuming

No need to repeat the diff.

> 
> Both are optional and the defaults preserve the current behaviour.
> 
> Signed-off-by: Enrique Hernández Bello <ehbello at gmail.com>
> ---
>  .../bindings/pci/rockchip,rk3399-pcie.yaml        | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
> index 720a5f9..7ac915c 100644
> --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
> @@ -40,6 +40,21 @@ properties:
>      maxItems: 1
>      description: pre-reset GPIO
>  
> +  rockchip,perst-inactive-ms:
> +    default: 100
> +    description:
> +      Time PERST# is held asserted before it is released, which is also the
> +      width of the reset pulse. The default meets T_PVPERL for a slot that
> +      is powered at the moment PERST# is asserted. Some endpoints need more
> +      settling time than that, while others stop responding when the pulse
> +      is that long. A value of 0 selects the 100 us minimum the PCI Express

us or ms?

> +      CEM specification sets for the pulse.

What is the nature of this timing? 100 ms is a lot. Are you sure you are
not describing RC delay (we have bindings for that already)

Best regards,
Krzysztof