[PATCH v5 09/15] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch

[Cristian Ciocaltea]

On 10/30/26 1:44 PM, Daniel Stone wrote:
> Hi,
> 
> On Tue, 13 Oct 2026 at 23:51, Cristian Ciocaltea
> <cristian.ciocaltea at collabora.com> wrote:
>> +                       if (!vp->dclk_src)
>> +                               vp->dclk_src = clk_get_parent(vp->dclk);
> 
> Why not do this at init, where we setup the rest of our clock tree?

Ack. I don't recall the reasoning for not doing this in the first place.

> The rest is:
> Reviewed-by: Daniel Stone <daniels at collabora.com>

Thanks,
Cristian