[PATCH 23/27] usb: dwc3: Configure RK3572 PIPE port before discovery

[Thinh Nguyen]

On Thu, Oct 22, 2026, Cunhao Lu via B4 Relay wrote:
> From: Cunhao Lu <1579567540 at qq.com>
> 
> Firmware may leave the USB3 PIPE port disabled, causing DWC3 to discover
> only USB2. Configure the port before reading controller capabilities.
> 
> Signed-off-by: Cunhao Lu <1579567540 at qq.com>
> ---
>  drivers/usb/dwc3/dwc3-generic-plat.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> index ca69ac0eb07ce..11e71fc76be1a 100644
> --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -22,6 +22,10 @@
>  #define EIC7700_HSP_AXI_LP_XM_CSYSREQ	BIT(0)
>  #define EIC7700_HSP_AXI_LP_XS_CSYSREQ	BIT(16)
>  
> +#define RK3572_PIPE_USB3		0x1100
> +#define RK3572_PIPE_USB2_ONLY		0x0189
> +#define RK3572_PIPE_WRITE_MASK		GENMASK(31, 16)
> +
>  struct dwc3_generic {
>  	struct device		*dev;
>  	struct dwc3		dwc;
> @@ -85,6 +89,27 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g)
>  	return 0;
>  }
>  
> +static int dwc3_rk3572_init(struct dwc3_generic *dwc3g)
> +{
> +	struct device *dev = dwc3g->dev;
> +	enum usb_device_speed speed = usb_get_maximum_speed(dev);
> +	struct regmap *grf;
> +	u32 offset, value = RK3572_PIPE_USB2_ONLY;
> +
> +	grf = syscon_regmap_lookup_by_phandle_args(dev->of_node, "rockchip,grf",
> +						   1, &offset);
> +	if (IS_ERR(grf))
> +		return dev_err_probe(dev, PTR_ERR(grf), "failed to get PHP GRF\n");
> +
> +	if (device_property_match_string(dev, "phy-names", "usb3-phy") >= 0 &&
> +	    speed != USB_SPEED_LOW && speed != USB_SPEED_FULL &&
> +	    speed != USB_SPEED_HIGH)

This can just be:
	if (device_property_match_string(dev, "phy-names", "usb3-phy") >= 0 &&
	    (speed == USB_SPEED_UNKNOWN || speed >= USB_SPEED_SUPER))

> +		value = RK3572_PIPE_USB3;
> +
> +	/* Configure the PIPE port before the core reads its port count. */
> +	return regmap_write(grf, offset, RK3572_PIPE_WRITE_MASK | value);
> +}
> +

This looks like something that can be done in the phy driver. The other
Rockchip platforms such as RK3588 do this in the phy right? Why it must
be here?

BR,
Thinh