[REGRESSION][BISECTED] No display on rk3399-gru-kevin
Damon Ding
damon.ding at rock-chips.com
Wed Jun 17 20:49:31 PDT 2026
Hi Vicente,
On 6/18/2026 7:15 AM, Vicente Bergas wrote:
> On Wed, Jun 17, 2026 at 10:45 AM Heiko Stübner <heiko at sntech.de> wrote:
>>
>> Hi Vicente,
>>
>> Am Mittwoch, 17. Juni 2026, 01:05:27 Mitteleuropäische Sommerzeit schrieb Vicente Bergas:
>>> Hello,
>>> there are two issues that result on a black screen on the rk3399-gru-kevin.
>>>
>>> The first one is due to:
>>> c8079f83e0bf312645050c17d9c87deb707369c1
>>> gpio: rockchip: convert to dynamic GPIO base allocation
>>
>> can you check that your kernel contains
>> "gpio: rockchip: Fix GPIO regression after conversion to dynamic base allocation"
>> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=5cd9c6d332f46d1de8b68117fe2a3f1b08ee80ff
>
> Yes, that commit is in v7.1 and it indeed fixes the gpio issue.
> I tested reverting c8079f83 alone and reverting all three.
> Now i've tested only reverting 51eb548a and d84b087c, and it works.
> The thing is both bugs coexisted at some point and
> git bisect finds them in order.
>
>>> Reverting this does not fix the problem as there is a second one:
>>> 51eb548ade20158b4f4f8693a95b1f31a2480e8e
>>> drm/bridge: analogix_dp: Apply DP helper API drm_dp_channel_eq_ok()
>>>
>>> That second one depends on:
>>> d84b087c7662dd65cd51b228219987c31b1cee02
>>> drm/bridge: analogix_dp: Apply DP helper APIs to get adjusted voltages
>>> and pre-emphasises
>>>
>>> Reverting all three commits from v7.1 make the display work again.
>>>
>>> Please, can this be resolved?
>>
>> and as Damon wrote, please provide logs, so we can see the actual problem
>
> It is quite difficult to read the logs from a black screen...
> Jokes apart, here they are:
>
> Relevant log entries:
> <6>[ 0.043668] /dp at fec00000: Fixed dependency cycle(s) with /vop at ff8f0000
> <6>[ 0.043735] /vop at ff8f0000: Fixed dependency cycle(s) with /dp at fec00000
> <6>[ 0.044192] /dp at fec00000: Fixed dependency cycle(s) with /vop at ff900000
> <6>[ 0.044250] /vop at ff900000: Fixed dependency cycle(s) with /dp at fec00000
> <6>[ 0.045064] /vop at ff900000: Fixed dependency cycle(s) with /dp at ff970000
> <6>[ 0.045122] /vop at ff8f0000: Fixed dependency cycle(s) with /dp at ff970000
> <6>[ 0.045194] /dp at ff970000: Fixed dependency cycle(s) with /vop at ff8f0000
> <6>[ 0.045264] /dp at ff970000: Fixed dependency cycle(s) with /vop at ff900000
> <6>[ 0.058590] /dp at ff970000: Fixed dependency cycle(s) with /edp-panel
> <6>[ 0.058733] /edp-panel: Fixed dependency cycle(s) with /dp at ff970000
> <6>[ 0.101266] platform ff8f0000.vop: Adding to iommu group 2
> <6>[ 0.102073] platform ff900000.vop: Adding to iommu group 3
> <3>[ 0.105258] rockchip-dp ff970000.dp: no DP phy configured
> <3>[ 0.308638] rockchip-dp ff970000.dp: no DP phy configured
> <6>[ 0.310104] panfrost ff9a0000.gpu: clock rate = 500000000
> <6>[ 0.311210] panfrost ff9a0000.gpu: mali-t860 id 0x860 major 0x2
> minor 0x0 status 0x0
> <6>[ 0.311223] panfrost ff9a0000.gpu: features: 00000000,00000407,
> issues: 00000000,24040400
> <6>[ 0.311231] panfrost ff9a0000.gpu: Features: L2:0x07120206
> Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff
> JS:0x7
> <6>[ 0.311239] panfrost ff9a0000.gpu: shader_present=0xf l2_present=0x1
> <6>[ 0.312664] [drm] Initialized panfrost 1.6.0 for ff9a0000.gpu on minor 0
> <3>[ 0.624232] rockchip-dp ff970000.dp: no DP phy configured
> <3>[ 0.639611] rockchip-dp ff970000.dp: no DP phy configured
> <6>[ 0.641512] rockchip-drm display-subsystem: bound ff900000.vop
> (ops 0xffff800080c9a3c8)
> <6>[ 0.642646] rockchip-drm display-subsystem: bound ff8f0000.vop
> (ops 0xffff800080c9a3c8)
> <4>[ 0.643198] [drm] Missing drm_bridge_add() before attach
> <6>[ 0.643238] rockchip-drm display-subsystem: bound ff970000.dp
> (ops 0xffff800080c9e840)
> <6>[ 0.644029] rockchip-drm display-subsystem: bound fec00000.dp
> (ops 0xffff800080c9f0c8)
> <6>[ 0.644102] cdn-dp fec00000.dp: [drm:cdn_dp_pd_event_work] Not
> connected; disabling cdn
> <6>[ 0.644837] [drm] Initialized rockchip 1.0.0 for
> display-subsystem on minor 1
> <4>[ 0.786773] panel-edp edp-panel: Skipping disable of already
> disabled panel
> <3>[ 0.796517] rockchip-dp ff970000.dp: EQ Max loop
> <3>[ 0.797745] rockchip-dp ff970000.dp: LT EQ failed!
> <3>[ 0.797757] rockchip-dp ff970000.dp: eDP link training failed (-5)
> <3>[ 0.797770] rockchip-dp ff970000.dp: unable to do link train, ret=-5
> <3>[ 0.797783] [drm:analogix_dp_bridge_atomic_enable] *ERROR* dp
> commit error, ret = -5
> <3>[ 0.797823] rockchip-dp ff970000.dp: failed to set bridge, retry: 0
> <4>[ 0.797937] panel-edp edp-panel: Skipping disable of already
> disabled panel
> <3>[ 0.808097] rockchip-dp ff970000.dp: EQ Max loop
> <3>[ 0.809284] rockchip-dp ff970000.dp: LT EQ failed!
> <3>[ 0.809299] rockchip-dp ff970000.dp: eDP link training failed (-5)
> <3>[ 0.809314] rockchip-dp ff970000.dp: unable to do link train, ret=-5
> <3>[ 0.809326] [drm:analogix_dp_bridge_atomic_enable] *ERROR* dp
> commit error, ret = -5
> <3>[ 0.809353] rockchip-dp ff970000.dp: failed to set bridge, retry: 1
> <4>[ 0.809463] panel-edp edp-panel: Skipping disable of already
> disabled panel
> <3>[ 0.819481] rockchip-dp ff970000.dp: EQ Max loop
> <3>[ 0.820745] rockchip-dp ff970000.dp: LT EQ failed!
> <3>[ 0.820758] rockchip-dp ff970000.dp: eDP link training failed (-5)
> <3>[ 0.820772] rockchip-dp ff970000.dp: unable to do link train, ret=-5
> <3>[ 0.820781] [drm:analogix_dp_bridge_atomic_enable] *ERROR* dp
> commit error, ret = -5
> <3>[ 0.820806] rockchip-dp ff970000.dp: failed to set bridge, retry: 2
> <4>[ 0.820919] panel-edp edp-panel: Skipping disable of already
> disabled panel
> <3>[ 0.831075] rockchip-dp ff970000.dp: EQ Max loop
> <3>[ 0.832336] rockchip-dp ff970000.dp: LT EQ failed!
> <3>[ 0.832346] rockchip-dp ff970000.dp: eDP link training failed (-5)
> <3>[ 0.832356] rockchip-dp ff970000.dp: unable to do link train, ret=-5
> <3>[ 0.832367] [drm:analogix_dp_bridge_atomic_enable] *ERROR* dp
> commit error, ret = -5
> <3>[ 0.832388] rockchip-dp ff970000.dp: failed to set bridge, retry: 3
> <4>[ 0.832496] panel-edp edp-panel: Skipping disable of already
> disabled panel
> <3>[ 0.842613] rockchip-dp ff970000.dp: EQ Max loop
> <3>[ 0.843754] rockchip-dp ff970000.dp: LT EQ failed!
> <3>[ 0.843765] rockchip-dp ff970000.dp: eDP link training failed (-5)
> <3>[ 0.843778] rockchip-dp ff970000.dp: unable to do link train, ret=-5
> <3>[ 0.843791] [drm:analogix_dp_bridge_atomic_enable] *ERROR* dp
> commit error, ret = -5
> <3>[ 0.843815] rockchip-dp ff970000.dp: failed to set bridge, retry: 4
> <3>[ 0.843857] rockchip-dp ff970000.dp: too many times retry set
> bridge, give it up
> <6>[ 0.854625] Console: switching to colour frame buffer device 300x100
> <6>[ 0.887526] rockchip-drm display-subsystem: [drm] fb0:
> rockchipdrmfb frame buffer device
>
>
I have tested RK3399 IND EVB locally based on kernel v7.1, and eDP
training completes successfully with normal display output with patch
0001-arm64-dts-rockchip-Enable-eDP-display-for-RK3399-IND.patch applied.
From your logs, the failure occurs during the EQ stage of eDP training.
Please apply the additional patch
0002-drm-bridge-analogix_dp-Read-CR-EQ-delay-from-DPCD-in.patch without
reverting the two commits mentioned above (51eb548a and d84b087c), then
retest to check if the issue gets improved.
(BTW: This is a test-only temporary patch with minor style flaws, but
the patch needs upstreaming. I'll rework and send a formal version soon.)
If the problem persists, try adding a small delay at the location
mentioned below for further verification:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a5dc645d7005..6dac3974acb5 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -401,6 +401,8 @@ static int
analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
analogix_dp_get_adjust_training_lane(dp, link_status);
+ usleep_range(5000, 6000);
+
if (drm_dp_channel_eq_ok(link_status, lane_count)) {
/* traing pattern Set to Normal */
retval = analogix_dp_training_pattern_dis(dp);
(Note: This delay is only for testing purpose)
Best regards,
Damon
-------------- next part --------------
From 82188d8c190ad926f14126a889701d57108a917f Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding at rock-chips.com>
Date: Thu, 18 Jun 2026 11:31:14 +0800
Subject: [PATCH 1/2] arm64: dts: rockchip: Enable eDP display for RK3399 IND
EVB board
Signed-off-by: Damon Ding <damon.ding at rock-chips.com>
---
.../boot/dts/rockchip/rk3399-evb-ind.dts | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
index 70aee1ab904c..3d7242d480ad 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
@@ -17,6 +17,14 @@ aliases {
chosen {
stdout-path = "serial2:1500000n8";
+ bootargs = "root=PARTUUID=614e0000-0000 rootwait";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ power-supply = <&vcc_lcd>;
+ pwms = <&pwm2 0 25000 0>;
};
vcc5v0_sys: regulator-vcc5v0-sys {
@@ -29,6 +37,17 @@ vcc5v0_sys: regulator-vcc5v0-sys {
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
};
+
+ vcc_lcd: vcc-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_lcd";
+ startup-delay-us = <20000>;
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
};
&cpu_b0 {
@@ -492,3 +511,34 @@ &vopl {
&vopl_mmu {
status = "okay";
};
+
+&edp {
+ force-hpd;
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ backlight = <&backlight>;
+ power-supply = <&vcc_lcd>;
+ no-hpd;
+
+ port {
+ panel_in_edp: endpoint {
+ remote-endpoint = <&edp_out_panel>;
+ };
+ };
+ };
+ };
+};
+
+&edp_out {
+ edp_out_panel: endpoint {
+ remote-endpoint = <&panel_in_edp>;
+ };
+};
+
+&pwm2 {
+ pinctrl-0 = <&pwm2_pin_pull_down>;
+ status = "okay";
+};
--
2.34.1
-------------- next part --------------
From 6115abdc02618d699b58364d1bae985e42001f85 Mon Sep 17 00:00:00 2001
From: Damon Ding <damon.ding at rock-chips.com>
Date: Thu, 18 Jun 2026 11:32:22 +0800
Subject: [PATCH 2/2] drm/bridge: analogix_dp: Read CR/EQ delay from DPCD
instead of fixed delay time
Signed-off-by: Damon Ding <damon.ding at rock-chips.com>
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 10 ++++++++--
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 8dee5f2fbde5..a5dc645d7005 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -325,7 +325,7 @@ static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
u8 voltage_swing, pre_emphasis, training_lane;
u8 link_status[DP_LINK_STATUS_SIZE];
- usleep_range(100, 101);
+ drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
lane_count = dp->link_train.lane_count;
@@ -386,7 +386,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
u32 reg;
u8 link_status[DP_LINK_STATUS_SIZE];
- usleep_range(400, 401);
+ drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
lane_count = dp->link_train.lane_count;
@@ -747,6 +747,12 @@ static int analogix_dp_commit(struct analogix_dp_device *dp)
{
int ret;
+ ret = drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to read dpcd caps: %d\n", ret);
+ return ret;
+ }
+
/* Keep the panel disabled while we configure video */
drm_panel_disable(dp->plat_data->panel);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 91b215c6a0cf..21d4d7f4ad34 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -170,6 +170,8 @@ struct analogix_dp_device {
bool fast_train_enable;
bool psr_supported;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
struct analogix_dp_plat_data *plat_data;
};
--
2.34.1
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