[PATCH v2 3/6] dt-bindings: soc: rockchip: grf: Add RV1106 compatibles

[Heiko Stübner]

Hi Krzysztof,

Am Dienstag, 21. Juli 2026, 10:16:33 Mitteleuropäische Sommerzeit schrieb Krzysztof Kozlowski:
> On Tue, Jul 14, 2026 at 01:36:40PM -0600, Simon Glass wrote:
> > Add the compatibles for the general register files of the Rockchip
> > RV1106: the main GRF, and the per-bank GPIO IOC blocks used by the pin
> > controller.
> > 
> > Signed-off-by: Simon Glass <sjg at chromium.org>
> > ---
> > 
> > Changes in v2:
> > - Drop the grf-cru clock-controller child and use the syscon-only
> >   group for the main GRF, since the CRU now provides the MMC phase
> >   clocks
> > - Use a single gpio-ioc compatible for the per-bank IOC blocks in
> >   place of the ioc and pmuioc regions
> > 
> >  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > index 2cc43742b8e3..fd9235ac1334 100644
> > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > @@ -64,6 +64,8 @@ properties:
> >                - rockchip,rk3588-vo1-grf
> >                - rockchip,rk3588-vop-grf
> >                - rockchip,rv1103b-ioc
> > +              - rockchip,rv1106-gpio-ioc
> 
> And this also answers my previous email (pinctrl/gpio bank): you have
> one GPIO IOC, not multiple ones, although commit msg tells different
> story. Confusing. The compatible here defines register layout (see
> writing bindings - it is explicitly documented there) so do you have one
> device or multiple with the same register layout?

It's actually option 3 ;-) .

The TRM describes separate General-Register-Files
	GPIO0 - the actual GPIO controller -  0xFF380000
GPIO0_IOC - 0xFF388000  (pinconfig)
	[ bunch of other devices like the video encoder ]
	GPIO1 - 0xFF530000
GPIO1_IOC - 0xFF538000
	...
GPIO2_IOC - 0xFF548000 
	...
GPIO3_IOC - 0xFF558000
	...
GPIO4_IOC - 0xFF568000

But their register-layouts are definitly not identical. For example in
GPIO0_IOC there is one register controlling Schmitt Triggers at offset
0x58, ( GPIO0_IOC_GPIO0A_IE_SMT ) - because only the first 8 pins have
those, while in GPIO1_IOC, 4 SMT register start at 0x280.

So they do need separate compatibles, per your comment.


Heiko