[PATCH 2/2] nvmem: rockchip-efuse: add write support for RK3399
Hrushiraj Gandhi
hrushirajg23 at gmail.com
Wed Jul 15 04:01:07 PDT 2026
Implement rockchip_rk3399_efuse_write() using the Array Program Mode
(A_PGM) as described in the RK3399 TRM. Each bit is programmed
individually by asserting STROBE for 15us with the target bit address
set in the EFUSE_CTRL register.
Introduce struct rockchip_efuse_soc_data to hold both reg_read and
reg_write callbacks per SoC, replacing the bare function pointer
previously stored in of_device_id.data. Move nvmem_config to the
probe stack so read_only can be set per-device based on whether a
write callback is provided.
Signed-off-by: Hrushiraj Gandhi <hrushirajg23 at gmail.com>
---
drivers/nvmem/rockchip-efuse.c | 152 +++++++++++++++++++++++++++------
1 file changed, 127 insertions(+), 25 deletions(-)
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index 013e67136f3b..19eb61380ea4 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -37,12 +37,16 @@
#define RK3399_NBYTES 4
#define RK3399_STROBSFTSEL BIT(9)
#define RK3399_RSB BIT(7)
+#define RK3399_PS BIT(4)
#define RK3399_PD BIT(5)
#define RK3399_PGENB BIT(3)
#define RK3399_LOAD BIT(2)
#define RK3399_STROBE BIT(1)
#define RK3399_CSB BIT(0)
+#define RK3399_PGM_TIME_US 15
+
#define REG_EFUSE_CTRL 0x0000
#define REG_EFUSE_DOUT 0x0004
@@ -52,6 +56,16 @@ struct rockchip_efuse_chip {
struct clk *clk;
};
+/**
+ * struct rockchip_efuse_soc_data - per-SoC efuse callbacks
+ * @reg_read: mandatory read callback
+ * @reg_write: optional write callback; NULL means read-only
+ */
+struct rockchip_efuse_soc_data {
+ int (*reg_read)(void *ctx, unsigned int offset, void *val, size_t bytes);
+ int (*reg_write)(void *ctx, unsigned int offset, void *val, size_t bytes);
+};
+
static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
@@ -177,6 +191,7 @@ static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
efuse->base + REG_EFUSE_CTRL);
udelay(1);
+
while (addr_len--) {
writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE |
((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
@@ -203,48 +218,120 @@ static int rockchip_rk3399_efuse_read(void *context, unsigned int offset,
return 0;
}
-static struct nvmem_config econfig = {
- .name = "rockchip-efuse",
- .add_legacy_fixed_of_cells = true,
- .type = NVMEM_TYPE_OTP,
- .stride = 1,
- .word_size = 1,
- .read_only = true,
+/**
+ * rockchip_rk3399_efuse_write - program fuse bits on RK3399 (A_PGM mode)
+ * @context: pointer to rockchip_efuse_chip
+ * @offset: byte offset in the efuse space
+ * @val: data to write (only set bits are programmed; OTP cannot clear)
+ * @bytes: number of bytes
+ *
+ * Each bit is programmed individually using a hardware-timed STROBE pulse.
+ * The caller must ensure VQPS (1.8V~1.98V) is present during the write.
+ * Per TRM Section 21.6, only one bit is programmed per STROBE cycle.
+ */
+static int rockchip_rk3399_efuse_write(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct rockchip_efuse_chip *efuse = context;
+ u8 *buf = val;
+ int ret;
+
+ ret = clk_prepare_enable(efuse->clk);
+ if (ret < 0) {
+ dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
+ return ret;
+ }
+
+ while (bytes--) {
+ u8 byte = *buf++;
+ int bit;
+
+ for (bit = 0; bit < 8; bit++) {
+ u32 addr, ctrl;
+
+ if (!(byte & BIT(bit)))
+ continue;
+
+ addr = offset * 8 + bit;
+
+ /*
+ * A_PGM mode (TRM table 23-3):
+ * CSB=L, PGENB=L, PS=H, PD=L, LOAD=L, RSB=L,
+ * STROBSFTSEL=H (software controls STROBE)
+ * STROBE is asserted separately below.
+ */
+ ctrl = RK3399_STROBSFTSEL | RK3399_PS |
+ ((addr & RK3399_A_MASK) << RK3399_A_SHIFT);
+
+ writel(ctrl, efuse->base + REG_EFUSE_CTRL);
+ udelay(1);
+
+ writel(ctrl | RK3399_STROBE, efuse->base + REG_EFUSE_CTRL);
+ udelay(RK3399_PGM_TIME_US);
+
+ writel(ctrl, efuse->base + REG_EFUSE_CTRL);
+ udelay(1);
+ }
+
+ offset++;
+ }
+
+ /* Return to standby mode: PD=H, CSB=H */
+ writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL);
+
+ clk_disable_unprepare(efuse->clk);
+
+ return 0;
+}
+
+static const struct rockchip_efuse_soc_data rk3288_efuse_data = {
+ .reg_read = rockchip_rk3288_efuse_read,
+};
+
+static const struct rockchip_efuse_soc_data rk3328_efuse_data = {
+ .reg_read = rockchip_rk3328_efuse_read,
+};
+
+static const struct rockchip_efuse_soc_data rk3399_efuse_data = {
+ .reg_read = rockchip_rk3399_efuse_read,
+ .reg_write = rockchip_rk3399_efuse_write,
};
static const struct of_device_id rockchip_efuse_match[] = {
/* deprecated but kept around for dts binding compatibility */
{
.compatible = "rockchip,rockchip-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3066a-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3188-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3228-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3288-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3368-efuse",
- .data = (void *)&rockchip_rk3288_efuse_read,
+ .data = &rk3288_efuse_data,
},
{
.compatible = "rockchip,rk3328-efuse",
- .data = (void *)&rockchip_rk3328_efuse_read,
+ .data = &rk3328_efuse_data,
},
{
.compatible = "rockchip,rk3399-efuse",
- .data = (void *)&rockchip_rk3399_efuse_read,
+ .data = &rk3399_efuse_data,
},
{ /* sentinel */},
};
@@ -252,20 +339,26 @@ MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
static int rockchip_efuse_probe(struct platform_device *pdev)
{
- struct resource *res;
- struct nvmem_device *nvmem;
+ const struct rockchip_efuse_soc_data *soc_data;
struct rockchip_efuse_chip *efuse;
- const void *data;
+ struct nvmem_device *nvmem;
+ struct nvmem_config econfig = {
+ .name = "rockchip-efuse",
+ .add_legacy_fixed_of_cells = true,
+ .type = NVMEM_TYPE_OTP,
+ .stride = 1,
+ .word_size = 1,
+ };
+ struct resource *res;
struct device *dev = &pdev->dev;
- data = of_device_get_match_data(dev);
- if (!data) {
+ soc_data = of_device_get_match_data(dev);
+ if (!soc_data) {
dev_err(dev, "failed to get match data\n");
return -EINVAL;
}
- efuse = devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip),
- GFP_KERNEL);
+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
if (!efuse)
return -ENOMEM;
@@ -278,12 +371,20 @@ static int rockchip_efuse_probe(struct platform_device *pdev)
return PTR_ERR(efuse->clk);
efuse->dev = dev;
+
if (of_property_read_u32(dev->of_node, "rockchip,efuse-size",
&econfig.size))
econfig.size = resource_size(res);
- econfig.reg_read = data;
- econfig.priv = efuse;
- econfig.dev = efuse->dev;
+
+ econfig.reg_read = soc_data->reg_read;
+ if (soc_data->reg_write &&
+ of_property_read_bool(dev->of_node, "rockchip,efuse-write-enable"))
+ econfig.reg_write = soc_data->reg_write;
+
+ econfig.read_only = !econfig.reg_write;
+ econfig.priv = efuse;
+ econfig.dev = dev;
+
nvmem = devm_nvmem_register(dev, &econfig);
return PTR_ERR_OR_ZERO(nvmem);
@@ -300,3 +401,4 @@ static struct platform_driver rockchip_efuse_driver = {
module_platform_driver(rockchip_efuse_driver);
MODULE_DESCRIPTION("rockchip_efuse driver");
MODULE_LICENSE("GPL v2");
+
--
2.47.3
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