[PATCH 01/12] dt-bindings: clock: rockchip: Add RV1106 CRU support

[Jonas Karlman]

Hi Simon,

On 7/6/2026 9:57 PM, Simon Glass wrote:
> Add the clock binding header and schema for the Rockchip RV1106 clock
> and reset unit. The clock IDs match the numbering used by the vendor
> kernel so that existing devicetrees keep working. The header also
> covers the GRF clock controller, which provides the MMC drive and
> sample phase clocks.
> 
> The RV1103 is a package variant of the RV1106 and uses the same CRU.
> 
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
> 
>  .../bindings/clock/rockchip,rv1106-cru.yaml   |  59 ++++
>  .../dt-bindings/clock/rockchip,rv1106-cru.h   | 301 ++++++++++++++++++
>  2 files changed, 360 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
>  create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
> new file mode 100644
> index 000000000000..884a4a8bb0fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RV1106 Clock and Reset Unit
> +
> +maintainers:
> +  - Simon Glass <sjg at chromium.org>
> +  - Heiko Stuebner <heiko at sntech.de>
> +
> +description:
> +  The RV1106 clock controller generates the clock and also implements a
> +  reset controller for SoC peripherals.
> +
> +properties:
> +  compatible:
> +    const: rockchip,rv1106-cru
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#clock-cells":
> +    const: 1
> +
> +  "#reset-cells":
> +    const: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: xin24m
> +
> +  rockchip,grf:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to the syscon managing the "general register files" (GRF),
> +      if missing pll rates are not changeable, due to the missing pll
> +      lock status.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +  - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clock-controller at ff3b0000 {
> +      compatible = "rockchip,rv1106-cru";
> +      reg = <0xff3b0000 0x20000>;
> +      rockchip,grf = <&grf>;
> +      #clock-cells = <1>;
> +      #reset-cells = <1>;
> +    };
> diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
> new file mode 100644
> index 000000000000..acbf9c1ee6af
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
> @@ -0,0 +1,301 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang <zhangqing at rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1106_H
> +
> +/* pll clocks */
> +#define PLL_APLL		1

Clock indices should start at 0 and be a continuous enumeration.

> +#define PLL_DPLL		2
> +#define PLL_CPLL		3
> +#define PLL_GPLL		4
> +#define ARMCLK			5
> +
> +/* clk (clocks) */
> +#define PCLK_DDRPHY		11

As mentioned above, indices should be a continuous enumeration.

> +#define PCLK_DDR_ROOT		12
> +#define PCLK_DDRMON		13
> +#define CLK_TIMER_DDRMON	14
> +#define PCLK_DDRC		15
> +#define PCLK_DFICTRL		16
> +#define ACLK_DDR_ROOT		17
> +#define ACLK_SYS_SHRM		18
> +#define HCLK_NPU_ROOT		19

[snip]

> +/* mmc phase clocks provided by the grf-cru */
> +#define SCLK_EMMC_DRV		1
> +#define SCLK_EMMC_SAMPLE	2
> +#define SCLK_SDMMC_DRV		3
> +#define SCLK_SDMMC_SAMPLE	4
> +#define SCLK_SDIO_DRV		5
> +#define SCLK_SDIO_SAMPLE	6

For other Rockchip SoCs the grf clocks have been exposed from the CRU,
please take a look at e.g. SCLK_SDMMC_DRV and other similar clocks for
RK3528.

Regards,
Jonas

> +
> +#endif