[PATCH v3 1/4] dt-bindings: crypto: rockchip: Add RK356x/RK3588 crypto engine binding
Dawid Olesinski
dawidro at gmail.com
Sun Aug 16 12:39:44 PDT 2026
Add a YAML device tree binding for the Rockchip second-generation (V2)
cryptographic hardware accelerator present on the RK3568 and RK3588 SoCs.
The IP block exposes AES-ECB, AES-CBC, AES-XTS block ciphers, SHA-1,
SHA-224, SHA-256, SHA-384, SHA-512, MD5, and SM3 hash algorithms, each
with a hardware DMA engine controlled via linked-list descriptors.
The binding covers two compatible strings:
- rockchip,rk3568-crypto: clocks and resets are driven directly by the
non-secure CRU (accessible to Linux at EL1).
- rockchip,rk3588-crypto: clocks and resets live in SECURECRU, a
register bank sandboxed to TrustZone. Linux must request them through
the ARM SCMI firmware interface (scmi_clk / scmi_reset), as direct
MMIO access to SECURECRU from EL1 triggers a bus fault.
Co-developed-by: Corentin Labbe <clabbe at baylibre.com>
Signed-off-by: Corentin Labbe <clabbe at baylibre.com>
Signed-off-by: Dawid Olesinski <dawidro at gmail.com>
Tested-by: Diederik de Haas <diederik at cknow-tech.com> # Quartz64-B,
NanoPi R5S, NanoPC-T6 LTS
---
.../crypto/rockchip,rk3588-crypto.yaml | 83 +++++++++++++++++++
MAINTAINERS | 2 +
2 files changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
new file mode 100644
index 000000000000..32d241c19453
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip cryptographic offloader
+
+maintainers:
+ - Heiko Stuebner <heiko at sntech.de>
+ - Corentin Labbe <clabbe at baylibre.com>
+ - Dawid Olesinski <dawidro at gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3568-crypto
+ - items:
+ - enum:
+ - rockchip,rk3588-crypto
+ - const: rockchip,rk3568-crypto
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core clock for the crypto IP internal logic
+ - description: AXI interconnect clock interface
+ - description: AHB interface clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: aclk
+ - const: hclk
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: core
+ - const: aclk
+ - const: hclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ crypto at fe370000 {
+ compatible = "rockchip,rk3588-crypto", "rockchip,rk3568-crypto";
+ reg = <0x0 0xfe370000 0x0 0x2000>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>,
+ <&scmi_clk SCMI_HCLK_SECURE_NS>;
+ clock-names = "core", "aclk", "hclk";
+ resets = <&scmi_reset SCMI_SRST_CRYPTO_CORE>;
+ reset-names = "core";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index c8d4b913f26c..50b77a750db3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23131,9 +23131,11 @@ F: drivers/media/platform/rockchip/rkcif/
ROCKCHIP CRYPTO DRIVERS
M: Corentin Labbe <clabbe at baylibre.com>
+M: Dawid Olesinski <dawidro at gmail.com>
L: linux-crypto at vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml
+F: Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml
F: drivers/crypto/rockchip/
ROCKCHIP I2S TDM DRIVER
--
2.47.3
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