[RFC PATCH 2/5] arm64: dts: rockchip: add ISP nodes to rk3588

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Sat, Apr 25, 2026 at 02:58:47AM +0900, Paul Elder wrote:
> From: Xu Hongfei <xuhf at rock-chips.com>
> 
> Add device tree nodes for the ISP and their iommus on the RK3588.
> 
> Signed-off-by: Xu Hongfei <xuhf at rock-chips.com>
> Signed-off-by: Paul Elder <paul.elder at ideasonboard.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 8b98e5c3cc8b..607b03d55dfd 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -3535,6 +3535,66 @@ gpio4: gpio at fec50000 {
>  			#interrupt-cells = <2>;
>  		};
>  	};
> +
> +	isp0: isp at fdcb0000 {
> +		compatible = "rockchip,rk3588-isp";
> +		reg = <0x0 0xfdcb0000 0x0 0x7f00>;
> +		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "isp_irq", "mi_irq";
> +		clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>,
> +			 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>,
> +			 <&cru CLK_ISP0_CORE_VICAP>;
> +		clock-names = "aclk", "hclk", "clk_core",
> +			      "clk_core_marvin", "clk_core_vicap";
> +		power-domains = <&power RK3588_PD_VI>;
> +		iommus = <&isp0_mmu>;
> +		status = "disabled";
> +	};
> +
> +	isp0_mmu: iommu at fdcb7f00 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdcb7f00 0x0 0x100>;
> +		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "isp0_mmu";

I don't think interrupt-names is needed. Same for the second IOMMU.

> +		clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VI>;
> +		#iommu-cells = <0>;
> +		rockchip,disable-mmu-reset;
> +		status = "disabled";
> +	};
> +
> +	isp1: isp at fdcc0000 {
> +		compatible = "rockchip,rk3588-isp";
> +		reg = <0x0 0xfdcc0000 0x0 0x7f00>;
> +		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "isp_irq", "mi_irq";
> +		clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>,
> +			 <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>,
> +			 <&cru CLK_ISP1_CORE_VICAP>;
> +		clock-names = "aclk", "hclk", "clk_core",
> +			      "clk_core_marvin", "clk_core_vicap";
> +		power-domains = <&power RK3588_PD_ISP1>;
> +		iommus = <&isp1_mmu>;
> +		status = "disabled";
> +	};
> +
> +	isp1_mmu: iommu at fdcc7f00 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdcc7f00 0x0 0x100>;
> +		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "isp1_mmu";
> +		clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_ISP1>;
> +		#iommu-cells = <0>;
> +		rockchip,disable-mmu-reset;
> +		status = "disabled";
> +	};
>  };
>  
>  #include "rk3588-base-pinctrl.dtsi"

-- 
Regards,

Laurent Pinchart