[PATCH v3 3/4] soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset

[Nicolas Frattaroli]

On Friday, 20 March 2026 11:34:15 Central European Summer Time Daniele Briguglio wrote:
> Add the RK3588_SYSGRF_SOC_CON6 register offset to the RK3588 GRF
> header. This register contains the I2S MCLK output to IO gate bits,
> needed by the clock driver.
> 
> Signed-off-by: Daniele Briguglio <hello at superkali.me>
> ---
>  include/soc/rockchip/rk3588_grf.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h
> index 02a7b2432d99..db0092fc66ad 100644
> --- a/include/soc/rockchip/rk3588_grf.h
> +++ b/include/soc/rockchip/rk3588_grf.h
> @@ -19,4 +19,6 @@
>  /* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
>  #define RK3588_PMUGRF_OS_REG6_LP5_CKR			BIT(0)
>  
> +#define RK3588_SYSGRF_SOC_CON6			0x0318
> +
>  #endif /* __SOC_RK3588_GRF_H */
> 
> 

Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli at collabora.com>

Verified the definition by comparing it to hardware documentation,
it checks out.