[PATCH v3 4/5] dt-bindings: clock: Add support for rockchip pvtpll

[Diederik de Haas]

On Mon Oct 20, 2025 at 4:37 AM CEST, Elaine Zhang wrote:
> Add pvtpll documentation for rockchip.
>
> Signed-off-by: Elaine Zhang <zhangqing at rock-chips.com>
> ---
>  .../bindings/clock/rockchip,clk-pvtpll.yaml   | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
> new file mode 100644

Should this file have the 'clk-' part in its name?
In a way this is different from the other DT binding files, but none of
the others have the 'clk-' part in their file name:

me at pc:~/linux/Documentation/devicetree/bindings/clock$ ls -lh rockchip,*
-rw-rw-r-- 1 me me 2,9K okt 20 11:32 rockchip,px30-cru.yaml
-rw-rw-r-- 1 me me 1,9K okt 20 11:32 rockchip,rk3036-cru.yaml
-rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3128-cru.yaml
-rw-rw-r-- 1 me me 2,3K okt 20 11:32 rockchip,rk3188-cru.yaml
-rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3228-cru.yaml
-rw-rw-r-- 1 me me 2,6K okt 20 11:32 rockchip,rk3288-cru.yaml
-rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rk3308-cru.yaml
-rw-rw-r-- 1 me me 2,1K okt 20 11:32 rockchip,rk3328-cru.yaml
-rw-rw-r-- 1 me me 2,4K okt 20 11:32 rockchip,rk3368-cru.yaml
-rw-rw-r-- 1 me me 2,5K okt 20 11:32 rockchip,rk3399-cru.yaml
-rw-rw-r-- 1 me me 1,5K okt 20 11:32 rockchip,rk3528-cru.yaml
-rw-rw-r-- 1 me me 1,1K okt 20 11:32 rockchip,rk3562-cru.yaml
-rw-rw-r-- 1 me me 1,8K okt 20 11:32 rockchip,rk3568-cru.yaml
-rw-rw-r-- 1 me me 1,2K okt 20 11:32 rockchip,rk3576-cru.yaml
-rw-rw-r-- 1 me me 1,6K okt 20 11:32 rockchip,rk3588-cru.yaml
-rw-rw-r-- 1 me me 2,2K okt 20 11:32 rockchip,rv1108-cru.yaml
-rw-rw-r-- 1 me me 1,3K okt 20 11:32 rockchip,rv1126-cru.yaml

> index 000000000000..8be34bcde7b0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-pvtpll.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,clk-pvtpll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Pvtpll
> +
> +maintainers:
> +  - Elaine Zhang <zhangqing at rock-chips.com>
> +  - Heiko Stuebner <heiko at sntech.de>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - rockchip,rv1103b-core-pvtpll
> +          - rockchip,rv1103b-enc-pvtpll
> +          - rockchip,rv1103b-isp-pvtpll
> +          - rockchip,rv1103b-npu-pvtpll
> +          - rockchip,rv1126b-core-pvtpll
> +          - rockchip,rv1126b-isp-pvtpll
> +          - rockchip,rv1126b-enc-pvtpll
> +          - rockchip,rv1126b-aisp-pvtpll
> +          - rockchip,rv1126b-npu-pvtpll
> +          - rockchip,rk3506-core-pvtpll
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#clock-cells":
> +    const: 0
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-output-names:
> +    maxItems: 1
> +
> +  rockchip,cru:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      Phandle to the main Clock and Reset Unit (CRU) controller.
> +      Required for PVTPLLs that need to interact with the main CRU
> +      for clock management operations.
> +
> +required:
> +  - "#clock-cells"
> +  - compatible
> +  - reg
> +  - clock-output-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    pvtpll_core: pvtpll-core at 20480000 {
> +      compatible = "rockchip,rv1126b-core-pvtpll", "syscon";
> +      reg = <0x20480000 0x100>;
> +      #clock-cells = <0>;
> +      clock-output-names = "clk_core_pvtpll";
> +    };
> +
> +  - |
> +    pvtpll_isp: pvtpll-isp at 21c60000 {
> +      compatible = "rockchip,rv1126b-isp-pvtpll", "syscon";
> +      reg = <0x21c60000 0x100>;
> +      rockchip,cru = <&cru>;
> +      #clock-cells = <0>;
> +      clock-output-names = "clk_isp_pvtpll";
> +    };
> +
> +  - |
> +    pvtpll_enc: pvtpll-enc at 21f00000 {
> +      compatible = "rockchip,rv1126b-enc-pvtpll", "syscon";
> +      reg = <0x21f00000 0x100>;
> +      #clock-cells = <0>;
> +      clock-output-names = "clk_vepu_pvtpll";
> +    };
> +
> +  - |
> +    pvtpll_aisp: pvtpll-aisp at 21fc0000 {
> +      compatible = "rockchip,rv1126b-aisp-pvtpll", "syscon";
> +      reg = <0x21fc0000 0x100>;
> +      rockchip,cru = <&cru>;
> +      #clock-cells = <0>;
> +      clock-output-names = "clk_vcp_pvtpll";
> +    };
> +
> +  - |
> +    pvtpll_npu: pvtpll-npu at 22080000 {
> +      compatible = "rockchip,rv1126b-npu-pvtpll", "syscon";
> +      reg = <0x22080000 0x100>;
> +      rockchip,cru = <&cru>;
> +      #clock-cells = <0>;
> +      clock-output-names = "clk_npu_pvtpll";

rockchip,cru line as the last line?

Cheers,
  Diederik

> +    };
> +
> +...