[PATCH v2 1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528

[Vinod Koul]

On Tue, 18 Nov 2025 17:52:05 +0800, Shawn Lin wrote:
> When PCIe link enters L1 PM substates, the PHY will turn off its
> PLL for power-saving. However, it turns off the PLL too fast which
> leads the PHY to be broken. According to the PHY document, we need
> to delay PLL turnoff time.
> 
> 

Applied, thanks!

[1/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
      commit: a2a18e5da64f8da306fa97c397b4c739ea776f37
[2/2] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
      commit: be866e68966d20bcc4a73708093d577176f99c0c

Best regards,
-- 
~Vinod