[PATCH] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi

[Bjorn Helgaas]

On Thu, Nov 06, 2025 at 11:51:59AM +0800, Shawn Lin wrote:
> This Wi-Fi advertises the L0s and L1 capabilities but actually
> it doesn't support them. This's comfirmed by Hisilicon team in
> actual productization.
> 
> Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
> ---
> 
>  drivers/pci/quirks.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 214ed06..67250d4 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2526,6 +2526,12 @@ static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
>  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
>  
>  /*
> + * The Hi1105 PCIe Wi-Fi doesn't support L0s and L1 but advertise the capability.
> + * Disable both L0s and L1 for now.
> + */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1);

PCI_VENDOR_ID_HUAWEI is 0x19e5.  Is there an upstream driver that
matches [19e5:1105]?  I didn't find anything.

I think quirk_disable_aspm_l0s_l1() might be a problem because the new
strategy is to enable ASPM early (in pcie_aspm_init_link_state(),
called from pci_scan_slot(), which happens before FINAL fixups are run
during pci_bus_add_device().

So I think we will enable L0s and L1 briefly before
quirk_disable_aspm_l0s_l1() runs, and it's possible we'd see a problem
then.

But if you apply this series:
  https://lore.kernel.org/r/20251106183643.1963801-1-helgaas@kernel.org

and then the patch below on top, I think we should avoid enabling L0s
and L1 at all:

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 44e780718953..24c278857159 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2536,6 +2536,7 @@ static void quirk_disable_aspm_l0s_l1_cap(struct pci_dev *dev)
 	pci_info(dev, "ASPM: L0s L1 removed from Link Capabilities to work around device defect\n");
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1_cap);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1_cap);
 
 /*
  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain