[PATCH] clk: rockchip: rk3288: Enable clock rate propagation for I2S0 output clock

[fdostie at gmail.com]

From: Fletcher Dostie <fdostie at gmail.com>

The I2S0 output clock (SCLK_I2S0_OUT) on rk3288 SoCs was missing the
CLK_SET_RATE_PARENT flag, which prevented the clock framework from
properly propagating rate changes to its parent. This caused the I2S0
output clock to not function.

Add the CLK_SET_RATE_PARENT flag to ensure that when the
I2S0 output clock rate is set, the change is correctly propagated to
its parent clock, fixing the I2S output clock.

Signed-off-by: Fletcher Dostie <fdostie at gmail.com>
---
 drivers/clk/rockchip/clk-rk3288.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 90d329216064..0f24060761ac 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -364,7 +364,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 			RK3288_CLKSEL_CON(8), 0,
 			RK3288_CLKGATE_CON(4), 2, GFLAGS,
 			&rk3288_i2s_fracmux),
-	COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
+	COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 			RK3288_CLKGATE_CON(4), 0, GFLAGS),
 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
-- 
2.48.1