[PATCH 2/2] PM / devfreq: rockchip-dfi: add support for LPDDR5

[Diederik de Haas]

Hi Nicolas,

On Fri May 30, 2025 at 3:38 PM CEST, Nicolas Frattaroli wrote:
> <snip>
> Downstream has some special case handling for a hardware version where
> not just the control bits differ, but also the register. Since I don't
> know whether that hardware version is in any production silicon, it's
> left unimplemented for now, with an error message urging users to report
> if they have such a system.
> <snip>
> ---
>  drivers/devfreq/event/rockchip-dfi.c | 84 ++++++++++++++++++++++++++++--------
>  include/soc/rockchip/rk3588_grf.h    |  8 +++-
>  include/soc/rockchip/rockchip_grf.h  |  1 +
>  3 files changed, 73 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
> index 54effb63519653d20b40eed88681330983399a77..5a2c9badcc64c552303c2f55c52e5420dec5ffc1 100644
> --- a/drivers/devfreq/event/rockchip-dfi.c
> +++ b/drivers/devfreq/event/rockchip-dfi.c
> @@ -34,15 +34,18 @@
>  
>  /* DDRMON_CTRL */
>  #define DDRMON_CTRL	0x04
> +#define DDRMON_CTRL_LPDDR5		BIT(6)
>  #define DDRMON_CTRL_DDR4		BIT(5)
>  #define DDRMON_CTRL_LPDDR4		BIT(4)
>  #define DDRMON_CTRL_HARDWARE_EN		BIT(3)
>  #define DDRMON_CTRL_LPDDR23		BIT(2)
>  #define DDRMON_CTRL_SOFTWARE_EN		BIT(1)
>  #define DDRMON_CTRL_TIMER_CNT_EN	BIT(0)
> -#define DDRMON_CTRL_DDR_TYPE_MASK	(DDRMON_CTRL_DDR4 | \
> +#define DDRMON_CTRL_DDR_TYPE_MASK	(DDRMON_CTRL_LPDDR5 | \
> +					 DDRMON_CTRL_DDR4 | \
>  					 DDRMON_CTRL_LPDDR4 | \
>  					 DDRMON_CTRL_LPDDR23)
> +#define DDRMON_CTRL_LP5_BANK_MODE_MASK	GENMASK(8, 7)
>  
>  #define DDRMON_CH0_WR_NUM		0x20
>  #define DDRMON_CH0_RD_NUM		0x24
> @@ -116,13 +119,60 @@ struct rockchip_dfi {
>  	int buswidth[DMC_MAX_CHANNELS];
>  	int ddrmon_stride;
>  	bool ddrmon_ctrl_single;
> +	u32 lp5_bank_mode;
> +	bool lp5_ckr;	/* true if in 4:1 command-to-data clock ratio mode */
>  	unsigned int count_multiplier;	/* number of data clocks per count */
>  };
>  
> +static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctrl,
> +					u32 *mask)
> +{
> +	u32 ddrmon_ver;
> +
> +	*mask = DDRMON_CTRL_DDR_TYPE_MASK;
> +
> +	switch (dfi->ddr_type) {
> +	case ROCKCHIP_DDRTYPE_LPDDR2:
> +	case ROCKCHIP_DDRTYPE_LPDDR3:
> +		*ctrl = DDRMON_CTRL_LPDDR23;
> +		break;
> +	case ROCKCHIP_DDRTYPE_LPDDR4:
> +	case ROCKCHIP_DDRTYPE_LPDDR4X:
> +		*ctrl = DDRMON_CTRL_LPDDR4;
> +		break;
> +	case ROCKCHIP_DDRTYPE_LPDDR5:
> +		ddrmon_ver = readl_relaxed(dfi->regs);
> +		if (ddrmon_ver < 0x40) {
> +			*ctrl = DDRMON_CTRL_LPDDR5 | dfi->lp5_bank_mode;
> +			*mask |= DDRMON_CTRL_LP5_BANK_MODE_MASK;
> +			break;
> +		}
> +
> +		/*
> +		 * As it is unknown whether the unpleasant special case
> +		 * behaviour used by the vendor kernel is needed for any
> +		 * shipping hardware, ask users to report if they have
> +		 * some of that hardware.
> +		 */
> +		dev_err(&dfi->edev->dev,
> +			"unsupported DDRMON version 0x%04X, please let linux-rockchip know!\n",
> +			ddrmon_ver);
> +		return -EOPNOTSUPP;

I'm guessing you mean the linux-rockchip mailing list here? If so, I
think it's better to make that explicit as 'Joe User' who may run into
this issue may not be aware of that mailing list. The 'linux' and
'rockchip' name combo is used in quite a few places.

Cheers,
  Diederik

> +	default:
> +		dev_err(&dfi->edev->dev, "unsupported memory type 0x%X\n",
> +			dfi->ddr_type);
> +		return -EOPNOTSUPP;
> +	}
> +
> +	return 0;
> +}
> +
>  static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
>  {
>  	void __iomem *dfi_regs = dfi->regs;
>  	int i, ret = 0;
> +	u32 ctrl;
> +	u32 ctrl_mask;
>  
>  	mutex_lock(&dfi->mutex);
>  
> @@ -136,8 +186,11 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
> <snip>
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